A heterojunction structure, a semiconductor device structure and a method of manufacturing the same
By inserting an intermediate structural layer between the active semiconductor layers, the diffusion problem in the metal-oxide-semiconductor heterojunction process is solved, which blocks element diffusion and allows carrier transport, forming a more ideal heterojunction interface and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV SHENZHEN GRADUATE SCHOOL
- Filing Date
- 2022-04-19
- Publication Date
- 2026-04-28
AI Technical Summary
In existing metal-oxide-semiconductor heterojunction processes, the amorphous properties of metal oxides and the high-temperature process lead to element diffusion, making it difficult to form an ideal semiconductor heterojunction and thus failing to fully realize its performance advantages.
An intermediate structural layer, such as aluminum oxide, hafnium oxide, or tantalum oxide, is inserted between two active semiconductor layers to block the diffusion of metal and oxygen elements and allow carrier transport through a low-barrier band structure, forming an ideal heterojunction interface.
This enables deeper heterojunction potential wells, improving the high mobility and high stability of semiconductor devices and enhancing the performance of transistors or diodes.
Smart Images
Figure CN114899224B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to heterojunction field-effect transistors, specifically to a heterojunction structure, a semiconductor device structure, and a method for manufacturing the same. Background Technology
[0002] A semiconductor heterojunction is a special type of PN junction formed by sequentially depositing two or more thin films of different semiconductor materials onto the same substrate. Due to the energy band differences between the two different semiconductors (mainly the difference between the conduction band bottom level and the Fermi level), potential wells and barriers can be formed at the contact interface, thus forming a heterojunction (e.g., ...). Figure 1 As shown in the figure, a large number of electrons can exist in the heterojunction potential well formed by the two semiconductor interfaces. Semiconductor heterojunctions are considered an effective means to obtain higher performance semiconductor devices, such as current high-mobility and high-stability transistors and high-voltage diodes.
[0003] In existing metal-oxide-semiconductor (MOS) heterojunction processes, due to the amorphous nature of MOS semiconductors and the high-temperature processes (such as annealing) commonly used in device fabrication, elemental diffusion easily occurs between two or more metal oxides. This makes it difficult to form ideal semiconductor heterojunctions, hindering the full utilization and leveraging of the performance advantages of heterojunctions in MOS devices. Consequently, the performance of existing high-mobility, high-stability transistors or high-voltage diodes requires further improvement. Summary of the Invention
[0004] The main technical problem solved by this invention is to propose a heterojunction structure, a semiconductor device structure and a manufacturing method thereof, so as to better leverage the performance advantages of heterojunction in metal-oxide-semiconductor devices and further improve device performance.
[0005] According to a first aspect, one embodiment provides a heterojunction structure for a semiconductor device, comprising: a substrate and a heterostructure layer above the substrate;
[0006] The heterostructure layer includes at least two active layers and an intermediate structure layer located between two adjacent active layers, wherein the band gaps of the two adjacent active layers are different, so as to form a heterojunction between the two adjacent active layers. The intermediate structure layer is used to block the diffusion of metal and oxygen elements. The thickness and band structure of the intermediate structure layer allow charge carriers to pass through and transport between the first active layer and the second active layer.
[0007] Optionally, the intermediate structural layer is: aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.
[0008] Optionally, the active layer is IGZO, IZO, ZTO, ITZO, AZO, ZnO, GaO, or InO.
[0009] Optionally, the thickness of the intermediate structural layer is 0-5 nm.
[0010] According to a second aspect, one embodiment provides a heterojunction semiconductor device structure, comprising:
[0011] Substrate;
[0012] A heterostructure layer, wherein the heterostructure layer is any of the above-mentioned heterojunction structures, is located on a portion of the upper surface of the substrate;
[0013] A gate insulating layer is located on a portion of the upper surface of the heterostructure layer;
[0014] The gate electrode layer is located above the gate insulating layer;
[0015] A passivation layer covering the gate electrode layer and the gate insulating layer;
[0016] The source / drain electrode layer is in contact with the heterostructure layer at its bottom and is located at both ends of the gate electrode layer, wherein the passivation layer separates the source / drain electrode layer from the gate electrode layer.
[0017] According to a third aspect, one embodiment provides a heterojunction semiconductor device structure, comprising:
[0018] Substrate;
[0019] The gate electrode layer is located on the upper surface of the substrate portion;
[0020] A gate insulating layer is located on the upper surface of the substrate and covers the gate electrode layer;
[0021] A heterostructure layer, wherein the heterostructure layer is any of the above-mentioned heterojunction structures, is located on a portion of the upper surface of the gate insulating layer;
[0022] The source and drain electrode layers are distributed at both ends of the gate electrode layer, and their bottoms simultaneously contact the heterostructure layer and the gate insulating layer.
[0023] According to a fourth aspect, one embodiment provides a heterojunction semiconductor device structure, comprising:
[0024] Substrate;
[0025] The gate electrode layer is located on the upper surface of the substrate portion;
[0026] A gate insulating layer is located on the upper surface of the substrate and covers the gate electrode layer;
[0027] A heterostructure layer, wherein the heterostructure layer is any of the heterojunction structures described above, is located on a portion of the upper surface of the gate insulating layer;
[0028] An etching barrier layer is located on a portion of the upper surface of the heterostructure layer;
[0029] The source and drain electrode layers are distributed at both ends of the gate electrode layer, and their bottoms simultaneously contact the etch barrier layer, the heterostructure layer, and the gate insulating layer.
[0030] According to a fifth aspect, one embodiment provides a heterojunction semiconductor device structure, comprising:
[0031] Substrate;
[0032] The bottom electrode is located on the upper surface of the substrate;
[0033] A heterostructure layer located on the surface above the bottom electrode, wherein the heterostructure layer is any of the heterojunction structures described above;
[0034] The top electrode is located on a portion of the surface above the heterostructure layer;
[0035] A passivation layer is distributed at both ends of the top electrode, and the bottom of the passivation layer simultaneously contacts the heterostructure layer and the bottom electrode.
[0036] According to a sixth aspect, one embodiment provides a heterojunction semiconductor device structure, comprising:
[0037] Substrate;
[0038] A heterostructure layer, wherein the heterostructure layer is any of the above-mentioned heterojunction structures, is located on a portion of the upper surface of the substrate;
[0039] A gate electrode layer, located on a portion of the surface above the heterostructure layer;
[0040] A passivation layer covers the gate electrode layer;
[0041] The source / drain electrode layers are in contact with the heterostructure layer at the bottom and distributed at both ends of the gate electrode layer, wherein the passivation layer separates the source / drain electrode layers from the gate electrode layer.
[0042] According to a seventh aspect, one embodiment provides a method for manufacturing a heterojunction semiconductor device structure, comprising:
[0043] A first active layer is formed on the substrate;
[0044] An intermediate structural layer is formed on the upper surface of the first active layer;
[0045] A second active layer is formed on the upper surface of the intermediate structural layer. The second active layer and the first active layer have different band gaps, so that a heterojunction is formed between the first active layer and the second active layer. The intermediate structural layer can block the diffusion of metal and oxygen elements and has a predetermined thickness. The thickness and band structure of the intermediate structural layer allow charge carriers to pass through and transport between the first active layer and the second active layer.
[0046] According to the heterojunction structure, semiconductor device structure, and manufacturing method of the above embodiments, the method involves forming an intermediate structural layer material between two active semiconductor layers. This intermediate structural layer material, on the one hand, blocks the diffusion of metal elements between the two active semiconductor layers; on the other hand, its energy band has a low potential barrier for electrons, allowing electrons to freely migrate or tunnel extensively between the two active semiconductor layers. This results in a more ideal heterojunction interface between the first and second active layers, achieving a deeper heterojunction potential well. This forms a more ideal semiconductor heterojunction, truly utilizing and leveraging the performance advantages of heterojunctions in metal-oxide-semiconductor devices. It improves the performance of existing high-mobility, high-stability transistors or high-voltage diodes. Attached Figure Description
[0047] Figure 1 This is a diagram of the energy band structure of a semiconductor heterojunction in the prior art.
[0048] Figure 2 This is the energy band diagram of the semiconductor heterojunction provided in this embodiment;
[0049] Figure 3 This is a schematic diagram of the heterojunction structure provided in this embodiment applied to a top-gate self-aligned thin-film transistor.
[0050] Figure 4 This is a schematic diagram of the heterojunction structure provided in this embodiment applied to a bottom-gate back-channel etched thin-film transistor.
[0051] Figure 5 This is a schematic diagram of the heterojunction structure provided in this embodiment applied to a bottom-gate etch-blocking thin-film transistor.
[0052] Figure 6 This is a schematic diagram of the heterojunction structure provided in this embodiment applied to a Schottky diode.
[0053] Figure 7 This is a schematic diagram of the heterojunction structure provided in this embodiment applied to a Schottky gate transistor. Detailed Implementation
[0054] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.
[0055] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.
[0056] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).
[0057] As is known from the background technology, in existing metal-oxide-semiconductor heterojunction processes, due to the amorphous characteristics of metal-oxide-semiconductors and the high-temperature processes (such as annealing) commonly used in device fabrication, element diffusion easily occurs between two or more metal oxides, making it difficult to form an ideal semiconductor heterojunction and thus failing to truly utilize and leverage the performance advantages of heterojunctions in metal-oxide-semiconductor devices.
[0058] In embodiments of the present invention, it can be combined with Figure 2 An intermediate structural layer 30, such as aluminum oxide, hafnium oxide, or tantalum oxide, is inserted between two active semiconductor layers. This intermediate structural layer 30 can block the diffusion of metal elements between the two active semiconductor layers. For example, if the first active layer 10 and the second active layer 20 are two semiconductor materials with different energy bands, the energy band of the intermediate structural layer 30 has a lower potential barrier for electrons, allowing electrons to freely migrate or tunnel extensively between the two semiconductors. This enables the formation of a more ideal heterojunction interface between the first active layer 10 and the second active layer 20, resulting in a deeper heterojunction potential well.
[0059] This embodiment provides a heterojunction structure for a semiconductor device, comprising: a substrate and a heterostructure layer above the substrate. The heterostructure layer includes at least two active layers and an intermediate structure layer located between two adjacent active layers. The adjacent active layers have different band gaps to form a heterojunction between them. The intermediate structure layer blocks the diffusion of metal and oxygen elements, and its thickness and band structure allow charge carriers to pass through and transport between the first and second active layers.
[0060] In this embodiment, the intermediate structural layer can be made of alumina, hafnium oxide, tantalum oxide, or titanium oxide. The thickness of this intermediate structural layer is preferably no more than 5 nm. While still functioning, the thinner the intermediate structural layer, the better; for example, it can be around 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.
[0061] The active layer can be made of IGZO, IZO, ZTO, ITZO, AZO, ZnO, GaO, or InO. Two or more active layers can be selected from different active layer materials as needed, and this intermediate structural layer can be applied in bilayer, trilayer, or more semiconductor heterojunctions.
[0062] Please refer to the reference. Figure 3 This embodiment provides a heterojunction semiconductor device structure, specifically the application of the above-described heterojunction structure in a top-gate self-aligned thin-film transistor. The structure includes: a substrate 100, a heterostructure layer, a gate insulating layer 104, a gate electrode layer 105, a passivation layer 106, and a source / drain electrode layer 106.
[0063] The substrate 100 can be made of materials such as silicon or glass, or flexible materials such as PI or PET.
[0064] The heterostructure layer includes a bilayer, triple-layer, or multilayer semiconductor heterojunction composed of at least two active layers. For example, a bilayer semiconductor heterojunction structure includes a first active layer 101, a second active layer 102, and an intermediate structure layer 103 disposed between the two active layers. The bilayer semiconductor heterojunction structure is located on a portion of the upper surface of the substrate.
[0065] The gate insulating layer 104 is located on a portion of the surface above the heterostructure layer.
[0066] The gate electrode layer 105 is located above the gate insulating layer 104.
[0067] The passivation layer 106 covers the gate electrode layer 105 and the gate insulating layer 104.
[0068] The bottom of the source / drain electrode layer 107 contacts the heterostructure layer and is located at both ends of the gate electrode layer 105, wherein the passivation layer 106 separates the source / drain electrode layer 107 from the gate electrode layer 105.
[0069] Please refer to the reference. Figure 4 This embodiment provides a heterojunction semiconductor device structure, specifically the heterojunction structure described above applied in a bottom-gate back-channel etched thin-film transistor. Its structure includes: a substrate 200, a gate electrode layer 202, a gate insulating layer 201, a heterostructure layer, and a source / drain electrode layer 206.
[0070] The substrate 200 material can be silicon, glass, or flexible materials such as PI and PET.
[0071] The gate electrode layer 202 is located on a portion of the surface above the substrate and is made of metal.
[0072] The gate insulating layer 201 is located on the upper surface of the substrate 200 and covers the gate electrode layer 202.
[0073] The heterostructure layer is located on a portion of the upper surface of the gate insulating layer 201, and includes a bilayer, triple-layer, or more semiconductor heterojunction composed of at least two active layers. For example, the figure shows a bilayer semiconductor heterojunction structure, including a first active layer 203, a second active layer 205, and an intermediate structure layer 204 disposed between the two active layers.
[0074] The source and drain electrode layers 206 are distributed on both sides of the gate electrode layer 202, and their bottoms are in contact with both the heterostructure layer and the gate insulating layer.
[0075] Please refer to the reference. Figure 5 This embodiment provides a heterojunction semiconductor device structure, specifically, the heterojunction structure described above can be applied in a bottom-gate etch-block thin-film transistor. The structure includes: a substrate 300, a gate electrode layer 302, a gate insulating layer 301, a heterostructure layer, an etch-block layer 306, and a source / drain electrode layer 307. The substrate 300 can be made of materials such as silicon or glass, or flexible materials such as PI or PET.
[0076] The gate electrode layer 302 is located on a portion of the upper surface of the substrate 300 and is made of metal.
[0077] The gate insulating layer 301 is located on the upper surface of the substrate 300 and covers the gate electrode layer 302.
[0078] The heterostructure layer is located on a portion of the upper surface of the gate insulating layer 301, and includes a two-layer, three-layer, or more semiconductor heterojunction composed of at least two active layers. For example, the figure shows a two-layer semiconductor heterojunction structure, including a first active layer 303, a second active layer 305, and an intermediate structure layer 304 disposed between the two active layers.
[0079] The etching barrier layer 306 is a metal oxide and is located on part of the upper surface of the heterostructure layer.
[0080] The source / drain electrode layer 307 is distributed at both ends of the gate electrode layer 302, and the bottom of the source / drain electrode layer 307 simultaneously contacts the etch barrier layer 306, the heterostructure layer and the gate insulating layer 301.
[0081] Please refer to the reference. Figure 6 This embodiment provides a heterojunction semiconductor device structure, specifically the heterojunction structure described above applied in a Schottky diode. The structure includes a substrate 400, a bottom electrode 401, a heterostructure layer, a top electrode 405, and a passivation layer 406.
[0082] The substrate 400 material can be silicon, glass, or flexible materials such as PI and PET.
[0083] The bottom electrode 401 is made of metal and is located on the upper surface of the substrate 400.
[0084] The heterostructure layer is located on a portion of the surface above the bottom electrode 400 and includes a bilayer, triple-layer, or more semiconductor heterojunction composed of at least two active layers. For example, the figure shows a bilayer semiconductor heterojunction structure, including a first active layer 402, a second active layer 404, and an intermediate structure layer 403 disposed between the two active layers.
[0085] The top electrode 405 is metal and is located on a portion of the surface above the heterostructure layer.
[0086] The passivation layer 406 is distributed at both ends of the top electrode 405, and the bottom of the passivation layer 406 simultaneously contacts the heterostructure layer and the bottom electrode 401.
[0087] Please refer to the reference. Figure 7 This embodiment provides a heterojunction semiconductor device structure, specifically the heterojunction structure described above applied to a Schottky gate transistor, the structure of which includes: a substrate 500, a heterostructure layer, a gate electrode layer 504, a passivation layer 505, and a source / drain electrode layer 506.
[0088] The substrate 500 material can be silicon, glass, or flexible materials such as PI and PET.
[0089] The heterostructure layer is located on a portion of the upper surface of the substrate 500 and includes a bilayer, triple-layer, or more semiconductor heterojunction composed of at least two active layers. For example, the figure shows a bilayer semiconductor heterojunction structure, including a first active layer 502, a second active layer 503, and an intermediate structure layer 502 disposed between the two active layers.
[0090] The gate electrode layer 504 is metal and serves as the Schottky top gate electrode, located on a portion of the surface above the heterostructure layer. A passivation layer 505 covers the gate electrode layer 504.
[0091] The source / drain electrode layers 506 are located at both ends of the gate electrode layer 504, the bottom of the source / drain electrode layers 506 contacts the heterostructure layer, and the passivation layer 505 separates the source / drain electrode layers 506 from the gate electrode layer 504. This embodiment also provides a method for manufacturing a heterojunction semiconductor device structure, including:
[0092] Step 1: Form the first active layer on the substrate.
[0093] Step 2: An intermediate structural layer is formed on the upper surface of the first active layer.
[0094] The intermediate structural layer can be prepared by direct sputtering, reactive sputtering, ALD growth, or post-treatment of elemental materials (such as oxidation), etc.
[0095] Step 3: A second active layer is formed on the upper surface of the intermediate structure layer. The second active layer and the first active layer have different band gaps, so that a heterojunction is formed between the first active layer and the second active layer. The intermediate structure layer can block the diffusion of metal and oxygen elements and has a preset thickness. The thickness and band structure of the intermediate structure layer allow charge carriers to pass through and transport between the first active layer and the second active layer.
[0096] When forming a semiconductor heterojunction with three or more layers, an intermediate structural layer can be formed between two active layers multiple times through direct sputtering, reactive sputtering, ALD growth, or post-processing of elemental materials (such as oxidation). The material of the intermediate structural layer can be aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.
[0097] By forming an intermediate structural layer material, such as aluminum oxide, hafnium oxide, or tannin oxide, between two active semiconductor layers, the diffusion of metal elements between the two active layers is hindered. Furthermore, the energy band of the intermediate structural layer material has a lower potential barrier for electrons, allowing electrons to migrate freely or tunnel extensively between the two active semiconductor layers. This enables the formation of a more ideal heterojunction interface between the first and second active layers, resulting in a deeper heterojunction potential well. This leads to a more ideal semiconductor heterojunction, allowing for the full utilization and leveraging of the performance advantages of heterojunctions in metal-oxide-semiconductor devices. It also improves the performance of existing high-mobility, high-stability transistors or high-voltage diodes.
[0098] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.
Claims
1. A heterojunction structure for semiconductor devices, characterized in that, include: Heterogeneous structural layers located on the substrate and above the substrate; The heterostructure layer includes at least two active layers and an intermediate structure layer located between two adjacent active layers. The two adjacent active layers include a first active layer and a second active layer. The band gaps of the two adjacent active layers are different, so as to form a heterojunction between the two adjacent active layers. The intermediate structure layer is used to block the diffusion of metal and oxygen elements. The thickness and band structure of the intermediate structure layer allow charge carriers to pass through and transport between the first active layer and the second active layer. The intermediate structural layer is: aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.
2. The heterojunction structure as described in claim 1, characterized in that, The active layer is IGZO, IZO, ZTO, ITZO, AZO, ZnO, GaO, or InO.
3. The heterojunction structure as described in claim 1, characterized in that, The thickness of the intermediate structural layer does not exceed 5 nm.
4. A heterojunction semiconductor device structure, characterized in that, include: Substrate; A heterostructure layer, wherein the heterostructure layer is any one of the structures in claims 1-3, is located on a portion of the upper surface of the substrate; A gate insulating layer is located on a portion of the upper surface of the heterostructure layer; The gate electrode layer is located above the gate insulating layer; A passivation layer covering the gate electrode layer and the gate insulating layer; The source / drain electrode layer is in contact with the heterostructure layer at its bottom and is located at both ends of the gate electrode layer, wherein the passivation layer separates the source / drain electrode layer from the gate electrode layer.
5. A heterojunction semiconductor device structure, characterized in that, include: Substrate; The gate electrode layer is located on the upper surface of the substrate portion; A gate insulating layer is located on the upper surface of the substrate and covers the gate electrode layer; A heterostructure layer, wherein the heterostructure layer is any one of the structures in claims 1-3, is located on a portion of the upper surface of the gate insulating layer; The source and drain electrode layers are distributed at both ends of the gate electrode layer, and their bottoms simultaneously contact the heterostructure layer and the gate insulating layer.
6. A heterojunction semiconductor device structure, characterized in that, include: Substrate; The gate electrode layer is located on the upper surface of the substrate portion; A gate insulating layer is located on the upper surface of the substrate and covers the gate electrode layer; A heterostructure layer, wherein the heterostructure layer is any one of the structures in claims 1-3, is located on a portion of the upper surface of the gate insulating layer; An etching barrier layer is located on a portion of the upper surface of the heterostructure layer; The source and drain electrode layers are distributed at both ends of the gate electrode layer, and their bottoms simultaneously contact the etch barrier layer, the heterostructure layer, and the gate insulating layer.
7. A heterojunction semiconductor device structure, characterized in that, include: Substrate; The bottom electrode is located on the upper surface of the substrate; A heterostructure layer located on the surface above the bottom electrode, wherein the heterostructure layer is any one of the structures in claims 1-3; The top electrode is located on a portion of the surface above the heterostructure layer; A passivation layer is distributed at both ends of the top electrode, and the bottom of the passivation layer simultaneously contacts the heterostructure layer and the bottom electrode.
8. A heterojunction semiconductor device structure, characterized in that, include: Substrate; A heterostructure layer, wherein the heterostructure layer is any one of the structures in claims 1-3, is located on a portion of the upper surface of the substrate; A gate electrode layer, located on a portion of the surface above the heterostructure layer; A passivation layer covers the gate electrode layer; The source / drain electrode layers are in contact with the heterostructure layer at the bottom and distributed at both ends of the gate electrode layer, wherein the passivation layer separates the source / drain electrode layers from the gate electrode layer.
9. A method for manufacturing a heterojunction semiconductor device structure, characterized in that, include: A first active layer is formed on the substrate; An intermediate structural layer is formed on the upper surface of the first active layer; A second active layer is formed on the upper surface of the intermediate structural layer. The second active layer and the first active layer have different band gaps, so that a heterojunction is formed between the first active layer and the second active layer. The intermediate structural layer can block the diffusion of metal and oxygen elements and has a preset thickness. The thickness and band structure of the intermediate structural layer allow charge carriers to pass through and be transported between the first active layer and the second active layer. The intermediate structural layer is: aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.