Enhanced high electron mobility transistor power devices and their fabrication methods

Abstract

This invention discloses an enhanced high electron mobility transistor (HEMT) power device and its fabrication method. The device comprises, from bottom to top, a substrate, a pre-lay layer, a nucleation layer, a gradient layer, a high-resistivity layer, a channel layer, a barrier layer, and a P-type layer. A source and drain are formed on the barrier layer, and a gate is formed on the P-type layer. Passivation layers are disposed on the barrier layers between the source and the P-type layer, and between the drain and the P-type layer, respectively. The P-type layer comprises an InGaN superlattice and an AlGaN superlattice stacked on top of the InGaN superlattice. This invention can simultaneously achieve multiple process objectives, including improving material crystal quality, increasing hole injection efficiency, and enhancing device saturation current, threshold voltage, and reliability. It effectively improves the activation efficiency of acceptor doping and increases the hole carrier concentration of the P-type layer material. Correspondingly, it can also reduce the acceptor doping concentration and decrease the impurity scattering mechanism affecting hole carriers.

Description

Technical Field

[0001] This invention relates to a semiconductor power device and its fabrication method, and more particularly to an enhancement-mode high electron mobility transistor power device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) materials possess advantages such as a wide bandgap, high breakdown field strength, and high electron saturation velocity. The strong polarization effect of its heterostructure can form a two-dimensional electron gas (2DEG) with high electron concentration and high mobility. This makes GaN-based materials ideal for fabricating high electron mobility transistor (HEMT) power switching devices with high power density, low on-resistance, and high operating frequency characteristics, showing great promise in applications such as consumer fast charging, new energy vehicles, and data centers. To achieve fail-safety, system stability, and reduced circuit complexity, researchers are dedicated to developing enhancement-mode (normally off) power switching devices. Currently, the main technical routes for realizing enhancement-mode HEMT power devices include grooved gate, thin barrier, fluoride ion implantation, and P-type gate, but each has its own drawbacks. For example, etching damage in the grooved gate process reduces the electron mobility of the gate channel; thin barrier devices have a lower threshold voltage, and insufficient 2DEG affects the device's saturation current and on-state resistance; fluoride ion treatment technology has high-temperature reliability issues.

[0003] Compared to other technologies, the P-type gate structure offers advantages such as simple drive design, outstanding high-frequency performance, and good device consistency, making it the mainstream design for GaN-based enhancement-mode power devices. However, the monolayer P-type GaN (P-GaN) material used in traditional P-type gate technology has a high Mg acceptor activation energy and readily forms Mg-H complexes, resulting in low hole carrier concentration and threshold voltage. Increasing the Mg doping concentration to improve hole concentration leads to crystal quality issues in P-GaN materials, such as point defects, inverted triangles, or trapezoidal defects. Furthermore, high Mg concentrations can diffuse into the HEMT barrier layer and channel layer, forming carrier traps and leakage channels, reducing the reliability of HEMT devices. Therefore, the aforementioned problems with using monolayer P-GaN as the gate structure material for power devices are significant factors limiting the performance of HEMT devices. Summary of the Invention

[0004] Objective of the invention: The objective of this invention is to provide an enhanced high electron mobility transistor power device that increases hole injection efficiency and enhances device saturation current, threshold voltage, and reliability; another objective of this invention is to provide a method for fabricating an enhanced high electron mobility transistor power device.

[0005] Technical solution: The enhanced high electron mobility transistor power device of the present invention includes a substrate, a pre-laying layer, a nucleation layer, a gradient layer, a high-resistance layer, a channel layer, a barrier layer, and a P-type layer stacked in sequence from bottom to top. Source and drain electrodes are formed on the barrier layer, and a gate electrode is formed on the P-type layer. Passivation layers are provided on the barrier layer between the source electrode and the P-type layer and between the drain electrode and the P-type layer respectively; the P-type layer includes an InGaN superlattice and an AlGaN superlattice stacked on the InGaN superlattice.

[0006] Further, the InGaN superlattice includes periodically overlapping InGaN barrier layers and InGaN well layers. Among them, the In alloy component of the InGaN barrier layer is lower than that of the well layer, and the thicknesses of both the barrier layer and the well layer are greater than or equal to 0.1 nm.

[0007] Furthermore, in the InGaN barrier layer: 0 ≤ In alloy content < 100%; in the InGaN well layer: 0 < In alloy content ≤ 100%.

[0008] Further, the AlGaN superlattice includes periodically overlapping AlGaN barrier layers and AlGaN well layers. Among them, the Al alloy component of the AlGaN barrier layer is higher than that of the AlGaN well layer, and the AlGaN well layer is an acceptor-doped layer. The thicknesses of both the barrier layer and the well layer are greater than or equal to 0.1 nm.

[0009] Furthermore, in the AlGaN barrier layer: 0 < Al alloy content ≤ 100%; in the AlGaN well layer: 0 ≤ Al alloy content < 100%.

[0010] Further, the alloy component ratio of the P-type layer is Al / In = 4.7, so that the lattice constant of the composite superlattice reaches a high match with the in-plane lattice constant of the GaN channel layer material.

[0011] Furthermore, the hole carrier mobility of the P-type layer is not less than 1 cm 2 V -1 S -1 and the hole carrier concentration is not less than 1×10[[ID=XX]] 17 / cm 3 .

[0012] Further, the substrate is a silicon substrate, the pre-laying layer is an Al pre-laying layer, the nucleation layer is an AlN nucleation layer, the gradient layer is an AlGaN gradient layer, the high-resistance layer is a GaN high-resistance layer, the channel layer is a GaN channel layer, the barrier layer is an AlGaN barrier layer, and the passivation layer is a SiN passivation layer.

[0013] On the other hand, the above-mentioned method for fabricating enhanced high electron mobility transistor power devices includes growing a substrate, a pre-lay layer, a nucleation layer, a gradient layer, a high-resistivity layer, a channel layer, a barrier layer, and a P-type layer sequentially from bottom to top; fabricating a source electrode and a drain electrode on the barrier layer; fabricating a gate electrode on the P-type layer; and etching the P-type layer outside the gate region.

[0014] Specifically, firstly, in an MOCVD reaction chamber environment with a pressure range of 50–500 mbar and a temperature range of 800–1500 °C, a silicon substrate is treated with NH3; then, an Al pre-lay layer is epitaxially grown at a temperature range of 400–800 °C with a thickness between 1 nm and 1 mm; an AlN nucleation layer is epitaxially grown at a temperature range of 400–1500 °C with a thickness between 1 nm and 1 mm; an AlGaN graded layer is epitaxially grown at a temperature range of 600–1500 °C with a thickness between 1 nm and 1 mm; and a GaN high-resistivity layer is epitaxially grown at a temperature range of 600–1200 °C with a thickness between 1 nm and 10 mm, and a carbon doping concentration of 1 × 10⁻⁶. 15 / cm 3 ~1×10 22 / cm 3 Epitaxial growth of GaN channel layer at a temperature range of 800–1200℃ and a thickness of 1 nm–10 mm; epitaxial growth of AlGaN barrier layer at a temperature range of 800–1500℃ and a thickness of 1 nm–1 mm.

[0015] Secondly, an InGaN superlattice is epitaxially grown, wherein the In alloy composition of the barrier layer is lower than that of the well layer, the temperature range is 400–900℃, and the thickness of both the InGaN barrier layer and the InGaN well layer is greater than or equal to 0.1 nm. An AlGaN superlattice is then epitaxially grown, using Mg acceptors to dope only the AlGaN well layer, with a doping concentration of 1 × 10⁻⁶. 15 / cm 3 ~1×10 21 / cm 3 The temperature range is 500 to 1000℃, and the thickness of both the AlGaN barrier layer and the AlGaN well layer is greater than or equal to 0.1 nm.

[0016] Finally, the composite superlattice outside the gate region is completely etched using photolithography and etching processes; a silicon nitride thin film passivation layer is prepared on the surface using plasma-enhanced chemical vapor deposition at a temperature range of 500–900 °C with a thickness of 10 nm–1000 nm; Ti / Al / Ni / Au metal is deposited using photolithography and electron beam evaporation processes with a thickness of 10 nm–1000 nm, and rapid thermal annealing is performed at 500–900 °C under nitrogen for 10–100 seconds to form the source and drain ohmic electrodes; Ni / Au (or Ti, Pd) gate contact metal is deposited using photolithography and electron beam evaporation processes with a thickness of 10 nm–1000 nm, completing the fabrication of the HEMT device.

[0017] Furthermore, the method for preparing the P-type layer includes periodically overlapping InGaN barrier layers and InGaN well layers to obtain an InGaN superlattice structure; and periodically overlapping AlGaN barrier layers and AlGaN well layers on the InGaN superlattice structure to obtain a P-type layer.

[0018] Furthermore, InGaN barrier layers and InGaN well layers are periodically overlapped and grown using molecular beam epitaxy or compound chemical vapor deposition; AlGaN barrier layers and AlGaN well layers are periodically overlapped and grown using molecular beam epitaxy or compound chemical vapor deposition.

[0019] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0020] (1) Effectively improves the activation efficiency of acceptor doping and increases the hole carrier concentration of the P-type layer material; correspondingly, it can also reduce the acceptor doping concentration and reduce the impurity scattering mechanism of hole carriers.

[0021] (2) Enhance the public transport of hole carriers in the superlattice and improve the hole carrier injection efficiency. By controlling the thickness of the periodic sublayers of the superlattice structure, the quantum bound energy levels in each layer are coupled to form a subband structure. This ensures that more holes are injected into the conductive channel of the device during operation, and an equal amount of electrons are generated in the conductive channel through conductivity modulation, thereby increasing the saturation operating current of the device.

[0022] (3) Improve the reliability of HEMT devices. The InGaN superlattice introduces negative polarization charge at the interface with its device barrier layer, which improves the conduction band at the AlGaN / GaN heterojunction interface, increases the threshold turn-on voltage of the device, and further realizes enhanced device operating characteristics. The InGaN superlattice can also prevent Mg from diffusing into the device barrier layer and channel layer, avoiding the formation of carrier traps and leakage channels.

[0023] (4) The lattice constant of the composite superlattice is highly matched with the lattice constant in the GaN channel layer, which can effectively reduce dislocation defects, significantly improve the crystal quality of the material, thereby improving the gate hysteresis phenomenon and suppressing the current collapse effect. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the present invention;

[0025] Figure 2 This is a schematic diagram of the AlGaN superlattice and InGaN composite superlattice structure in the P-type layer of the present invention;

[0026] In the figure, 1. Substrate; 2. Pre-lay layer; 3. Nucleation layer; 4. Gradient layer; 5. High resistivity layer; 6. Channel layer; 7. Barrier layer; 8. P-type layer; 81. InGaN superlattice; 8101. InGaN barrier layer; 8102. InGaN well layer; 82. AlGaN superlattice; 8201. AlGaN barrier layer; 8202. AlGaN well layer; 9. Source; 10. Drain; 11. Gate; 12. Passivation layer. Detailed Implementation

[0027] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0028] Example 1

[0029] like Figure 1 As shown, the enhanced high electron mobility transistor power device of the present invention includes a substrate 1, a pre-lay layer 2, a nucleation layer 3, a gradient layer 4, a high resistivity layer 5, a channel layer 6, a barrier layer 7, a P-type layer 8, a source 9, a drain 10, a gate 11, and a passivation layer 12. The substrate 1, the pre-lay layer 2, the nucleation layer 3, the gradient layer 4, the high resistivity layer 5, the channel layer 6, the barrier layer 7, and the P-type layer 8 are stacked sequentially from bottom to top. The source 9, the drain 10, and the passivation layer 12 are disposed on the barrier layer 7. The passivation layer 12 is disposed between the source 9 and the P-type layer 8, and between the drain 10 and the P-type layer 8, respectively. The gate 11 is disposed on the P-type layer 8.

[0030] Specifically, substrate 1 is a silicon substrate, pre-lay layer 2 is an Al pre-lay layer, nucleation layer 3 is an AlN nucleation layer, gradient layer 4 is an AlGaN gradient layer, high-resistivity layer 5 is a GaN high-resistivity layer, channel layer 6 is a GaN channel layer, barrier layer 7 is an AlGaN barrier layer, and passivation layer 12 is a SiN passivation layer. The thicknesses of each layer are as follows: GaN high-resistivity layer thickness is 1 nm to 1 mm, preferably 3 μm; GaN channel layer thickness is 1 nm to 1 mm, preferably 200 nm; AlGaN barrier layer thickness is 1 nm to 1 mm, preferably 20 nm; and SiN passivation layer thickness is 1 nm to 1 mm, preferably 200 nm.

[0031] like Figure 2 As shown, the P-type layer 8 includes an InGaN superlattice 81 and an AlGaN superlattice 82, where the AlGaN superlattice 82 is stacked on the InGaN superlattice 81. The AlGaN superlattice 82 includes periodically overlapping AlGaN barrier layers 8201 and AlGaN well layers 8202. Among them, the InGaN superlattice 81 includes periodically overlapping InGaN barrier layers 8101 and InGaN well layers 8102. Among them, the In alloy component of the InGaN barrier layer 8101 is lower than that of the well layer. Specifically, in the InGaN barrier layer 8101: 0 ≤ In alloy content < 100%; in the InGaN well layer 8102: 0 < In alloy content ≤ 100%; the thicknesses of both the InGaN barrier layer 8101 and the InGaN well layer 8102 are greater than or equal to 0.1 nm. The Al alloy component of the AlGaN barrier layer 8201 is higher than that of the AlGaN well layer 8202, and the AlGaN well layer 8202 is an acceptor-doped layer. Specifically, in the AlGaN barrier layer 8201: 0 < Al alloy content ≤ 100%; in the AlGaN well layer 8202: 0 ≤ Al alloy content < 100%; the thicknesses of both the AlGaN barrier layer 8201 and the AlGaN well layer 8202 are greater than or equal to 0.1 nm.

[0032] The alloy component ratio of the P-type layer 8 is Al / In = 4.7, and the hole carrier mobility is not less than 1 cm' 2 V -1 S -1 and the hole carrier concentration is not less than 1×10 17 / cm 3 .

[0033] According to the first principle of elasticity, each layer of the superlattice with nanoscale thickness in the P-type layer 8 is in a completely strained state. There is a piezoelectric polarization electric field caused by lattice mismatch between the AlGaN barrier layer and the AlGaN well layer, which can effectively reduce the activation energy of acceptor doping, thereby effectively improving the activation efficiency of acceptors and the hole carrier concentration in the P-type layer. Correspondingly, the reduction of acceptor doping concentration can also weaken the impurity scattering mechanism suffered by hole carriers. The quantized bound energy levels in the periodic sub-layers of the superlattice structure can be coupled to form a sub-band structure, enhancing the delocalized transport of hole carriers in the superlattice, improving the injection efficiency of hole carriers, ensuring that more holes are injected into the device conduction channel under the working state, and generating an equal amount of electrons through the conductance modulation effect, thereby increasing the saturation working current of the device.

[0034] Secondly, the InGaN superlattice introduces negative polarization charge at the interface with its device barrier layer, increasing the conduction band at the AlGaN / GaN heterojunction interface and raising the threshold turn-on voltage of the device, thus achieving enhanced device operating characteristics. The InGaN superlattice also prevents acceptors from diffusing into the device barrier layer and channel layer, avoiding the formation of carrier traps and leakage channels, thereby improving the reliability of HEMT devices.

[0035] Finally, AlGaN and InGaN superlattices were used to construct Al x In y Ga 1-x-y The in-plane lattice constant of N material lies between that of AlGaN and InGaN superlattices, and satisfies Vegard's law:

[0036]

[0037] When the Al / In alloy composition ratio x / y = 4.7, Al x In y Ga 1-x-y The lattice constant of the N material is highly matched with the lattice constant of the GaN channel layer, which can effectively reduce dislocation defects, significantly improve the crystal quality of the material, thereby improving the gate hysteresis phenomenon and suppressing the current collapse effect.

[0038] Example 2

[0039] The method for fabricating an enhanced high electron mobility transistor power device according to the present invention includes the following steps:

[0040] (1) First, in an MOCVD reaction chamber environment with a pressure range of 50 mbar and a temperature range of 800 °C, the silicon substrate was treated with NH3 for 10 minutes.

[0041] (2) Epitaxial growth of Al pre-lay layer at a temperature range of 400℃ and a thickness of 1nm;

[0042] (3) Epitaxial growth of AlN nucleation layer at a temperature range of 400℃ and a thickness of 1nm;

[0043] (4) Epitaxial growth of AlGaN graded layers, with a temperature range of 600°C and a thickness of 1 nm;

[0044] (5) Epitaxial growth of a GaN high-resistivity layer at a temperature range of 600°C, a thickness of 1 nm, and a carbon doping concentration of 1 × 10⁻⁶. 15 / cm 3 ;

[0045] (6) Epitaxial growth of GaN channel layer at a temperature range of 800℃ and a thickness of 1nm;

[0046] (7) Epitaxial growth of AlGaN barrier layer at a temperature range of 800℃ and a thickness of 1nm;

[0047] (8) An InGaN superlattice is grown on an epitaxial layer, wherein the In alloy composition of the barrier layer is lower than that of the well layer, the temperature range is 400℃, the thickness of the InGaN barrier layer and the InGaN well layer is 1nm, and the In composition is 10% and 20%, respectively.

[0048] (9) Epitaxial growth of AlGaN superlattice, using Mg acceptors to dope only the AlGaN well layer, with a doping concentration of 1×10⁻⁶. 21 / cm 3 The temperature range is 500℃, and the thickness of both the AlGaN barrier layer and the AlGaN well layer is 1nm; the Al composition is 60% and 81%, respectively.

[0049] (10) The composite superlattice outside the gate region is completely etched using photolithography and etching processes;

[0050] (11) A silicon nitride thin film passivation layer was prepared on the surface by plasma-enhanced chemical vapor deposition, with a temperature range of 500℃ and a thickness of 10nm.

[0051] (12) Deposit Ti / Al / Ni / Au metal using photolithography and electron beam evaporation processes, with a total thickness of 10nm, and perform rapid thermal annealing for 100 seconds under nitrogen at 500℃ to form source and drain ohmic electrodes.

[0052] (13) Ni / Au (or Ti, Pd) gate contact metal was deposited using photolithography and electron beam evaporation processes, with a total thickness of 10 nm, to complete the fabrication of HEMT devices.

[0053] Example 3

[0054] The method for fabricating an enhanced high electron mobility transistor power device according to the present invention includes the following steps:

[0055] (1) First, in an MOCVD reaction chamber environment with a pressure range of 1500 mbar and a temperature range of 1500 °C, the silicon substrate was treated with NH3 for 10 minutes.

[0056] (2) Epitaxial growth of Al pre-lay layer at a temperature range of 1000℃ and a thickness of 1mm;

[0057] (3) Epitaxial growth of AlN nucleation layer at a temperature range of 1500℃ and a thickness of 1mm;

[0058] (4) Epitaxial growth of AlGaN graded layers at a temperature range of 1500℃ and a thickness of 1mm;

[0059] (5) Epitaxial growth of a GaN high-resistivity layer at a temperature range of 1200℃, a thickness of 10mm, and a carbon doping concentration of 1×10⁻⁶. 22 / cm 3 ;

[0060] (6) Epitaxial growth of GaN channel layer at a temperature range of 1200℃ and a thickness of 10mm;

[0061] (7) Epitaxial growth of AlGaN barrier layer at a temperature range of 1500℃ and a thickness of 1mm;

[0062] (8) An InGaN superlattice is grown on an epitaxial layer, wherein the In alloy composition of the barrier layer is lower than that of the well layer, the temperature range is 900℃, the thickness of the InGaN barrier layer and the InGaN well layer is 100μm, and the In composition is 10% and 20%, respectively.

[0063] (9) Epitaxial growth of AlGaN superlattice, using Mg acceptors to dope only the AlGaN well layer, with a doping concentration of 1×10⁻⁶. 21 / cm 3 The temperature range is 1000℃, and the thickness of both the AlGaN barrier layer and the AlGaN well layer is 100μm; the Al composition is 60% and 81%, respectively.

[0064] (10) The composite superlattice outside the gate region is completely etched using photolithography and etching processes;

[0065] (11) A silicon nitride thin film passivation layer was prepared on the surface by plasma-enhanced chemical vapor deposition, with a temperature range of 900℃ and a thickness of 1000nm;

[0066] (12) Deposit Ti / Al / Ni / Au metal using photolithography and electron beam evaporation processes, with a total thickness of 1000nm, and perform rapid thermal annealing for 10 seconds under nitrogen at 900℃ to form source and drain ohmic electrodes.

[0067] (13) Ni / Au (or Ti, Pd) gate contact metal was deposited using photolithography and electron beam evaporation processes, with a total thickness of 1000 nm, to complete the fabrication of HEMT devices.

[0068] Example 4

[0069] The method for fabricating an enhanced high electron mobility transistor power device according to the present invention includes the following steps:

[0070] (1) First, in the MOCVD reaction chamber environment with a pressure of 100mbar and a temperature of 1000℃, the silicon substrate was treated with NH3 for 10 minutes.

[0071] (2) Epitaxial growth of Al pre-lay at 800℃ with a thickness of 30nm;

[0072] (3) Epitaxial growth of AlN nucleation layer at 1050℃ with a thickness of 250nm;

[0073] (4) Epitaxial growth of AlGaN graded layer at 1100℃ with a thickness of 500nm;

[0074] (5) Epitaxial growth of a GaN high-resistivity layer at 1000℃ with a thickness of 3μm and a carbon doping concentration of 1×10⁻⁶. 18 / cm 3 ;

[0075] (6) Epitaxial growth of GaN channel layer at 1000℃ with a thickness of 200nm;

[0076] (7) Epitaxial growth of AlGaN barrier layer at 1000℃ with a thickness of 20nm;

[0077] (8) An InGaN superlattice is grown on an epitaxial layer, wherein the In alloy composition of the barrier layer is lower than that of the well layer, the temperature range is 600℃, the thickness of the InGaN barrier layer and the InGaN well layer is 10nm, and the In composition is 10% and 20%, respectively.

[0078] (9) Epitaxial growth of AlGaN superlattice, using Mg acceptors to dope only the AlGaN well layer, with a doping concentration of 1×10⁻⁶. 19 / cm 3 The temperature range is 600℃, the thickness of the AlGaN barrier layer and the AlGaN well layer is 10nm, and the Al composition is 60% and 81%, respectively.

[0079] (10) The composite superlattice outside the gate region is completely etched using photolithography and etching processes;

[0080] (11) A silicon nitride thin film passivation layer was prepared on the surface by plasma-enhanced chemical vapor deposition at a temperature of 350℃ and a thickness of 200nm.

[0081] (12) Ti / Al / Ni / Au metal was deposited using photolithography and electron beam evaporation processes, with a total thickness of 350nm. The metal was then rapidly annealed for 30 seconds under nitrogen at 500℃ to form source and drain ohmic electrodes.

[0082] (13) Ni / Au (or Ti, Pd) gate contact metal was deposited using photolithography and electron beam evaporation processes, with a total thickness of 200 nm, to complete the fabrication of HEMT devices.

[0083] The composite superlattice structure P-type gate material was prepared using a metal-organic chemical vapor deposition (MOCVD) system. Trimethylgallium, trimethylaluminum, and trimethylindium were used as metal-organic growth sources of gallium, aluminum, and indium, respectively, during the MOCVD growth process, and ammonia was used as the nitrogen source.

[0084] This invention can replace the traditional P-type layer material fabrication method for enhanced high electron mobility transistors (HEMTs). The composite superlattice structure P-type layer material that matches the device channel layer lattice can significantly improve the material crystal quality, while also suppressing current collapse effect, increasing hole injection efficiency, enhancing device saturation current and threshold voltage, and improving the performance and reliability of HEMT devices, among other things.

Claims

1. An enhancement-mode high electron mobility transistor power device, characterized in that, The device includes a substrate (1), a pre-deposition layer (2), a nucleation layer (3), a graded layer (4), a high-resistance layer (5), a channel layer (6), a barrier layer (7), and a P-type layer (8) stacked in sequence from bottom to top. Source electrodes (9) and drain electrodes (10) are formed on the barrier layer (7), and a gate electrode (11) is formed on the P-type layer (8). Passivation layers (12) are provided on the barrier layer (7) between the source electrode (9) and the P-type layer (8) and between the drain electrode (10) and the P-type layer (8), respectively; the P-type layer (8) includes an InGaN superlattice (81) and an AlGaN superlattice (82) stacked on the InGaN superlattice (81); the InGaN superlattice (81) includes periodically overlapping InGaN barrier layers (8101) and InGaN well layers (8102); the AlGaN superlattice (82) includes periodically overlapping AlGaN barrier layers (8201) and AlGaN well layers (8202).

2. The enhanced high electron mobility transistor power device according to claim 1, characterized in that, The In alloy composition of the InGaN barrier layer (8101) is lower than that of the well layer, and the thicknesses of both the barrier layer and the well layer are greater than or equal to 0.1 nm.

3. The enhanced high electron mobility transistor power device according to claim 2, characterized in that, In the InGaN barrier layer (8101): 0 ≤ In alloy content < 100%; in the InGaN well layer (8102): 0 < In alloy content ≤ 100%.

4. The enhanced high electron mobility transistor power device according to claim 1, characterized in that, The Al alloy composition of the AlGaN barrier layer (8201) is higher than that of the AlGaN well layer (8202), and the AlGaN well layer (8202) is an acceptor-doped layer. The thicknesses of both the barrier layer and the well layer are greater than or equal to 0.1 nm.

5. The enhanced high electron mobility transistor power device according to claim 4, characterized in that, In the AlGaN barrier layer (8201): 0 < Al alloy content ≤ 100%; in the AlGaN well layer (8202): 0 ≤ Al alloy content < 100%.

6. The enhanced high electron mobility transistor power device according to claim 1, characterized in that, The alloy composition ratio of the P-type layer (8) is Al / In = 4.7, so that the lattice constant of the composite superlattice reaches a match with the in-plane lattice constant of the GaN channel layer (6) material 7. The enhanced high electron mobility transistor power device according to claim 1, characterized in that, The hole carrier mobility of the P-type layer (8) is not less than 1 cm⁻¹. 2 V -1 S -1 Hole carrier concentration not less than 1×10 17 / cm 3 .

8. The enhanced high electron mobility transistor power device according to claim 1, characterized in that, The substrate (1) is a silicon substrate, the pre-deposition layer (2) is an Al pre-deposition layer, the nucleation layer (3) is an AlN nucleation layer, the graded layer (l4) is an AlGaN graded layer, the high-resistance layer (5) is a GaN high-resistance layer, the channel layer (6) is a GaN channel layer, the barrier layer (7) is an AlGaN barrier layer, and the passivation layer (12) is a SiN passivation layer.

9. A method for fabricating an enhanced high electron mobility transistor power device according to any one of claims 1-8, characterized in that, It includes growing the substrate, the pre-deposition layer, the nucleation layer, the graded layer, the high-resistance layer, the channel layer, the barrier layer, and the P-type layer in sequence from bottom to top; preparing source electrodes and drain electrodes on the barrier layer respectively; preparing a gate electrode on the P-type layer; etching the P-type layer outside the gate region.

10. The method for fabricating an enhanced high electron mobility transistor power device according to claim 9, characterized in that, The preparation method of the P-type layer includes periodically overlapping and growing InGaN barrier layers and InGaN well layers by molecular beam epitaxy or chemical vapor deposition of compounds to obtain an InGaN superlattice structure; and periodically overlapping and growing AlGaN barrier layers and AlGaN well layers on the InGaN superlattice structure by molecular beam epitaxy or chemical vapor deposition of compounds to obtain the P-type layer.

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