A gate-all-around transistor and a method for manufacturing the same

Abstract

The present invention discloses a ring-gate transistor and a method for manufacturing the same, which relates to the field of semiconductor technology and is used to improve the leakage of the parasitic channel in the ring-gate transistor and enhance the conductive performance of the ring-gate transistor. The ring-gate transistor comprises: a substrate, a stacked structure formed on the substrate, a germanium-containing semiconductor structure formed between the substrate and the stacked structure, and a gate stack surrounding the periphery of at least one layer of nanosheets. The stacked structure comprises a source region, a drain region, and at least one layer of nanosheets. The at least one layer of nanosheets is located between the source region and the drain region, and the at least one layer of nanosheets is in contact with the source region and the drain region, respectively. The width of the germanium-containing semiconductor structure is smaller than the width of the at least one layer of nanosheets. The germanium content in the germanium-containing semiconductor structure is higher than the germanium content in the at least one layer of nanosheets. There is a gap between the at least one layer of nanosheets and the germanium-containing semiconductor structure. The method for manufacturing the ring-gate transistor is used to manufacture the above-mentioned ring-gate transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate-all-around transistor and a manufacturing method thereof. Background Art

[0002] Compared with fin field-effect transistors, the gate-all-around transistor has a gate stack formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, thereby suppressing the short channel effect and enhancing the gate control capability of the gate-all-around transistor.

[0003] However, in the case where the channel of the all-around gate transistor includes at least one layer of nanosheets, it is difficult to suppress leakage of the parasitic channel in the all-around gate transistor using existing manufacturing methods, thereby reducing the operating performance of the all-around gate transistor. Summary of the Invention

[0004] The object of the present invention is to provide a ring-gate transistor and a manufacturing method thereof, which are used to improve the leakage of the parasitic channel in the ring-gate transistor and enhance the conductive performance of the ring-gate transistor.

[0005] In order to achieve the above object, the present invention provides a gate-all-around transistor, which includes:

[0006] substrate,

[0007] A stacked structure is formed on a substrate. The stacked structure includes a source region, a drain region, and at least one layer of nanosheets. The at least one layer of nanosheets is located between the source region and the drain region, and the at least one layer of nanosheets is in contact with the source region and the drain region, respectively.

[0008] A germanium-containing semiconductor structure is formed between the substrate and the stacked structure. The width of the germanium-containing semiconductor structure is smaller than the width of the at least one nanosheet. The germanium content in the germanium-containing semiconductor structure is higher than the germanium content in the at least one nanosheet. A gap is formed between the at least one nanosheet and the germanium-containing semiconductor structure.

[0009] and a gate stack surrounding the periphery of at least one nanosheet.

[0010] Compared with the prior art, in the ring-gate transistor provided by the present invention, a germanium-containing semiconductor structure is formed between the substrate and the stack structure. Moreover, the width of the germanium-containing semiconductor structure is smaller than the width of the nanosheet. Based on this, under the condition that other specification factors are the same, compared with the bottom of the gate stack included in the ring-gate transistor in the prior art being in contact with a parasitic channel having a width equal to the width of the nanosheet, the effective contact width between the bottom of the gate stack included in the ring-gate transistor provided by the present invention and the germanium-containing semiconductor structure is smaller. In the above case, when the ring-gate transistor is in a working state, the path width of the carriers that can be formed in the germanium-containing semiconductor structure under the gate control action of the gate stack is smaller, thereby significantly reducing the leakage current of the source region and the drain region through the germanium-containing semiconductor structure, that is, the leakage of the parasitic channel in the ring-gate transistor can be improved, thereby improving the conductivity of the ring-gate transistor.

[0011] Furthermore, the germanium content in the germanium-containing semiconductor structure is higher than the germanium content in at least one layer of the nanosheet. Based on this, during the manufacturing process of the all-around gate transistor provided by the present invention, an etchant that only etches the germanium-containing semiconductor structure can be selected based on the difference in germanium content between the germanium-containing semiconductor structure and the nanosheet. This allows for selective etching of only the two sides of the germanium-containing semiconductor layer used to manufacture the germanium-containing semiconductor structure along the width direction, without affecting the channel layer used to manufacture the nanosheet. This improves the yield of the all-around gate transistor while reducing the manufacturing difficulty of the all-around gate transistor.

[0012] The present invention also provides a method for manufacturing a gate-all-around transistor, the method comprising:

[0013] A substrate is provided.

[0014] A stacked structure and a germanium-containing semiconductor structure are provided on a substrate. The stacked structure includes a source region, a drain region, and at least one nanosheet. The at least one nanosheet is located between the source region and the drain region, and the at least one nanosheet is in contact with each of the source region and the drain region. The germanium-containing semiconductor structure is located between the substrate and the stacked structure. The width of the germanium-containing semiconductor structure is smaller than the width of the at least one nanosheet. The germanium content in the germanium-containing semiconductor structure is higher than the germanium content in the at least one nanosheet. A gap is defined between the at least one nanosheet and the germanium-containing semiconductor structure.

[0015] A gate stack is formed around the periphery of at least one nanosheet.

[0016] Compared with the prior art, the method for manufacturing the ring-gate transistor provided by the present invention has the same beneficial effects as the ring-gate transistor provided by the present invention, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0018] Figure 1 Part (1) is a schematic diagram of the structure after the first fin structure and the barrier layer on the substrate; Figure 1 Part (2) is a cross-sectional view of the structure after the fin field effect transistor is formed on the substrate;

[0019] Figure 2 Part (1) is a cross-sectional view of the structure after the second fin structure is processed by the anti-punch-through injection process; Figure 2 Part (2) is a cross-sectional view of the structure after forming a ring-gate transistor based on the second fin structure;

[0020] Figure 3 Schematic diagram of a structure after sequentially forming a germanium-containing semiconductor layer and at least one stacked film layer on a substrate in an embodiment of the present invention;

[0021] Figure 4 Schematic diagram of the structure after the fin-shaped structure is formed in an embodiment of the present invention;

[0022] Figure 5 Part (1) is a cross-sectional view of the structure along the BB' direction of the rear fin-shaped structure in an embodiment of the present invention; Figure 5 Parts (2) and (3) are two structural cross-sectional views along the A-A' direction after the fin-shaped structure is formed in an embodiment of the present invention;

[0023] Figure 6 Schematic diagram of the structure after selective oxidation of the germanium-containing semiconductor layer in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of the structure after the oxide layer is removed according to an embodiment of the present invention;

[0025] Figure 8 Parts (1) and (2) are schematic diagrams of two structures after selective etching of the germanium-containing semiconductor layer in an embodiment of the present invention;

[0026] Figure 9 Schematic diagram of the structure after the shallow trench isolation structure is formed in an embodiment of the present invention;

[0027] Figure 10 Parts (1) and (2) are cross-sectional views of the structure along the BB' direction and along the AA' direction after forming the sacrificial gate and the sidewall in the embodiment of the present invention, respectively;

[0028] Figure 11It is a cross-sectional view of the structure along the BB' direction after the source region and the drain region are formed in an embodiment of the present invention;

[0029] Figure 12 A cross-sectional view of the structure along the BB' direction after the dielectric layer is formed in an embodiment of the present invention;

[0030] Figure 13 This is a schematic diagram of the structure after removing the sacrificial gate in an embodiment of the present invention;

[0031] Figure 14 Parts (1) and (2) are cross-sectional views of a structure after nanosheets are formed along the BB' direction and the AA' direction, respectively;

[0032] Figure 15 Parts (1) and (2) are cross-sectional views of another structure after nanosheets are formed in an embodiment of the present invention along the BB' direction and along the AA' direction, respectively;

[0033] Figure 16 Parts (1) and (2) are respectively cross-sectional views of the structures of two ring-gate transistors along the A-A' direction provided by the embodiments of the present invention.

[0034] Figure 17 A flow chart of a method for manufacturing a gate-all-around transistor provided in an embodiment of the present invention.

[0035] Figure numerals: 11 is a substrate, 12 is a fin-shaped structure, 121 is a germanium-containing semiconductor layer, 122 is a stacked layer, 1221 is a sacrificial layer, 1222 is a channel layer, 13 is an oxide layer, 14 is a shallow trench isolation structure, 15 is a fin, 151 is a source formation region, 152 is a drain formation region, 153 is a transition region, 16 is a sacrificial gate, 17 is a sidewall, 18 is a source region, 19 is a drain region, 20 is a dielectric layer, 21 is a nanosheet, 22 is a germanium-containing semiconductor structure, 221 is a first semiconductor portion, 222 is a second semiconductor portion, 23 is a gate stack, 231 is a gate dielectric layer, 232 is a gate, 24 is a first fin-shaped structure, 25 is a barrier layer, 26 is a second fin structure, and 27 is a central region. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0037] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0038] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0040] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0041] The first fin structure and shallow trench isolation structure of the fin field effect transistor are formed on the substrate. The portion of the first fin structure exposed outside the shallow trench isolation structure is the fin. The portion of the fin surrounded by the gate stack structure corresponds to the channel of the fin field effect transistor. In this case, when the fin field effect is in operation, the channel is controlled by the gate stack structure, thereby enabling conduction between the source region and the drain region. The portion of the first fin structure surrounded by the shallow trench isolation structure is separated from the gate stack structure by the shallow trench isolation structure, making this portion away from the control of the gate stack structure, making it easy for the channel punch-through effect to occur, resulting in a parasitic channel.

[0042] like Figure 1 As shown, in order to solve the problem of parasitic channel leakage in the fin field effect transistor, in the process of manufacturing the fin field effect transistor, after the first fin structure 24 and the shallow trench isolation structure 14 are formed on the substrate 11, impurity ions with a conductivity type opposite to that of the impurities doped in the source region and the drain region are injected into at least the first fin structure 24 through an anti-punch-through injection process to form a blocking layer 25 in the middle and lower part of the first fin structure 24, thereby utilizing the highly doped blocking layer 25 to suppress the parasitic channel.

[0043] With the development of semiconductor technology, ring-gate transistors have emerged. Compared with fin field-effect transistors, the gate-all-around transistor has a gate stack structure formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, thereby enhancing the gate control capability of the ring-gate transistor, suppressing the short channel effect, and making the ring-gate transistor have higher working performance. However, when the channel width of the ring-gate transistor is relatively wide, it is difficult to solve the problem of parasitic channel leakage in the ring-gate transistor by the above-mentioned anti-punch-through injection process. Specifically, as Figure 2 As shown, during the manufacturing process of the all-around gate transistor, the second fin structure 26 formed on the substrate 11 also has a relatively wide channel width. Therefore, when ion impurities are injected into the second fin structure 26 using an anti-punch-through implantation process, the ion impurities have difficulty entering the central region 27 of the second fin structure 26 along its width. That is, the barrier layer 25 is not fully formed in the central region 27 of the second fin structure 26 along its width. In this case, after applying an appropriate voltage to the gate stack 23 of the all-around gate transistor, the source and drain regions are not only able to conduct through the channel, but the central region 27 also suffers from parasitic channel leakage, which in turn reduces the operating performance of the all-around gate transistor.

[0044] To address the above technical issues, embodiments of the present invention provide a gate-all-around transistor and a method for manufacturing the same. In the gate-all-around transistor provided by the embodiments of the present invention, a germanium-containing semiconductor structure is formed between the substrate and the stacked structure. Furthermore, the width of the germanium-containing semiconductor structure is smaller than the width of the nanosheet. This significantly reduces leakage current in the source and drain regions through the germanium-containing semiconductor structure when the gate-all-around transistor is in operation, thereby improving leakage in the parasitic channel of the gate-all-around transistor.

[0045] like Figure 12 and Figure 16 As shown, an embodiment of the present invention provides a ring-gate transistor, which includes: a substrate 11, a stacked structure, a germanium-containing semiconductor structure 22, and a gate stack 23. The stacked structure is formed on the substrate 11. The stacked structure includes a source region 18, a drain region 19, and at least one layer of nanosheets 21. The at least one layer of nanosheets 21 is located between the source region 18 and the drain region 19, and the at least one layer of nanosheets 21 is in contact with the source region 18 and the drain region 19, respectively. The germanium-containing semiconductor structure 22 is formed between the substrate 11 and the stacked structure. The width of the germanium-containing semiconductor structure 22 is smaller than the width of the at least one layer of nanosheets 21. The germanium content in the germanium-containing semiconductor structure 22 is higher than the germanium content in the at least one layer of nanosheets 21. There is a gap between the at least one layer of nanosheets 21 and the germanium-containing semiconductor structure 22. The gate stack 23 surrounds the outer periphery of the at least one layer of nanosheets 21.

[0046] Specifically, the substrate may be any semiconductor substrate such as a silicon substrate, a silicon germanium substrate, or the like.

[0047] In the aforementioned stacked structure, the source and drain regions comprised therein are made of semiconductor materials. The materials of the source and drain regions may be the same or different. For example, the source and drain regions may both be made of silicon, silicon-germanium, or germanium. Another example is the source region may be made of silicon, and the drain region may be made of silicon-germanium.

[0048] The specifications and number of layers of the nanosheets included in the above stacked structure can be set according to actual needs and are not specifically limited here. Figure 16 As shown, the stacked structure may include two layers of nanosheets 21. Furthermore, when the stacked structure includes at least two layers of nanosheets 21, a gap exists between the bottom nanosheet 21 and the germanium-containing semiconductor structure 22. Gaps also exist between adjacent nanosheets 21. The sizes of these two types of gaps can be set based on the specifications of the gate stack 23 and are not specifically limited here. Furthermore, the material of the nanosheets 21 may be silicon, silicon-germanium, germanium, or a Group III-V semiconductor material.

[0049] For the above-mentioned germanium-containing semiconductor structure, the specific position of the germanium-containing semiconductor structure below the stacked structure along the width direction of the germanium-containing semiconductor structure can be set according to actual needs. Figure 8As shown in part (2) of FIG, the germanium-containing semiconductor structure can be located below the center and to the left of the stacked structure. For example: Figure 8 Part (1) and Figure 16 As shown, the germanium-containing semiconductor structure 22 may be located directly below the stacked structure. Figures 6 to 8 As shown, in the process of manufacturing the ring-gate transistor provided by an embodiment of the present invention, when a germanium-containing semiconductor structure is obtained by selectively etching at least a wider germanium-containing semiconductor layer 121 along the width direction of the nanosheet, compared with the germanium-containing semiconductor structure being offset from the bottom center of the stacked structure, the germanium-containing semiconductor structure being located directly below the stacked structure corresponds to the fact that the selective etching rates of both sides of the germanium-containing semiconductor layer 121 during the above-mentioned selective etching process are equal. Therefore, the germanium-containing semiconductor layer 121 can provide equal supporting forces on both sides of the at least one stacked layer 122 located thereon along the width direction during the above-mentioned selective etching process, which is beneficial to prevent the fin structure 12 including the germanium-containing semiconductor layer 121 and the at least one stacked layer 122 from bending or collapsing during the selective etching process, thereby improving the yield of the ring-gate transistor.

[0050] In addition, the material of the germanium-containing semiconductor structure can be any semiconductor material containing germanium. For example, the material of the germanium-containing semiconductor structure can be germanium silicon or germanium. Specifically, the content of germanium in the germanium-containing semiconductor structure can be determined based on the content of germanium in the nanosheet, and the difference in the germanium content between the two can be set according to actual needs, which is not specifically limited here. For example, the material of the at least one layer of nanosheet can be Si 1-x Ge x , the material of the germanium-containing semiconductor structure can be Si 1-y Ge y . Among them, 0≤x≤1, 0<y≤1, yx≥0.2.

[0051] Furthermore, along the thickness direction of the substrate, the materials of the various parts of the germanium-containing semiconductor structure may be the same or different. Part of the germanium-containing semiconductor structure along the height direction contains germanium, while the rest of the structure may not contain germanium. Specifically, the materials of the various parts of the germanium-containing semiconductor structure along the height direction may be set according to actual needs. For example: Figures 4 to 8 ,as well as Figure 16As shown, during the process of manufacturing the all-around gate transistor, if only the germanium-containing semiconductor layer 121 is etched during the above-mentioned selective etching process, the germanium-containing semiconductor structure 22 only includes the portion of the germanium-containing semiconductor layer 121 that remains after the nanosheets 21 are formed. In this case, along the thickness direction of the substrate 11, the material of each portion of the germanium-containing semiconductor structure 22 is the same. For another example: if during the above-mentioned selective etching process, not only the germanium-containing semiconductor layer is laterally thinned, but also the etched portion of the substrate located below the germanium-containing semiconductor layer is laterally thinned. In this case, along the thickness direction of the substrate, the materials of the upper and lower portions of the germanium-containing semiconductor structure are different.

[0052] It is conceivable that the width of the at least one nanosheet layer mentioned above is different depending on the size of the ring-gate transistor. Accordingly, the specific width of the germanium-containing semiconductor structure whose width is smaller than the nanosheet is also different. In addition, if Figures 6 to 8 ,as well as Figure 16 As shown, the smaller the width of the germanium-containing semiconductor structure 22, the smaller the support force that the germanium-containing semiconductor structure 22 can provide for at least one layer of the stack 122 in the fin structure 12. Correspondingly, the more layers of the stack 122, the wider the germanium-containing semiconductor structure 22 is required to provide support. Therefore, the more layers of nanosheets 21 included in the stacked structure, the smaller the width difference between the germanium-containing semiconductor structure 22 and the nanosheet 21. Based on the above content, the specific width of the germanium-containing semiconductor structure 22, and the difference in width between the germanium-containing semiconductor structure 22 and the nanosheet 21, can be set according to the width and number of layers of the nanosheet 21, as well as actual needs, and are not specifically limited here. Exemplarily, the width of the above-mentioned germanium-containing semiconductor structure 22 can be 5nm to 15nm. Within the above data range, the preferred width of the germanium-containing semiconductor structure 22 is 5nm to 8nm.

[0053] As for the height of each part of the germanium-containing semiconductor structure along the length direction, it can be set according to actual needs. Specifically, the height of the germanium-containing semiconductor structure located in the source region and the drain region, as well as the height of the part located below the nanosheet can be equal or unequal. For example: Figure 14 and Figure 16 As shown in part (1) of FIG, if the etchant for etching the sacrificial layer does not affect the germanium-containing semiconductor layer after selective etching when the portion of the sacrificial layer located in the transition region is removed, then the germanium-containing semiconductor layer after selective etching is the germanium-containing semiconductor structure 22. At this time, the height of the portion of the germanium-containing semiconductor structure 22 located below the source region 18 and the drain region 19 is equal to the height of the portion of the germanium-containing semiconductor structure 22 located below the nanosheet 21. For another example: Figure 15 and Figure 16As shown in part (2) of the figure, if the etchant for etching the sacrificial layer etches the portion of the germanium-containing semiconductor layer that has been selectively etched that is located in the transition region when removing the portion of the sacrificial layer that is located in the transition region, the top of the germanium-containing semiconductor layer that has been selectively etched will be lost. At this time, when the portion of the germanium-containing semiconductor structure 22 that is located below the source region 18 and the drain region 19 is the first semiconductor portion 221, and the portion of the germanium-containing semiconductor structure 22 that is located below at least one layer of nanosheets 21 is the second semiconductor portion 222, the top height of the second semiconductor portion 222 is greater than zero and less than the top height of the first semiconductor portion 221. Specifically, the height difference between the first semiconductor portion 221 and the second semiconductor portion 222 can be determined based on the actual application scenario and is not specifically limited here.

[0054] For the above gate stack, if Figure 16 As shown, the gate stack 23 may include a gate dielectric layer 231 and a gate 232 formed at least on the periphery of the nanosheet 21 through a gap. The gate dielectric layer 231 may also be formed above the substrate 11 and the portion of the germanium-containing semiconductor structure 22 that exposes the gate formation region. Specifically, the material of the gate dielectric layer 231 may be an insulating material with a low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate 232 may be a conductive material such as doped polysilicon, TiN, TaN or TiSiN. The thickness of the gate dielectric layer 231 and the gate 232 may be set according to actual needs and is not specifically limited here.

[0055] In some cases, such as Figures 12 to 16 As shown, the ring-gate transistor provided by the embodiment of the present invention may further include a sidewall 17 and a dielectric layer 20. The dielectric layer 20 covers the substrate 11, and its top is flush with the top of the gate stack 23. It should be understood that in the process of manufacturing the ring-gate transistor provided by the embodiment of the present invention, as shown in FIG. Figures 12 to 16 As shown, the presence of the dielectric layer 20 can protect the source region 18 and the drain region 19 from being affected by operations such as etching and cleaning when etching the sacrificial gate 16 and the portion of the sacrificial layer 1221 located in the transition region 153. Specifically, the material of the above-mentioned dielectric layer 20 can be an insulating material such as SiO2 or SiN. As for the above-mentioned sidewall 17, the sidewall 17 is formed between the dielectric layer 20 and the gate stack 23. The presence of the above-mentioned sidewall 17 facilitates the formation of the gate stack 23 of the ring-gate transistor and isolates the gate stack 23 from the conductive structure formed subsequently. The material of the above-mentioned sidewall 17 is an insulating material. Specifically, the material of the above-mentioned sidewall 17 and the thickness of the sidewall 17 can be designed according to the actual application scenario, and are not specifically limited here.

[0056] From the above content, we can see that if Figure 12 and Figure 16 As shown, in the ring-gate transistor provided by the embodiment of the present invention, a germanium-containing semiconductor structure 22 is formed between the substrate 11 and the stack structure. Moreover, the width of the germanium-containing semiconductor structure 22 is smaller than the width of the nanosheet 21. Based on this, under the condition that other specification factors are the same, compared with the bottom of the gate stack included in the ring-gate transistor in the prior art being in contact with a parasitic channel having a width equal to the width of the nanosheet, the ring-gate transistor provided by the embodiment of the present invention includes a gate stack 23 having a smaller effective contact width with the germanium-containing semiconductor structure 22. In the above case, when the ring-gate transistor is in a working state, the path width of the carriers that can be formed in the germanium-containing semiconductor structure 22 under the gate control action of the gate stack 23 is smaller, so that the leakage current of the source region 18 and the drain region 19 through the germanium-containing semiconductor structure 22 can be significantly reduced, that is, the leakage of the parasitic channel in the ring-gate transistor can be improved, and the conductive performance of the ring-gate transistor can be improved. In addition, as Figures 6 to 8 As shown, the germanium content in the germanium-containing semiconductor structure is higher than the germanium content in at least one layer of the nanosheet. Based on this, during the manufacturing process of the all-around gate transistor provided by the embodiment of the present invention, the difference in germanium content between the germanium-containing semiconductor structure and the nanosheet can be used to select an etchant that only etches the germanium-containing semiconductor structure. This allows selective etching of only the two sides of the germanium-containing semiconductor layer 121 used to manufacture the germanium-containing semiconductor structure along the width direction without affecting the channel layer 1222 used to manufacture the nanosheet. This improves the yield of the all-around gate transistor while reducing the manufacturing difficulty of the all-around gate transistor.

[0057] In one example, the germanium-containing semiconductor structure may be doped with a concentration of 1E17 cm -3 to 5E18cm -3 The doping type of the impurities in the germanium-containing semiconductor structure is opposite to the doping type of the impurities in the source and drain regions, thereby suppressing leakage between the source and drain regions and the germanium-containing semiconductor structure, and further improving the conductivity of the all-around gate transistor.

[0058] Specifically, the doping type of impurities in the above-mentioned germanium-containing semiconductor structure can be determined according to the conductivity type of the ring-gate transistor. For example: when the ring-gate transistor manufactured is an NMOS transistor, the source region and the drain region are doped with N-type impurities (such as phosphorus). At this time, the germanium-containing semiconductor structure is doped with P-type impurities (such as boron). For another example: when the ring-gate transistor manufactured is a PMOS transistor, the source region and the drain region are doped with P-type impurities (such as boron). At this time, the germanium-containing semiconductor structure is doped with N-type impurities (such as phosphorus). In addition, the specific doping concentration of P-type impurities or N-type impurities in the germanium-containing semiconductor structure can be set according to actual needs, and is not specifically limited here.

[0059] It should be noted that the germanium-containing semiconductor structure may not be doped with P-type impurities and N-type impurities.

[0060] In one example, Figure 16 As shown, the above-mentioned ring-gate transistor may further include a shallow trench isolation structure 14. The shallow trench isolation structure 14 is formed on the portion of the substrate 11 exposed outside the germanium-containing semiconductor structure 22. The gate stack 23 is located on the germanium-containing semiconductor structure 22 and the shallow trench isolation structure 14. The top height of the germanium-containing semiconductor structure 22 is less than or equal to the top height of the shallow trench isolation structure 14. It should be understood that when other transistors or conductive structures are also formed on the substrate 11, forming a shallow trench isolation structure 14 on the portion of the substrate 11 exposed outside the germanium-containing semiconductor structure 22 can isolate the ring-gate transistor from the source region 18 or drain region 19 of the other transistors and other conductive structures, avoid electrical connection with each other, and improve the reliability between the ring-gate transistor and other structures formed on the substrate 11.

[0061] Specifically, the shallow trench isolation structure can be made of insulating materials such as SiN, Si3N4, SiO2 or SiCO. The thickness of the shallow trench isolation structure can be set according to actual needs, as long as it can be applied to the all-around gate transistor provided in the embodiment of the present invention.

[0062] like Figure 17 As shown, the embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. Figures 3 to 16 The manufacturing process is described by referring to a perspective view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the ring-gate transistor includes:

[0063] First, a substrate is provided. Specific materials of the substrate can be referred to above and will not be described in detail here.

[0064] like Figures 3 to 15 As shown, a stacked structure and a germanium-containing semiconductor structure 22 are provided on a substrate 11. The stacked structure includes a source region 18, a drain region 19, and at least one layer of nanosheets 21. The at least one layer of nanosheets 21 is located between the source region 18 and the drain region 19, and the at least one layer of nanosheets 21 is in contact with the source region 18 and the drain region 19, respectively. The germanium-containing semiconductor structure 22 is located between the substrate 11 and the stacked structure. The width of the germanium-containing semiconductor structure 22 is smaller than the width of the at least one layer of nanosheets 21. The germanium content in the germanium-containing semiconductor structure 22 is higher than the germanium content in the at least one layer of nanosheets 21. A gap exists between the at least one layer of nanosheets 21 and the germanium-containing semiconductor structure 22.

[0065] Specifically, information such as the materials of the stacked structure and the germanium-containing semiconductor structure, the number of nanosheets included in the stacked structure, and the specific specifications of the germanium-containing semiconductor structure can be found in the previous text and will not be repeated here.

[0066] In one example, the stacking of the structure and the germanium-containing semiconductor structure on the substrate may include the following steps:

[0067] like Figures 3 to 5 As shown, a fin structure 12 is formed on a substrate 11. The fin structure 12 includes at least a germanium-containing semiconductor layer 121 and at least one stacked layer 122 formed on the germanium-containing semiconductor layer 121. Each stacked layer 122 includes a sacrificial layer 1221 and a channel layer 1222 located on the sacrificial layer 1221.

[0068] Specifically, the above-mentioned germanium-containing semiconductor layer is used to form a film layer of at least part of the germanium-containing semiconductor structure. Therefore, the thickness of the germanium-containing semiconductor layer can be set with reference to the height of the germanium-containing semiconductor structure. In addition, the material of the germanium-containing semiconductor layer is at least the same as the material of the upper part of the germanium-containing semiconductor structure. For example, the material of the germanium-containing semiconductor layer can be Si 1-y Ge y . Wherein, 0<y≤1. The channel layer in the above stack is a film layer used to form the nanosheet, so the number of layers of the stack formed on the germanium-containing semiconductor layer is equal to the number of layers of the nanosheet. In addition, the material and thickness of the channel layer are the same as the material and thickness of the nanosheet. For example: the material of the channel layer is Si 1-x Ge x . Wherein, 0≤x≤1, and yz≥0.2, so as to protect the etchant for etching the germanium-containing semiconductor layer from affecting the nanosheets during at least the selective etching of the germanium-containing semiconductor layer, thereby improving the yield of the ring-gate transistor. For the sacrificial layer, the thickness of the sacrificial layer can be determined according to the spacing between adjacent nanosheets and the minimum vertical distance between the bottom nanosheet and the germanium-containing semiconductor structure, which is not specifically limited here. The material of the sacrificial layer can be a semiconductor material that has a certain etching selectivity ratio with the germanium-containing semiconductor layer and the channel layer, respectively, so as to form a corresponding channel layer on each sacrificial layer through processes such as epitaxial growth, and to reduce the degree to which the germanium-containing semiconductor layer and the channel layer are affected by operations such as etching and cleaning when the portion of the channel layer located in the transition zone is subsequently released. For example: the material of the sacrificial layer can be Si 1-z Ge z . Wherein, 0≤z≤1. And, the material of the germanium-containing semiconductor layer is Si 1-y Ge y , and the material of the channel layer is Si 1-x Ge x In the case of , yz≥0.2, and |xz|≥0.2.

[0069] In actual application, Figure 3As shown, epitaxial growth and other processes can be used to sequentially form film layers for manufacturing germanium-containing semiconductor layers and stacked layers on the substrate 11. As mentioned above, when the germanium-containing semiconductor structure included in the manufactured all-around transistor is doped with corresponding P-type impurities or N-type impurities, an in-situ doping process can also be used to at least dope impurities of the corresponding doping type and concentration into the film layer used to manufacture the germanium-containing semiconductor layer. Figure 4 As shown, processes such as photolithography and dry etching can be used to etch at least the film layers used to manufacture the stack 122 and the germanium-containing semiconductor layer 121 from top to bottom to form the fin structure 12. According to the thickness of the germanium-containing semiconductor layer 121, the objects to be etched and the composition of the formed fin structure 12 are also different. For example: Figure 4 、 Figure 5 As shown in parts (1) and (2) of FIG, when the thickness of the germanium-containing semiconductor layer 121 is less than the thickness of the shallow trench isolation structure to be formed subsequently, it is necessary to etch the film layers used to manufacture the stack 122 and the germanium-containing semiconductor layer 121, as well as the substrate 11, in sequence from top to bottom. At this time, the fin structure 12 includes the etched portion of the substrate 11, the germanium-containing semiconductor layer 121, and at least one stack 122. For another example: Figure 5 As shown in part (3) of FIG. 1 , when the thickness of the germanium-containing semiconductor layer 121 is equal to the thickness of the shallow trench isolation structure to be formed subsequently, only the film layers used to form the stacked layer 122 and the germanium-containing semiconductor layer 121 need to be etched sequentially from top to bottom. At this point, the fin structure 12 only includes the germanium-containing semiconductor layer 121 and at least one stacked layer 122.

[0070] It is worth noting that, as mentioned above, the materials of the germanium-containing semiconductor layer, the channel layer and the sacrificial layer are Si 1- y Ge y , Si 1-x Ge x , Si 1-z Ge z In this case, the film layer located on the substrate and used to manufacture the germanium-containing semiconductor layer can also serve as a strain buffer layer to provide stress to the film layer subsequently formed thereon for manufacturing at least one stack, so that strain is generated in the nanosheet formed based on the channel layer included in the above stack, thereby improving the carrier mobility of the ring-gate transistor and enhancing the driving performance of the ring-gate transistor.

[0071] like Figures 6 to 8 As shown, the germanium-containing semiconductor layer 121 is selectively etched along the width direction of the germanium-containing semiconductor layer 121 so that the width of the germanium-containing semiconductor layer 121 is equal to the width of the germanium-containing semiconductor structure 22 .

[0072] In actual applications, because the germanium-containing semiconductor layer has a certain etching selectivity with the sacrificial layer and channel layer included in the stack, an etchant that only etches the germanium-containing semiconductor layer can be selected to directly etch the germanium-containing semiconductor layer. For example, the germanium-containing semiconductor layer can be etched using a dry etching process using a CF4 and O2 plasma in a He gas protective atmosphere. Alternatively, a quasi-atomic layer etching process can be used to selectively etch the germanium-containing semiconductor layer.

[0073] For example, when the germanium-containing semiconductor layer is selectively etched using a quasi-atomic layer etching process, the selective etching of the germanium-containing semiconductor layer may include the following steps: Figure 6 As shown, a wet etching solution with oxidizing properties is used to selectively oxidize the germanium-containing semiconductor layer 121, so that the sidewalls of the germanium-containing semiconductor layer 121 along the width direction are recessed inward by a fixed thickness relative to the sidewalls of at least one stacked layer 122, and an oxide layer 13 is formed on the sidewalls of the germanium-containing semiconductor layer 121 along the width direction. Figure 7 As shown, remove the oxide layer. Figure 8 As shown, the above operations are repeated until the width of the germanium-containing semiconductor layer 121 is equal to the width of the germanium-containing semiconductor structure.

[0074] Specifically, the type and concentration of the above-mentioned oxidizing wet etching solution can be set according to the actual application scenario. For example, the oxidizing wet etching solution can be a nitric acid solution or a hydrogen peroxide solution. The mass fraction of the nitric acid can be 20% to 70%. The mass fraction of hydrogen peroxide can be 20% to 40%. Figure 6 As shown, since the above-mentioned wet etching solution with oxidizing properties only oxidizes the germanium-containing semiconductor layer 121, after the germanium-containing semiconductor layer 121 is selectively oxidized by the wet etching solution with oxidizing properties along the width direction of the germanium-containing semiconductor layer 121 (the direction is parallel to the A-A' direction), the sidewalls of the germanium-containing semiconductor layer 121 along the width direction are recessed inwardly by a fixed thickness relative to the sidewalls of at least one stacked layer 122. It should be understood that the size of the above-mentioned fixed thickness is different depending on factors such as the specifications of the germanium-containing semiconductor layer 121 and the conditions of selective oxidation. For example: after each selective oxidation, the sidewalls of the germanium-containing semiconductor layer 121 along the width direction can be recessed inwardly by 0.25 nm relative to the sidewalls of at least one stacked layer 122. As shown Figure 7 As shown, the oxide layer formed on the sidewall of the germanium-containing semiconductor layer 121 can then be removed by an etchant such as hydrofluoric acid. It can be seen that the above two operations can make the germanium-containing semiconductor layer 121 thinner to a certain thickness in the horizontal direction. Figure 8 As shown, the number of repetitions of the above two steps can be determined according to the thickness of the germanium-containing semiconductor layer 121 being laterally thinned each time and the difference between the germanium-containing semiconductor layer 121 and the germanium-containing semiconductor structure.

[0075] It is worth noting that during the selective oxidation process, the thickness of each oxidation will be saturated after a certain period of time. In other words, after the time of each selective oxidation is greater than or equal to the saturation time, the formed oxide layer can isolate the sidewalls of the remaining portion of the germanium-containing semiconductor layer from the oxidizing wet etching solution, preventing the portion from continuing to react. Therefore, without having to precisely control the etching time, the thickness of each lateral thinning can be precisely controlled, ensuring that the width of the germanium-containing semiconductor layer after selective etching is equal to the width of the germanium-containing semiconductor structure, preventing the conductive performance of the ring-gate transistor from being poorly improved due to the larger width of the germanium-containing semiconductor layer after selective etching, and preventing the fin structure from bending or collapsing due to the smaller width of the germanium-containing semiconductor layer after selective etching, thereby further improving the yield of the ring-gate transistor.

[0076] It should be noted that if any fin structure has a different spacing from the structures on either side of it along the width of the fin structure, then after selective etching of the germanium-containing semiconductor layer included in the fin structure, the inward recessed thickness of the two sidewalls of the germanium-containing semiconductor layer along the width direction may be different, causing the germanium-containing semiconductor structure included in the manufactured all-around transistor to deviate from the bottom center of the stacked structure. For example, if multiple fin structures are formed on a substrate, and at least one fin structure has a different spacing from two adjacent fin structures along the width direction of the fin structure, this phenomenon may occur.

[0077] like Figure 9 As shown, a shallow trench isolation structure 14 is formed on the portion of the substrate 11 exposed outside the fin structure. The portion of the fin structure exposed outside the shallow trench isolation structure 14 is a fin portion 15. The fin portion 15 includes a source formation region 151, a drain formation region 152, and a transition region 153 located between the source formation region 151 and the drain formation region 152.

[0078] In actual applications, chemical vapor deposition (CVD) or other processes can be used to form an isolation material covering the substrate, which is then planarized. The planarized isolation material is then etched back until the remaining thickness is less than or equal to the bottom surface of the lowest sacrificial layer, resulting in a shallow trench isolation structure.

[0079] like Figure 11 、 Figure 14 and Figure 15 As shown, the source and drain regions are processed to form source and drain regions 18 and 19. The portion of each sacrificial layer located within the transition region 153 is removed, so that the portion of each channel layer located within the transition region 153 forms a corresponding nanosheet 21. The remaining portion of the germanium-containing semiconductor layer 121 forms a germanium-containing semiconductor structure 22.

[0080] Specifically, the formation process of the source region, drain region, and nanosheets mentioned above varies depending on the process used to form the gate stack included in the gate-all-around transistor. The following uses the gate-last process to form the gate stack included in the gate-all-around transistor as an example to specifically illustrate the formation process of the source region, drain region, and nanosheets mentioned above:

[0081] like Figure 10 As shown, after forming the shallow trench isolation structure 14 on the portion of the substrate 11 exposed outside the fin structure, and before processing the source and drain formation regions, the method for manufacturing the gate-all-around transistor further includes the steps of forming a sacrificial gate 16 and a spacer 17 covering the periphery of the transition region 153. The spacer 17 is formed on at least two sides of the sacrificial gate 16 along the width direction.

[0082] Specifically, a process such as chemical vapor deposition can be used to deposit a gate material for forming a sacrificial gate on the formed structure. Then, a process such as dry etching can be used to etch the gate material, leaving the portion of the gate material covering the periphery of the transition region to obtain a sacrificial gate. The gate material can be amorphous silicon, polycrystalline silicon, or other easily removable materials. Figure 10 As shown, after forming the sacrificial gate 16, a sidewall spacer 17 can be formed at least on the sidewall of the sacrificial gate 16 in the above manner. The sidewall spacer 17 can be made of an insulating material such as silicon nitride. The thickness of the sidewall spacer 17 can be set according to actual needs.

[0083] Then, a dry etching process or a wet etching process may be used to remove the portion of the fin located in the source formation region and the drain formation region. Figure 11 As shown, epitaxial growth or other processes are then used to epitaxially form a source region 18 at least in the source formation region, and a drain region 19 at least in the drain formation region. Alternatively, ion implantation can be performed directly on the portions of the fin located in the source formation region and the drain formation region, so that the source formation region corresponds to the source region, and the drain formation region corresponds to the drain region.

[0084] like Figure 12 As shown, when the gate-all-around transistor being manufactured further includes a dielectric layer 20, after forming the source region 18 and the drain region 19, before subsequent operations, it is necessary to form the dielectric layer 20 covering the substrate 11 using deposition and etching processes. The top height of the dielectric layer 20 is equal to the top height of the sacrificial gate 16.

[0085] like Figure 13As shown, after forming the source region 18 and the drain region 19, and before removing the portion of each sacrificial layer located within the transition region 153, the method for manufacturing the gate-all-around transistor further includes the step of removing the sacrificial gate to expose the channel layer and the portion of the sacrificial layer covered by the sacrificial gate. Exemplarily, the sacrificial gate can be removed using a dry etching process or a wet etching process.

[0086] like Figure 14 and Figure 15 As shown, a wet etching or dry etching process can be used to remove the portion of each sacrificial layer located in the transition region, so that the portion of each channel layer located in the transition layer forms a corresponding nanosheet 21. As mentioned above, the materials of the germanium-containing semiconductor layer, the channel layer and the sacrificial layer are Si in order. 1-y Ge y , Si 1-x Ge x , Si 1-z Ge z In this case, since the germanium content in the germanium-containing semiconductor layer is the highest among the above three, and in the process of removing the portion of the sacrificial layer located in the transition region, the portion of the germanium-containing semiconductor layer corresponding to the transition region after selective etching will gradually be exposed. Therefore, the etchant used to etch part of the sacrificial layer may affect the portion of the germanium-containing semiconductor layer corresponding to the transition region after selective etching, thereby causing the finally formed germanium-containing semiconductor structure 22 to be as follows: Figure 15 On the contrary, if the etchant used to etch the part of the sacrificial layer does not affect the part of the germanium-containing semiconductor layer corresponding to the transition region after the selective etching, the germanium-containing semiconductor structure 22 finally formed is as shown in FIG. Figure 14 shown.

[0087] like Figure 16 As shown, a gate stack 23 is formed around the periphery of at least one layer of nanosheets 21. Exemplarily, the gate stack 23 can be formed by processes such as atomic layer deposition. The gate stack 23 may include a gate dielectric layer 231 and a gate 232 formed on the gate dielectric layer 231. The gate dielectric layer 231 may only surround the periphery of each layer of nanosheets 21. Alternatively, the gate dielectric layer 231 may also be additionally formed on the substrate 11 (or shallow trench isolation structure 14) and the germanium-containing semiconductor structure 22 corresponding to the gate formation area. Specifically, the material of the gate stack 23 can be referred to above and will not be repeated here.

[0088] It should be noted that, in addition to the germanium-containing semiconductor structure, the aforementioned source region, drain region, nanosheet, and gate stack structures can be formed in a variety of ways. Forming these structures is not a key feature of the present invention, and therefore, this specification only briefly describes them to facilitate implementation by those skilled in the art. Those skilled in the art can readily devise alternative methods for fabricating these structures.

[0089] As can be seen from the above manufacturing process, although the film layer used to manufacture the nanosheet and the film layer used to manufacture the germanium-containing semiconductor structure are etched simultaneously through the same mask, so that the width of the stack in the obtained fin structure and the initial width of the germanium-containing semiconductor layer are both equal to the width of the larger nanosheet, after the fin structure is obtained, only the germanium-containing semiconductor layer used to manufacture the germanium-containing semiconductor structure is selectively etched, so that its sidewalls are concave inward relative to the sidewalls of the stack, that is, the width of the germanium-containing semiconductor layer after selective etching is smaller. In this case, in the ring-gate transistor finally manufactured, even if the bottom of the gate stack is still in contact with the top of the germanium-containing semiconductor structure, compared with the prior art, the width of the germanium-containing semiconductor structure is smaller, thereby improving the parasitic channel leakage in the ring-gate transistor including at least one nanosheet layer and enhancing the conductive performance of the ring-gate transistor.

[0090] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0091] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A gate-all-around transistor, characterized in that: include: substrate, A stacked structure is formed on a substrate; the stacked structure includes a source region, a drain region and at least one layer of nanosheets; The at least one layer of nanosheets is located between the source region and the drain region, and the at least one layer of nanosheets is in contact with the source region and the drain region respectively; a germanium-containing semiconductor structure formed between the substrate and the stacked structure; The width of the germanium-containing semiconductor structure is smaller than the width of the at least one layer of nanosheets; The germanium content in the germanium-containing semiconductor structure is higher than the germanium content in the at least one layer of nanosheets; and there is a gap between the at least one layer of nanosheets and the germanium-containing semiconductor structure; and a gate stack surrounding the periphery of at least one nanosheet.

2. The gate-all-around transistor according to claim 1, wherein: Along the thickness direction of the substrate, the materials of various parts of the germanium-containing semiconductor structure are the same.

3. The gate-all-around transistor according to claim 1, wherein: The portion of the germanium-containing semiconductor structure located below the source region and the drain region is a first semiconductor portion; the portion of the germanium-containing semiconductor structure located below the at least one layer of nanosheets is a second semiconductor portion; A top height of the second semiconductor portion is greater than zero and smaller than a top height of the first semiconductor portion.

4. The gate-all-around transistor according to claim 1, wherein: The width of the germanium-containing semiconductor structure is 5 nm to 15 nm; and / or, The material of at least one layer of nanosheets is Si 1-x Ge x ; The material of the germanium-containing semiconductor structure is Si 1-y Ge y ; Among them, 0≤x≤1, 0<y≤1, yx≥0.

2.

5. The gate-all-around transistor according to any one of claims 1 to 4, characterized in that: The germanium-containing semiconductor structure is doped with a concentration of 1E17 cm -3 to 5E18cm -3 P-type impurities or N-type impurities; the doping type of the impurities in the germanium-containing semiconductor structure is opposite to the doping type of the impurities in the source region and the drain region; and / or, The gate-all-around transistor further includes a shallow trench isolation structure; the shallow trench isolation structure is formed on a portion of the substrate exposed outside the germanium-containing semiconductor structure; the gate stack is located on the germanium-containing semiconductor structure and the shallow trench isolation structure; The top height of the germanium-containing semiconductor structure is less than or equal to the top height of the shallow trench isolation structure.

6. A method for manufacturing a gate-all-around transistor, characterized in that: include: providing a substrate; A stacking structure and a germanium-containing semiconductor structure are formed on the substrate; the stacking structure includes a source region, a drain region and at least one layer of nanosheets; The at least one layer of nanosheets is located between the source region and the drain region, and the at least one layer of nanosheets is in contact with the source region and the drain region respectively; The germanium-containing semiconductor structure is located between the substrate and the stacked structure; The width of the germanium-containing semiconductor structure is smaller than the width of the at least one layer of nanosheets; The germanium content in the germanium-containing semiconductor structure is higher than the germanium content in the at least one layer of nanosheets; and there is a gap between the at least one layer of nanosheets and the germanium-containing semiconductor structure; A gate stack is formed around the periphery of at least one nanosheet.

7. The method for manufacturing a gate-all-around transistor according to claim 6, wherein: The stacked structure and the germanium-containing semiconductor structure on the substrate include: forming a fin structure on the substrate; the fin structure comprising at least a germanium-containing semiconductor layer and at least one stacked layer formed on the germanium-containing semiconductor layer; each stacked layer comprising a sacrificial layer and a channel layer located on the sacrificial layer; Selectively etching the germanium-containing semiconductor layer along a width direction of the germanium-containing semiconductor layer so that the width of the germanium-containing semiconductor layer is equal to the width of the germanium-containing semiconductor structure; forming a shallow trench isolation structure on a portion of the substrate exposed outside the fin structure; the portion of the fin structure exposed outside the shallow trench isolation structure is a fin portion; the fin portion includes a source formation region, a drain formation region, and a transition region located between the source formation region and the drain formation region; The source formation region and the drain formation region are processed to form the source region and the drain region; and the portion of each sacrificial layer located in the transition region is removed so that the portion of each channel layer located in the transition region forms the corresponding layer of the nanosheet; and the remaining portion of the germanium-containing semiconductor layer forms the germanium-containing semiconductor structure.

8. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: The selectively etching the germanium-containing semiconductor layer comprises: selectively oxidizing the germanium-containing semiconductor layer using an oxidizing wet etching solution, so that the sidewalls of the germanium-containing semiconductor layer along the width direction are recessed inwardly by a fixed thickness relative to the sidewalls of the at least one stacked layer, and forming an oxide layer on the sidewalls of the germanium-containing semiconductor layer along the width direction; removing the oxide layer; The above operation is repeated until the width of the germanium-containing semiconductor layer is equal to the width of the germanium-containing semiconductor structure.

9. The method for manufacturing a gate-all-around transistor according to claim 8, wherein: The wet etching solution with oxidizing properties is a nitric acid solution or a hydrogen peroxide solution; and / or, The oxide layer is removed using hydrofluoric acid.

10. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: The formation process of the germanium-containing semiconductor layer includes an epitaxial growth process and an in-situ doping process; and / or, After forming a shallow trench isolation structure on a portion of the substrate exposed outside the fin structure and before processing the source formation region and the drain formation region, the method for manufacturing the gate-all-around transistor further includes: forming a sacrificial gate and a sidewall spacer covering the periphery of the transition region; the sidewall spacer is formed on at least two sides of the sacrificial gate along the width direction; After processing the source formation region and the drain formation region to form the source region and the drain region, and before removing the portion of each sacrificial layer located in the transition region, the method for manufacturing the ring-gate transistor further includes: removing the sacrificial gate.

11. The method for manufacturing a gate-all-around transistor according to any one of claims 7 to 10, wherein: The material of the germanium-containing semiconductor layer is Si 1-y Ge y ; The material of the channel layer is Si 1-x Ge x ; The material of the sacrificial layer is Si 1-z Ge z ; Among them, 0≤x≤1, 0<y≤1, 0≤z≤1, yx≥0.2, yz≥0.2, |xz|≥0.2.

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