An interconnected spin majority gate device based on magnetic tunnel junction

Abstract

An interconnected spin majority gate device based on a magnetic tunnel junction comprises, from the surface to the substrate, a top electrode layer, a magnetic pinning layer, an insulating tunneling layer, a first magnetic magnetization free layer FL1, an isolation coupling layer, a second magnetic magnetization free layer FL2, a heavy metal layer, and a bottom electrode layer. The magnetic pinning layer consists of a magnetic layer and a coupled antiferromagnetic layer. An isolation coupling layer is provided between the first and second magnetic magnetization free layers to separate them. The magnetic pinning layer, the insulating tunneling layer, and the magnetic magnetization free layers constitute a magnetic tunnel junction. The magnetization direction of the magnetic magnetization free layers is controlled by the spin-transfer torque effect generated by the current, and logic is implemented by the exchange coupling effect of the interconnected magnetic magnetization free layers. The device includes four dual-magnetization free layer magnetic tunnel junctions sharing a common magnetic magnetization free layer, denoted as the first, second, and third inputs MTJ and the output, respectively. The device has a cross shape with four branches, three of which are input branches and the fourth branch is the output branch.

Description

Technical Field

[0001] This invention relates to the field of spintronic device technology, and more particularly, to logic devices and logic circuits based on magnetic tunnel junctions. Background Technology

[0002] In 1996, Slonczewski and Berger independently predicted the existence of the spin-transfer-torque (STT) in spin valve structures. Subsequently, the STT effect was gradually applied in devices such as hard drives and memory. STT-MRAM, which uses STT current to write data and tunnel magnetoresistance to read data, was also developed in 2007. Applying magnetic tunnel junctions to the processor field, utilizing their non-volatile storage, can achieve in-memory computing, thereby revolutionizing traditional computer architecture.

[0003] In addition, in the post-Moore's Law era, the development of silicon-based CMOS devices has gradually become insufficient, and spintronic devices have become a strong competitor to replace CMOS devices. This invention proposes an interconnectable magnetic tunnel junction-based logic device that can implement basic logic functions such as AND, OR, and NOT, and the devices can be interconnected to implement more complex logic operations such as full adders.

[0004] The inventor's patent CN2018115316772 relates to a method for growing semi-metallic epitaxial magnetic tunnel junctions, but the design and application of the device are of particular significance. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides interconnectable logic devices and logic circuits based on magnetic tunnel junctions, the purpose of which is to solve the problem that existing spin majority gate devices based on the STT effect are difficult to implement NOT gates and interconnections.

[0006] To achieve the above objectives, the present invention provides an interconnected spin majority gate device based on a dual-magnetized free-layer magnetic tunnel junction, comprising: an upper electrode layer, a magnetic pinning layer, an insulating tunneling layer, a first magnetic magnetized free layer FL1, an isolation coupling layer, a second magnetic magnetized free layer FL2, a heavy metal layer, and a bottom electrode layer stacked sequentially from the surface to the substrate; the magnetic pinning layer consists of a magnetic layer and a coupled antiferromagnetic layer, and an isolation coupling layer is provided between the first and second magnetic magnetized free layers FL1 and FL2 to separate the magnetic magnetized free layers; the magnetic pinning layer, the insulating tunneling layer, and the magnetic magnetized free layers constitute a magnetic tunnel junction, the magnetization direction of the magnetic magnetized free layers is controlled by the spin-transfer torque effect generated by the current, and the logic function is realized by the exchange coupling effect of the interconnected magnetic magnetized free layers;

[0007] The device unit includes four dual-magnetized free-layer magnetic tunnel junctions sharing a common magnetic magnetized free layer, which are denoted as first input MTJ(1), second input MTJ(2), third input MTJ(3) and output MTJ(4) respectively. The device structure is cross-shaped with four branches, of which three branches are input branches and the fourth branch is output branch. The first input MTJ(1), second input MTJ(2) and third input MTJ(3) are located at the endpoints of the three input branches respectively, and the output branch MTJ(4) is located at the endpoint of the output branch.

[0008] The magnetization direction of the free layer of the first input MTJ (1), the magnetization direction of the free layer of the second input MTJ (2), and the magnetization direction of the free layer of the third input MTJ (2) are all determined by the direction and magnitude of the current perpendicular to the film surface of the input device. The magnetization direction of the free layer of the output MTJ (4) is determined by the magnetization direction of the free layer of the first input MTJ (1), the magnetization direction of the free layer of the second input MTJ (2), the free magnetization direction of the third input MTJ (3), and the interconnection structure.

[0009] The output MTJ (4), the first input MTJ (1), the second input MTJ (2), and the third input MTJ (3) constitute three input "majority decision gates". That is, the magnetization direction of the magnetization free layer of the output MTJ (4) is consistent with the majority of the magnetization directions of the magnetization free layer of the first input MTJ (1), the second input MTJ (2), and the third input MTJ (3). At the same time, when the first input MTJ (1) is in a high-resistance state, the second input MTJ (2), the third input MTJ (3), and the output MTJ (4) constitute a logic "OR" function; when the first input MTJ (1) is in a low-resistance state, the second input MTJ (2), the third input MTJ (3), and the output MTJ (4) constitute a logic "AND" function.

[0010] The interconnection structures between adjacent MTJs are divided into two categories. One type consists of connected "device perpendicular magnetization - device in-plane magnetization - device perpendicular magnetization" regions. Magnetization signals transmitted through this structure are reversed, forming the logic "NOT". The other type of interconnection structure directly connects perpendicularly magnetized free layers. Magnetization signals transmitted through this structure remain unchanged, achieving the "BUFFER" function. The mechanism of the logic implementation of this invention is as described above. When interconnecting between MTJs or devices, if the "NOT" function is required, the surface treatment (oxidation, etching) of the isolation layer forms "perpendicular magnetization - in-plane magnetization - perpendicular magnetization" regions. If the "BUFFER" function is required, their magnetized free layers are directly connected.

[0011] As another aspect of the present invention, the present invention provides an interconnectable logic circuit based on a dual-magnetized free-layer magnetic tunnel junction, comprising: N interconnected spin majority gate devices, wherein M interconnected spin majority gates have 3 necessary inputs MTJ, the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) are all floating, and their data writing relies entirely on the STT current. L interconnected spin majority gates have 2 necessary inputs MTJ, the first input MTJ(1) and the second input MTJ(2) are written through the STT current, and the third input MTJ(3) is connected to the output terminal of the preceding interconnected spin majority gate. K interconnected spin majority gates have 1 necessary input MTJ, the first input MTJ(1) is written through the STT current, and the second input MTJ(2) and the third input MTJ(3) are connected to the output terminal of the preceding interconnected spin majority gate. NMLK spin majority gates have 0 necessary inputs MTJ, the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) are all connected to the output terminal of the preceding interconnected spin majority gate. The input MTJ can be omitted when it is in a non-essential MTJ position. When data reading is not required, the output MTJ(4) of the interconnected spin majority gate devices in the logic circuit can be omitted.

[0012] The first magnetic magnetization layer FL1 is a magnetic material providing high TMR and perpendicular anisotropy, such as CoFeB or CoFeAl. The second magnetic magnetization layer FL2 is a material providing high-speed domain movement, such as Co. An isolation layer between the first and second magnetic magnetization layers FL1 and FL2 is used to ferromagnetically couple the two layers and adjust lattice matching; the isolation layer is made of materials such as Ru. Both layers are 5-100 nanometers thick, and reference can be made to the inventors' prior disclosure.

[0013] When there are N interconnected spin majority gate devices, M interconnected spin majority gate devices have 3 necessary input MTJs, with the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) all floating, and their data writing relies entirely on the STT current; L interconnected spin majority gate devices have 2 necessary input MTJs, with the first input MTJ(1) and the second input MTJ(2) written through the STT current, and the third input MTJ(3) connected to the output of the preceding interconnected spin majority gate device; K interconnected spin majority gate devices have 1 necessary input MTJ, with the first input MTJ(1) written through the STT current, and the second input MTJ(2) and the third input MTJ(3) connected to the output of the preceding interconnected spin majority gate device; NMLK spin majority gate devices have 0 necessary input MTJs, with the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) all connected to the output of the preceding interconnected spin majority gate. The input MTJs can be omitted when they are in a non-necessary MTJ position. When data reading is not required, the output MTJ(4) of the interconnected spin majority gate devices in the logic circuit can be omitted.

[0014] The output MTJ of the preceding interconnected spin majority gate device is connected to the magnetized free layer of the input MTJ of the following interconnected spin majority gate device through a magnetized free layer interconnection structure, thereby realizing the "NOT" and "BUFFER" functions depending on the different interconnection structures.

[0015] Preferably, the logic circuit implements a one-bit full adder function, including three spin majority gate devices, referred to sequentially as a first interconnected spin majority gate device, a second interconnected spin majority gate device, and a third interconnected spin majority gate device; the first interconnected spin majority gate device has three necessary input MTJs and one output MTJ, which are connected to the magnetization free layer of the input MTJ of the second interconnected spin majority gate device through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure; the second interconnected spin majority gate device has one necessary input MTJ and one output MTJ, and its other two ends are respectively connected to the output terminals of the first interconnected spin majority gate device and the third interconnected spin majority gate device through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure; the third interconnected spin majority gate device has three necessary input MTJs and one output MTJ, wherein the second input MTJ is connected to the other three terminals through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure, and its output terminal is connected to the second interconnected spin majority gate device through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure;

[0016] Injecting the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) of the first interconnected spin majority gate with a bit A, a bit B, and a carry C from the previous stage, respectively. inThe current is used to obtain the carry C. o Simultaneously, this result serves as the output of the first interconnected spin majority gate device, and after being inverted, it is input to the second interconnected spin majority gate device; the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) of the third interconnected spin majority gate device are respectively injected with the current bit A and the carry C from the previous stage. in The current of position B is inverted and then input to the second interconnected spin majority gate; the carry C from the previous stage is injected into the necessary input MTJ of the second interconnected spin majority gate device. in The current, the magnetization free layer information of the necessary input MTJ, and the output results of the first interconnected spin majority gate device and the third interconnected spin majority gate device are combined with spin majority operations to obtain the local bit and S.

[0017] In this invention, the magnetization direction of the three magnetized free layers of the MTJ responsible for signal input is determined by the direction of the injected current, while the magnetization direction of the output MTJ's magnetized free layer is jointly determined by the magnetization directions of the three input MTJs' magnetized free layers, enabling the implementation of logic functions such as "AND" and "OR". Simultaneously, by utilizing the chiral coupling caused by the special local in-plane magnetization structure, the "NOT" logic function can be implemented in any MTJ interconnect structure.

[0018] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0019] 1. This invention simultaneously achieves the interconnection of "NOT" logic function and devices through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure. In this structure, the SOT effect generated by the heavy metal layer drives the magnetic domains at the output of the preceding interconnected spin majority gate to move to the input of the following interconnected spin majority gate. Chiral coupling caused by the Dzyaloshinskii-Moriya interface interaction causes the magnetic domains passing through this structure to flip, thereby realizing the logic "NOT".

[0020] 2. The interconnect logic device provided by this invention supports three-bit input and one-bit output. In addition to being a majority decision gate, it can also utilize its programmability to implement logic "AND" and "OR" functions.

[0021] 3. This invention utilizes magnetic signals to store and process data, and the data is non-volatile, so it can still be retained even after power is cut off.

[0022] 4. The interconnect logic device provided by this invention supports interconnection of devices to form logic circuits, and performs more complex logic functions such as half-adders.

[0023] 5. The interconnect logic device provided by the present invention adopts a vertically magnetized thin film, which has the advantages of high density and high integration. At the same time, the vertically magnetized film greatly reduces the write current, and the dual-magnetized free layer structure improves its thermal stability.

[0024] 6. The interconnection logic circuit provided by this invention only requires current and magnetic signal conversion at the input and output, and does not require electromagnetic signal conversion during signal transmission and operation, which greatly improves the operation efficiency. Attached Figure Description

[0025] Figure 1 Side view of the interconnectable logic device provided by the present invention;

[0026] Figure 2 A plan view of interconnectable logic devices provided for this invention;

[0027] Figure 3 This invention provides a structural diagram of the interconnection region in an interconnectable logic device.

[0028] Figure 4 A schematic diagram of the operation of the interconnectable logic device provided by the present invention;

[0029] Figure 5 This is a planar structural diagram of the interconnectable logic circuits used in this invention to implement the full adder function. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0031] Figure 1The interconnectable logic device provided by this invention includes a top electrode layer 10, magnetic pinning layers 20 and 30, insulating tunneling layers 40 (41, 42, 43, 44), FL1 magnetic magnetization free layers 50 (51, 52, 53, 54), isolation coupling layers 60 (61, 62), FL2 magnetic magnetization free layers 70, a heavy metal layer 80, and a bottom electrode layer 90, stacked sequentially. The magnetic pinning layers consist of antiferromagnetic layers 20 (21, 22, 23, 24) and ferromagnetic layers 30 (31, 32, 33, 34), which form the pinning layer of the magnetic tunnel junction through antiferromagnetic coupling. The FL1 magnetic magnetization free layers 50 and FL2 magnetic magnetization free layers 70 achieve ferromagnetic coupling by adjusting the thickness of the isolation coupling layer 60, forming the magnetization free layers of the magnetic tunnel junction. Except for the region below the modified isolation coupling layer 62, all magnetic layers are out-of-plane magnetized. The electrodes are respectively connected to the magnetized free layer 11 of the first input MTJ, the magnetized free layer 12 of the second input MTJ, the magnetized free layer 13 of the third input MTJ, the magnetized free layer 14 of the output MTJ, and the bottom electrodes 90 (91, 92) below the common magnetized free layer region.

[0032] Figure 2 The interconnectable logic device planar diagram provided by the present invention shows that the four MTJs are located on the four branches of the cross structure. The first input magnetic tunnel junction 101, the second input magnetic tunnel junction 102 and the third input magnetic tunnel junction 103 are located at the ends of the three short branches, the output magnetic tunnel junction 104 is located in the middle of the long branch, and the right side of the magnetic tunnel junction 104 is the interconnection area.

[0033] Figure 3 The diagram shows the interconnection region structure in the interconnectable logic device provided by this invention. The magnetization direction of the FL2 magnetic magnetization free layer 70 is perpendicular to the film surface. After special treatment of the isolation layer 60 above it, such as oxidation or etching, in-plane magnetization is formed in local areas. Due to the chiral coupling caused by the DMI effect, the FL2 magnetic magnetization free layer 70 forms a special state of "vertical magnetization-in-plane magnetization-vertical magnetization". On the other hand, the devices are separated by the insulating region 92, so an in-plane current can be applied to the heavy metal layer 80. Due to the strong SOC effect of the heavy metal, the SOT current induces the magnetic domains on the left to move to the right. After passing through the "vertical magnetization-in-plane magnetization-vertical magnetization" region, the magnetization direction is reversed, thereby realizing the logic "NOT" function.

[0034] Figure 4This is a schematic diagram of the interconnectable logic device provided by the present invention. The write current flows through the upper electrode layers 11, 12, and 13 of the first input magnetic tunnel junction 101, the second input magnetic tunnel junction 102, and the third input magnetic tunnel junction 103 to the common bottom electrode layer 91. Due to the spin-transfer torque effect, the magnetization directions of the mutually ferromagnetically coupled FL1 and FL2 magnetized free layers in the input magnetic tunnel junctions are completely determined by the direction and magnitude of the current. When the electron flow is from top to bottom, the magnetization directions of the FL1 magnetized free layer and the FL2 magnetized free layer directly below it are both perpendicular to the film surface and upwards. When the electron flow is from bottom to top, the magnetization directions of the FL1 magnetized free layer and the FL2 magnetized free layer directly below it are both perpendicular to the film surface and downwards. We assume that the upward magnetization of the magnetized free layers in the magnetic tunnel junction represents 0 in binary, and the downward magnetization represents 1 in binary. At this time, the current flow direction has been converted into a magnetic signal. Due to the exchange coupling between adjacent magnetic domains, the FL2 magnetized free layer of the output MTJ is influenced by the magnetization states of the other three input MTJ magnetized free layers, and its magnetization direction is consistent with the majority of the three magnetization states. For the output magnetic tunnel junction 104, the resistance value can be read out based on the TMR effect to determine the magnetization direction of its magnetized free layer. By applying a small current between its upper electrode 14 and the common bottom electrode 91, the signal can be read out using TMR. We assume that the high-resistance state is 1 and the low-resistance state is 0. The truth table of interconnectable logic devices is shown below.

[0035] Table 1 Truth Table for Interconnectable Logic Devices

[0036]

[0037]

[0038] Specifically, when the magnetization free layer of the first input MTJ is controlled to be in the 0 state, the second input MTJ, the third input MTJ, and the output MTJ constitute a logic "AND"; when the magnetization free layer of the first input MTJ is controlled to be in the 1 state, the second input MTJ, the third input MTJ, and the output MTJ constitute a logic "OR".

[0039] Figure 5 This is a planar structural diagram of the interconnectable logic circuit provided by the present invention to implement the full adder function. It mainly consists of three interconnectable logic devices, including nine magnetic tunnel junctions, of which magnetic tunnel junctions 1001, 1002, 1003, 2001, 3001, 3002 and 3003 are input magnetic tunnel junctions, and magnetic tunnel junctions 1004 and 2004 are output magnetic tunnel junctions. Its truth table is shown below.

[0040] Table 2 Truth Values ​​of Full Adder Devices

[0041] IN1 IN2 IN3 OUT1 OUT2 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

[0042] IN1, IN2, and IN3 are inputs, representing two bits of the current position and one bit of carry from the previous stage, respectively. OUT1 and OUT2 are outputs, representing the current position, S, and carry C, respectively. in .

[0043] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. An interconnected spin majority gate device based on a magnetic tunnel junction, characterized in that, This is an interconnected spin majority gate device based on a dual-magnetized free-layer magnetic tunnel junction, comprising: a top electrode layer, a magnetic pinning layer, an insulating tunneling layer, a first magnetic magnetized free layer FL1, an isolation coupling layer, a second magnetic magnetized free layer FL2, a heavy metal layer, and a bottom electrode layer stacked sequentially from the surface to the substrate; the magnetic pinning layer consists of a ferromagnetic layer and a coupled antiferromagnetic layer, and an isolation coupling layer is provided between the first and second magnetic magnetized free layers FL1 and FL2 to separate the magnetic magnetized free layers; the magnetic pinning layer, the insulating tunneling layer, the first magnetic magnetized free layer FL1, the isolation coupling layer, and the second magnetic magnetized free layer FL2 constitute a magnetic tunnel junction, and the magnetization direction of the magnetic magnetized free layers is controlled by the spin-transfer torque effect generated by the current, and the logic function is realized by the exchange coupling effect of the interconnected magnetic magnetized free layers; The device unit includes four dual-magnetized free-layer magnetic tunnel junctions sharing a common magnetic magnetized free layer, which are denoted as the first input MTJ (1), the second input MTJ (2), the third input MTJ (3), and the output MTJ (4) in sequence. The device structure is cross-shaped with four branches, of which three branches are input branches and the fourth branch is an output branch. The first input MTJ (1), the second input MTJ (2), and the third input MTJ (3) are located at the endpoints of the three input branches, and the output branch MTJ (4) is located at the endpoint of the output branch. The magnetization direction of the free layer of the first input MTJ (1), the magnetization direction of the free layer of the second input MTJ (2), and the magnetization direction of the free layer of the third input MTJ (3) are all determined by the direction and magnitude of the current perpendicular to the film surface of the input device. The magnetization direction of the free layer of the output MTJ (4) is determined by the magnetization direction of the free layer of the first input MTJ (1), the magnetization direction of the free layer of the second input MTJ (2), the magnetization direction of the free layer of the third input MTJ (3), and the interconnection structure. The output MTJ (4), the first input MTJ (1), the second input MTJ (2), and the third input MTJ (3) constitute three input "majority decision gates". That is, the magnetization direction of the magnetized free layer of the output MTJ (4) is consistent with the majority of the magnetization directions of the magnetized free layer of the first input MTJ (1), the second input MTJ (2), and the third input MTJ (3). At the same time, when the first input MTJ (1) is in a high-resistance state, the second input MTJ (2), the third input MTJ (3), and the output MTJ (4) constitute a logic "OR" function; when the first input MTJ (1) is in a low-resistance state, the second input MTJ (2), the third input MTJ (3), and the output MTJ (4) constitute a logic "AND" function. The interconnection structures between adjacent MTJs are divided into two types. One type consists of connected "vertical magnetization-in-plane magnetization-vertical magnetization" regions. The magnetization signal transmitted through this structure is reversed, forming the logic "NOT". The other type of interconnection structure is directly interconnected by the vertical magnetization free layers of the devices. The magnetization signal remains unchanged after passing through this structure, realizing the "BUFFER" function. When interconnecting between MTJs or between devices, if the "NOT" function is required, the surface treatment of the isolation layer forms a "vertical magnetization-in-plane magnetization-vertical magnetization" region. If the "BUFFER" function is required, their magnetization free layers are directly connected. The first magnetic magnetization layer FL1 is a magnetic material that provides high TMR and vertical anisotropy, including CoFeB and CoFeAl. The second magnetic magnetization layer FL2 is Co, which provides a material for high-speed magnetic domain movement. The isolation layer between the first magnetic magnetization layer FL1 and the second magnetic magnetization layer FL2 is used to ferromagnetically couple the two and adjust the lattice matching, including Ru material. When N interconnected spin majority gate devices form a logic circuit, M interconnected spin majority gate devices have 3 necessary inputs MTJ, the first input MTJ (1), the second input MTJ (2) and the third input MTJ (3) are all floating, and their data writing relies entirely on the STT current; L interconnected spin majority gates have 2 necessary inputs MTJ, the first input MTJ (1) and the second input MTJ (2) are written through the STT current, and the third input MTJ (3) is connected to the output terminal of the previous interconnected spin majority gate device; K interconnected spin majority gate devices have 1 necessary input MTJ, the first input MTJ (1) is written through the STT current, and the second input MTJ (2) and the third input MTJ (3) are connected to the output terminal of the previous interconnected spin majority gate device; NMLK spin majority gate devices have 0 necessary inputs MTJ, the first input MTJ (1), the second input MTJ (2) and the third input MTJ (3) are all connected to the output terminal of the previous interconnected spin majority gate; The output MTJ of the preceding interconnected spin majority gate device is connected to the magnetized free layer of the input MTJ of the following interconnected spin majority gate device through a magnetized free layer interconnection structure, thereby realizing the "NOT" and "BUFFER" functions depending on the different interconnection structures.

2. The interconnected spin majority gate device based on a magnetic tunnel junction as described in claim 1, characterized in that, The logic circuit implements a one-bit full adder function and includes three spin majority gate devices, referred to sequentially as the first interconnected spin majority gate device, the second interconnected spin majority gate device, and the third interconnected spin majority gate device. The first interconnected spin majority gate device has three necessary input MTJs and one output MTJ, which are connected to the magnetization free layer of the input MTJ of the second interconnected spin majority gate device through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure. The second interconnected spin majority gate device has one necessary input MTJ and one output MTJ, and its other two ends are connected to the output terminals of the first interconnected spin majority gate device and the third interconnected spin majority gate device through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure. The third interconnected spin majority gate device has three necessary input MTJs and one output MTJ, wherein the second input MTJ is connected to the other three terminals through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure, and its output terminal is connected to the second interconnected spin majority gate device through a "vertical magnetization-in-plane magnetization-vertical magnetization" interconnection structure. Injecting a local bit A, a carry C from the previous stage into the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) of the first interconnected spin majority gate, respectively. in The current is used to obtain the carry C. o Meanwhile, this result serves as the output of the first interconnected spin majority gate device, and after being inverted, it is input to the second interconnected spin majority gate device; the first input MTJ(1), the second input MTJ(2), and the third input MTJ(3) of the third interconnected spin majority gate device are respectively injected with the current bit A and the carry C from the previous stage. in The current of position B is inverted and then input into the second interconnected spin majority gate; the carry C from the previous stage is injected into the necessary input MTJ of the second interconnected spin majority gate device. in The current, the magnetization free layer information of the necessary input MTJ, and the output results of the first interconnected spin majority gate device and the third interconnected spin majority gate device are combined with spin majority operations to obtain the local bit and S.

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