A crosstalk suppression circuit and a crosstalk suppression method

Abstract

The present application discloses a crosstalk suppression circuit and a crosstalk suppression method. The circuit includes an upper bridge arm driving circuit and a lower bridge arm driving circuit. Any one of the bridge arm driving circuits includes a first switching transistor, at least one second switching transistor, an auxiliary Miller clamping circuit corresponding to each second switching transistor, and a driving chip. Wherein: the drain of the first switching transistor is connected to the drains of at least one of the second switching transistors; the source of the first switching transistor is connected to the sources of at least one of the second switching transistors; the gate of the first switching transistor is connected to the built-in Miller clamping of the driving chip; the gates of at least one of the second switching transistors are connected to one end of the corresponding auxiliary Miller clamping circuit; the other end of each auxiliary Miller clamping circuit is connected to the built-in Miller clamping of the driving chip. Wherein, the auxiliary Miller clamping circuit corresponding to any one of the second switching transistors in any one of the bridge arm driving circuits is used to discharge the crosstalk current of the corresponding second switching transistor.

Description

Technical Field

[0001] The present application relates to the technical field of power electronic drive circuits, and relates to, but is not limited to, a crosstalk suppression circuit and a crosstalk suppression method. Background Art

[0002] The crosstalk phenomenon is particularly obvious in the application of switching tubes. If not suppressed, there is a greater risk, either causing the risk of bridge arm breakdown or resulting in device damage. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a crosstalk suppression circuit and a crosstalk suppression method.

[0004] In a first aspect, an embodiment of the present application provides a crosstalk suppression circuit, the circuit includes: an upper bridge arm drive circuit and a lower bridge arm drive circuit. Any bridge arm drive circuit includes a first switching tube, at least one second switching tube, an auxiliary Miller clamping circuit corresponding to each second switching tube, and a drive chip; wherein: the drain of the first switching tube is connected to the drains of at least one of the second switching tubes; the source of the first switching tube is connected to the sources of at least one of the second switching tubes; the gate of the first switching tube is connected to the built-in Miller clamping of the drive chip; the gates of at least one of the second switching tubes are connected to one end of the corresponding auxiliary Miller clamping circuit; the other end of each auxiliary Miller clamping circuit is connected to the built-in Miller clamping of the drive chip; wherein, the auxiliary Miller clamping circuit corresponding to any second switching tube in any bridge arm drive circuit is used to discharge the crosstalk current of the corresponding second switching tube.

[0005] In a second aspect, an embodiment of the present application provides a crosstalk suppression method, which is applied to a crosstalk suppression circuit. The circuit includes: an upper bridge arm drive circuit and a lower bridge arm drive circuit. Any bridge arm drive circuit includes a first switching tube, at least one second switching tube, an auxiliary Miller clamping circuit corresponding to each second switching tube, and a drive chip; the method includes: when the first switching tube and at least one second switching tube in the lower bridge arm drive circuit / the upper bridge arm drive circuit are in the off state, and the first switching tube in the upper bridge arm drive circuit / the lower bridge arm drive circuit is driven by the drive chip and changes from the off state to the on state; or; when the first switching tube and at least one second switching tube in the lower bridge arm drive circuit / the upper bridge arm drive circuit are in the off state, and the first switching tube in the upper bridge arm drive circuit / the lower bridge arm drive circuit is driven by the drive chip and changes from the on state to the off state: the second switching tube in the lower bridge arm drive circuit / the upper bridge arm drive circuit discharges the crosstalk current of the corresponding second switching tube through the corresponding auxiliary Miller clamping circuit.

[0006] In the embodiment of the present application, the gate of the first switching transistor is shorted to the Miller clamping pin to trigger the built-in Miller clamping of the driving chip. The second switching transistors connected in parallel with the first switching transistor are connected to the Miller clamping pin through the auxiliary Miller clamping circuit, so there is no risk that the Miller clamping cannot be triggered. Each parallel-connected second switching transistor discharges the crosstalk current through the low-impedance loop of the auxiliary Miller clamping circuit, which plays a role in suppressing crosstalk and reduces the risk of arm punch-through or device damage. The gates of the parallel-connected second switching transistors are isolated from each other, and device damage will not be caused due to asynchronous switching of each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. is a schematic circuit diagram of a crosstalk suppression circuit according to an embodiment of the present application;

[0008] Figure 2 FIG. is a schematic circuit diagram of a switching transistor with a bridge connection in the related art;

[0009] Figure 3a is Figure 2 a corresponding schematic diagram of the voltage signal of a switching transistor;

[0010] Figure 3b is Figure 2 a corresponding schematic diagram of the voltage signal of another switching transistor;

[0011] Figure 4 FIG. is a schematic circuit diagram of another crosstalk suppression circuit according to an embodiment of the present application;

[0012] Figure 5 FIG. is a schematic diagram of the working mode of a crosstalk suppression circuit according to an embodiment of the present application;

[0013] Figure 6 FIG. is a schematic circuit diagram of a crosstalk suppression circuit in the related art;

[0014] Figure 7 FIG. is a schematic circuit diagram of another crosstalk suppression circuit in the related art;

[0015] Figure 8 FIG. is a schematic circuit diagram of yet another crosstalk suppression circuit in the related art;

[0016] Figure 9 FIG. is a schematic circuit diagram of still another crosstalk suppression circuit in the related art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The technical solution of the present application will be further elaborated in detail below in conjunction with the drawings and embodiments.

[0018] Figure 1 FIG. is a schematic circuit diagram of a crosstalk suppression circuit according to an embodiment of the present application, as Figure 1As shown, the circuit includes:

[0019] An upper-bridge-arm drive circuit 11 and a lower-bridge-arm drive circuit 12. Any one of the bridge-arm drive circuits includes a first switching tube 101, at least one second switching tube 102, an auxiliary Miller clamping circuit 103 corresponding to each second switching tube 102, and a drive chip 104; where:

[0020] The drain d of the first switching tube 101 is connected to the drain d of at least one of the second switching tubes 102; the source s of the first switching tube 101 is connected to the source s of at least one of the second switching tubes 102;

[0021] The gate g of the first switching tube 101 is connected to the built-in Miller clamp 1041 of the drive chip 104;

[0022] The gate g of at least one of the second switching tubes 102 is connected to one end of the corresponding auxiliary Miller clamping circuit 103;

[0023] The other end of each auxiliary Miller clamping circuit 103 is connected to the built-in Miller clamp 1041 of the drive chip 104;

[0024] Among them, the auxiliary Miller clamping circuit 103 corresponding to any one of the second switching tubes 102 in any one of the bridge-arm drive circuits is used to discharge the crosstalk current of the corresponding second switching tube 102.

[0025] Among them, the drive chip can control the turn-on or turn-off of the first switching tube or the second switching tube through a drive signal; the drive chip can be used to control, through a drive signal, that the first switching tube and at least one second switching tube in the lower-bridge-arm drive circuit / the upper-bridge-arm drive circuit are all in the off state; and can also control, through a drive signal, the first switching tube in the upper-bridge-arm drive circuit / the lower-bridge-arm drive circuit to be converted from the off state to the on state; the drive chip is further used to control, through a drive signal, the first switching tube in the upper-bridge-arm drive circuit / the lower-bridge-arm drive circuit to be converted from the conducting state to the off state.

[0026] The first switching tube or the second switching tube can be a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), for example, it can be a silicon carbide MOSFET; due to the characteristics of fast switching speed and low loss of the silicon carbide MOSFET, it is used more and more in power electronic circuits. However, compared with traditional Insulated Gate Bipolar Transistors (IGBTs) or silicon-based MOSFETs, the silicon carbide MOSFET also brings new challenges.

[0027] When a power electronic converter is applied in the high-power field, it is often necessary to use MOSFETs in parallel. Since the switching tubes of the upper-bridge-arm drive circuit 11 and the lower-bridge-arm drive circuit 12 share the drive signal, crosstalk will occur on each of the parallel switching tubes. Generally speaking, the turn-on and turn-off speeds of the parallel MOSFETs are not synchronized, and it becomes more difficult to effectively suppress the crosstalk of the parallel MOSFETs. In the embodiment of the present application, the auxiliary Miller clamping circuit 103 can provide a low-impedance loop to discharge the crosstalk current of the second switching tube when there is crosstalk current in the second switching tube.

[0028] As Figure 1 shown, Cds1 is the parasitic capacitance between the source and drain of the first switching tube 101 in the upper-bridge-arm drive circuit 11, the diode 111 is the parasitic diode (also known as the body diode) between the source and drain of the first switching tube 101 in any bridge-arm drive circuit, Cgd1 is the parasitic capacitance between the gate and drain of the first switching tube 101 in the upper-bridge-arm drive circuit 11, and Cgs1 is the parasitic capacitance between the gate and source of the first switching tube 101 in the upper-bridge-arm drive circuit 11; Cdsn is the parasitic capacitance between the source and drain of the second switching tube 101 in the upper-bridge-arm drive circuit 11, the diode 121 is the parasitic diode between the source and drain of the second switching tube 102 in any bridge-arm drive circuit, Cgdn is the parasitic capacitance between the gate and drain of the second switching tube 101 in the upper-bridge-arm drive circuit 11, and Cgsn is the parasitic capacitance between the gate and source of the second switching tube 101 in the upper-bridge-arm drive circuit 11.

[0029] Similarly, Cds2 is the parasitic capacitance between the source and drain of the first switching tube 101 in the lower-bridge-arm drive circuit 12, Cgd2 is the parasitic capacitance between the gate and drain of the first switching tube 101 in the lower-bridge-arm drive circuit 12, and Cgs2 is the parasitic capacitance between the gate and source of the first switching tube 101 in the lower-bridge-arm drive circuit 12; Cdsm is the parasitic capacitance between the source and drain of the second switching tube 101 in the lower-bridge-arm drive circuit 12, Cgdm is the parasitic capacitance between the gate and drain of the second switching tube 101 in the lower-bridge-arm drive circuit 12, and Cgsm is the parasitic capacitance between the gate and source of the second switching tube 101 in the lower-bridge-arm drive circuit 12.

[0030] As Figure 2 shown, the circuit includes two silicon carbide MOSFETs connected in a bridge structure, namely the upper transistor Q 1 and the lower transistor Q 2 . Taking the lower transistor Q 2 as an example, the crosstalk between the upper transistor Q 1 and the lower transistor Q 2 will be described as follows:

[0031] As shown Figure 3a in the figure, when the lower transistor Q 2 is in the off state, if the arm current is outward, that is, the current flows through the body diode of the lower transistor Q 2 , at this time, the voltage Vds2 between the drain and source of the lower transistor Q 2 is equal to 0, and the voltage Vgs2 between the gate and source of the lower transistor Q 2 is equal to 0; the voltage Vds1 between the drain and source of the upper transistor Q 1 is equal to the preset value Vdc, and the voltage Vgs1 between the gate and source of the upper transistor Q 1 is equal to 0.

[0032] If the upper transistor Q 1 switches from the off state to the on state, the current will commutate from the lower transistor Q 2 to the upper transistor Q 1 . The Vds2 voltage of the lower transistor Q 2 will quickly rise to Vdc, and the Vds1 voltage of the upper transistor Q 1 will drop to 0. Since the switching-on speed of the silicon carbide MOSFET is very fast, the voltage change speed (i.e., dv / dt) is very large. This dv / dt will generate a current from d to g in the parasitic capacitance Cgd2 of the lower transistor Q 2 . This current will charge Cgd2 and raise its voltage. The current flow path is either through the parasitic capacitance Cgs2 or through the drive circuit. The part of the current passing through Cgs2 will charge Cgs2 and cause the voltage Vgs2 of Cgs2 to rise. Therefore, even when the lower transistor Q 2 is in the off state, the voltage of Vgs2 will also rise. If the rise of Vgs2 exceeds the preset value Vth, that is, the rise amplitude is too large, it will cause mis-turn-on of the lower transistor Q 2 , and further lead to arm shoot-through.

[0033] As shown Figure 3b in the figure, when the lower transistor Q 2 is in the off state and the upper transistor Q 1 is in the on state, the Vds2 of the lower transistor Q 2 is equal to Vdc, the Vgs2 of the lower transistor Q 2 is equal to 0, and the Vds1 of the upper transistor Q 1 is equal to 0. If the arm current direction is outward at this time, when the upper transistor Q 1 turns off, the Vds1 of the upper transistor Q 1 will quickly change from 0 to Vdc, and the lower transistor Q 2The Vds2 of will quickly change from Vdc to 0. This voltage change will also generate a very high dv / dt, creating a current that discharges through the Cgd2 of the lower transistor. The part of this current flowing through the Cgs2 of the lower transistor will cause a drop in Vgs2. If the drop in Vgs2 is too large, the Vgs2 voltage will be lower than the minimum voltage allowed by the device, resulting in device damage.

[0034] From the above analysis, it can be seen that the crosstalk phenomenon is particularly obvious in the application of silicon carbide MOSFETs. If not suppressed, there is a greater risk, either causing the risk of arm-to-arm breakdown or leading to device damage.

[0035] In the embodiment of the present application, the gate of the first switch transistor is short-circuited with the Miller clamping pin to trigger the built-in Miller clamping of the driving chip. The second switch transistors connected in parallel with the first switch transistor are connected to the Miller clamping pin through an auxiliary Miller clamping circuit. There is no risk that the Miller clamping cannot be triggered. Each parallel second switch transistor discharges the crosstalk current through the low-impedance loop of the auxiliary Miller clamping circuit, playing a role in suppressing crosstalk and reducing the risk of arm-to-arm breakdown or device damage; the gates of the parallel second switch transistors are isolated from each other, and device damage will not be caused due to asynchronous switching of each other.

[0036] Figure 4 It is a schematic circuit diagram of another crosstalk suppression circuit in the embodiment of the present application, as Figure 4 shown, any one of the auxiliary Miller clamping circuits 103 includes: a first resistor, a second resistor, a first capacitor, and a third switch transistor;

[0037] The first end of each first resistor, the first end of the corresponding second resistor, and the first end of the corresponding third switch transistor are commonly connected to the built-in Miller clamping 1041 of the driving chip 104;

[0038] The second end of each first resistor, the first end of the corresponding first capacitor, and the second end of the corresponding third switch transistor are commonly connected to the gate of the corresponding second switch transistor 102;

[0039] The second end of each second resistor and the second end of the corresponding first capacitor are commonly connected to the third end of the corresponding third switch transistor.

[0040] Among them, the first resistor in the upper arm driving circuit 11 can be represented as R 1 , the second resistor can be represented as R 2 , the first capacitor can be represented as C 1 , and the third switch transistor can be represented as T 1 ; the first resistor in the lower arm driving circuit 12 can be represented as R 3 , the second resistor can be represented as R 4 , the first capacitor can be represented as C 2, the third switching transistor can be represented as T 2 .

[0041] Wherein, the third switching transistor is any one of a triode, a MOSFET, a JFET junction field effect transistor, and an IGBT insulated gate bipolar transistor; the resistance value of the first resistor is greater than a preset resistance threshold value; the third switching transistor of any one of the auxiliary Miller clamp circuits 103 is used to discharge the crosstalk current of the switching transistor of the corresponding bridge arm drive circuit when it is turned on.

[0042] When the third switching transistor is a triode, in the upper bridge arm drive circuit 11, when crosstalk occurs, since a weak current flows into the Miller clamp pin, a voltage drop is generated between the emitter and the base of the auxiliary triode T 1 . When the voltage drop of R 1 is greater than the forward bias voltage of the emitter of the auxiliary triode T 1 , the auxiliary triode T 1 is turned on, and the second switching transistor Q n can discharge the crosstalk current through the auxiliary triode T 1 ; in the lower bridge arm drive circuit 12, when the voltage drop of R 3 is greater than the forward bias voltage of the emitter of the auxiliary triode T 2 , the auxiliary triode T 2 is turned on, and the second switching transistor Q m can discharge the crosstalk current through the auxiliary triode T 2 .

[0043] Wherein, the driving chip is used to control, in the first time period, the driving signal of the lower bridge arm drive circuit / the upper bridge arm drive circuit to change from high level to low level; control the first switching transistor and at least one second switching transistor of the upper bridge arm drive circuit / the lower bridge arm drive circuit to turn off; in the second time period, control the first switching transistor and at least one of the second switching transistors of any bridge arm drive circuit to remain off; in the third time period, control the driving signal of the upper bridge arm drive circuit / the lower bridge arm drive circuit to change from low level to high level; in the fourth time period, control the driving signal of the upper bridge arm drive circuit / the lower bridge arm drive circuit to change from high level to low level; in the fifth time period, control the first switching transistor and at least one of the second switching transistors of any bridge arm drive circuit to remain off; in the sixth time period, control the driving signal of the lower bridge arm drive circuit / the upper bridge arm drive circuit to change from low level to high level.

[0044] Taking the lower transistors Q2 to Qn in the lower bridge arm drive circuit as an example to illustrate the working principle of the parallel switching transistors:

[0045] As Figure 5 shown, Vgs1 is the upper transistor Q 1The voltage between the gate and the source of, Vgs2 is for the upper transistor Q 2 The voltage between the gate and the source of, Vgsm is for the lower transistor Q m The voltage between the gate and the source of, Vds_Q2 is for the lower transistor Q 2 The voltage between the drain and the source; The first period can be from t 0 to t 1 period. At t 0 to t 1 period, the drive signal Vg2 of the lower transistor Q 2 to Q n changes from high level to low level. When the gate voltage Vgs2 of Q 2 is lower than its threshold voltage, Q 2 turns off, and the built-in Miller clamp 1041 of the drive chip 104 is triggered.

[0046] The second period can be from t 1 to t 2 period. The t 1 to t 2 period is the dead time period. During the dead time period, both the lower transistor and the upper transistor remain off.

[0047] The third period can include the t 2 to t 3 period, the t 3 to t 4 period and the t 4 to t 5 period; At t 2 to t 3 period, the gate drive signal of the upper transistor Q 1 to Q n changes from low level to high level, Q1 turns on, crosstalk current appears, and charges Cgd2. Since the Miller clamp pin is in the triggered state at this time, the drive chip provides a low-impedance loop. Therefore, the change amplitude of the gate voltage Vgs2 of Q 2 is small. For the parallel devices Q m , at this time, the auxiliary triode T 2 has not conducted yet, and there is a weak current on R 3 flowing from Q m into the Miller clamp pin through the auxiliary Miller clamp circuit; At t 3 to t 4 period, the voltage drop on R 3 is greater than the emitter forward bias voltage of T 2 , T 2 conducts, and the potential from the gate of Q m to the Miller clamp pin is quickly pulled low, and the Miller clamp of Q m is formed; At t 4 to t 5During the period, Q 1 is in the conducting state, and Q 2 is in the off state.

[0048] The fourth period can be from t 5 to t 6 period. At the moment of t 5 , the gate drive signal changes from high level to low level, and the crosstalk current discharges Cgd2. After the gate voltage oscillation caused by crosstalk from Q 1 ends until t 2 to Q m , since the lower transistor drive signal changes from low level to high level, the gate voltage of Q 6 rises and the Miller clamp pin is closed. 2 The Miller clamp pin is closed.

[0049] The fifth period can be the dead time period after the moment of t 6 . The sixth period can be from t 6 to t 7 period. The gate voltage Vgs2 of Q 2 changes from low level to high level. Since the Miller clamp pin has been closed, the auxiliary Miller clamp circuit 103 will not work, and the rising speed of the current and the falling speed of the voltage from Q 2 to Q m will not slow down.

[0050] The working principle of the upper transistor Q 1 to Q n in the upper bridge arm drive circuit is exactly the same as that of the lower transistor, which is omitted here.

[0051] Based on the above analysis, the Miller clamp is triggered by the gate voltage of Q 1 or Q 2 . Since they are directly connected, effective triggering of the Miller clamp can be ensured. And the parallel-connected Q n or Q m can discharge the crosstalk current through T 1 or R 3 when the voltage drop across R 1 or T 2 is greater than the forward bias voltage of the emitter of the auxiliary triode T n or Q m . Therefore, it can play a role in suppressing crosstalk. During the turn-on and turn-off processes of Q 1 or T 2 or Q 1 or Q 2 , the auxiliary Miller clamp circuit does not work. Therefore, the switching speed of the MOSFET at the upper and lower transistor positions is not affected.

[0052] In addition, since R 1 or R 3has a relatively large resistance (several thousand ohms), Q 1 and Q n between, Q 2 and Q m do not affect each other during the turn-on and turn-off processes, and can be respectively controlled by their own gate resistors R g Control, and the turn-on and turn-off synchronization and dynamic current sharing can be achieved by adjusting their respective Rg.

[0053] In the embodiments of the present application, the gate of the first switching tube is short-circuited with the Miller clamping pin to trigger the built-in Miller clamping of the driving chip. The second switching tubes connected in parallel with the first switching tube are connected to the Miller clamping pin through an auxiliary Miller clamping circuit, so there is no risk that the Miller clamping cannot be triggered. The crosstalk current of the parallel second switching tubes is discharged through the low-impedance loop of the auxiliary Miller clamping circuit, reducing the risk of arm shoot-through or device damage; the gates of the parallel second switching tubes are isolated from each other, and device damage will not be caused due to asynchronous switching of each other. After the voltage drop across the first resistor of the second switching tube connected in parallel with the first switching tube is greater than the forward bias voltage of the third switching tube, the crosstalk current can be discharged through the third switching tube.

[0054] In some embodiments, as Figure 4 shown, any arm driving circuit further includes: a third resistor 112 corresponding to the first switching tube and a fourth resistor 122 corresponding to each second switching tube 102;

[0055] The third resistor 112 is the gate resistor of the first switching tube 101, and the resistance value of the third resistor 112 is adjusted within a first resistance value range;

[0056] Each fourth resistor 122 is the gate resistor of the corresponding second switching tube 102, and the resistance value of the fourth resistor 122 is adjusted within a second resistance value range;

[0057] Wherein, the turn-on and / or turn-off of the first switching tube and at least one second switching tube in any arm driving circuit are synchronized.

[0058] Wherein, since the resistance values of R1 or R3 are relatively large (several thousand ohms), the first switching tube Q of the upper arm driving circuit 11 1 and the second switching tube Q n between, the first switching tube Q of the lower arm driving circuit 12 2 and the second switching tube Q m do not affect each other during the turn-on and turn-off processes, and can be respectively controlled by their own gate resistors (also known as gate resistors) Rg.

[0059] In the embodiments of the present application, the gates of the parallel-connected switching tubes are not directly shorted to each other, and the switching-on and switching-off speeds can be adjusted separately. The switching-on and switching-off synchronization and dynamic current sharing can be achieved by adjusting the resistance values of the respective switching tube Rg.

[0060] In some embodiments, during the switching-on and / or switching-off process of the first switching tube of any bridge arm driving circuit, the auxiliary Miller clamping circuit corresponding to at least one of the second switching tubes of the corresponding bridge arm driving circuit does not work.

[0061] In the embodiments of the present application, during the switching-on and switching-off process of Q1 or Q2, the auxiliary Miller clamping circuit does not work. Therefore, the switching speed of the MOSFETs at the upper and lower tube positions is not affected and remains unchanged.

[0062] In the related art, crosstalk suppression of parallel-connected switching tubes can be achieved by the following methods:

[0063] In one method, as Figure 6 shown, a capacitor C 1 can be connected in parallel between the gate g and the source s of the first switching tube Q 1 . A capacitor C 1 can be connected in parallel between the gate g and the source s of the second switching tube Q 2 connected in parallel with the first switching tube Q n . With the crosstalk current remaining unchanged, a smaller dv / dt is achieved by increasing the gate capacitance, thereby achieving the effect of reducing the voltage change. However, the additional parallel capacitor will slow down the switching speed, thus increasing the switching loss of silicon carbide.

[0064] In another method, as Figure 7 shown, Miller clamping is achieved by directly connecting the gates of the parallel MOSFETs to the built-in Miller clamping pins of the driver chip. During the device turn-off period, the internal MOSFET of the chip is always in the conducting state, thereby pulling down the voltage Vgs1 between g and s1(s) to play a clamping role. If the chip is an external Miller clamp, PNP or NPN transistors, P-type MOSFETs or N-type MOSFETs need to be added, which is also called the direct connection method here. When this direct connection method is applied to parallel MOSFETs, there are some problems that lead to an unsatisfactory actual clamping effect: the transmission paths from the driver chip to MOSFET1 (i.e., Q 1 ) to MOSFET n (i.e., Q n ) gates are different, and the gate drive turn-on and turn-off resistance values of MOSFET 1 to MOSFET n are different. The switching of MOSFET 1 to MOSFET n is significantly asynchronous, and the Miller clamp is forced to turn on, resulting in damage to the MOSFET.

[0065] In yet another method, asFigure 8 As shown, the crosstalk suppression circuit includes: auxiliary Miller clamping circuits 801 to 803, driving power amplification devices 811 to 813, a DC power supply 82, a driving chip 83, a built-in Miller clamping circuit 831 of the driving chip 83, resistors Rg81 to Rg83, and switching transistors Q81 to Q83. An auxiliary Miller clamping circuit is added between the gate of each switching transistor and the built-in Miller clamping pin to suppress the crosstalk of each MOSFET. When crosstalk occurs, since a weak current flows into the Miller clamping pin, a voltage drop is generated between the emitter and the base of the auxiliary triode. When this voltage exceeds the forward bias voltage of the triode, the triode conducts, and the crosstalk current is directly discharged to the negative power supply through the triode. However, in this method, the gates of each MOSFET are connected to the Miller clamping pin through large resistors, especially when the switching frequency is high, the Miller clamping function is too late to be triggered.

[0066] In another method, as Figure 9 shown, the crosstalk suppression circuit includes: auxiliary Miller clamping circuits 901 to 903, a capacitor C91, a triode T91, a diode D91, driving power amplification devices 911 to 913, a driving chip 93, a built-in Miller clamping circuit 931 of the driving chip 93, and switching transistors Q91 to Q93. However, in this method, the gates of each MOSFET are also connected to the Miller clamping pin through large resistors, especially when the switching frequency is high, the Miller clamping function is too late to be triggered.

[0067] The crosstalk suppression circuit proposed in the embodiment of the present application, as Figure 4 shown, has no risk that the Miller clamping function cannot be triggered; each parallel MOSFET can discharge the crosstalk current through a low-impedance loop; during the turn-on and turn-off processes of each silicon carbide MOSFET, the auxiliary Miller clamping circuit does not work, and the switching speed can remain unchanged; the gates of each parallel silicon carbide MOSFET are not directly short-circuited to each other, and the switching speed can be adjusted separately.

[0068] The embodiment of the present application also provides a crosstalk suppression method, and the method may include the following steps:

[0069] Step S102: When the first switch tube and at least one second switch tube in the lower arm driving circuit / the upper arm driving circuit are in the off state, and the first switch tube in the upper arm driving circuit / the lower arm driving circuit is driven by the driving chip and is converted from the off state to the on state; or;

[0070] When the first switch tube and at least one second switch tube in the lower arm driving circuit / the upper arm driving circuit are in the off state, and the first switch tube in the upper arm driving circuit / the lower arm driving circuit is driven by the driving chip and is converted from the on state to the off state:

[0071] The second switch tube of the lower arm drive circuit / upper arm drive circuit discharges the crosstalk current of the corresponding second switch tube through the corresponding auxiliary Miller clamping circuit.

[0072] As Figure 1 shown, the drain d of the first switch tube 101 is connected to the drain d of at least one of the second switch tubes 102; the source s of the first switch tube 101 is connected to the source s of at least one of the second switch tubes 102; the gate g of the first switch tube 101 is connected to the built-in Miller clamp 1041 of the drive chip 104; the gate g of at least one of the second switch tubes 102 is connected to one end of the corresponding auxiliary Miller clamping circuit 103; the other end of each auxiliary Miller clamping circuit 103 is connected to the built-in Miller clamp 1041 of the drive chip 104.

[0073] In the embodiment of the present application, the gate of the first switch tube is short-circuited with the Miller clamp pin to trigger the built-in Miller clamp of the drive chip. The other second switch tubes connected in parallel with the first switch tube are connected to the Miller clamp pin through the auxiliary Miller clamping circuit. There is no risk that the Miller clamp cannot be triggered. The crosstalk current of each parallel second switch tube is discharged through the low-impedance loop of the auxiliary Miller clamping circuit, which plays a role in suppressing crosstalk and reduces the risk of arm breakdown or device damage; the gates of the parallel second switch tubes are isolated from each other, and the device will not be damaged due to asynchronous switching.

[0074] In some embodiments, in the first time period, control the drive signal of the lower arm drive circuit / upper arm drive circuit to change from high level to low level; control the first switch tube and at least one second switch tube of the upper arm drive circuit / lower arm drive circuit to turn off; in the second time period, control the first switch tube and at least one of the second switch tubes of any arm drive circuit to remain off; in the third time period, control the drive signal of the upper arm drive circuit / lower arm drive circuit to change from low level to high level; in the fourth time period, control the drive signal of the upper arm drive circuit / lower arm drive circuit to change from high level to low level; in the fifth time period, control the first switch tube and at least one of the second switch tubes of any arm drive circuit to remain off; in the sixth time period, control the drive signal of the lower arm drive circuit / upper arm drive circuit to change from low level to high level.

[0075] In some embodiments, any one of the auxiliary Miller clamping circuits includes: a first resistor, a second resistor, a first capacitor, and a third switching transistor; wherein: the first ends of each of the first resistors, the corresponding first ends of the second resistors, and the corresponding first ends of the third switching transistors are commonly connected to the built-in Miller clamping of the driving chip; the second ends of each of the first resistors, the corresponding first ends of the first capacitors, and the corresponding second ends of the third switching transistors are commonly connected to the gates of the corresponding second switching transistors; the second ends of each of the second resistors and the corresponding second ends of the first capacitors are commonly connected to the third ends of the corresponding third switching transistors.

[0076] In some embodiments, the resistance value of the first resistor is greater than a preset resistance threshold value; the third switching transistor of any one of the auxiliary Miller clamping circuits is configured to discharge the crosstalk current of the switching transistor of the corresponding bridge arm driving circuit when it is turned on.

[0077] In some embodiments, the first switching transistor or the second switching transistor is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor); the third switching transistor is any one of a triode, a MOSFET, a JFET (Junction Field Effect Transistor), and an IGBT (Insulated Gate Bipolar Transistor).

[0078] In some embodiments, any one of the bridge arm driving circuits further includes: a third resistor corresponding to the first switching transistor and a fourth resistor corresponding to each of the second switching transistors; the third resistor is the gate resistor of the first switching transistor, and the resistance value of the third resistor is adjustable within a first resistance value range; each of the fourth resistors is the gate resistor of the corresponding second switching transistor, and the resistance value of the fourth resistor is adjustable within a second resistance value range; wherein, the turn-on and / or turn-off of the first switching transistor of any one of the bridge arm driving circuits is synchronized with at least one of the second switching transistors.

[0079] In some embodiments, during the turn-on and / or turn-off process of the first switching transistor of any one of the bridge arm driving circuits, the auxiliary Miller clamping circuit corresponding to at least one of the second switching transistors of the corresponding bridge arm driving circuit does not work.

[0080] In some embodiments, the driving chip is configured to control, through a driving signal, the first switching transistor and at least one second switching transistor of the lower bridge arm driving circuit / the upper bridge arm driving circuit to be in an off state; the driving chip is further configured to control, through a driving signal, the first switching transistor of the upper bridge arm driving circuit / the lower bridge arm driving circuit to be switched from an off state to an on state; the driving chip is further configured to control, through a driving signal, the first switching transistor of the upper bridge arm driving circuit / the lower bridge arm driving circuit to be switched from a conducting state to an off state.

[0081] It should be noted here that the description of the above method embodiments is similar to that of the above circuit embodiments and has similar beneficial effects to those of the circuit embodiments. For the technical details not disclosed in the method embodiments of the present application, please refer to the description of the circuit embodiments of the present application for understanding.

[0082] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the order numbers of the above processes do not mean the order of execution is prior or posterior, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0083] It should be noted that in this text, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0084] In several embodiments provided by the present application, it should be understood that the disclosed circuits and methods can be implemented in other ways. The circuit embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling or communication connection between the components shown or discussed with each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0085] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in each embodiment of the present application, each functional unit can be fully integrated into one processing unit, or each unit can be separately used as one unit, or two or more units can be integrated into one unit; the above integrated units can be implemented in the form of hardware or in the form of a combination of hardware and software functional units.

[0086] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: removable storage devices, read-only memory (ROM), magnetic disks or optical discs, and other various media that can store program codes. Alternatively, if the above integrated units of the present application are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a laundry device to execute all or part of the methods described in the various embodiments of the present application. And the foregoing storage medium includes: removable storage devices, ROM, magnetic disks or optical discs, and other various media that can store program codes.

[0087] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0088] As described above, only the embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A crosstalk suppression circuit, characterized in that, the circuit includes: an upper bridge arm driving circuit and a lower bridge arm driving circuit. Any one of the bridge arm driving circuits includes a first switching tube, at least one second switching tube, an auxiliary Miller clamping circuit corresponding to each of the second switching tubes, and a driving chip; wherein: the drain of the first switching tube is connected to the drains of at least one of the second switching tubes; the source of the first switching tube is connected to the sources of at least one of the second switching tubes; the gate of the first switching tube is connected to the built-in Miller clamping of the driving chip; the gates of at least one of the second switching tubes are connected to one end of the corresponding auxiliary Miller clamping circuit; the other end of each of the auxiliary Miller clamping circuits is connected to the built-in Miller clamping of the driving chip; wherein, the auxiliary Miller clamping circuit corresponding to any one of the second switching tubes in any one of the bridge arm driving circuits is used to discharge the crosstalk current of the corresponding second switching tube.

2. The circuit according to claim 1, characterized in that, any one of the auxiliary Miller clamping circuits includes: a first resistor, a second resistor, a first capacitor and a third switching tube; wherein: the first ends of each of the first resistors, the first ends of the corresponding second resistors, and the first ends of the corresponding third switching tubes are commonly connected to the built-in Miller clamping of the driving chip; the second ends of each of the first resistors, the first ends of the corresponding first capacitors, and the second ends of the corresponding third switching tubes are commonly connected to the gates of the corresponding second switching tubes; the second ends of each of the second resistors and the second ends of the corresponding first capacitors are commonly connected to the third ends of the corresponding third switching tubes.

3. The circuit according to claim 2, characterized in that, the resistance value of the first resistor is greater than a preset resistance threshold value; the third switching tube of any one of the auxiliary Miller clamping circuits is used to discharge the crosstalk current of the switching tube of the corresponding bridge arm driving circuit when it is turned on.

4. The circuit according to claim 2, characterized in that, the first switching tube or the second switching tube is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor); the third switching tube is any one of a triode, a MOSFET, a JFET (Junction Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor).

5. The circuit according to claim 2, characterized in that, any one of the bridge arm driving circuits further includes: a third resistor corresponding to the first switching tube and a fourth resistor corresponding to each of the second switching tubes; the third resistor is the gate resistor of the first switching tube, and the resistance value of the third resistor is adjusted within a first resistance range; each of the fourth resistors is the gate resistor of the corresponding second switching tube, and the resistance value of the fourth resistor is adjusted within a second resistance range; wherein, the turning on and / or off of the first switching tube and at least one of the second switching tubes in any one of the bridge arm driving circuits are synchronized.

6. The circuit according to any one of claims 1 to 5, characterized in that, during the turning on and / or off process of the first switching tube in any one of the bridge arm driving circuits, the auxiliary Miller clamping circuit corresponding to at least one of the second switching tubes in the corresponding bridge arm driving circuit does not work.

7. The circuit according to any one of claims 1 to 5, characterized in that, The driving chip is used to control, by a driving signal, the first switch and at least one second switch in the lower arm driving circuit / the upper arm driving circuit to be in an off state; The driving chip is further used to control, by a driving signal, the first switch in the upper arm driving circuit / the lower arm driving circuit to be switched from an off state to an on state; The driving chip is further used to control, by a driving signal, the first switch in the upper arm driving circuit / the lower arm driving circuit to be switched from a conducting state to an off state.

8. The circuit according to claim 7, wherein, the driving chip is used for: in a first period, controlling the driving signal of the lower arm driving circuit / the upper arm driving circuit to change from a high level to a low level; controlling the first switch and at least one second switch in the upper arm driving circuit / the lower arm driving circuit to be turned off; in a second period, controlling the first switch and at least one second switch in any one of the arm driving circuits to remain off; in a third period, controlling the driving signal of the upper arm driving circuit / the lower arm driving circuit to change from a low level to a high level; in a fourth period, controlling the driving signal of the upper arm driving circuit / the lower arm driving circuit to change from a high level to a low level; in a fifth period, controlling the first switch and at least one second switch in any one of the arm driving circuits to remain off; in a sixth period, controlling the driving signal of the lower arm driving circuit / the upper arm driving circuit to change from a low level to a high level.

9. A crosstalk suppression method, wherein, it is applied to a crosstalk suppression circuit, the circuit including: an upper arm driving circuit and a lower arm driving circuit, any one of the arm driving circuits including a first switch, at least one second switch, an auxiliary Miller clamping circuit corresponding to each second switch, and a driving chip; wherein, the drain of the first switch is connected to the drains of at least one second switch; the source of the first switch is connected to the sources of at least one second switch; the gate of the first switch is connected to the built-in Miller clamping of the driving chip; the gates of at least one second switch are connected to one end of the corresponding auxiliary Miller clamping circuit; the other end of each auxiliary Miller clamping circuit is connected to the built-in Miller clamping of the driving chip; the method includes: when the first switch and at least one second switch in the lower arm driving circuit / the upper arm driving circuit are in an off state, and the first switch in the upper arm driving circuit / the lower arm driving circuit is driven by the driving chip to be switched from an off state to an on state; or; when the first switch and at least one second switch in the lower arm driving circuit / the upper arm driving circuit are in an off state, and the first switch in the upper arm driving circuit / the lower arm driving circuit is driven by the driving chip to be switched from a conducting state to an off state: The second switch tube of the lower arm driving circuit / the upper arm driving circuit discharges the crosstalk current of the corresponding second switch tube through the corresponding auxiliary Miller clamping circuit.

10. The method according to claim 9, wherein, the method further includes: In the first period, controlling the driving signal of the lower arm driving circuit / the upper arm driving circuit to change from high level to low level; controlling the first switch tube and at least one second switch tube of the upper arm driving circuit / the lower arm driving circuit to turn off; In the second period, controlling the first switch tube and at least one of the second switch tubes of any one of the arm driving circuits to remain off; In the third period, controlling the driving signal of the upper arm driving circuit / the lower arm driving circuit to change from low level to high level; In the fourth period, controlling the driving signal of the upper arm driving circuit / the lower arm driving circuit to change from high level to low level; In the fifth period, controlling the first switch tube and at least one of the second switch tubes of any one of the arm driving circuits to remain off; In the sixth period, controlling the driving signal of the lower arm driving circuit / the upper arm driving circuit to change from low level to high level.

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