Relaxation oscillator and method for self-calibration thereof

Abstract

The application provides a relaxation oscillator and a self-calibration method thereof. The first adjusting circuit and the second adjusting circuit are arranged in the relaxation oscillator. When the clock signal is high, the first adjusting circuit provides the first adjusting signal to the first amplifier, and the second adjusting circuit stores the self-offset voltage. When the clock signal is low, the second adjusting circuit provides the second adjusting signal to the first amplifier, and the first adjusting circuit stores the self-offset voltage. The self-offset voltage of the first adjusting circuit and the second adjusting circuit is collected to generate the corresponding first adjusting signal and the second adjusting signal, so as to compensate the input voltage of the first amplifier when the clock signal is high and low respectively, thereby reducing the offset voltage of the first amplifier, improving the output stability of the first amplifier, realizing the self-calibration of the offset voltage of the relaxation oscillator, and ensuring the frequency stability of the clock signal.

Description

Technical Field

[0001] This invention relates to the field of oscillator technology, and in particular to a relaxation oscillator and its self-calibration method. Background Technology

[0002] Relaxation oscillators are common circuits in modern electronic systems, widely used in fields such as radio, telecommunications, and computers to generate stable clock signals, which are then divided and provided to other synchronization circuits. A relaxation oscillator typically includes a resistor-capacitor (RC) circuit. The clock signal is generated by charging and discharging the capacitor through the RC circuit, and the frequency of the clock signal is changed by altering the time constant of the RC circuit.

[0003] Figure 1 The circuit shown is a simplified circuit diagram of an existing relaxation oscillator. The relaxation oscillator includes a first current source I1, a second current source I2, a resistor R, a first capacitor C1, an NMOS transistor M, and an amplifier AMP. The first current source I1 provides a constant voltage Vref, connected to the inverting input terminal INN of the amplifier AMP. The second current source I2 provides an input voltage and is connected to the non-inverting input terminal INP of the amplifier AMP. The amplifier AMP outputs a clock signal CK, which is supplied to the gate of the NMOS transistor M. When the voltage at INP is lower than that at INN, the amplifier AMP outputs a low level (CK-), the NMOS transistor M is turned off, current charges capacitor C1, and the voltage at INP gradually increases. When the voltage at INP is higher than that at INN, the amplifier AMP outputs a high level (CK+), the NMOS transistor M is turned on, capacitor C1 discharges, and the voltage at INP gradually decreases until it falls below that at INN, thus forming a periodic oscillation. This process repeats continuously, and the amplifier AMP outputs a square wave clock signal CK.

[0004] However, due to the influence of CMOS technology, the amplifier AMP will have a large offset voltage, and the offset voltage is greatly affected by PVT conditions. This will cause the INP terminal flip voltage value to change, resulting in a change in the frequency of the output square wave signal.

[0005] Therefore, there is an urgent need for a new relaxation oscillator to reduce offset voltage and improve the output stability of the relaxation oscillator. Summary of the Invention

[0006] The purpose of this invention is to provide a relaxation oscillator and its self-calibration method to solve at least one of the problems of how to reduce offset voltage and how to improve output stability.

[0007] To solve the above-mentioned technical problems, the present invention provides a relaxation oscillator, comprising: a main oscillator circuit, a first adjustment circuit, and a second adjustment circuit;

[0008] The master oscillator circuit is used to generate clock signals;

[0009] The first adjustment circuit is configured to provide a first adjustment signal to the main oscillation circuit when the clock signal is high; and to store the offset voltage of the first adjustment circuit when the clock signal is low.

[0010] The second adjustment circuit is configured to store the offset voltage of the second adjustment circuit when the clock signal is high; and to provide a second adjustment signal to the main oscillation circuit when the clock signal is low.

[0011] The first adjustment signal is generated based on the offset voltage of the first adjustment circuit, and the second adjustment signal is generated based on the offset voltage of the second adjustment circuit.

[0012] Optionally, in the relaxation oscillator, the main oscillator circuit includes a first current source, a second current source, and a first amplifier; wherein,

[0013] The first amplifier has a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal; the first input terminal is connected to the second current source to receive an input voltage; the second input terminal is connected to the first current source to receive a reference voltage; the third input terminal and the fourth input terminal are connected to the first adjustment circuit or the second adjustment circuit.

[0014] Optionally, in the relaxation oscillator, the main oscillator circuit further includes a resistor, a first capacitor, and an NMOS transistor; the output terminal of the first current source is connected to one end of the resistor, and the other end of the resistor is connected to ground; one end of the first capacitor is connected to the output terminal of the second current source and the drain of the NMOS transistor, and the other end of the first capacitor is connected to the source of the NMOS transistor and connected to ground; the gate of the NMOS transistor is connected to the output terminal of the first amplifier to receive a clock signal.

[0015] Optionally, in the relaxation oscillator, the first adjustment circuit includes a second amplifier, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch;

[0016] The second amplifier has a fifth input terminal, a sixth input terminal, a seventh input terminal, and an eighth input terminal; the fifth input terminal is connected to the output terminal of the second current source to receive the input voltage; a second switch is connected between the sixth input terminal and the first current source; a first switch is connected between the fifth input terminal and the sixth input terminal; a fifth switch is connected between the seventh input terminal and the output terminal of the second amplifier; a second capacitor is connected between the seventh input terminal and the sixth input terminal; a third switch is connected between the eighth input terminal and the third input terminal; a fourth switch is connected between the output terminal of the second amplifier and the fourth input terminal; and a sixth switch is connected between the eighth input terminal and the sixth input terminal.

[0017] Optionally, in the relaxation oscillator, when the clock signal is high, the second switch, the third switch, and the fourth switch are closed; the first switch, the fifth switch, and the sixth switch are open, so that the second capacitor is discharged, and the output terminal of the second amplifier outputs the first adjustment signal to the fourth input terminal;

[0018] When the clock signal is low, the first switch, the fifth switch, and the sixth switch are closed; the second switch, the third switch, and the fourth switch are open, so that the second capacitor is charged, and the output voltage of the second amplifier is the offset voltage of the first adjustment circuit.

[0019] Optionally, in the relaxation oscillator, the second adjustment circuit includes a third amplifier, a third capacitor, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch.

[0020] The third amplifier has a ninth input terminal, a tenth input terminal, an eleventh input terminal, and a twelfth input terminal; the ninth input terminal is connected to the output terminal of the second current source to receive the input voltage; the tenth input terminal is connected to the first current source via the eighth switch; the ninth input terminal is connected to the tenth input terminal via the seventh switch; the eleventh input terminal is connected to the output terminal of the third amplifier via the eleventh switch; the eleventh input terminal is connected to the tenth input terminal via the third capacitor; the twelfth input terminal is connected to the third input terminal via the ninth switch; the output terminal of the third amplifier is connected to the fourth input terminal via the tenth switch; and the twelfth input terminal is connected to the ninth input terminal via the twelfth switch.

[0021] Optionally, in the relaxation oscillator, when the clock signal is high, the seventh switch, the eleventh switch, and the twelfth switch are closed; the eighth switch, the ninth switch, and the tenth switch are open, so that the third capacitor is charged, and the output voltage of the third amplifier is the offset voltage of the second adjustment circuit.

[0022] When the clock signal is low, the eighth, ninth, and tenth switches are closed; the seventh, eleventh, and twelfth switches are open, so that the third capacitor is discharged, and the output terminal of the third amplifier outputs the second adjustment signal to the fourth input terminal.

[0023] Optionally, in the relaxation oscillator, the third input terminal is connected to a fourth capacitor and then to a ground terminal; the third input terminal is also connected to a fifth capacitor and then to a ground terminal.

[0024] Optionally, in the relaxation oscillator, the sixth capacitor and the seventh capacitor are also connected in parallel between the third input terminal and the fourth input terminal.

[0025] Based on the same inventive concept, the present invention also provides a self-calibration method for a relaxation oscillator, comprising:

[0026] When the clock signal generated by the main oscillator circuit is high, the first adjustment circuit provides a first adjustment signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; and the second adjustment circuit stores the offset voltage of the second adjustment circuit.

[0027] When the clock signal generated by the main oscillator circuit is low, the second adjustment circuit provides a second adjustment signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; and the first adjustment circuit stores the offset voltage of the first adjustment circuit.

[0028] The first adjustment signal is generated based on the offset voltage of the first adjustment circuit, and the second adjustment signal is generated based on the offset voltage of the second adjustment circuit.

[0029] In summary, this invention provides a relaxation oscillator and its self-calibration method. Specifically, this invention incorporates a first adjustment circuit and a second adjustment circuit into the relaxation oscillator. When the clock signal is high, the first adjustment circuit provides a first adjustment signal to the first amplifier in the main oscillator circuit, and the second adjustment circuit stores its own offset voltage. When the clock signal is low, the second adjustment circuit provides a second adjustment signal to the first amplifier in the main oscillator circuit, and the first adjustment circuit stores its own offset voltage. Therefore, this invention, by acquiring the offset voltages of the first and second adjustment circuits, generates corresponding first and second adjustment signals to compensate the input voltage of the first amplifier when the clock signal is high and low, respectively. This reduces the offset voltage of the first amplifier, improves its output stability, achieves self-calibration of the relaxation oscillator's offset voltage, and ensures the frequency stability of the clock signal. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a relaxation oscillator in the prior art.

[0031] Figure 2 Circuit diagram of the relaxation oscillator in an embodiment of the present invention.

[0032] Figure 3 A schematic diagram of the connection of the relaxation oscillator when the clock signal is high level in an embodiment of the present invention.

[0033] Figure 4 A schematic diagram of the connection of the relaxation oscillator when the clock signal is low in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0035] Please see Figure 2This embodiment provides a relaxation oscillator, including: a main oscillator circuit, a first adjustment circuit, and a second adjustment circuit; the main oscillator circuit is used to generate a clock signal; the first adjustment circuit is used to provide a first adjustment signal to the main oscillator circuit when the clock signal is high; and to store the offset voltage of the first adjustment circuit when the clock signal is low; the second adjustment circuit is used to store the offset voltage of the second adjustment circuit when the clock signal is high; and to provide a second adjustment signal to the main oscillator circuit when the clock signal is low; wherein the first adjustment signal is generated based on the offset voltage of the first adjustment circuit, and the second adjustment signal is generated based on the offset voltage of the second adjustment circuit.

[0036] As can be seen, the present invention generates corresponding first and second adjustment signals by acquiring the offset voltages of the first and second adjustment circuits, respectively, to compensate the input voltage of the main oscillator circuit when the clock signal is high and low, thereby reducing the offset voltage in the main oscillator circuit, realizing self-calibration of the offset voltage of the relaxation oscillator, and ensuring the frequency stability of the clock signal.

[0037] The following is in conjunction with the appendix Figure 2-4 This embodiment provides a detailed description of the relaxation oscillator.

[0038] Please see Figure 2 The main oscillator circuit includes a first current source I1, a second current source I2, and a first amplifier A1. The first amplifier A1 has a first input terminal a1, a second input terminal a2, a third input terminal a3, and a fourth input terminal a4. The first input terminal a1 is connected to the second current source I2 to receive an input voltage Vin. The second input terminal a2 is connected to the first current source I1 to receive a reference voltage Vref. The third input terminal a3 and the fourth input terminal a4 are connected to either the first adjustment circuit or the second adjustment circuit. Further, the main oscillator circuit also includes a resistor R, a first capacitor C1, and an NMOS transistor M. The output terminal of the first current source I1 is connected to one end of the resistor R, and the other end of the resistor R is connected to ground. One end of the first capacitor C1 is connected to the output terminal of the second current source I2 and the drain of the NMOS transistor M, and the other end of the first capacitor C1 is connected to the source of the NMOS transistor M and connected to the ground terminal; the gate of the NMOS transistor M is connected to the output terminal of the first amplifier A1 to receive the clock signal CK.

[0039] Furthermore, when the input voltage Vin is lower than the reference voltage Vref, the clock signal output by the first amplifier A1 is low (CK-), the NMOS transistor M is turned off, the output current of the second current source I2 charges the first capacitor C1, and the voltage at the first input terminal a1 gradually increases. When the input voltage Vin rises to a level greater than the reference voltage Vref, the clock signal output by the first amplifier A1 is high (CK+), the NMOS transistor M is turned on, the first capacitor C1 discharges, and the voltage at the first input terminal a1 gradually decreases until the input voltage Vin is lower than the reference voltage Vref, thus forming one cycle of oscillation in the main oscillator circuit.

[0040] To prevent the clock signal CK output by the main oscillator circuit from becoming unstable due to offset voltage, the relaxation oscillator provided in this embodiment also includes a first adjustment circuit and a second adjustment circuit. Please continue reading. Figure 2 The first adjustment circuit includes a second amplifier A2, a second capacitor C2, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, and a sixth switch K6. The second amplifier A2 has a fifth input terminal b1, a sixth input terminal b2, a seventh input terminal b3, and an eighth input terminal b4. The fifth input terminal b1 is connected to the output terminal of the second current source I2 to receive the input voltage Vin. The sixth input terminal b2 is connected to the first current source I1 via the second switch K2. The fifth input terminal b1 is connected to the sixth input terminal b2 via the first switch K1. The seventh input terminal b3 is connected to the output terminal of the second amplifier A2 via the fifth switch K5. The seventh input terminal b3 is connected to the sixth input terminal b2 via the second capacitor C2. The eighth input terminal b4 is connected to the third input terminal a3 of the first amplifier A1 via the third switch K3. The output terminal of the second amplifier A2 is connected to the fourth input terminal a4 of the first amplifier A1 via the fourth switch K4. The sixth switch K6 is connected between the eighth input terminal b4 and the sixth input terminal b2.

[0041] The second adjustment circuit includes a third amplifier A3, a third capacitor C3, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, and a twelfth switch K12. The third amplifier A3 has a ninth input terminal c1, a tenth input terminal c2, an eleventh input terminal c3, and a twelfth input terminal c4. The ninth input terminal c1 is connected to the output terminal of the second current source I2 to receive the input voltage Vin. The tenth input terminal c2 is connected to the first current source I1 via the eighth switch K8. The ninth input terminal c1 is connected to the tenth input terminal c2 via the seventh switch K7. The eleventh input terminal c3 is connected to the output terminal of the third amplifier A3 via the eleventh switch K11. The eleventh input terminal c3 is connected to the tenth input terminal c2 via the third capacitor C3. The twelfth input terminal c4 is connected to the twelfth input terminal c4 via the ninth switch K9. The tenth switch K10 is connected between the output terminal of the third amplifier A3 and the fourth input terminal a4 of the first amplifier A1. The twelfth input terminal c4 is connected between the twelfth input terminal c1 and the ninth input terminal c1.

[0042] Furthermore, a fourth capacitor C4 is connected to the third input terminal a3 of the first amplifier A1, and is also connected to ground. A fifth capacitor C5 is connected to the third input terminal, and is also connected to ground. A sixth capacitor C6 and a seventh capacitor C7 are also connected in parallel between the third input terminal a3 and the fourth input terminal a4 of the first amplifier A1.

[0043] Furthermore, the first amplifier A1, the second amplifier A2, and the third amplifier A3 are all four-input amplifiers and are of the same model. In the relaxation oscillator, the first amplifier A1 is the main amplifier, while the second amplifier A2 and the third amplifier A3 are auxiliary amplifiers. The clock signal CK output by the first amplifier A1 is not only the switching signal for the NMOS transistor M but also the control signal for switches K1-K12; the specific control process is detailed below.

[0044] Please see Figure 2 and 3When the clock signal is high (CK+), the second switch K2, the third switch K3, and the fourth switch K4 in the first adjustment circuit are closed; the first switch K1, the fifth switch K5, and the sixth switch K6 are open. It can be seen that the fifth input terminal b1 of the second amplifier A2 is connected to the input voltage Vin, and the sixth input terminal b2 is connected to the reference voltage Vref. The two ends of the second capacitor C2 are connected to the sixth input terminal b2 and the seventh input terminal b3, respectively. The eighth input terminal b4 is connected to the third input terminal a3, and the output terminal of the second amplifier A2 is connected to the fourth input terminal a4. At this time, the second capacitor C2 releases the previously stored offset voltage of the second amplifier A2, and generates the first adjustment signal based on this, which is input to the fourth input terminal a4 of the first amplifier A1 to compensate for the input voltage Vin of the first amplifier A1, thereby reducing the offset voltage of the first amplifier A1 and ensuring the stability of the output of the first amplifier A1.

[0045] Simultaneously, the seventh switch K7, the eleventh switch K11, and the twelfth switch K12 in the second adjustment circuit are closed; the eighth switch K8, the ninth switch K9, and the tenth switch K10 are open. It can be seen that the ninth input terminal c1 and the tenth input terminal c2 of the third amplifier A3 are short-circuited and both are connected to the input voltage Vin. The output terminal of the third amplifier A3 is connected to the third capacitor C3. At this time, because the ninth input terminal c1 and the tenth input terminal c2 are connected to the same signal, the voltage output by the third amplifier A3 is the offset voltage of the third amplifier A3, and the offset voltage is stored in the third capacitor C3.

[0046] Please see Figure 2 and 4 When the clock signal is low (CK-), the first switch K1, the fifth switch K5, and the sixth switch K6 in the first adjustment circuit are closed; the second switch K2, the third switch K3, and the fourth switch K4 are open. Therefore, the fifth input terminal b1 and the sixth input terminal b2 of the second amplifier A2 are short-circuited and both are connected to the input voltage Vin. The output terminal of the second amplifier A2 is connected to the second capacitor C2. At this time, because the fifth input terminal b1 and the sixth input terminal b2 are connected to the same signal, the voltage output by the second amplifier A2 is the offset voltage of the second amplifier A2, and this offset voltage is stored in the second capacitor C2.

[0047] Simultaneously, the eighth switch K8, the ninth switch K9, and the tenth switch K10 in the second adjustment circuit are closed. The seventh switch K7, the eleventh switch K11, and the twelfth switch K12 are open. It can be seen that the ninth input terminal c1 of the third amplifier A3 is connected to the input voltage Vin, and the tenth input terminal c2 is connected to the reference voltage Vref. The two ends of the third capacitor C3 are connected to the tenth input terminal c2 and the eleventh input terminal c3, respectively. The twelfth input terminal c4 is connected to the third input terminal a3, and the output terminal of the third amplifier A3 is connected to the fourth input terminal a4. At this time, the third capacitor C3 releases the previously stored offset voltage of the third amplifier A3, and generates the second adjustment signal based on this, which is input to the fourth input terminal a4 of the first amplifier A1 to compensate for the input voltage Vin of the first amplifier A1, thereby reducing the offset voltage of the first amplifier A1 and ensuring the stability of the output of the first amplifier A1.

[0048] It is understood that the first adjustment circuit and the second adjustment circuit provided in this embodiment constitute a ping-pong structure to adjust the offset voltage of the first amplifier A1 when the clock signal CK is at a high level and a low level, respectively, so as to alleviate the influence of the offset voltage on the output signal and ensure the high stability of the output signal frequency.

[0049] Furthermore, taking the third amplifier A3 as an example, assume that the received signal gain of the first input terminal a1 and the second input terminal a2 of the first amplifier A1 is Am; the received signal gain of the third input terminal a3 and the fourth input terminal a4 is Amn. The received signal gain of the fifth input terminal b1 and the sixth input terminal b2 of the second amplifier A2 is An, and the received signal gain of the seventh input terminal b3 and the eighth input terminal b4 is Ann. Similarly, the received signal gain of the ninth input terminal c1 and the tenth input terminal c2 of the third amplifier A3 is An, and the received signal gain of the eleventh input terminal c3 and the twelfth input terminal c4 is Ann.

[0050] When the clock signal is high (CK+), the third amplifier A3 is in the offset voltage storage stage, meaning the output voltage of the third amplifier A3 is its offset voltage. If the offset voltages of the ninth input terminal c1 and the tenth input terminal c2 are set to Vosn, and the offset voltages of the eleventh input terminal c3 and the twelfth input terminal c4 are set to Vosn', then the output voltage Von of the third amplifier A3 is:

[0051] AnVosn-Ann(Vosn'+Von)=Von (1)

[0052] When the clock signal is low (CK-), the third amplifier A3 is in the signal amplification stage, that is, it outputs the second adjustment signal to the first amplifier A1. Assuming the offset voltage of the first input terminal a1 and the second input terminal a2 is Vosm, and the offset voltage of the third input terminal a3 and the fourth input terminal a4 is Vosm', then the output voltage Vo of the first amplifier A1 is:

[0053] Vo=Am(Vin+Vosm)+Amn(Vcm+Vosm') (2)

[0054] Wherein, Vcm is the second adjustment signal input from the third amplifier A3 to the first amplifier A1:

[0055] Vcm=AnVin-AnnVon (3)

[0056] Let the output voltage Vo of the first amplifier A1 be zero, then Vin is the offset voltage of the first amplifier A1. According to formulas (1), (2), and (3), the offset voltage of the relaxation oscillator without the first and second adjustment circuits is An times the offset voltage of the first amplifier A1. Therefore, the relaxation oscillator provided in this embodiment generates corresponding first and second adjustment signals by acquiring its own offset voltage in the first and second adjustment circuits, respectively, to compensate the input voltage of the first amplifier when the clock signal is high and low, thereby reducing the offset voltage of the first amplifier A1, improving the output stability of the first amplifier A1, realizing self-calibration of the offset voltage of the relaxation oscillator, and ensuring the frequency stability of the clock signal. Moreover, the offset voltage change is very small under PVT conditions, solving the problem of output signal frequency error caused by comparator offset voltage change in the design of high-precision oscillators.

[0057] Based on the same inventive concept, this embodiment also provides a self-calibration method for a relaxation oscillator, comprising: when the clock signal generated by the main oscillator circuit is high, a first adjustment circuit provides a first adjustment signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; and a second adjustment circuit stores the offset voltage of the second adjustment circuit; when the clock signal generated by the main oscillator circuit is low, the second adjustment circuit provides a second adjustment signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; and the first adjustment circuit stores the offset voltage of the first adjustment circuit; wherein the first adjustment signal is generated based on the offset voltage of the first adjustment circuit, and the second adjustment signal is generated based on the offset voltage of the second adjustment circuit.

[0058] In summary, this embodiment provides a relaxation oscillator and its self-calibration method. Specifically, this embodiment incorporates a first adjustment circuit and a second adjustment circuit into the relaxation oscillator. When the clock signal is high, the first adjustment circuit provides a first adjustment signal to the first amplifier A1 in the main oscillator circuit, and the second adjustment circuit stores its own offset voltage. When the clock signal is low, the second adjustment circuit provides a second adjustment signal to the first amplifier A2 in the main oscillator circuit, and the first adjustment circuit stores its own offset voltage. Therefore, this embodiment generates corresponding first and second adjustment signals by acquiring the offset voltages of the first and second adjustment circuits. These signals compensate for the input voltage of the first amplifier A1 when the clock signal is high and low, respectively, thereby reducing the offset voltage of the first amplifier A1, improving the output stability of the first amplifier A1, achieving self-calibration of the offset voltage of the relaxation oscillator, and ensuring the frequency stability of the clock signal.

[0059] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A relaxation oscillator characterized by, The method comprises the following steps: A main oscillator circuit, a first adjusting circuit and a second adjusting circuit are provided; The main oscillator circuit is configured to generate a clock signal; The first adjusting circuit is configured to provide a first adjusting signal to the main oscillator circuit when the clock signal is high, and store a first adjusting circuit offset voltage when the clock signal is low; The second adjusting circuit is configured to store a second adjusting circuit offset voltage when the clock signal is high, and provide a second adjusting signal to the main oscillator circuit when the clock signal is low; The first adjusting signal is generated according to the first adjusting circuit offset voltage, and the second adjusting signal is generated according to the second adjusting circuit offset voltage; The first adjusting circuit comprises a second amplifier, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; The second amplifier has a fifth input terminal, a sixth input terminal, a seventh input terminal and an eighth input terminal; the fifth input terminal is connected to an output terminal of a second current source to receive an input voltage; the sixth input terminal is connected to the first current source through the second switch; the fifth input terminal is connected to the sixth input terminal through the first switch; the seventh input terminal is connected to an output terminal of the second amplifier through the fifth switch; the seventh input terminal is connected to the sixth input terminal through the second capacitor; the eighth input terminal is connected to the third input terminal through the third switch; the output terminal of the second amplifier is connected to the fourth input terminal through the fourth switch; and the eighth input terminal is connected to the sixth input terminal through the sixth switch; The second adjusting circuit comprises a third amplifier, a third capacitor, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch; The third amplifier has a ninth input terminal, a tenth input terminal, an eleventh input terminal and a twelfth input terminal; the ninth input terminal is connected to the output terminal of the second current source to receive the input voltage; the tenth input terminal is connected to the first current source through the eighth switch; the ninth input terminal is connected to the tenth input terminal through the seventh switch; the eleventh input terminal is connected to an output terminal of the third amplifier through the eleventh switch; the eleventh input terminal is connected to the tenth input terminal through the third capacitor; the twelfth input terminal is connected to the third input terminal through the ninth switch; the output terminal of the third amplifier is connected to the fourth input terminal through the tenth switch; and the twelfth input terminal is connected to the ninth input terminal through the twelfth switch; The main oscillator circuit comprises a first current source, a second current source and a first amplifier; wherein, ​ The first amplifier has a first input end, a second input end, a third input end and a fourth input end; the first input end is connected with the second current source to receive an input voltage; the second input end is connected with the first current source to receive a reference voltage; the third input end and the fourth input end are connected with the first adjusting circuit or the second adjusting circuit.

2. The relaxation oscillator of claim 1, wherein, The main oscillator circuit further comprises a resistor, a first capacitor and an NMOS tube; an output end of the first current source is connected with one end of the resistor, and the other end of the resistor is connected to a ground end; one end of the first capacitor is connected with an output end of the second current source and a drain of the NMOS tube, and the other end of the first capacitor is connected with a source of the NMOS tube and connected to the ground end; a gate of the NMOS tube is connected with an output end of the first amplifier to access a clock signal.

3. The relaxation oscillator of claim 1, wherein, When the clock signal is high, the second switch, the third switch and the fourth switch are closed; the first switch, the fifth switch and the sixth switch are opened to make the second capacitor discharge, and an output end of the second amplifier outputs the first adjusting signal to the fourth input end; When the clock signal is low, the first switch, the fifth switch and the sixth switch are closed; the second switch, the third switch and the fourth switch are opened to make the second capacitor charge, and an output voltage of the output end of the second amplifier is the offset voltage of the first adjusting circuit.

4. The relaxation oscillator of claim 1, wherein, When the clock signal is high, the seventh switch, the eleventh switch and the twelfth switch are closed; The eighth switch, the ninth switch and the tenth switch are opened to make the third capacitor charge, and an output voltage of an output end of the third amplifier is the offset voltage of the second adjusting circuit; When the clock signal is low, the eighth switch, the ninth switch and the tenth switch are closed; The seventh switch, the eleventh switch and the twelfth switch are opened to make the third capacitor discharge, and the output end of the third amplifier outputs the second adjusting signal to the fourth input end.

5. The relaxation oscillator of claim 1, wherein, The third input end is connected with a fourth capacitor and connected to a ground end; the third input end is connected with a fifth capacitor and connected to a ground end.

6. The relaxation oscillator of claim 1, wherein, The third input end and the fourth input end are further connected with a sixth capacitor and a seventh capacitor in parallel.

7. A self-calibration method employing a relaxation oscillator as claimed in any one of claims 1 to 6, characterized in that, Comprise: When the clock signal generated by the main oscillator circuit is high, the first adjusting circuit provides a first adjusting signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; And, the second adjusting circuit stores the offset voltage of the second adjusting circuit; When the clock signal generated by the main oscillator circuit is low, the second adjusting circuit provides a second adjusting signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; and, the first adjusting circuit stores the offset voltage of the first adjusting circuit; When the clock signal generated by the main oscillator circuit is low, the second adjusting circuit provides a second adjusting signal to the main oscillator circuit to correct the offset voltage of the main oscillator circuit; and, the first adjusting circuit stores the offset voltage of the first adjusting circuit; The first adjustment signal is generated according to a disordered voltage of the first adjustment circuit, and the second adjustment signal is generated according to a disordered voltage of the second adjustment circuit.

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