Phased Array Module

Abstract

The present invention relates to a phased array module, comprising a plurality of antenna boards. Each antenna board has the same layout and comprises a plurality of antenna elements, which are positioned so that they together form a matrix pattern on the antenna board, and an integrated circuit containing a plurality of transceiver devices. Each transceiver is connected to an antenna element on the antenna board, whereby the corner antenna elements of three adjacent antenna boards in the plurality of antenna boards form an equilateral triangle. The matrix pattern formed by the plurality of antenna elements is shaped as a square or a rectangle.

Description

Technical Field

[0001] The present invention generally relates to the field of millimeter wave phased array modules for high data rate communications. Background Art

[0002] The frequency band available around 60 GHz provides up to 9 GHz of bandwidth for high-speed wireless communications and negligible interference. The 60 GHz band is considered very promising for very high throughput, such as for 4G and 5G cellular systems, compared to current low radio frequency (RF) wireless services. Wireless transceivers (i.e., devices that contain both transmitters and receivers) operating in this frequency range typically utilize phased arrays (also called beamformers) to ease the wireless link budget. Therefore, beamforming circuits are needed in such systems. Millimeter wave beamforming requires two operations: in the transmitter, the signal is split onto different antenna paths and then the signal is phase shifted, while in the receiver, the signals in different antenna paths are phase shifted and then the signals are combined. Beamformers can be implemented in various ways.

[0003] Modules for beamforming typically include multiple integrated circuits embedded in the module, each containing multiple transceivers. Each transceiver is connected to a different antenna on the antenna board. In a conventional phased array module, only the integrated circuit (IC) arranged to be used as a master node is equipped with a single baseband block and a single mixer and frequency synthesis block. The IC used as a passive slave chip contains only phase shift and amplifier functions.

[0004] During the production phase, such multi-chip phased array modules contain chips with different process corners. This difference affects the output gain and phase performance and therefore requires calibration. Traditional calibration during production requires an expensive setup that includes mmWave equipment, which increases the one-time calibration cost.

[0005] In addition, mmWave phased array modules also require online, in-situ calibration during their long-term operation to compensate for temperature changes and aging effects. However, traditional phased array modules with a single master node and no auxiliary circuits cannot support this function.

[0006] like Figure 1As shown, the phased array module includes multiple chips, one of which is arranged to be used as a master node (101), and the remaining chips (102) form multiple slave chips. Each chip includes multiple transceivers, each transceiver is connected to the antenna element of the antenna board, the antenna board includes the chip and includes an antenna switch. The slave chips each receive their input signals from the antenna output signals of the chip serving as the master node through an input / output interface. Assuming that the master node contains M (e.g. 16) antenna elements and each slave node contains N (e.g. 16) antennas, an MxN (e.g. 256) antenna module is obtained. A top view of a typical antenna board of a phased array module is shown in FIG. Figure 2 As shown, a scenario is considered in which each slave node includes N=16 patch antennas (represented as small squares) arranged in a regular pattern of equally spaced rows and columns. In this layout, the minimum distance between two adjacent antennas is half the wavelength (i.e., λ / 2). Figure 2 The dashed squares in the figure represent the segment boundaries between slave nodes. To achieve improved beam steering performance, the phase and gain information of each transceiver front end / antenna path must be calibrated. Due to various circumstances, such as production tolerances, network conditions, interference, etc., the signals transmitted through different antenna paths may experience different phase and / or delay shifts than expected, resulting in performance degradation. This effect can be reduced or even eliminated through in-situ calibration.

[0007] In order to be able to calibrate each node of the phased array module, i.e. to calibrate all antenna paths of this node, the node comprises one antenna used as a reference antenna. Then, a calibration of the phase shift or gain of each pair of antennas is performed with respect to the reference antenna. For any slave node, this pair of antennas may belong to the same chip or to two adjacent slave chips.

[0008] In order to perform calibration on any two signal paths, it is necessary to find a reference antenna positioned so that the geometric distance to the two paths in calibration is the same. Figure 2 , in slave node 204, the calibration of antennas "1" and "3" can be performed using antenna "6" (thus, using a reference antenna on the same chip) or using antenna "2" of slave node 205 as a reference. It is also necessary to calibrate the various front-end paths of the different chips belonging to the phased array module. For example, antenna "4" of slave chip 205 can be used as a reference when calibrating antenna "3" of slave chip 204 and antenna "1" of slave chip 206. Examples can also be found in the columns, for example, using antenna "1" of slave chip 206 as a reference also allows the antenna pair consisting of antenna "3" of slave chip 204 and antenna "4" of slave chip 205 to be calibrated. Also, diagonal antenna elements can also be linked, for example, antenna "3" in slave chip 205 can be used as a reference to calibrate antenna "1" of slave chip 206 and antenna "8" of chip 204.

[0009] From the given example it can be seen that calibration of the relative mismatch (eg in gain or phase shift) between the antennas in each slave node results in two subsets of elements, such as Figure 3 The antenna patches are marked 1 and 2. Elements of the same subset are located on the diagonal. Only antennas of the same subset can be combined in a single calibration step using a certain reference antenna. However, calibration is not possible using one element of the first subset and one element of the second subset, because Figure 3 In the example above, it is not possible to find a reference antenna with equal distance between nodes with label “1” and label “2”. Antenna layout is an obstacle to achieving this goal.

[0010] Solutions have been proposed in the art, where self-calibration (also called auto-calibration) is implemented in a phased array module, ie where the phased array module itself is so equipped that it can be used to perform calibration of the module without any external connections.

[0011] In US2015 / 255868, a method and apparatus for self-calibration of an antenna array are disclosed. The apparatus includes first and second couplers, a calibration transceiver, and a controller. The first coupler is operably connected to a first number of antennas. The second coupler is operably connected to a second number of antennas. The calibration transceiver is operably connected to the first and second couplers via a common path. The controller is configured to perform calibration on at least one or more transmit / receive paths of the second number of antennas based on one or more signals received from or sent to the first and second couplers by the calibration transceiver via the common path from the first and second couplers.

[0012] In US2011 / 248796, an RF feed network for an antenna array is disclosed. In some embodiments, the tile architecture of the array antenna is composed of a plurality of sub-arrays, whereby each sub-array contains eight rows, each row having eight antenna elements. The even rows are offset relative to the odd rows.

[0013] Therefore, there is a need for a phased array module having antennas positioned on respective antenna boards such that calibration can be performed without limitations as described in prior art solutions. Summary of the invention

[0014] It is an object of embodiments of the present invention to provide a phased array module, wherein antenna panels of the phased array module are arranged to allow calibration to be performed in a flexible manner.

[0015] The above mentioned objects are achieved by the solution according to the invention.

[0016] In a first aspect, the invention relates to a phased array module comprising a plurality of antenna boards. Each antenna board has the same layout and comprises a plurality of antenna elements and an integrated circuit containing a plurality of transceiver devices, the antenna elements being so positioned as to form together the same regular pattern on the antenna board, and each transceiver device being connected to an antenna element on the antenna board. The corner antenna elements of three adjacent antenna boards of the plurality of antenna boards form an equilateral triangle. The proposed module is characterized in that the matrix pattern has a square or rectangular shape.

[0017] The proposed solution does allow a flexible and complete calibration of the individual antenna paths. Since the corner antennas are positioned as equilateral triangles and the antenna elements of each antenna board are in a regular matrix pattern (same for each antenna board), the antenna elements along the edges of adjacent antenna boards are positioned so that two antenna paths can be calibrated while using the third antenna element as a reference, since the latter has the same geometric distance to the two antennas of the calibrated paths. Due to the regular antenna pattern within each antenna board, calibration can also be performed within the antenna board.

[0018] Advantageously, all antenna elements of the antenna board have the same signal path length to the integrated circuit to which the antenna elements are connected.

[0019] In some embodiments, each integrated circuit includes N 2 antennas, where N is an integer.

[0020] In a preferred embodiment, the integrated circuit of one of the plurality of antenna boards is arranged to function as a master node, and the integrated circuits of the remaining antenna boards are arranged to function as slave nodes, each slave node receiving as input a signal output by a different antenna element of the master node in a receiving mode, or each slave node transmitting as output a signal input by a different antenna element of the master node in a transmitting mode. The integrated circuit acting as the master node and the integrated circuit acting as the slave node advantageously have the same architecture.

[0021] The integrated circuit acting as a master node and the integrated circuit acting as a slave node preferably have the same number of antenna elements.

[0022] In some embodiments, the master node is connected to baseband circuitry arranged for processing baseband input / output signals. Advantageously, the phased array module further comprises an analog to digital converter for processing baseband signals.

[0023] In a preferred embodiment, integrated circuits arranged to function as master nodes and their antenna pads are located on one side of the substrate, while integrated circuits arranged to function as slave nodes and their antenna pads are located on the opposite side of the substrate.

[0024] In one embodiment, at least one integrated circuit of the phased array module includes a tone generator for generating a test signal for calibration.

[0025] In another embodiment, the clock of an integrated circuit of a slave node operable as a reference is connected to the clock of an integrated circuit of a master node.

[0026] In yet another embodiment, the integrated circuit is configured as a slave node, whereby one antenna element of the antenna board of the slave node is arranged as a reference receiving antenna and two or more other antenna elements of the antenna board are arranged as transmitting antenna elements. In this case, there is no need to have an integrated circuit configured as a master node in the phased array module.

[0027] In another aspect, the present invention relates to a method for calibrating a pair of antenna elements of a phased array module. The method comprises:

[0028] - selecting two antenna paths to be calibrated in the phased array module, each antenna path comprising the antenna elements of the pair and an RF front end to which the antenna elements are connected,

[0029] - selecting in the phased array module another antenna element as a reference antenna in a reference antenna path, said reference antenna path also comprising an RF front end to which the reference antenna is connected, whereby the reference antenna is positioned such that the geometric distance to the two antenna paths is the same,

[0030] - Calibrating the antenna element pair by using both antenna paths for transmitting signals and using a reference antenna path for receiving the transmitted signals, or vice versa, whereby the transmitted signals propagate overflowing through the antennas.

[0031] In some embodiments, the antenna element pair can be calibrated in transmit mode, whereby the reference antenna then serves as a reference receiver. In other embodiments, the antenna is calibrated in receive mode and the reference antenna can be considered as a reference transmitter. The calibration includes configuring the RF front end, such as the gain and phase shift of the various antenna paths used in the calibration process.

[0032] In some embodiments, performing calibration comprises comparing the gain or phase shift of the two antenna paths.

[0033] In an embodiment, the two antenna elements are located on the same antenna board. In other embodiments, the reference antenna and one of the two antenna elements are located on the same antenna board.

[0034] For the purpose of summarizing the present invention and the advantages achieved relative to the prior art, certain objects and advantages of the present invention have been described above in this document. Of course, it should be understood that not all such objects or advantages may be achieved according to any particular embodiment of the present invention. Thus, for example, those skilled in the art will recognize that the present invention can be embodied or performed in a manner that achieves or optimizes one advantage or a group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0035] The above and other aspects of the present invention will be apparent from and elucidated with reference to the embodiment(s) described herein below. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout the various views.

[0037] Figure 1 A phased array module comprising a master chip and a slave chip is illustrated, including antennas and connection input / output ports.

[0038] Figure 2 An arrangement of slave chips of a phased array module known in the art is shown.

[0039] Figure 3 shows how to have Figure 1 Two sets of calibration elements are obtained within the same slave node of the arrangement.

[0040] Figure 4 A cross section of a phased array module including a master node and a plurality of slave nodes is illustrated.

[0041] Figure 5 A possible architecture of an integrated circuit for use in a phased array module according to the present invention is illustrated.

[0042] Figure 6 shows a node suitable for use as a master node Figure 5 architecture.

[0043] Figure 7 The diagram shows a suitable Figure 5 architecture.

[0044] Figure 8 FIG. 4 shows the arrangement of slave tiles of a phased array module according to an embodiment of the present invention.

[0045] Fig. 9 The diagram shows the Figure 8 Arrangement of chip-to-antenna signal routing.

[0046] Fig.10 An arrangement of slave tiles with a 3x3 antenna array according to an embodiment of the present invention is illustrated.

[0047] Fig.11 An arrangement of slave tiles having a rectangular shape according to an embodiment of the present invention is shown.

[0048] Fig.12 The configuration of the master and slave chips is shown when a certain antenna is in a calibration state.

[0049] Fig.13 Another configuration is shown when the reference antenna and the antenna being calibrated belong to the same chip. DETAILED DESCRIPTION

[0050] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims.

[0051] Furthermore, the terms first, second, etc. in the specification and in the claims are used to distinguish between similar elements and are not necessarily used to describe a sequence in time, space, in ranking, or in any other manner. It is understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in a different sequence than described or illustrated herein.

[0052] It is to be noted that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, the term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of a device stating that it comprises means "A and B" should not be limited to devices consisting only of components "A and B". It means that for the present invention, the only relevant components of the device are A and B.

[0053] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the various appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment. Thus, the various appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment.

[0054] Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this disclosure method should not be interpreted as reflecting an intention that the claimed invention requires more features than those expressly recited in each claim. On the contrary, as reflected in the appended claims, inventive aspects reside in fewer features than all of the features of a single preceding disclosed embodiment. Therefore, the claims appended after the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim itself representing a separate embodiment of the invention.

[0055] In addition, although some embodiments described herein include some features included in other embodiments but do not include other features included in other embodiments, as will be understood by those skilled in the art, the combination of features of different embodiments is intended to fall within the scope of the present invention and form different embodiments. For example, in the appended claims, any of the claimed embodiments can be used in any combination.

[0056] It should be noted that the use of a particular term in describing certain features or aspects of the present invention should not be taken as implying that the term is redefined herein to be limited to including any specific characteristics of the feature or aspect of the present invention with which the term is associated.

[0057] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other examples, well-known methods, structures, and techniques are not shown in detail to avoid confusing the understanding of this description.

[0058] The present invention proposes a phased array module, including multiple antenna boards, each antenna board including an integrated circuit. The integrated circuit architecture and antenna module design, each of which contains multiple transceivers, allow automatic calibration as well as field calibration in the production stage. In this way, the testing and calibration costs in the production stage can be reduced. Using the proposed solution, the phase and gain changes of each antenna path of the phased array module can be calibrated at low cost.

[0059] The phased array module includes multiple integrated circuits (ICs), each of which is arranged on a different antenna board. Figure 1The same high-level representation shown in FIG: one of the integrated circuits and its associated antenna board can be set up to function as a master node 101, while the other integrated circuits are set up as slave nodes 102, each connected to multiple antennas 103. The connection port in the master chip is an output I / O 104, and each slave chip is connected to the master chip via an input I / O 105. The various integrated circuits of the phased array module are also referred to as tiles or just chips in this specification. Preferably, the master chip and the slave chips have the same architecture. However, in some embodiments, in principle, the master chip can have a different architecture than the slave nodes. In the following description, it is assumed that all ICs have the same schematic. Using only one type of chip to implement a master / slave multi-tile configuration has obvious benefits that will become apparent.

[0060] like Figure 4 , a typical cross-sectional view of a multi-chip phased array module obtained after chip assembly is shown, wherein there is a chip as a master node and multiple slave nodes on the corresponding antenna boards. Multiple antenna boards 107, each including multiple antenna elements, such as patch antennas, are connected to the substrate 112 of the phased array module via RF solder bumps 109. Each antenna board includes an integrated circuit connected to the antenna board via an RF column 111. Typically, the antenna board provided with the integrated circuit as the master node 110 is placed on one side of the substrate, while the antenna board 107 with the chip 108 as the slave node 106 is located on the opposite side of the substrate. It is also conceivable to use, for example, a monopole antenna, a dipole antenna or a bow-tie antenna instead of a patch antenna.

[0061] Figure 5 The architecture of an integrated circuit that can be used in a phased array module according to the present invention is shown. At the chip level, there are multiple parallel transceiver front ends (313) on the same die, usually one with a transmit function and one with a receive function, and the die is connected to a power combiner (302) / distributor (303) and a transmit phase shifter (319) / receive phase shifter (301). Each antenna front end (315) can be connected to the antenna switch (in Figure 5 The integrated circuit also includes the baseband and local oscillator (LO) (306) functionality required to operate as a master node. When the path of the RF signal I / O (300) is muted and the switch (313) is closed to connect the mixer, the master node is configured to operate as a transmitter or receiver. Figure 5 The IC can up-convert / down-convert (304 / 305) the baseband signal through the local oscillator and mixer blocks. Figure 6 is shown in the figure. Figure 5 The IC can also be configured to function as a slave node as follows: Figure 5The LO, baseband processing blocks and mixers in the DAC are muted and the switch to the signal I / O is closed (314). The final configuration thus obtained is as follows Figure 7 As shown. In that case, the distributor (303) and combiner (302) of the slave node transmit and receive modulated millimeter wave signals through the signal I / O interface (311 / 312) connected to the master node. In order to steer the beam at each slave node transceiver element, the phase shifter (301 / 319) at each signal path independently controls the signal phase.

[0062] Figure 6 An integrated circuit used as a master node and its connection to multiple (e.g., M=16) ICs used as slave nodes to form a phased array transceiver module under normal operation are shown. Antennas (403)) are connected in the slave nodes through each antenna I / O interface (404). In this case, the master chip (400) has M I / O ports to connect to M slave chips, each of which is equipped with N antennas, forming an M×N antenna module. The baseband IC (405) processes the baseband input / output signals.

[0063] Figure 7 The IC is shown operating as a slave node. The LO and baseband sections are disabled, with the RF amplifiers for Rx (501) and Tx (502) connected to the signal IO (503), which is further connected to the master chip.

[0064] Note that under normal operation, the slave node IC is configured to act as a transmitter or receiver for all antenna paths simultaneously, since the I / O interface (503) is shared by the receive amplifier (501) and the transmit amplifier (502) of the slave node.

[0065] Calibration is performed by comparing each time, for example, the gain and / or phase shift of two antenna paths with a reference antenna path, wherein the active antenna path and the reference antenna path come from the same motherboard (112). The antenna path comprises an antenna element and an RF front end formed by an antenna front end (315) and a phase shifter (301, 319). In receive mode, the gain is adjusted by a low noise amplifier LNA (317) and a phase shifter (301). In transmit mode, the gain is adjusted by a power amplifier PA (318) and a phase shifter (319). It is worth noting that the propagation occurs via antenna leakage / overflow, wherein no explicit electromagnetic coupler is required. This results in a simpler circuit implementation. The chip to which the reference antenna is connected is called a reference chip. The antenna path comprises the antenna element itself and the RF front end to which the antenna is connected. The two RF front ends with their respective antennas may belong to the same slave node, or to two different nodes. Furthermore, the reference antenna as part of the reference antenna path may be located on an antenna board containing one of the antennas being calibrated or on an antenna board of a different slave node. If the antenna is calibrated in transmit mode, the integrated circuit to which the reference antenna is connected is called a reference receiver. If the antenna is calibrated in receive mode, the integrated circuit to which the reference antenna is connected is called the reference transmitter.

[0066] For calibration purposes, Figure 5 The integrated circuit also includes a tone generation block (308) and a calibration DAC (307), which is activated in the chip configured as the master node when the two antenna paths are to be calibrated in the transmit mode, and the master chip thus operates as a transmitter. In this case, the two slave antenna front ends are configured as slave transmitters and cascaded to the master node. As mentioned above, the two slave antenna front ends can belong to the same slave node or to two different slave nodes. Thanks to the distribution of the reference frequency (315) across the board by the module, the transmit and receive nodes are well synchronized; therefore, no third party external circuitry / equipment is required.

[0067] Similarly, when the two slave antenna front ends are configured as receivers in calibration, the slave receivers are connected to the master IO (311 / 312). In the master chip, the down-conversion mixer (304) is enabled. The baseband signal enters the calibration ADC block (309) in the master chip, where the digitally quantized gain and phase information is accessible through the serial peripheral interface (SPI) port (310). The integrated circuit of a particular node operates as a reference transmitter, and its tone generator (308), DAC (307), LO (306) and up-conversion mixer (305) are enabled.

[0068] In order to be able to calibrate each slave node, i.e. calibrate all antenna paths of this node, this node requires one antenna path to be used as a reference antenna path, as already mentioned. The calibration of the phase shift or gain of each pair of antenna paths is performed with respect to the reference antenna. Note that for any slave node, the pair of antennas in the calibration may belong to the same IC or may consist of one antenna of this slave IC and one antenna of a neighboring slave IC.

[0069] The present invention proposes a phased array module, comprising a plurality of slave nodes, which are arranged to overcome the disadvantage of performing calibration for different subsets separately (see Figure 3 ). Recall that in order to perform calibration on any two signal paths, it is necessary to find a reference transmitter or receiver antenna that is positioned so that the geometric distance to the two paths in calibration is the same. In order to achieve low-loss signal routing from one slave tile to the N antenna patches while maintaining full coverage of the antenna elements, offsets are introduced between the rows or columns of different slave tiles to form equilateral triangles (75) between the antenna elements of the antenna panels of different slave nodes that are positioned at the edges between three adjacent slave nodes. Having adjacent slave nodes means that those pairs of slave nodes can be considered to be adjacent or neighboring. Figure 8 An illustration is provided. In this embodiment, the antenna arrangement within the same antenna board remains shaped as a square to allow H-shaped signal routing. All antenna boards have the same arrangement. The antenna elements on each antenna board are therefore positioned to form together the same matrix pattern as on the other antenna boards. Note that dummy antennas (76) can be provided externally. These are used to ensure that the edge patch antennas have a similar environment (i.e. a similar electromagnetic environment) as the center antenna.

[0070] exist Figure 8In the scheme of FIG. 7 , antenna element “1” in 72 can be used as a reference for calibrated antennas “1” and “2” in tile 71. Antenna “5” in tile 73 can be a reference for antennas “4” and “12” in tile 71. Similarly, antenna “9” in tile 73 can be a reference for antennas “8” and “16” in tile 71. This allows calibration of odd and even rows. Furthermore, in this configuration, adjacent rows can be calibrated by using antenna “3” in 71 or antenna “9” in 73 as a reference for antenna pair “4 / 7” in 71. In order to calibrate the mismatch between different tiles, antenna “4” in 72, antenna “4” in 71, and antenna “1” in node 73 form an equilateral triangle that can also be used in the calibration process. In other words, it can also be said that antenna “4” in 72, antenna “4” in 71, and antenna “1” in node 73 form a parallelogram (and different from a rectangle) together with antenna “1” of tile 74. Calibration of antennas "4" and "8" in tile 71 can be accomplished by linking the relative phase and gain information between the calibrated "4 / 7" and "7 / 8" pairs in tile 71, where antenna element "7" in tile 71 acts as an intermediate node to assist propagation. In certain embodiments of the present invention, the proposed configuration reduces local signal routing complexity, e.g. Figure 8 In the embodiment shown, full self-calibration coverage is simultaneously maintained. Fig. 9 Symmetrical chip-to-antenna signal routing is shown, where each signal path is the same length. Figure 8 The square antenna matrix layout in , makes it much easier to equalize distances compared to the non-square floor plan of patch antennas.

[0071] In another embodiment, tiles forming an odd square array are used, e.g. Fig.10 As in the previously discussed embodiment, in Fig.10 The equilateral triangle formed by antenna "3" in tile 92, antenna "1" in 93, and antenna "3" in tile 91 is preserved at the boundary corners. The antenna paths from tile 91 to / from antennas "4" and "5" can be calibrated through antenna "1" in tile 92. Considering antennas "5" and "1" in tile 91, they can be calibrated by using antenna "2" in the same tile as a reference. Since the relative gain / phase between antenna "5" and antenna "1" is known, antenna "4" calibration can be propagated back to antenna "1" in tile 91 using antenna "5" as an intermediate node.

[0072] Fig.11 An alternative embodiment is shown in the figure. Here the antenna layout has a rectangle in each tile that does not contain N 2Here, for vertical propagation by linking antennas "7" and "4" in 1001, only antenna element "3" in 1001 can be used as a reference, since there is no reference node in tile 1003 that can be used as a possible reference.

[0073] Fig.12 The phased array module and chip configuration are shown when the phased array module is calibrated for the antenna paths of several transmitter slave nodes. It is assumed that a low frequency IQ sinusoidal signal is generated, for example, by an on-chip tone generator and DAC in the integrated circuit (1104) of the slave node. The tone is up-converted by the LO module in the master chip and fed to the slave chips through their I / O ports. The signal is further amplified in the slave node and fed to the open space through the antenna in the slave node. The selected chip (1105) is configured as a reference receiver to process the overflow leakage signal, i.e., the portion of the signal that leaks back from the individual transmitters when they send their signals from the antennas (1101, 1102, 1103) (see Fig.11 ). In the reference receiver, the LO block runs at the same frequency as the master chip. Therefore, after down-conversion and A / D conversion, the phase and gain information is measured by the ADC. In order to keep the calibrated antenna path in the same environment so that the overflow path matches, any other front-end circuitry is disabled. It is worth noting that when the chip operates as a reference transceiver, its reference clock is connected to the master chip (1112) to maintain consistency.

[0074] Fig.13 The scenario is shown when the antenna path in calibration and the reference path are located at the same slave node for master chip redundancy. The tone signal is generated, up-converted and split to the front end / antenna 1201 and 1203. Assuming that antenna 1202 is the reference antenna, the received signal is fed to the mixer and down-converted through the common LO shared with the transmitter. Then, the phase / amplitude information is obtained through the ADC. In other words, in this case, all processing can be performed in the slave node.

[0075] A similar configuration can be implemented for the slave receiver calibration. The reference antenna is then the transmitter antenna through which the test signal used for calibration is transmitted, which is generated using Fig.13 The tone generator and DAC shown in FIG. 1200 generate the test signal. Antennas 1201 and 1203 are now receiving antennas that each receive the test signal. The combined signal is then fed to a mixer, etc. When "7" and "4" in tile 71 use "3" as a reference, this situation corresponds to Figure 8 The situation mentioned in .

[0076] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary, rather than restrictive. The foregoing description describes certain embodiments of the present invention in detail. However, it will be appreciated that no matter how detailed the foregoing description appears in text, the present invention can be implemented in many ways. The present invention is not limited to the disclosed embodiments.

[0077] By studying the drawings, the present disclosure and the appended claims, those skilled in the art may understand and implement other variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude pluralities. A single processor or other unit may perform the functions of several items recited in the claims. The mere fact that certain measures are stated in mutually different dependent claims does not mean that a combination of these measures cannot be used to advantage. The computer program may be stored / distributed on a suitable medium (such as an optical storage medium or solid-state medium supplied together with or as part of other hardware), but may also be distributed in other forms (such as via the Internet or other wired or wireless telecommunications systems). Any reference numerals in the claims should not be interpreted as limiting the scope.

Claims

1. A phased array module comprising a plurality of antenna panels, each antenna panel having the same layout and comprising a plurality of antenna elements, the plurality of antenna elements being positioned to form a matrix pattern together on the antenna panels, and an integrated circuit containing a plurality of transceiver devices, each transceiver device being connected to an antenna element on the antenna panel, whereby corner antenna elements of three adjacent antenna panels of the plurality of antenna panels form an equilateral triangle, It is characterized in that The matrix pattern formed by the plurality of antenna elements is shaped as a square or a rectangle.

2. The phased array module according to claim 1, characterized in that: Each antenna board includes N 2 antennas, N is an integer.

3. The phased array module according to claim 1, characterized in that: The integrated circuit of one of the multiple antenna boards is arranged to be used as a master node, and the integrated circuits of the remaining antenna boards are arranged to be used as slave nodes, wherein in a receiving mode, each slave node receives a signal output by a different antenna element of the master node as input, or in a transmitting mode, each slave node transmits a signal input to a different antenna element of the master node as output.

4. The phased array module according to claim 3, characterized in that: The integrated circuit used as a master node and the integrated circuit used as a slave node have the same architecture.

5. The phased array module according to claim 3, characterized in that: The integrated circuit used as a master node and the integrated circuit used as a slave node have the same architecture.

6. The phased array module of claim 3, the master node being connected to a baseband circuit arranged to process baseband input / output signals.

7. The phased array module according to claim 6, characterized in that: An analog-to-digital converter is also included to process the baseband signal.

8. The phased array module according to claim 3, characterized in that: The integrated circuits arranged to function as master nodes and their antenna pads are located on one side of a substrate, while the integrated circuits arranged to function as slave nodes and their antenna pads are located on an opposite side of the substrate.

9. The phased array module according to claim 1, characterized in that: At least one integrated circuit includes a tone generator (308) for generating a test signal for calibration.

10. The phased array module according to claim 1, characterized in that: The clock of an integrated circuit of a slave node, which can be operated as a reference, is connected to the clock of the integrated circuit acting as a master node.

11. The phased array module according to claim 1, wherein: The integrated circuit is configured as a slave node, whereby one antenna element of the antenna board of the slave node is arranged as a reference receiving antenna, while two or more other antenna elements of the antenna board are arranged as transmitting antenna elements.

12. The phased array module according to claim 1, wherein: The antenna elements of at least one of the antenna boards have the same signal path length to the integrated circuit.

13. A method for calibrating a pair of antenna elements of a phased array module as claimed in any one of the preceding claims, the method comprising: - selecting two antenna paths to be calibrated in the phased array module, each antenna path comprising the antenna element and an RF front end to which the antenna element is connected, - selecting in the phased array module another antenna element as a reference antenna in a reference antenna path, the reference antenna path also comprising an RF front end, the reference antenna being connected to the RF front end, whereby the reference antenna is positioned such that the geometric distance to the antenna elements of the two antenna paths is the same, - calibrating the antenna element pair by using the two antenna paths for transmitting signals and using the reference antenna path for receiving transmitted signals, or vice versa, whereby the transmitted signals propagate overflowing through the antennas.

14. The method for calibration according to claim 13, characterized in that Performing the calibration includes comparing the gain or phase shift of the two antenna paths.

15. The method for calibration according to claim 13, characterized in that The two antenna elements are located on the same antenna board.

16. The method for calibration according to claim 13, characterized in that: in, One of the two antenna elements and the reference antenna are located on the same antenna board.

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