Memory controller and memory control method

Abstract

A memory controller and a memory control method are disclosed. The memory controller includes a first buffer configured to receive a memory request from a host and store the received memory request therein, a command generator configured to generate a first command corresponding to the memory request and set a type of the first command, the type of the first command indicating whether an address included in the memory request corresponds to a processing-in-memory (PIM) memory, a second buffer configured to store a plurality of commands including the first command therein, and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2021-0017653, filed February 8, 2021, and Korean Patent Application No. 10-2021-0058628, filed May 6, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference for all purposes. TECHNICAL FIELD

[0002] The following description relates to a memory controller and a memory control method. BACKGROUND

[0003] In a model such as a von Neumann architecture, data is stored in a memory. The memory can be separate from a processor, and data can move between the two. In such an architecture, a delay inevitably occurs due to frequent movement of data. As the speed of the processor increases, the memory can be improved. However, in addition to increasing the transfer speed, the improvement of the memory can be to increase the performance of storing a large amount of data in a small space. An increase in the latency for waiting until data is extracted from the memory to the processor can limit the speed of the processor to the transfer speed at a bottleneck point. In a typical computer architecture, a von Neumann bottleneck can occur in which throughput is limited due to latency. SUMMARY

[0004] This summary is provided to introduce a selection of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0005] In one general aspect, a memory controller includes a first buffer configured to receive a memory request from a host and store the received memory request therein, a command generator configured to generate a first command corresponding to the memory request and set a type of the first command, the type of the first command indicating whether an address included in the memory request corresponds to a processing-in-memory (PIM) memory, a second buffer configured to store a plurality of commands including the first command therein, and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.

[0006] To determine whether to change the order of the first command, the command scheduler can be configured to maintain the order of the first command in response to the type of the first command indicating the PIM memory.

[0007] To determine whether to change the order of the first commands, the command scheduler can be configured to change the order of the first commands in response to the type of the first commands indicating general-purpose memory.

[0008] The memory request can include a field indicating the address, the field can include a region separation bit that distinguishes addresses of the general-purpose memory and addresses of the PIM memory, and to set the type of the first command, the command generator can be configured to set the type of the first command based on the region separation bit.

[0009] In another general aspect, a memory controller includes: a first buffer configured to receive a memory request from a host and store the received memory request therein; a request arbiter configured to: set a type of a first command, the type of the first command indicating whether an address included in the memory request corresponds to a processing-in-memory (PIM) memory, and determine whether to change an order of the memory request to be transferred to a command generator based on the type of the first command; a command generator, wherein the command generator can be configured to generate the first command and the type of the first command corresponding to the memory request based on the order of the memory request; a second buffer configured to store a plurality of commands including the first command therein; and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.

[0010] To determine whether to change the order of the memory request, the request arbiter can be configured to maintain the order of the memory request in response to the type of the first command indicating the PIM memory.

[0011] To determine whether to change the order of the memory request, the request arbiter can be configured to change the order of the memory request in response to the type of the first command indicating the general-purpose memory.

[0012] To determine whether to change the order of the first commands, the command scheduler can be configured to maintain the order of the first commands in response to the type of the first commands indicating the PIM memory.

[0013] To determine whether to change the order of the first commands, the command scheduler can be configured to change the order of the first commands in response to the type of the first commands indicating the general-purpose memory.

[0014] The memory request can include a field indicating the address, the field can include a region separation bit that distinguishes addresses of the general-purpose memory and addresses of the PIM memory, and to set the type of the first command, the request arbiter can be configured to set the type of the first command based on the region separation bit.

[0015] In another general aspect, a memory control method includes receiving, by a first buffer, memory requests from a host and storing the received memory requests therein; generating, by a command generator, a first command corresponding to the memory requests and setting a type of the first command, the type of the first command indicating whether an address included in the memory requests corresponds to a processing-in-memory (PIM) memory; storing, by a second buffer, a plurality of commands including the first command therein; and determining, by a command scheduler, whether to change an order of the first command stored in the second buffer based on the type of the first command.

[0016] The step of determining whether to change the order of the first command can include maintaining, by the command scheduler, the order of the first command in response to the type of the first command indicating the PIM memory.

[0017] The step of determining whether to change the order of the first command can include changing, by the command scheduler, the order of the first command in response to the type of the first command indicating a general-purpose memory.

[0018] In another general aspect, a memory control method includes receiving, by a first buffer, memory requests from a host and storing the received memory requests therein; setting, by a request arbiter, a type of a first command, the type of the first command indicating whether an address included in the memory requests corresponds to a processing-in-memory (PIM) memory, and determining whether to change an order of the memory requests to be transferred to a command generator based on the type of the first command; generating, by the command generator, the first command corresponding to the memory requests and the type of the first command based on the order of the memory requests; storing, by a second buffer, a plurality of commands including the first command therein; and determining, by a command scheduler, whether to change an order of the first command stored in the second buffer based on the type of the first command.

[0019] The step of determining whether to change the order of the memory requests can include maintaining the order of the memory requests in response to the type of the first command indicating the PIM memory.

[0020] The step of determining whether to change the order of the memory requests can include changing the order of the memory requests in response to the type of the first command indicating a general-purpose memory.

[0021] The step of determining whether to change the order of the first command can include maintaining the order of the first command in response to the type of the first command indicating the PIM memory.

[0022] The step of determining whether to change the order of the first command can include changing the order of the first command in response to the type of the first command indicating a general-purpose memory.

[0023] The memory request can include a field indicating the address, the field can include a region separation bit that distinguishes addresses of a general-purpose memory and addresses of a PIM memory, and the step of setting the type of the first command can include setting the type of the first command based on the region separation bit.

[0024] In another general aspect, a memory controller includes: a command generator configured to set a type of a command based on a region separation bit of an address in a stored memory request, the type indicating whether the address corresponds to a processing-in-memory (PIM) memory; a command scheduler configured to determine whether to change an order of commands stored in a buffer based on the type of the command set by the command generator.

[0025] The region separation bit can correspond to a range of values, and to set the type of the command, the command generator can be configured to: in response to a value of the field of the address being greater than the range of values, set the type of the command indicating that the address corresponds to the PIM memory; and in response to the value of the field being within the range of values, set the type of the command indicating that the address corresponds to the general-purpose memory.

[0026] To determine whether to change the order of the commands, the command scheduler can be configured to: in response to the type of the command indicating the PIM memory, maintain the order of the command and change an order of one or more other commands stored in the buffer.

[0027] The memory controller can be configured to access the memory based on the order of the commands.

[0028] Other features and aspects will be apparent from the following specific description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 An example of a configuration of a memory controller is shown.

[0030] Figure 2 An example is shown in which a field of a memory request that is stored by a memory controller includes an address.

[0031] Figure 3 An example of a command to be stored in a second buffer is shown.

[0032] Figure 4 An example of a memory control method is shown.

[0033] Figure 5 An example of a configuration of a memory controller is shown.

[0034] Figure 6 An example of a memory control method is shown.

[0035] Throughout the drawings and detailed description, unless otherwise described or provided, like references indicate like elements. The drawings can not be to scale, and the dimensions, proportions, and shapes of the components in the drawings can be exaggerated for clarity, illustration and convenience. DETAILED DESCRIPTION

[0036] The following detailed description is presented to aid the reader in gaining a comprehensive understanding of the methods, apparatuses, and / or systems described herein. However, various changes, modifications, and equivalents can be used, and the disclosure herein has been presented to enable any person skilled in the art to make or use the methods, apparatuses, and / or systems described herein, as well as alternatives and equivalents to what is presented. For example, the order in which steps are presented herein are merely examples and are not limited to the order presented unless a particular order is required (e.g., by a numbering or letters). Also, descriptions of features in each figure are presented with the understanding that the features of each figure might be included on other figures in this disclosure. Furthermore, descriptions of features in this disclosure should not be seen as limiting, unless otherwise stated or provided.

[0037] The features described herein can be implemented in different ways depending upon the particular application or applications. Rather than be bound to the examples described herein, the examples described herein have been provided to illustrate some of the many possible ways in which the methods, apparatuses, and / or systems described herein can be implemented.

[0038] The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the terms "comprises," "comprising," "includes," "including," and "has," "having," their variants, and / or the like, indicate the presence of the stated features, numbers, operations, elements, components, and / or combinations of the same, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof.

[0039] Throughout this specification, where a component is described as being "connected to" or "coupled to" another component, it can be directly connected to or coupled to the other component, or one or more other components can be interposed therebetween. Conversely, where a component is described as being "directly connected to" or "directly coupled to" another component, no other components are interposed therebetween. Similarly, expressions such as "between" and "among," and "adjacent to" and "immediately adjacent to," should also be interpreted in the same way. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Although terms such as "first", "second", and "third" can be used herein to describe various components, assemblies, regions, layers or sections, these components, assemblies, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one component, assembly, region, layer or section from another component, assembly, region, layer or section. Thus, a component, assembly, region, layer or section referred to as a first component, a first assembly, a first region, a first layer or a first section in an example described herein can also be referred to as a second component, a second assembly, a second region, a second layer or a second section without departing from the teachings of the examples.

[0041] The use of the term "may" with respect to an example or embodiment herein (e.g., as to what an example or embodiment can include or implement) means that at least one example or embodiment includes or implements that feature, and all examples are not limited in this regard.

[0042] Further, in the description of the example embodiments, detailed descriptions of structures or functions known in the art can be omitted when it is deemed that such descriptions will cause obscure of the example embodiments to those skilled in the art. Hereinafter, the examples will be described in detail with reference to the accompanying drawings, and the same reference numerals in the drawings always denote the same elements.

[0043] Figure 1 An example of a configuration of a memory controller is shown.

[0044] Referring to Figure 1 The memory controller 120 can include a first buffer 121, a command generator 123, a command scheduler 124, and a second buffer 125. The command generator 123 and the command scheduler 124 can be integrated into a single device, which can also be referred to herein as a command controller. The command controller can perform the operations of the command generator 123 and the command scheduler 124.

[0045] In such processing, the order of the commands stored in the queue can be changed. For example, for more efficient memory access, the general memory controller can change the order of the commands "read", "read", and "write" stored in the queue to the order of the commands "write", "read", and "read".

[0046] Processing in memory (PIM) memory can be used to perform operations in a single chip memory to prevent the Von Neumann bottleneck that occurs in typical computer architectures. PIM memory can not only store data, but can also perform operations that are executed therein by an internal processor. Thus, the efficiency of a typical PIM memory can decrease when the order of commands in a queue is changed. Operations performed in a typical PIM memory can be suited for (or can efficiently handle) the original order of commands stored in a queue, but not the reordered order of commands. Moreover, additional operations to change the order of commands that are reordered for operations performed in a typical PIM memory to the original order can use additional resources and cause performance degradation.

[0047] In one example, the memory controller 120 can maintain or determine the order of memory commands for a PIM memory region. To do so, the command generator 123 can validate the addresses included in the memory requests transmitted from the host 110. For example, the command generator 123 can identify whether the addresses included in the memory requests correspond to a general memory region (or general memory) or a PIM memory region (or PIM memory) based on an area separating bit included in the memory requests. When the memory requests are determined to correspond to a PIM memory region, the command generator 123 can generate a command by setting a type indicating a request for a PIM memory region. The command generator 123 can transmit the generated command to the queue of the second buffer 125, and the command scheduler 124 can maintain the order of commands for the PIM memory region for access to the memory 130.

[0048] The host 110 can transmit memory requests to the first buffer 121 of the memory controller 120. The first buffer 121 can receive the memory requests from the host 110 and store the memory requests. The memory requests can include information of commands to be executed by the memory controller 120. The memory requests can include a type of a command and an address of the command. Moreover, for a write, the memory requests can also include content to be written in the address of the command.

[0049] The host 110 can include various types of processors. For example, the host 110 can include a graphic processing unit (GPU) or a central processing unit (CPU). The host 110 can include an input and output device configured to directly transfer a request to a memory region without a processor. For example, the host 110 can include an input and output device configured to transfer a request to the memory controller 120 through direct memory access (DMA) rather than a processor. However, examples are not limited to the foregoing example, and the host 110 can include any type or all types of devices that can transfer a memory request to the memory controller 120.

[0050] The first buffer 121 can store one or more memory requests received from the host 110 in a queue. The queue can be a waiting line set in a structure of the queue. The first buffer 121 can transfer the memory requests stored in the queue to the command generator 123. The first buffer 121 can transfer the memory requests stored in the queue to the command generator 123 in a sequence order.

[0051] The command generator 123 can receive the memory requests and set a type and an execution order of a command and transfer them to the second buffer 125. The memory requests transferred from the first buffer 121 can be transferred to the command generator 123 in an order in which the memory requests are stored in the queue.

[0052] The command generator 123 can generate a first command corresponding to the memory request and set a type of the first command indicating whether an address included in the memory request corresponds to a PIM memory. Here, the first command can be used to designate one command among one or more commands stored in the queue.

[0053] The command generator 123 can distinguish an address in which a command corresponding to the memory request is to be executed, based on an address of the memory request, as a general memory (i.e., a non-PIM memory) and a PIM memory. The command generator 123 can verify a region separation bit included in an address field of the memory request and verify whether the memory request corresponds to the general memory or the PIM memory. That is, the command generator 123 can set the type of the first command based on the region separation bit.

[0054] The region separation bit can denote a bit that distinguishes a memory region and a PIM memory region by 0 and 1. That is, the region separation bit can correspond to a value range. For example, in the case of a 4-bit address, when the region separation bit is the first bit, a value range of 0000 to 0111 can indicate a general memory region, and a value range of 1000 to 1111 can indicate a PIM memory region. That is, in response to a value of a field of an address included in a memory request not being within the value range (e.g., not within the value range of 0000 to 0111), the command generator 123 can set a type of a command indicating that the address corresponds to a PIM memory; in response to a value of a field of an address included in a memory request being within the value range (e.g., within the value range of 0000 to 0111), the command generator 123 can set a type of a command indicating that the address corresponds to a general memory. However, examples are not limited thereto, and the region separation bit can be a bit at an arbitrary position in the address field.

[0055] The command generator 123 can set a command corresponding to a general memory as an out-of-order type, and set a command corresponding to a PIM memory as an in-order type. The out-of-order type can also be referred to herein as a general memory region type, and the in-order type can also be referred to herein as a PIM memory region type. A command set as the out-of-order type can have an execution order changed by the command scheduler 124, and a command set as the in-order type can have an execution order maintained.

[0056] The command generator 123 can generate a command corresponding to a memory request. The command generator 123 can generate a command based on information included in a memory request. The command generator 123 can generate a command based on a command type and a command address or content included in a memory request. The command can include, for example, any one of "activate", "precharge", "flush", "read", and "write", but examples are not limited thereto. The command generator 123 can transfer the generated command to the second buffer 125. The command generator 123 can transfer the generated command to the second buffer 125 in a sequence order.

[0057] The second buffer 125 can store a plurality of commands including a first command. The second buffer 125 can store a command transferred from the command generator 123 in a queue. The queue can be a waiting line set in a structure of the queue.

[0058] The command scheduler 124 can perform scheduling on the execution order of the commands stored in the second buffer 125. The command scheduler 124 can perform scheduling on the execution order of the commands based on the type of the commands. The command scheduler 124 can determine whether to change the order of the first command (e.g., whether to change the position of the first command within the execution order) stored in the second buffer 125 based on the type of the first command. The command scheduler 124 can change the execution order of the command set as the out-of-order type. For example, when the type of the first command indicates the general memory, the command scheduler 124 can change the order of the first command. The command scheduler 124 can maintain the execution order of the command set as the in-order type. For example, when the type of the first command indicates the PIM memory, the command scheduler 124 can maintain the order of the first command.

[0059] The memory 130 can have a plurality of channels. The memory 130 can be divided into regions in channel units, and each channel unit can be independently operated. Each channel can correspond to a memory controller. Referring to Figure 1 , one channel can correspond to a memory controller, and another channel can correspond to another memory controller. When memory requests occur from a plurality of hosts such as a processor and a DMA controller, the memory requests can be divided by each memory channel based on an address. The foregoing operations can be performed in parallel by the memory controllers of the channels corresponding to each memory request.

[0060] As illustrated, in one example, the memory controller 120 of one or more embodiments can modify the operation method of the general memory controller, so that a decrease in performance and stability that can occur in PIM operation can be prevented. For example, the memory controller 120 can set the type of the command by classifying the address where the command is to be executed into the general memory and the PIM memory, and determine whether to perform scheduling on the command in the queue based on the type.

[0061] When access to the PIM memory region is requested, the memory controller 120 can generate a command and store the command in the queue, and access the memory 130 in the order in which the command is stored in the queue. In contrast, when access to the general memory region is requested, the memory controller 120 can generate a command and store the command in the queue, perform scheduling on the command in the queue, and thus access the memory 130 in the order of the scheduling. Accordingly, the memory controller 120 of one or more embodiments can improve the efficiency of the operation of the PIM memory while maintaining the efficiency of the memory access to the general memory.

[0062] Although the above refers to Figure 1A memory controller 120 is described that controls a memory 130, but examples are not limited thereto. In addition to a memory 130, a memory controller 120 can be applicable to various storage devices that store data. For example, a controller that controls a cache or a write buffer can operate in a similar manner as described above with reference to Figure 1 A memory controller 120 is described that controls a memory 130, but examples are not limited thereto. In addition to a memory 130, a memory controller 120 can be applicable to various storage devices that store data. For example, a controller that controls a cache or a write buffer can operate in a similar manner as described above with reference to

[0063] Figure 2 An example is shown in which a field of a memory request used by a memory controller includes an address is stored.

[0064] In one example, a memory request transmitted from a host 110 can include an address field. The address field can include a plurality of bits, and one bit of the plurality of bits can be defined as a region separation bit. The region separation bit can be a bit that distinguishes a PIM memory region and a general memory region by 0 and 1.

[0065] For example, with reference to Figure 2 , a 64-bit system can use a 64-bit address system, and thus the address field can include 64 bits. Among the 64 bits, one bit can be set as a region separation bit 201.

[0066] In one example, the region separation bit 201 can be used as a flag that distinguishes a command type as an ordered type and an unordered type. In this example, the region separation bit 201 can indicate a type of an address, but can not indicate an address value.

[0067] In another example, the region separation bit 201 can indicate both a command type and an address value (e.g., a value range). For example, when the region separation bit 201 is a first bit, binary address values 000...0 to 011...1 can indicate a general memory region, and binary address values 100...0 to 111...1 can indicate a PIM memory region.

[0068] Figure 3 An example of a command to be stored in a second buffer is shown.

[0069] In one example, among commands stored in a second buffer 125 of a memory controller 120, a command of a PIM memory region type can have an order that is not changed by a command scheduler 124. The command scheduler 124 can change an order of a command of a general memory region type among commands stored in a queue for efficient access to a memory 130.

[0070] For example, with reference to Figure 3, commands 301, 303, 305, 307, and 309 can be stored in the second buffer 125. For example, the second buffer 125 can include commands 301, 303, 305, 307, and 309, and the respective types of commands 301, 303, 305, 307, and 309 can all be "write."

[0071] When the data structure of the second buffer 125 is a first-in-first-out (FIFO) queue, the order of the commands can be defined as from right to left. For example, the order from command 309 to command 301 (e.g., the order of command 309→ command 307→ command 305→ command 303→ command 301) can be the original order of the commands in the queue.

[0072] Commands 301 and 307 can be commands whose types are set to the general memory region type. Commands 301 and 307 are indicated as WRITE to be able to be distinguished from the commands of the PIM memory region type.

[0073] Commands 303, 305, and 309 can be commands whose types are set to the PIM memory region type. Commands 303, 305, and 309 are indicated as WRITE' to be able to be distinguished from the commands of the general memory region type.

[0074] The command scheduler 124 can rearrange the order of the commands for the general memory region to more efficiently access the memory 130. For example, although commands 307 and 301 can be stored in the queue in the order from command 307 to command 301, the execution order in which commands 307 and 301 are executed can be changed to the order from command 301 to command 307 by the scheduling performed by the command scheduler 124. In Figure 3 In the example of, the order of command 301 can be fourth and the order of command 307 can be fifth, and then command 301 can be indicated as "WRITE 4" and command 307 can be indicated as "WRITE 5."

[0075] The order of the commands of the PIM memory region type can not be changed by the command scheduler 124. For example, the execution order of commands 309, 305, and 303 can be maintained as the original order as in the queue. The command scheduler 124 can not change the order of commands 309, 305, and 303 for efficient memory access. In Figure 3 In the example of, the order of command 309 can be first, the order of command 305 can be second, command 303 can be third, and then command 309 can be indicated as "WRITE' 1," command 305 can be indicated as "WRITE' 2," and command 303 can be indicated as "WRITE' 3."

[0076] By the above-described operations, the memory controller 120 of one or more embodiments can reduce adverse latency of a typical memory controller that can be caused by operations added to an application in order to force compliance with an order of commands rearranged by the command scheduler for operations in a PIM memory. Accordingly, the memory controller 120 of one or more embodiments can improve performance and stability (e.g., by distinguishing an order of commands for a PIM memory from an order of commands for a general-purpose memory, and maintaining the order of commands for the PIM memory).

[0077] Figure 4 An example of a memory control method is illustrated.

[0078] In one example, a memory controller can include a first buffer, a command generator, a command scheduler, and a second buffer.

[0079] In operation 401, the first buffer can receive a memory request from a host and store the received memory request.

[0080] In operation 403, the command generator can generate a first command corresponding to the memory request.

[0081] In operation 405, the command generator can set a type of the first command, the type of the first command indicating whether an address included in the memory request corresponds to a PIM memory.

[0082] In operation 407, the second buffer can store a plurality of commands including the first command.

[0083] In operation 409, the command scheduler can determine whether to change an order of the first command stored in the second buffer based on the type of the first command. When the type of the first command indicates the PIM memory, the command scheduler can maintain the order of the first command. When the type of the first command indicates a general-purpose memory, the command scheduler can change the order of the first command.

[0084] Figure 5 An example of a configuration of a memory controller is illustrated.

[0085] In one example, the memory controller 520 can include a first buffer 521, a request arbiter 522, a command generator 523, a command scheduler 524, and a second buffer 525.

[0086] The memory controller 520 can receive memory requests from the host 510 and store the received memory requests in a queue. The general memory controller can transmit the memory requests to the command generator to enable efficient memory access by changing the order of the memory requests stored in the queue. In this process, the order of the memory requests stored in the queue can be changed. For example, the general memory controller can transmit the memory requests stored in the queue (e.g., a "read" request, a "read" request, and a "write" request) by changing the order of the memory requests to an order starting from the "write" request, so that the order is the "write" request, the "read" request, and the "read" request.

[0087] The PIM memory can not only store data, but also perform operations performed by an internal processor. Accordingly, when the order of the memory requests in the queue is changed, the order of the commands to be generated can also be changed, and thus the efficiency of the typical PIM memory can decrease. The operations performed in the typical PIM memory can be suitable for the original order of the memory requests stored in the queue, but not suitable for the rearranged order of the memory requests.

[0088] The memory controller 520 of one or more embodiments can set the order of the commands for the PIM memory region in the queue to not change. The host 510 can transmit memory requests to the memory controller 520, which can be stored in the first buffer 521 in the sequence order.

[0089] The request arbiter 522 can verify the address of the memory request stored in the first buffer 521 and determine whether the address corresponds to the general memory region or the PIM memory region. The request arbiter 522 can determine whether the address corresponds to the general memory region or the PIM memory region based on a region separation bit included in the address of the memory request. The request arbiter 522 can set the type of the memory region.

[0090] When the type of the memory region corresponds to the PIM memory region, the request arbiter 522 can transmit the memory request to the command generator 523 while maintaining the order of the memory requests in the queue. Alternatively, when the type of the memory region corresponds to the general memory region, the request arbiter 522 can transmit the memory request to the command generator 523 in an order enabling efficient access to the memory 530.

[0091] The command generator 523 can verify the type of the memory request transmitted from the request arbiter 522. The command generator 523 can generate a command and transmit the generated command to the queue of the second buffer 525. When the memory request is determined to correspond to the PIM memory region, the command scheduler 524 can maintain the order of the commands for the PIM memory region to access the memory 530.

[0092] To this end, the host 510 can transmit a memory request to the first buffer 521 of the memory controller 520. The first buffer 521 can receive the memory request from the host 510 and store the received memory request. The memory request can include information of a command to be executed by the memory controller 520. The memory request can include a type and an address of the command. In the case of a write request, the memory request can further include content to be included in the address of the command.

[0093] The first buffer 521 can store one or more memory requests received from the host 510 in a queue. The queue can be a waiting line set in a structure of the queue.

[0094] The request arbiter 522 can distinguish an address region in which a command corresponding to the memory request is to be executed, based on an address of the memory request, as a general memory and a PIM memory. The request arbiter 522 can verify a region separation bit included in an address field of the memory request, and determine whether the memory request corresponds to the general memory or the PIM memory.

[0095] The region separation bit can denote a bit that distinguishes a general memory region and a PIM memory region by 0 and 1. For example, in the case of a 4-bit address, when the region separation bit is a first bit, 0000 to 01111 can indicate the general memory region, and 1000 to 1111 can indicate the PIM memory region. However, examples are not limited thereto, and the region separation bit can be a bit at an arbitrary position in the address field.

[0096] The request arbiter 522 can set a command corresponding to the general memory as an out-of-order type, and set a command corresponding to the PIM memory as an in-order type. The out-of-order type can also be referred to herein as a general memory region type, and the in-order type can also be referred to herein as a PIM memory region type. An order in which the memory request is to be transmitted, which is set as the out-of-order type, can be changed by the request arbiter 522, and an order (execution) in which a command generated by the memory request is to be executed can be changed by the command scheduler 524. An order in which the memory request is to be transmitted, which is set as the in-order type, can be maintained, and an order (execution) in which a command generated by the memory request is to be executed can also be maintained.

[0097] The request arbiter 522 can transfer one or more memory requests stored in the queue to the command generator 523. For example, the request arbiter 522 can transfer the memory requests to the command generator 523 based on the type of the memory requests. The request arbiter 522 can change the order of the memory requests set as the out-of-order type, and transfer the memory requests to the command generator 523 in the changed order. The request arbiter 522 can maintain the order of the memory requests set as the in-order type, and transfer the memory requests to the command generator 523 in the maintained order.

[0098] The command generator 523 can generate a command corresponding to the memory request. For example, the command generator 523 can generate the command based on the information included in the memory request. The command generator 523 can generate the command based on the command type and the command address or content included in the memory request. The command can include, for example, any one of "activate", "precharge", "refresh", "read", and "write", but examples of the command are not limited thereto. The command generator 523 can transfer the generated command to the second buffer 525. The command generator 523 can transfer the generated command to the second buffer 525 in the sequence order.

[0099] The second buffer 525 can store a plurality of commands including the first command therein. The second buffer 525 can store one or more commands received from the command generator 523 in a queue. For example, the queue can be a waiting line set in the structure of the queue.

[0100] The command scheduler 524 can perform scheduling on the execution order of the command stored in the second buffer 525. For example, the command scheduler 524 can perform scheduling on the execution order of the command based on the type of the command. The command scheduler 524 can determine whether to change the order of the first command stored in the second buffer 525 based on the type of the first command. The command scheduler 524 can change the execution order of the command set as the out-of-order type. The command scheduler 524 can change the order of the first command when the type of the first command indicates a general memory. The command scheduler 524 can maintain the execution order of the command set as the in-order type. The command scheduler 524 can maintain the order of the first command when the type of the first command indicates a PIM memory.

[0101] The memory 530 can have a plurality of channels. The memory 530 can be divided into regions in a channel unit, and each channel unit can be independently operated. Each channel can correspond to a memory controller. Referring to Figure 5One channel can correspond to a memory controller, and another channel can correspond to another memory controller. When memory requests occur from multiple hosts, such as processors and DMA controllers, the memory requests can be divided by the memory channels based on addresses. The foregoing operations can be performed in parallel by the memory controllers of the channels corresponding to each memory request.

[0102] As illustrated, in one example, the memory controller 520 of one or more embodiments can modify the method of operation of a general-purpose memory controller, such that a reduction in performance and stability that can occur in PIM operations can be prevented. For example, the memory controller 520 can set a type of a memory request by differentiating an address of the memory request into general-purpose memory and PIM memory. Then, the memory controller 520 can determine whether to perform scheduling on an order in which the memory request is to be transmitted and whether to perform scheduling on commands in a queue based on the type. Accordingly, the memory controller 520 of one or more embodiments can thus improve efficiency of operations for PIM memory while maintaining efficiency of memory access to general-purpose memory.

[0103] Figure 6 An example of a memory control method is illustrated.

[0104] In one example, a memory controller can include a first buffer, a request arbiter, a command generator, a command scheduler, and a second buffer.

[0105] In operation 601, the first buffer can receive a memory request from a host and store the received memory request.

[0106] In operation 603, the request arbiter can set a type of a first command, the type of the first command indicating whether an address included in the memory request corresponds to PIM memory. The memory request can include a field indicating the address, which can include a region separation bit that differentiates an address of general-purpose memory from an address of PIM memory. The request arbiter can set the type of the first command based on the region separation bit.

[0107] In operation 605, the request arbiter can determine whether to change an order of the memory request to be transmitted to the command generator based on the type of the first command. When the type of the first command indicates PIM memory, the request arbiter can maintain the order of the memory request. When the type of the first command indicates general-purpose memory, the request arbiter can change the order of the memory request.

[0108] In operation 607, the command generator can generate a first command corresponding to the memory request and the type of the first command based on the order of the memory request.

[0109] In operation 609, the second buffer can store a plurality of commands including the first command.

[0110] In operation 611, the command scheduler can determine whether to change the order of the first command stored in the second buffer based on the type of the first command. When the type of the first command indicates the PIM memory, the command scheduler can maintain the order of the first command. When the type of the first command indicates the general-purpose memory, the command scheduler can change the order of the first command.

[0111] Herein, the term "memory" refers to a memory device, a memory device and a processor, a memory device and a processor and a bus, or a memory device and a bus. Figures 1 to 6The described memory controller, first buffer, command generator, command scheduler, second buffer, host, memory, request arbiter, memory controller 120, first buffer 121, command generator 123, command scheduler 124, second buffer 125, host 110, memory 130, memory controller 520, first buffer 521, request arbiter 522, command generator 523, command scheduler 524, second buffer 525, host 510, memory 530, and other devices, apparatuses, units, modules, and components are implemented by or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components performing operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer can be implemented by one or more processing elements, such as logic gates arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes or is connected to one or more memories that store instructions or software for execution by the processor or computer. The hardware components implemented by a processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application. The hardware components can also access, manipulate, process, create, and store data in response to the execution of the instructions or software. For simplicity, the singular term "processor" or "computer" can be used in the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or a processor or computer can include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component, or two or more hardware components, can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or additional processors and additional controllers. The one or more processors, or a processor and a controller, can implement a single hardware component, or two or more hardware components.The hardware components can have any one or more of various processing configurations, examples of which include a single processor, independent processors, a parallel processor, a single-instruction single-data (SISD) multiprocessor, a single-instruction multiple-data (SIMD) multiprocessor, a multiple-instruction single-data (MISD) multiprocessor, a multiple-instruction multiple-data (MIMD) multiprocessor, a controller and arithmetic logic unit (ALU), a DSP, a microcontroller, an application- specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic unit (PLU), a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or any other devices capable of responding to and executing instructions in a defined manner.

[0112] Figures 1 to 6 The methods performed in the middle column, which perform the operations described in this application, are performed by computing hardware (e.g., by one or more processors or computers) implemented to execute instructions or software as described above to perform the operations described in this application that are performed by the methods. For example, a single operation, or two or more operations, can be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations can be performed by one or more processors, or a processor and a controller, and one or more other operations can be performed by one or more other processors, or further processors and further controllers. The one or more processors, or a processor and a controller, can perform a single operation, or two or more operations.

[0113] The instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and perform the methods as described above can be written in a computer program, a code segment, instructions, or any combination thereof, to individually or collectively instruct or configure one or more processors or computers as a machine or special purpose computer to operate to perform the operations performed by the hardware components and methods as described above. In one example, the instructions or software include machine code (such as produced by a compiler) directly executable by the one or more processors or computers. In another example, the instructions or software include high-level code to be executed by the one or more processors or computers using an interpreter. The instructions or software can be written in any programming language based on the block diagrams and flowcharts shown in the drawings and corresponding descriptions in the specification, which disclose algorithms for performing the operations performed by the hardware components and methods as described above, using any programming language.

[0114] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and perform the methods as described above, as well as any associated data, data files, and data structures, can be recorded, stored, or fixed in one or more non-transitory computer-readable storage media, or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), magnetic RAM (MRAM), spin-transfer torque (STT)-MRAM, static random-access memory (SRAM), thyristor RAM (T-RAM), zero-capacitor RAM (Z-RAM), dual transistor RAM (TTRAM), conductive-bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM (PoRAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory devices), insulator resistance change memory, dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, nonvolatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drive (HDD), solid-state drive (SSD), flash memory, card-type memory such as a multimedia card or a micro card (e.g., a secure digital (SD) or extreme digital (XD)), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk, and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over a networked computer system so that the instructions or software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0115] While the present disclosure includes certain examples, it will be clear to those skilled in the art that various changes can be made to the form and details of these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each example should be considered as being applicable to similar features or aspects in other examples. If the described technology is performed in a different order, and / or if the described architectures, systems, devices, or circuits are combined, and / or if described components are replaced by other components or their equivalents, this can be accomplished without departing from the spirit and scope of the claims.

Claims

1. A memory controller, comprising: The first buffer is configured to receive memory requests from the host and store the received memory requests therein; The command generator is configured to generate a first command corresponding to a memory request and to set the type of the first command, the type of which indicates whether the address included in the memory request corresponds to the PIM memory to be processed in memory. The second buffer is configured to store multiple commands, including the first command, therein; as well as The command scheduler is configured to determine whether to change the order of the first commands stored in the second buffer based on the type of the first command. In order to determine whether to change the order of the first commands, the command scheduler is configured to maintain the order of the first commands in response to the type indication of the first command including the address in the memory request corresponding to the PIM memory.

2. The memory controller according to claim 1, wherein, To determine whether to change the order of the first commands, the command scheduler is configured to change the order of the first commands in response to a type indication of the first command, including an address in the memory request corresponding to general memory.

3. The memory controller according to any one of claims 1 to 2, wherein, The memory request includes a field indicating the address. The field includes a region separator bit that distinguishes the address of the general purpose memory from the address of the PIM memory, and To set the type of the first command, the command generator is configured to set the type of the first command based on the region delimiter.

4. A memory controller, comprising: The first buffer is configured to receive memory requests from the host and store the received memory requests therein; The request arbitrator is configured to: set the type of a first command, and determine whether to change the order of memory requests to be sent to the command generator based on the type of the first command, wherein the type of the first command indicates whether the address included in the memory request corresponds to the PIM memory to be processed in memory; A command generator, wherein the command generator is configured to generate a first command corresponding to a memory request and the type of the first command based on the order of memory requests; The second buffer is configured to store therein a plurality of commands, including the first command; and The command scheduler is configured to determine whether to change the order of the first commands stored in the second buffer based on the type of the first command. In order to determine whether to change the order of the first commands, the command scheduler is configured to maintain the order of the first commands in response to the type indication of the first command including the address in the memory request corresponding to the PIM memory.

5. The memory controller according to claim 4, wherein, To determine whether to change the order of memory requests, the request arbitrator is configured to maintain the order of memory requests in response to a type indication in the first command that the address included in the memory request corresponds to PIM memory.

6. The memory controller according to claim 4, wherein, To determine whether to change the order of memory requests, the request arbitrator is configured to change the order of memory requests in response to a type indication in the first command that includes an address in the memory request corresponding to general memory.

7. The memory controller according to claim 4, wherein, To determine whether to change the order of the first commands, the command scheduler is configured to change the order of the first commands in response to a type indication of the first command, including an address in the memory request corresponding to general memory.

8. The memory controller according to any one of claims 4 to 7, wherein, The memory request includes a field indicating the address. The field includes a region separator bit that distinguishes the address of the general purpose memory from the address of the PIM memory, and To set the type of the first command, the request arbitrator is configured to set the type of the first command based on the region separation bit.

9. A memory control method, comprising: The first buffer receives memory requests from the host and stores the received memory requests therein; The command generator generates a first command corresponding to the memory request and sets the type of the first command. The type of the first command indicates whether the address included in the memory request corresponds to the PIM memory to be processed in memory. A second buffer stores multiple commands, including the first command. as well as The command scheduler determines whether to change the order of the first commands stored in the second buffer based on the type of the first command. The steps for determining whether to change the order of the first command include: In response to the type indication of the first command, including the address in the memory request corresponding to the PIM memory, the order of the first commands is maintained by the command scheduler.

10. The memory control method according to claim 9, wherein, The steps to determine whether to change the order of the first command include: In response to the type indication of the first command, which includes the address in the memory request corresponding to general memory, the order of the first command is changed by the command scheduler.

11. A memory control method, comprising: The first buffer receives memory requests from the host and stores the received memory requests therein; The request arbitrator sets the type of the first command and determines whether to change the order of memory requests to be sent to the command generator based on the type of the first command. The type of the first command indicates whether the address included in the memory request corresponds to the PIM memory to be processed in memory. The command generator generates the first command and the type of the first command corresponding to the memory requests based on the order of the memory requests; A second buffer stores multiple commands, including the first command. as well as The command scheduler determines whether to change the order of the first commands stored in the second buffer based on the type of the first command. The steps for determining whether to change the order of the first command include: In response to the type indication of the first command, including the address in the memory request corresponding to the PIM memory, the order of the first commands is maintained.

12. The memory control method according to claim 11, wherein, The steps to determine whether to change the order of memory requests include: In response to the type indication of the first command, the address included in the memory request corresponds to the PIM memory, maintaining the order of memory requests.

13. The memory control method according to claim 11, wherein, The steps to determine whether to change the order of memory requests include: In response to the type indication of the first command, which includes an address in the memory request corresponding to general memory, the order of memory requests is changed.

14. The memory control method according to claim 11, wherein, The steps to determine whether to change the order of the first command include: In response to the type indication of the first command including the address in the memory request corresponding to general memory, the order of the first command is changed.

15. The memory control method according to any one of claims 11 to 14, wherein, The memory request includes a field indicating the address. The field includes a region separator bit that distinguishes the address of the general purpose memory from the address of the PIM memory, and The steps for setting the type of the first command include setting the type of the first command based on the region delimiter.

16. A memory controller, comprising: The command generator is configured to set the type of command based on the region separation bit of the address in the stored memory request, the type indicating whether the address corresponds to the PIM memory for processing within the memory; The command scheduler is configured to determine whether to change the order of commands stored in the buffer based on the type of commands set by the command generator. In order to determine whether to change the order of commands, the command scheduler is configured to maintain the order of commands in response to the type of the command indicating that the address corresponds to the PIM memory.

17. The memory controller of claim 16, wherein, The region separator corresponds to the value range, and To set the command type, the command generator is configured as follows: In response to a field value at the address not being within the specified value range, a setting is made indicating the type of command corresponding to the address in the PIM memory; and In response to the value of the field being within the specified range, the type of command indicating that the address corresponds to general-purpose memory is set.

18. The memory controller of claim 16, wherein, To determine whether to change the order of commands, the command scheduler is configured to change the order of commands in response to a command type indicating that the address corresponds to general-purpose memory.

19. The memory controller according to any one of claims 16 to 18, wherein, The memory controller is configured to access memory based on the order of commands.

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