USB power delivery interface

Abstract

Embodiments of this disclosure relate to a USB power delivery interface. The present invention discloses a USB PD type interface comprising: a first node receiving a first potential, a second node delivering a second potential, and a third node at a reference potential; a resistor connected between a fourth node coupled to the first node and a fifth node; a MOS transistor connected between the fifth node and the second node, a bipolar transistor having a collector connected to the gate of the MOS transistor and an emitter connected to the fourth node or the fifth node; and circuitry configured to deliver a control potential determined from a current in the first resistor to the base of the bipolar transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of French patent application No. 2100894, filed on January 29, 2021, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to USB (“Universal Serial Bus”) C-type interface circuitry suitable for implementing “power delivery” technology, or USB-C interface, also known as USB PD-type interface, or more simply, USB PD interface. Background Technology

[0004] USB PD technology is used in USB-C type cables and connectors. This technology, among other things, enables the management of power in electronic devices.

[0005] When a device called the sink is powered by another device called the source, the source's USB-C connector may be coupled to the sink's USB-C connector via a cable suitable for USB PD technology.

[0006] On the receiver side, a USB-C type connector is electrically coupled to the receiver's application or circuitry via a USB PD interface. The interface, for example, implements protocols defined by the USB PD interface, such as power supply negotiation, which negotiates that a source will be delivered to the receiver to supply power to the receiver.

[0007] The USB PD interface, which is known to act as a hub, has been subject to various limitations in the implementation of USB PD technology. Summary of the Invention

[0008] It is necessary to overcome all or part of the limitations of known USB PD interfaces, such as the known USB PD interfaces of devices, which are suitable for devices that play a hub role in the implementation of USB PD technology.

[0009] The embodiments overcome all or part of the limitations of known USB PD interfaces, for example, the limitations of known USB PD interfaces that make the implementation of USB PD technology suitable for devices with a sink role.

[0010] One embodiment provides a USB PD type interface including: a first node configured to receive a first power supply potential; a second node configured to deliver a second power supply potential; and a third node configured to be at a reference potential; a first resistor connected between a fourth node and a fifth node coupled to the first node; a first MOS transistor connected between the fifth node and the second node; a second bipolar transistor having a collector connected to the gate of the first transistor and an emitter connected to the fourth node or the fifth node; and a first circuit configured to deliver a control potential determined by the current in the first resistor to the base of the second transistor.

[0011] According to an embodiment, the first circuit is configured to determine a control potential to limit the current in the first resistor relative to a current threshold.

[0012] According to an embodiment, the first circuit is configured to increase the base-emitter voltage of the second transistor when the current in the first resistor increases above a current threshold.

[0013] According to an embodiment, the first resistor is a PMOS transistor, and the second transistor is a PNP transistor.

[0014] According to an embodiment, the emitter of the second transistor is connected to the fourth node, and the first circuit includes a direct connection between the base of the second transistor and the fifth node.

[0015] According to an embodiment, the first circuit includes: an NPN transistor having an emitter coupled (e.g., connected) to a third node; and a collector connected to a fourth or fifth node via a voltage divider bridge, the voltage divider bridge including an intermediate node configured to provide a control potential; and a circuit configured to provide a potential determined from a voltage across a first resistor to the base of the NPN transistor, wherein the gain between the voltage across the first resistor and the control potential is preferably variable and determined by a first power supply potential.

[0016] According to an embodiment, the first circuit includes an operational amplifier having a first input coupled to a fourth node, a second input coupled to a fifth node, and an output coupled to the base of a second transistor; and a diode and a resistor connected in series between the fourth or fifth node and the third node, the connection node of the diode and the resistor being configured to deliver a floating ground to the operational amplifier, the gain of the operational amplifier preferably being variable and determined by a first power supply potential.

[0017] According to an embodiment, the interface further includes a second circuit configured to deliver a binary signal in a first binary state when the second power supply potential is greater than a power supply potential that may have increased margin; and a switch configured to couple the second node to the third node when the binary signal is in the first state.

[0018] According to an embodiment, the second circuit includes: a PNP transistor having a base coupled to a fourth node, a collector coupled to a third node by a resistor, and an emitter that couples (e.g., connects to) a binary signal delivered through the collector of the PNP transistor to the second node; or a comparator including an operational amplifier having a first input coupled to the fourth node or coupled to the first node, a second input coupled to the second node, and an output that delivers the binary signal.

[0019] According to an embodiment, the interface further includes circuitry for controlling a first transistor, the circuitry including a transistor and a voltage divider bridge having an intermediate node connected to the gate of the first transistor. The transistor in the circuitry for controlling the first transistor has a conductive terminal coupled to a third node and another conductive terminal coupled to a fourth or fifth node via the voltage divider bridge. Preferably, the transistor in the circuitry for controlling the first transistor is an NPN transistor, and the interface further includes another voltage divider bridge coupling the fourth or fifth node to the third node, and has an intermediate node connected to the base of the NPN transistor for controlling the first transistor.

[0020] According to an embodiment, the circuit for controlling the first transistor further includes a switch configured to couple the control terminal of the transistor of the circuit for controlling the first transistor to a third node when the binary signal is in a first state.

[0021] According to an embodiment, the interface also includes a third POMS transistor that couples the fourth node to the first node.

[0022] According to an embodiment, the interface further includes circuitry for controlling a third transistor, the circuitry including a transistor and a voltage divider bridge having an intermediate node connected to the third transistor. The transistor for controlling the third transistor has a conductive terminal coupled to the third node and another conductive terminal coupled to a fourth or fifth node via the voltage divider bridge. Preferably, the transistor for controlling the third transistor is an NPN transistor, and the interface further includes another voltage divider bridge coupling the fourth or fifth node to the third node, and has an intermediate node connected to the base of the NPN transistor for controlling the third transistor.

[0023] According to an embodiment, the circuit for controlling the third transistor further includes a switch configured to couple the control terminal of the transistor of the control circuit to the third node of the control circuit when the binary signal is in the first state.

[0024] According to an embodiment, the interface further includes a fourth NPN transistor having an emitter connected to a fourth node or a fifth node, and a collector connected to the gate of the first transistor; a resistor; and a capacitor element connected in series between the base of the fourth transistor and the third node.

[0025] According to an embodiment, the interface further includes means for discharging a capacitor element, the means being configured to discharge the capacitor element when the second power supply potential is greater than a first power supply potential that may have increased the margin.

[0026] According to an embodiment, the discharge device includes a diode having an anode coupled to the base of a fourth transistor and a cathode coupled to the emitter of the fourth transistor, or the discharge device includes a switch connected in parallel with a capacitor.

[0027] According to an embodiment, the interface further includes a resistor and a Zener diode connected in series between the base of the fourth transistor and the conductive terminals of the transistor used in the circuit for controlling the first transistor. Attached Figure Description

[0028] The features and advantages described above, as well as others, will be given by way of illustration and non-illustration in the following description of specific embodiments with reference to the accompanying drawings, wherein:

[0029] Figure 1 An embodiment of a device suitable for having a sink role in an implementation of USB PD technology is illustrated schematically and in part.

[0030] Figure 2 To show in more detail Figure 1 An example of a portion of the USB PD interface of a device;

[0031] Figure 3 Shown in a more detailed way Figure 1 Another example of a device's USB PD interface;

[0032] Figure 4 schematically shown Figure 1 The implementation method of the USB PD interface in the device;

[0033] Figure 5 schematically shown Figure 1 Another embodiment of the USB PD interface of the device;

[0034] Figure 6 schematically shown Figure 5 Alternative implementations of the interface in the document;

[0035] Figure 7 schematically shown Figure 5Alternative implementations of the interface in the document;

[0036] Figure 8 schematically shown Figure 5 Another alternative embodiment of the interface in; and

[0037] Figure 9 schematically shown Figure 8 Alternative implementations of the interface. Detailed Implementation

[0038] Similar characteristics have been indicated by the same reference numerals in the various figures. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may be arranged with the same structures, dimensions, and material properties.

[0039] For clarity, only steps and elements useful for the examples described herein are illustrated and described in detail. In particular, USB PD technology is not described in detail, and the described embodiments and variations are compatible with USB PD technology, as described in subsequent versions of the "USB Power Delivery Specification" available, for example, at https: / / www.usb.org.

[0040] Unless otherwise specified, when referring to two elements connected together, it indicates a direct connection in the absence of any other elements besides the conductor, and when two elements are coupled together, it indicates that the two elements can be connected or that they can be coupled via one or more other elements.

[0041] In the following disclosure, unless otherwise stated, when referring to full positional limiting words such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or for orientation limiting words such as the terms “above,” “below,” “above,” “below,” etc., or when referring to orientation limiting words such as “horizontal,” “vertical,” etc., the directions shown in the figures are referenced.

[0042] Unless otherwise specified, the terms “about,” “approximately,” “substantially,” and “with” mean within 10%, preferably within 5%.

[0043] In the following description, unless otherwise stated, all potentials are referenced to the same reference potential, typically ground (GND).

[0044] In the following description, unless otherwise stated, MOS transistor refers to a "metal-oxide-semiconductor" type transistor, and PMOS transistor and NMOS transistor refer to P-channel MOS transistor and N-channel MOS transistor, respectively. Similarly, NPN transistor and PNP transistor refer to NPN type bipolar transistor and PNP type bipolar transistor, respectively.

[0045] Figure 1 An example of device 1 that can play the role of a sink in an implementation of USB PD technology is schematically shown and partially illustrated.

[0046] Device 1 includes Figure 1 The connector 100 is defined by a dotted line on the left side.

[0047] Connector 100 is adapted for USB PD technology. Connector 100 is configured to couple to a complementary connector adapted for USB PD technology. In other words, connector 100 is configured to electrically couple to a device (e.g., a laptop computer or charger) and is adapted to act as a sink during the implementation of USB PD technology to power device 1.

[0048] Connector 100 includes a first terminal 102 configured to couple with a first corresponding terminal of a complementary connector. When connector 100 is coupled to a device having a source via the complementary connector, terminal 102 is configured to receive a reference potential, typically ground (GND).

[0049] Connector 100 also includes a second terminal 104 configured to couple to a second corresponding terminal of the supplementary connector. Terminal 104 is configured to receive a power supply potential Vbus when connector 100 is coupled to a device having a source role via the complementary connector.

[0050] Connector 100 also includes communication terminals configured to couple to corresponding communication terminals of a complementary connector. In this example, the connector includes two communication terminals, CC1 and CC2. Communication terminals CC1 and CC2 are configured to allow data exchange via connector 100 using devices coupled to device 1 by implementing the communication protocol of USB-C technology.

[0051] Device 1 also includes a USB PD interface 110, in Figure 1 The middle is defined by a dashed line. Interface 110 is arranged between connector 110 and circuitry or application 120, which will be powered by device 1. Circuitry 120 is in Figure 1 The right side is defined by a dotted line.

[0052] Interface 110 includes a node 112 configured to receive a potential Vbus. Node 112 is disposed on one side of connector 100. Node 112 is coupled, preferably, to a terminal 104 of connector 100.

[0053] Interface 110 includes a node 114 configured to be connected to ground (GND). Node 114 is coupled, preferably, to terminal 102 of connector 100.

[0054] Interface 110 includes node 116 and a switch IT that couples node 112 to node 116. The path that couples node 112 to node 116 and includes switch IT is hereinafter referred to as the power supply path. Node 116 is configured to deliver a power supply potential Vin. For example, when switch IT is on, or in other words, when the switch path is active, node 116 is configured to deliver a non-zero power supply potential Vin. Node 116 is located on one side of application 120.

[0055] Nodes 114 and 116 are connected to application 120 so that the application can be powered by potential Vin when switch IT is turned on.

[0056] Node 110 includes a circuit CTRL for controlling switch IT. The circuit CTRL is configured, for example, to turn off switch IT when connector 100 is not coupled to a USB PD type source, or when the potential Vbus reaches a value greater than a high OVLO (“overvoltage lockout output”) threshold or less than a low UVLO (“undervoltage lockout output”) threshold. The UVLO and OVLO thresholds are defined by USB PD technology and are at least partially determined by a power supply negotiated according to a protocol defined by USB PD technology between device 1 and the device powering it. The UVLO and OVLO thresholds have different values ​​depending on the negotiated voltage, i.e., a target value for the potential Vbus corresponding to the negotiated power.

[0057] Therefore, the switch IT enables protection of application 120 from unwanted values ​​of the potential Vbus.

[0058] Device 1 also includes a capacitor element C connected between nodes 116 and 114. Figure 1 In the example, the capacitor element belongs to application 120, although it could also be represented as belonging to interface 110.

[0059] Figure 2 A partial example of interface 110 is shown in more detail. More specifically, Figure 2 The implementation of switch IT and its control circuit CTRL is shown.

[0060] In this example, switch IT ( Figure 1 This is implemented using a single PMOS transistor 220. The source of transistor 220 is coupled, for example, in... Figure 2 In this example, the transistor 200 is connected to node 201, which in this example is connected to node 112 of interface 110. The drain of transistor 200 is connected, for example, to node 116 of interface 110.

[0061] In this example, only a portion of the circuit CTRL is shown and Figure 2Defined by the dashed lines, a portion of the circuit CTRL includes an NPN transistor 202 and a voltage divider bridge connected in series between nodes 114 and 201. The emitter of transistor 202 is coupled to (e.g., connected to) node 114, and the collector of transistor 202 is coupled to node 201 by the voltage divider bridge. In this example, the voltage divider bridge includes two resistors R2 and R3, with resistor R2 having a terminal connected to node 201. The intermediate node of the voltage divider bridge 204, in this example, node 204 where resistor R2 is connected to resistor R3, is connected to the gate of transistor 200. The base of transistor 202 is configured to receive a binary signal EN. The binary signal EN is delivered through a portion of the circuit CTRL (not shown). When signal EN is in a first binary state (e.g., corresponding to a high potential), transistor 202 draws current from node 201 to node 114, such that the voltage between the source and gate of transistor 200, i.e., the voltage across resistor R2 in this example, is sufficient to keep resistor 200 on. When the signal EN is in the second binary state, for example, corresponding to a low potential (e.g., ground GND), transistor 202 is clamped, so that the voltage between the source and gate of the transistor is zero, and transistor 200 is subsequently clamped.

[0062] When a device that acts as the source for implementing USB PD technology is connected to connector 100 ( Figure 1 As long as the source does not deliver a potential Vbus equal to the default value (typically 5V), switch 200 remains open. When the potential Vbus stabilizes at this default value, switch 200 closes, and capacitor C ( Figure 1 )Charge.

[0063] When it will be by device 1 ( Figure 1 The re-coordination of the delivered power causes the potential Vbus to increase from the first setpoint value to the second setpoint value, and also causes the charging of the capacitor element C.

[0064] To limit the current drawn by the capacitor element C during charging, interface 110 includes circuitry 206 configured to limit the inrush current below a threshold defined by USB PD technology. Circuitry 206 includes a capacitor element C1 and a resistor R1 connected in series between node 116 and the gate of transistor 200.

[0065] In this example, the values ​​of resistor R1 and capacitor C1 are determined based on the current threshold and the maximum value of capacitor C as defined by USB PD technology, which is, for example, approximately several hundred nanofarads.

[0066] Figure 3 Shown in more detail Figure 1Another example of part of interface 110. More specifically, Figure 3 Another example of an implementation of the switch IT and its control circuit CTRL is shown. Figure 2 Interface 110 and shown in the figure Figure 3 The interface 110 shown includes several common elements, and these differences are highlighted here only in interface 110.

[0067] and Figure 2 Compared to interface 110, Figure 3 Interface 110 switch IT ( Figure 1 It is implemented not only using transistor 200, but also using PMOS transistor 300.

[0068] The source of transistor 300 is coupled, for example, in Figure 3 In the example, it is connected to node 201. The drain of transistor 300 is coupled to, for example, node 112 connected to interface 110.

[0069] In this example, node 204 of the control circuit CTRL is coupled to the gate of transistor 300, for example, via resistor R2'.

[0070] Transistor 300 provides protection against reverse voltage. In other words, resistor 300 prevents positive current from flowing from terminal 116 to terminal 112 when transistor 300 is turned off, for example when the gate-source circuit is zero or the potential Vbus is negative.

[0071] Combination Figure 2 and Figure 3 The example of the described interface 110 effectively enables the inrush current caused by the capacitor element C to be limited below a threshold defined by the USB PD technology when the value of the capacitor element C is less than or equal to the maximum value defined by the USB PD technology.

[0072] Applications 120 (e.g., audio applications) where the capacitor element C typically has a power consumption of P1 but occasionally requires a power supply P2 greater than P1 are considered examples, where the capacitor element C typically has a power consumption of P1 less than or equal to the maximum value defined by USB PD technology.

[0073] For the coupling to connector 100 ( Figure 1 For application 120 to be correctly powered by USB PD power, the negotiated power should be greater than power P2, or when the application consumes P1, the negotiated power should be greater than P1, and each time the application consumes power P2, the power can be renegotiated to be greater than power P2. However, a negotiated power-limited power supply that ensures the operation of application 120 always has power greater than P2 can be delivered simultaneously to device 1. Figure 1One or more other devices suitable for USB PD technology are powered. Furthermore, renegotiation of a power supply greater than power P2 is undesirable each time application 120 occasionally consumes power P2, and more generally, it is impossible when the time required to renegotiation of power supply is greater than the time application 120 needs power P2 to be properly powered.

[0074] The inventors therefore provide a technique for increasing the value of capacitor C above the maximum value defined by USB PD technology, so that application 120 can be correctly powered when the negotiated power is between power P1 and P2. More precisely, the inventors provide an increase in the value of capacitor C such that when application 120 occasionally consumes power P2, the difference between power P1 and power P2 is delivered by capacitor C, which makes it possible to keep the negotiated power less than P2.

[0075] As an example, application 120 has a power P1 of less than or equal to 30W and occasionally consumes power P2, equal to 100W for 5ms. Further, the negotiated power is assumed to be equal to 30W and corresponds to a 15V setpoint value for the potential Vbus. The capacitor element C should be able to deliver an additional 70W, i.e., an additional 4.6A of current, at a potential Vbus of 15V. To ensure that the potential Vbus does not drop to the UVLO threshold (which in this example is equal to 0.95 times the setpoint value of the potential Vbus), the potential Vbus should not drop more than 750mV. Consequently, the capacitor element C should have a value at least equal to 4.6 * 0.005 / 0.75 = 3000μF, which is significantly larger than the maximum value of the capacitor element C defined by USB PD technology.

[0076] However, when the value of capacitor C is greater than the maximum value defined by USB PD technology, and when the components R1 and C1 of circuit 206 have been determined based on the maximum value of capacitor C, circuit 206 no longer enables the surge current to be kept below the current threshold defined by USB PD technology during the charging of capacitor C.

[0077] The values ​​of elements R1 and C1 in circuit 206 can be modified based on the value of capacitor element C. However, this can result in different interfaces 110 depending on the value of capacitor element C; that is, different interfaces 110 can be generated depending on each application 120 connected to these interfaces 110. This can complicate development, and the production of these interfaces 110 is undesirable.

[0078] Figure 4 An example of interface 110' is schematically shown, its alternatives Figure 1 Interface 110 of device 1 in the middle.

[0079] Similar to interface 110 ( Figure 1 , Figure 2 and Figure 3 Interface 110' includes nodes 112, 114, 116 and 201, transistor 200 and circuit 206.

[0080] Interface 110' also includes a resistor Rshunt, which is connected between node 201 and node 400, which is connected to the source of transistor 200. Figure 4 In the embodiment shown, node 201 is connected to node 112. In an alternative embodiment, node 201 is composed of transistor 300. Figure 3 ) is coupled to node 112, and node 201 is then connected to the source of transistor 300.

[0081] Interface 110' also includes circuitry CTRL' for controlling transistor 200, only a portion of which is shown and defined by Figure 4 The dashed line in the diagram defines this part of the circuit CTRL', for example, equal to... Figure 2 The relevant description is of the CTRL section of the circuit. Figure 4 In the example, the voltage divider bridge R2, R3 of circuit CTRL' is connected to node 201, although it could be connected to node 400 in other examples. However, preferably, the voltage divider bridge R2, R3 is configured to be connected to node 201, which allows current in resistor Rshunt, used to control the gate-source voltage of transistor 200, to be supplied to application 120. Figure 1 The current.

[0082] Interface 110' also includes a PNP transistor 402. The collector of transistor 402 is connected to the gate of transistor 200, that is, to node 204 in this example. In this embodiment, the emitter of transistor 402 is connected to node 201.

[0083] Interface 110' includes a combination of Figure 4 The circuit 404 is defined by the dashed line in the diagram. Circuit 404 is configured to deliver a control potential to the base of transistor 402. The control potential is determined by circuit I in resistor Rshunt. More specifically, circuit 404 is configured to determine the base potential of resistor 202 from current I such that current I is limited with respect to a current threshold Ilim, i.e., such that current I remains less than the threshold Ilim. The current threshold Ilim is determined by USB PD technology, which defines the maximum value Imax of current I, and interface 110' is authorized to draw current from node 112. For example, the threshold Ilim is less than or equal to the value Imax.

[0084] exist Figure 4In this embodiment, circuit 404 corresponds to or includes a direct connection between node 400 and the base of transistor 402. The threshold Ilim is, for example, substantially equal to Vbelim multiplied by the value of resistor Rshunt, where Vbelim is the turn-on voltage of the base-emitter diode of transistor 402.

[0085] In this embodiment, when resistor 200 is conductive and potential Vin is less than potential Vbus, capacitor element C( Figure 1 A current I is drawn to charge the transistor 202. The difference between potentials Vin and Vbus then corresponds to the voltage across resistor Rshunt and the sum of the source-drain voltages of transistor 200. Once the current I equals Ilim, the base-emitter voltage of transistor 402 equals Vbelim and transistor 402 is turned on. If the current I tends to increase above the threshold Ilim, it tends to decrease the base voltage of transistor 402, and therefore decreases the emitter-collector voltage of transistor 402. This decrease in the emitter-collector voltage of transistor 402 corresponds to a decrease in the gate-source voltage of transistor 200, making transistor 200 more resistive, which causes the current I to decrease to the value Ilim. However, as long as the current I is less than the current Ilim, resistor 402 is clamped and resistor 200 is turned on (saturated).

[0086] Figure 5 Another example of interface 110' is shown schematically. (Relative to...) Figure 5 The described interface 110' includes relative to Figure 4 The interface 110' described has the same multiple components, and only the differences between the two interfaces 110' are emphasized here.

[0087] Figure 5 Interface 110' and Figure 4 The difference in the interface lies in its circuit 404.

[0088] In this embodiment, circuit 404 does not include a direct connection between the base of transistor 402 and node 400. In this embodiment, circuit 404 includes an NPN transistor 500. The emitter of transistor 500 is coupled, for example, to node 114. The collector of transistor 500 is coupled to node 201 via a voltage divider bridge. The voltage divider bridge includes an intermediate node 502 configured to deliver a control potential to the base of transistor 402. In this example, the voltage divider bridge includes two resistors R4 and R5, resistor R4 connected to node 201 and resistor R5 connected to resistor 500, and node 502 corresponds to the node where resistor R4 is connected to resistor R5. In this embodiment, circuit 404 includes circuit 504. Circuit 504 is configured to deliver a potential to the base of resistor 500, which is determined from the voltage across resistor Rshunt. Circuit 504 is therefore configured to receive the voltage across resistor Rshunt. Circuit 504 includes an input terminal connected to one terminal of resistor Rshunt and another resistor connected to the other terminal of resistor Rshunt. Circuit 504 delivers the base potential of transistor 500 such that this potential increases as the voltage across resistor Rshunt increases, thereby decreasing the control potential at node 502 as the voltage across resistor Rshunt increases. Therefore, as... Figure 4 As shown, when the current I in resistor Rshunt increases above the threshold Ilim and causes an increase in the voltage across resistor Rshunt, this controls a corresponding decrease in the potential at the base of transistor 402, and therefore a corresponding decrease in the gate-source voltage of transistor 200. This allows for a corresponding increase in the drain-source voltage of transistor 200 and thus a corresponding decrease in the current I. The current I in resistor Rshunt is therefore controlled to be limited relative to the threshold Ilim, or in other words, to keep the current I less than or equal to the threshold Ilim.

[0089] As with Figure 3 In contrast, where the threshold Ilim is determined by the value of resistor Rshunt and by the on-state voltage of the emitter-base diode of transistor 402, in this embodiment, the threshold Ilim is determined at least in part by the gain of circuit 504 between the voltage received by circuit 504 and the potential delivered by circuit 504.

[0090] Therefore, as with Figure 4 Compared to the previous embodiment, the value of resistor Rshunt can be reduced, which makes it possible to reduce the power dissipated by resistor Rshunt.

[0091] According to an embodiment, the gain of circuit 504 is variable, and it is determined by the value of the negotiated power, i.e., for example, by the value of the potential Vbus received by interface 110'. The provision of variable gain allows for adjustment of the value of the threshold Ilim based on the value of the negotiated power. As an example, although this is not explicitly stated... Figure 5 As shown, circuit 404 includes a voltage divider bridge between the bases of transistor 500 and the output of circuit 504 is coupled to the base of transistor 500, and at least one transistor of the voltage divider bridge has a value controlled by the value of Vbus. For example, the controlled value of the resistor is achieved by a parallel connection of a potential-controlled resistor determined by the potential Vbus and a MOS transistor.

[0092] In an alternative embodiment (not shown), the voltage divider bridges R4 and R5 of circuit 404 couple the collector of transistor 500 to node 400 instead of node 201.

[0093] In another embodiment (not shown), circuit 404 is implemented using an operational amplifier. The operational amplifier has a negative feedback loop (i.e., feedback between its output and its inverting input). The amplifier is configured to deliver a control potential to the base of transistor 402, which decreases as the current I increases with respect to a threshold Ilim, i.e., when the voltage across the resistor increases to a value greater than a voltage threshold (which is equal to Ilim multiplied by the value of resistor Rshunt). The amplifier has a first input (e.g., inverting) coupled to node 201 and a second input (e.g., non-inverting) coupled to node 400. The output of the amplifier is coupled to the base of transistor 402. The amplifier is powered by a potential Vbus referenced to a floating ground delivered to the operational amplifier. As an example, a Zener diode and a resistor are connected in series between nodes 201 and 114, and the node connecting the diode to the resistor is configured to deliver the floating ground to the operational amplifier.

[0094] According to a variation of this embodiment, the gain of the operational amplifier is variable and is determined by negotiated power, for example, by the value of the potential Vbus. As an example, the resistor in the feedback loop, or the resistor coupling the amplifier's input to the corresponding terminal of resistor Rshunt, has a controllable value. This controllable resistor is implemented, for example, by a method similar to that described for the case where the gain of circuit 504 is variable and determined by negotiated power.

[0095] Figure 6 schematically shown Figure 5 Alternative implementations of the interface. Only emphasized in... Figure 6 Interface 110' and in Figure 5 The differences between the interfaces.

[0096] In this variant, the emitter of transistor 402 is connected to node 400 instead of node 201. Circuit 404 is similar to... Figure 5 The case where the collector of transistor 500 is coupled to node 400 by the voltage divider bridge R4, R5 of circuit 404 has been shown as an example. In other examples (not shown), the voltage divider bridge R4, R5 of circuit 404 couples the collector of transistor 500 to node 201 instead of node 400. In another embodiment (not shown), circuit 404 is implemented using an operational amplifier, similar to the case already discussed. Figure 5 The situation described.

[0097] Device 1 was described only above. Figure 1 Examples of embodiments and variations of the switch IT implemented using transistor 200. Of course, in device 1 ( Figure 1 In the case where the switch IT uses transistors 200 and 300, examples of these embodiments and variations can be readily adopted by those skilled in the art, where transistor 300 then couples node 201 to node 112, as per [reference to...]. Figure 3 The above describes the process. This will then, within the capabilities of those skilled in the art, provide circuitry for controlling transistor 300, for example, by directly or via a resistor coupling node 204 of circuit CTRL' to the base of transistor 300, or by providing dedicated control circuitry for resistor 300. Such specific control circuitry is, for example, similar to circuit CTRL' and subsequently includes an NPN transistor whose emitter is coupled to, preferably, node 114, and whose collector is coupled to node 201 or to node 400 via a voltage divider bridge having an intermediate node connected to the gate of transistor 300, the base of which receives a binary control signal.

[0098] In the above about Figure 4 , Figure 5 and Figure 6 In the described embodiments and variations, when the capacitor element C ( Figure 1 During charging, for example, when the potential Vbus reaches its default value after transistor 200 is turned on, or after a modification to a higher value of potential Vbus due to a renegotiation of the power supplied by the source of interface 110', transistor 402 and its control circuit 404 enable the limitation of the current I in resistor Rshunt.

[0099] However, when the potential Vbus decreases, for example, in device 1 ( Figure 1 After the device that supplies the potential Vbus to it, or after renegotiating the power supply to the interface, the target value of the potential Vbus is modified, and the potential Vin becomes greater than the potential Vbus, which is undesirable.

[0100] Therefore, according to an alternative embodiment, interface 110' also includes a function for controlling the capacitance element C when the potential Vin is greater than the potential Vbus (potentially with added margin). Figure 1 A device for discharging electricity.

[0101] Figure 7 An example of such an alternative embodiment of interface 110' is illustrated schematically. Figure 7 Interface 110' includes... Figure 5 Multiple components share the same interface, and the differences between these interfaces are emphasized. Furthermore, to avoid... Figure 7 Overload, circuit 404 is shown here in the form of a box.

[0102] and Figure 5 Compared to interface 110', Figure 7 The interface 110' also includes circuit 700 and switch 702.

[0103] Circuit 702 is configured to deliver the binary signal cmd1 in a first binary state when the potential Vin is greater than the potential Vbus with the added margin, for example, corresponding to the high state signal cmd1. Circuit 702 is also configured to deliver the signal cmd1 in a second binary state when the potential Vin is less than or equal to the potential Vbus with the added margin, for example, corresponding to the low state of the signal cmd1.

[0104] Switch 702 is configured to couple node 116 to node 114 when signal cmd1 is in its first state.

[0105] Therefore, when the potential Vin becomes greater than the increased margin potential Vbus, that is, when the potential Vin becomes greater than the sum of the potential Vbus and the margin, circuit 700 switches signal cmd1 to its first binary state, which turns on switch 702. As a result, node 116 is coupled to node 114 via switch 702, and the capacitor element C connected between nodes 116 and 114 ( Figure 1 Discharge to grounded GND.

[0106] Once the potential Vin becomes equal to or greater than the grounded Vbus with added margin, circuit 700 switches signal cmd1 to its second binary state, which turns off switch 702. This causes the discharge of capacitor C to stop and the potential Vin to decrease.

[0107] Preferably, switch 702 is connected in series with resistor R6 between nodes 116 and 114, and the resistor preferably couples node 116 to switch 702.

[0108] For example, switch 702 is implemented by a MOS transistor (e.g., an NMOS transistor). For example, the gate of transistor 702 receives signal cmd1, the source of transistor 702 is coupled to (e.g., connected to) node 114, and the drain of transistor 702 is coupled to node 116.

[0109] according to Figure 7 In the embodiment shown, circuit 700 includes a PNP transistor 704. Transistor 704 has, in this example, a base coupled to node 201 via resistor R8, a collector coupled to node 114 via resistor R7, and an emitter connected, for example, to node 116. The signal cmd1 is available at the collector of transistor 704, or in other words, the signal cmd1 is delivered to the collector of transistor 704. For example, the margin added to potential Vbus is determined at least in part by the on-threshold of the base-emitter diode of transistor 704, and in this example, by the value of resistor R8.

[0110] According to an embodiment, interface 110' is also configured to, in capacitor element C ( Figure 1 During the discharge period, that is, when switch 702 is turned on, the power path between nodes 112 and 116 is disconnected to prevent positive current from flowing from node 116 to node 112.

[0111] More specifically, in Figure 7 In the illustrated embodiment, this function is implemented via circuit CTRL' and transistor 200. Circuit CTRL' is then configured to control the closing of transistor 200 when signal cmd1 is in its first binary state. According to an embodiment, circuit CTRL' includes a switch 706 that couples node 114 to the base of transistor 202, and switch 706 is configured to be turned on when signal cmd1 is in its first binary state. For example, switch 706 is implemented by a MOS transistor (e.g., an NMOS transistor). The NMOS transistor has, for example, its gate configured to receive signal cmd1, and its drain coupled to, preferably connected to node 114. Thus, when signal cmd1 is in its first binary state, switch 706 draws the base of transistor 202 to ground GND, thereby turning off transistor 200.

[0112] In another embodiment (not shown), transistor 300 ( Figure 3 A transistor 300 is configured between nodes 121 and 112, and the power path is disconnected by turning off two transistors 200 and 200. The circuitry of transistor 300 is adapted to control the circuit such that transistor 300 is turned off when signal cmd1 is in its first binary state, as is possible for those skilled in the art.

[0113] Although this is not Figure 7In the case of the above, interface 110' preferably includes transistor 300 between nodes 201 and 112. Therefore, when potential Vbus is lower than potential Vin and transistor 300 is blocked, potential Vbus is not modified by circuit 700. In fact, when there is no transistor 300, when potential Vbus is lower than potential Vin and transistor 200 is blocked, potential Vbus can be changed due to the positive leakage current flowing from node 116 to node 201 via circuit 700.

[0114] Despite Figure 7 In the circuit 404 and transistor 402, regarding Figure 5 The described methods are implemented and connected, but to the extent that those skilled in the art are capable, regarding Figure 7 The description is suitable for the following situations: the emitter of transistor 402 is connected to node 402 instead of node 201, and / or the voltage divider bridge R4, R5 of circuit 404 is connected to node 201 instead of node 400, or circuit 404 is implemented using an operational amplifier, or circuit 404 corresponds to node 201 and is directly connected to the base of transistor 402, and / or the voltage divider bridge R2, R3 of circuit CTRL' is connected to node 400 instead of node 201.

[0115] Figure 8 schematically shown Figure 5 Another alternative embodiment of interface 100'. Figure 8 Interface 110' includes and Figure 7 The interfaces 110' have the same multiple components, and the differences between the two interfaces 110' are only emphasized here. In order to avoid Figure 8 The overload, circuit 404 and control CTRL' are shown in boxes here.

[0116] exist Figure 8 In a variant, circuit 700 does not include transistor 704 and resistors R7 and R8. In this variant, circuit 700 includes a comparator 800 implemented by an operational amplifier. Operational amplifier 800 includes a first input coupled to node 201, such as inverting (-), a second input coupled to node 116, such as non-inverting (+), and an output delivering signal cmd1.

[0117] For example, such as Figure 8As shown, the first input of comparator 800 is coupled to node 112 via a voltage divider bridge, and the second input of comparator 800 is coupled to node 116 via another voltage divider bridge. Preferably, the first input is coupled, for example, to an intermediate node of a voltage divider bridge that couples node 201 to node 114, node 114 including, for example, two resistors R9 and R10 connected in series between node 201 and node 114, and the second input is coupled, for example, to a voltage divider bridge that couples node 116 to node 114. In another example not shown, the first input of comparator 800 is connected to node 112 instead of node 201 via a voltage divider bridge connected between nodes 112 and 114.

[0118] The margin added to potential Vbus during the comparison can be determined by the value of the resistor in the voltage divider bridge of circuit 700, and can be chosen to be zero, i.e., omitted.

[0119] Figure 8 The embodiment of circuit 700 is compared to Figure 7 The advantage of the embodiment of circuit 700 is that it has a shorter response time, which leads to faster detection when the potential Vin is greater than the potential Vbus, which may have increased the margin.

[0120] According to the embodiments, such as Figure 7 As shown, Figure 8 Interface 110' is also configured to be in capacitor element C ( Figure 1 During the discharge period, that is, when switch 702 is turned on, the power path between node 112 and node 116 is disconnected to prevent positive current from flowing from node 116 to node 112.

[0121] More specifically, Figure 8 In the embodiment shown, the interface includes a transistor 300 coupled from node 201 to node 112, and this functionality is implemented via the transistor 300 and a circuit CTRL” for controlling the transistor 300. The circuit CTRL” is then configured to control the transistor 300 to turn off when the signal cmd1 is in its first binary state.

[0122] according to Figure 8 The embodiment shown has a circuit CTRL” similar to the previously combined Figure 7The described circuit CTRL' includes an NPN transistor 802 and a voltage divider bridge connected in series between node 114 and node 201 or 400 (node ​​201 in this example). The emitter of transistor 802 is coupled (e.g., connected) to node 114, and the collector of transistor 802 is coupled to node 201 (or 400, if desired) via the voltage divider bridge. In this example, the voltage divider bridge includes two resistors R13 and R14, with the terminal of resistor R13 connected to node 201 (or 400, if desired). The intermediate node of the voltage divider bridge, in this example, the connection node 804 between resistors R13 and R14, is connected to the gate of transistor 300. The base of transistor 802 is configured to receive a binary signal EN'. The binary signal EN' is transmitted, for example, by a portion of the circuit CTRL” (not shown). When signal EN' is in a first binary state, for example, corresponding to a high potential, transistor 300 is turned on. When signal EN” is in a second binary state, for example, corresponding to a low potential, such as ground potential GND, transistor 300 is clamped. Figure 7 Similar to the circuit CTRL', in order to control the turn-off of transistor 300 when signal cmd1 is in its first binary state, circuit CTRL' includes a switch 806 that couples the base of transistor 802 to node 114. Switch 806 is configured to be turned on when signal cmd1 is in its first binary state. For example, switch 806 is implemented by a MOS transistor (e.g., an NMOS transistor). NMOS transistor 806 has, for example, a gate configured to receive signal cmd1, its drain coupled, preferably connected to the base of transistor 802, and its source coupled, preferably connected to node 114. Therefore, when signal cmd1 is in its first binary state, switch 806 pulls the base of transistor 802 to ground GND, thereby turning off transistor 300.

[0123] and Figure 7 Compared to the case where the power path is disconnected by turning off transistor 200, Figure 8 The embodiment that disconnects the power path by turning off transistor 300 has the following advantages: the body diode of the turn-off transistor 300 prevents positive current from flowing from node 116 to node 112, which is not the case with the body diode of transistor 200.

[0124] Although not shown, in other variations, circuit 700 is implemented as Figure 7 The relevant description in the text, and the power path is disconnected through transistor 300 and circuit "CTRL", or circuit 700 as per the description. Figure 8 The implementation is as described, and the power path is disconnected by transistor 200 and control circuit CTRL'.

[0125] In Figure 7The same method will be used within the capabilities of those skilled in the art regarding Figure 8 The description is suitable for the following situations: the emitter of transistor 402 is connected to node 400 instead of node 201, and / or the voltage divider bridge R4, R5 of circuit 404 is connected to node 201 instead of node 400, or circuit 404 is implemented by an operational amplifier, or circuit 404 corresponds to a direct connection from node 201 to the base of transistor 402, and / or the voltage divider bridge R2, R3 of circuit CTRL' is connected to node 400 instead of node 201.

[0126] Previous regarding Figure 4 , Figure 5 , Figure 6 , Figure 7 or Figure 8 In the described interface 110', when the power supply renegotiated by interface 110' causes an increase in potential Vbus, for the example required by USB PD technology, for capacitor element C ( Figure 1 ), and for the more general application 120, it is desirable not to draw current during the growth of potential Vbus.

[0127] Therefore, according to an embodiment, interface 110' includes a device configured to turn off transistor 200 when potential Vbus increases from a first setpoint value to a second setpoint value, these setpoint values ​​being determined, for example, by a corresponding negotiated power.

[0128] Figure 9 schematically shown Figure 8 In an alternative embodiment of interface 110', when interface 110' is configured to turn off switch 200, the potential Vbus increases due to power renegotiation. To avoid overloading the figures, circuits 404 and 700 are shown in block form. Furthermore, only emphasis is placed here. Figure 9 Interface 110' and Figure 8 The differences between the interfaces.

[0129] and Figure 8 Compared to interface 110', Figure 9 Interface 110' also includes an NPN transistor 900. Transistor 900 has an emitter coupled to, for example, a node 201 or node 400. Transistor 900 has a collector connected to the gate of transistor 200. Interface 110' also includes a resistor R15 and a capacitor C15 connected in series between the base of transistor 900 and node 114.

[0130] When the potential Vbus is at the first setpoint value, capacitor C15 is charged to a potential substantially equal to Vbus, or in other words, the potential of the electrode of capacitor C15 opposite to the electrode connected to node 114 is substantially equal to Vbus. If the potential Vbus increases to a second setpoint value greater than the first setpoint value, this causes an increase in the base-emitter voltage of transistor 900. As a result, this allows the midpoint of capacitor C15 to charge in line with the increase in potential Vbus, as long as transistor 900 remains on. Furthermore, as long as transistor 900 remains on, the gate-source voltage of transistor 200 causes transistor 200 to turn off and no current is drawn to node 116.

[0131] When the potential Vbus is set to its second setpoint value, and capacitor element C15 has been charged to a potential substantially equal to that second setpoint voltage, transistor 900 is clamped, and the gate-source voltage of transistor 200 is then determined by circuit CTRL' and is sufficient to switch transistor 200 to the on state, while limiting inrush current to capacitor element C15 via transistor 402 and its control circuit 404. Figure 1 )Charge.

[0132] According to an embodiment, interface 110' also includes a device for discharging capacitor element C15 when potential Vbus becomes less than potential Vin, for example, when the set point value of potential Vbus is corrected downward, or when the device delivering power to interface 110' is disconnected.

[0133] This is, for example, in Figure 9 In the situation, Figure 9 In the example, the discharge device is a simple diode D1 that couples the base of transistor 900 to the emitter of transistor 900, with the anode of diode D1 on the base side, for example connected to the base of transistor 900.

[0134] In another example, not shown, the discharge mechanism for capacitor C15 is implemented by a switch connected in parallel with capacitor C15. The switch is controlled, for example, by a signal cmd1 or a signal derived from cmd1, such that the switch is turned off when transistor 202 is clamped. For example, this switch is implemented using an NMOS transistor whose gate is coupled to the collector of transistor 202.

[0135] According to an embodiment, the circuit CTRL' is implemented by transistor 202 and a voltage divider bridge (e.g., R2, R3), and transistor 900 can also be used to turn off transistor 200 during an overvoltage event on potential Vbus. This is Figure 9In the case of interface 110', Zener diode D16 and resistor R16 are connected in series between the base of transistor 900 and the collector of transistor 202, with the anode of diode D16 on the collector side of transistor 202, for example, connected to the collector of transistor 202.

[0136] although Figure 9 This illustrates the case where the power path is interrupted by the turn-off of transistor 300 when the potential Vin is greater than the potential Vbus, which may have increased the margin. Figure 9 The description applies to the disconnection of the power path, which is performed by the shutdown of transistor 200, or even by both transistors 200 and 300.

[0137] In addition, for Figure 7 and Figure 8 Modify the following conditions regarding Figure 9 The description made is within the scope of the art: the emitter of transistor 402 is connected to node 400 instead of node 201, and / or the voltage divider bridges R2 and R3 of circuit CTRL' are connected to node 400 instead of node 201, and / or the voltage divider bridges R13 and R14 of circuit CTRL" are connected to node 400 instead of node 201, and / or interface 110' does not include transistor 300 and its control circuit.

[0138] The above description of... Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 In embodiments and variations, the signal EN and possibly the signal EN' are delivered, for example, by a processing unit (e.g., including a microprocessor, state machine, or microprocessor). As a variation, the signal EN is delivered by a voltage divider bridge that couples node 201 or node 400 to node 114, for example by an intermediate node of the voltage divider bridge, and possibly the signal EN' is delivered by the same voltage divider bridge, and for example, corresponding to the signal EN, or delivered by another voltage divider bridge that couples node 201 or 400 to node 114, the signal EN' is available at an intermediate node of that other voltage divider bridge.

[0139] Furthermore, although embodiments and variations of interface 110' are more specifically suited to operation using a capacitor element C with a larger value (e.g., at least ten times) greater than the maximum value of that capacitor element as defined by the USB PD technology already described, the advantage of interface 110' is that it can also be used with a capacitor element C value less than or equal to that maximum value. Regardless of the value of capacitor element C, interface 110' can therefore be implemented without needing to know that value.

[0140] Although interface 110' is described in the case that interface 110' is connected to a USB-C connector, interface 110' can be used with other types of connectors.

[0141] Furthermore, although embodiments and variations of the transistor being a bipolar transistor have been described, in embodiments where the signal EN is supported by digital circuitry (e.g., a microcontroller), transistor 202 may be replaced by a MOS transistor (e.g., an NMOS transistor). Similarly, in embodiments and variations where the control signal EN' of transistor 802 is provided by digital circuitry, transistor 802 may be replaced by a MOS transistor (e.g., an NMOS transistor).

[0142] In the embodiments and variations described in detail, the interface includes circuitry 206. However, circuitry 206 may be omitted, particularly when line 404 includes a direct connection from the base of transistor 402 to node 400, as already combined. Figure 4 As described.

[0143] Additionally, it should be noted that embodiments and variations in which interface 110' includes transistor 300, and in which none of circuits CTRL', CTRL'', and 700 are connected to node 112, have the advantage of preventing positive current leakage from node 116 to node 112 when potential Vin is greater than potential Vbus.

[0144] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, those skilled in the art can adapt the embodiments and variations described above to cases where transistor 200 and, when transistor 300 is present, NMOS transistors are used instead of PMOS transistors, particularly by replacing PNP transistors with NPN transistors, and by making the nodes suitable for the connections to these transistors. For example, when an NPN transistor is replaced by a PNP transistor, the NPN transistor couples its emitter at potential P to or connects to node 114, and the emitter of the PNP transistor is coupled to or connected to a node at a reference potential other than ground GND, this new reference potential being greater than the Vbus potential.

[0145] Finally, based on the functional indications given above, actual implementations of the described embodiments and variations are within the capabilities of those skilled in the art. In particular, circuits CTRL', CTRL'', 404, and 700 are not limited to the examples described above, and other embodiments of these circuits will be provided within the capabilities of those skilled in the art.

Claims

1. A Universal Serial Bus (USB) power delivery type interface, comprising: The first node is configured to receive a first power supply potential, the second node is configured to deliver a second power supply potential, and the third node is configured to be at a reference potential. The first resistor is connected between the fourth and fifth nodes coupled to the first node; A first metal-oxide-semiconductor transistor is connected between the fifth node and the second node; The second bipolar transistor has a collector connected to the gate of the first metal-oxide-semiconductor transistor and an emitter connected to the fourth node or the fifth node; as well as A first circuit is configured to deliver a control potential determined from the current in the first resistor to the base of the second bipolar transistor; The first circuit includes: an operational amplifier having a first input coupled to the fourth node, a second input coupled to the fifth node, and an output coupled to the base of the second bipolar transistor; And a diode and a resistor connected in series between the fourth node or the fifth node and the third node, wherein the node where the diode and the resistor are connected is configured to deliver a floating ground to the operational amplifier, the gain of which is variable and determined by the first power supply potential.

2. The interface of claim 1, wherein the first circuit is configured to determine the control potential to limit the current in the first resistor relative to a current threshold.

3. The interface of claim 2, wherein the first circuit is configured to increase the base-emitter voltage of the second bipolar transistor when the current in the first resistor increases to above the current threshold.

4. The interface according to claim 1, wherein the first metal-oxide-semiconductor transistor is a P-channel metal-oxide-semiconductor transistor, and the second bipolar transistor is a PNP transistor.

5. The interface according to claim 4, further comprising: The second circuit is configured to deliver a binary signal in a first binary state when the second power supply potential is greater than the first power supply potential, which may have an increased margin. as well as A switch is configured to couple the second node to the third node when the binary signal is in its first state.

6. The interface of claim 5, wherein the second circuitry comprises: A PNP transistor having a base coupled to the fourth node, a collector coupled to the third node via a resistor, and an emitter coupled to the second node, wherein the binary signal is delivered by the collector of the PNP transistor; or The comparator includes an operational amplifier having a first input coupled to the fourth node or the first node, a second input coupled to the second node, and an output that delivers the binary signal.

7. The interface of claim 5, wherein the emitter of the PNP transistor is connected to the second node.

8. The interface according to claim 4, further comprising: The circuit for controlling the first metal-oxide-semiconductor transistor includes a fifth transistor and a voltage divider bridge having an intermediate node connected to the gate of the first metal-oxide-semiconductor transistor. The fifth transistor of the circuit for controlling the first metal-oxide-semiconductor transistor has a conductive terminal coupled to the third node and another conductive terminal coupled to the fourth node or the fifth node through the voltage divider bridge. The fifth transistor of the circuit for controlling the first metal-oxide-semiconductor transistor is an NPN transistor, and the interface further includes another voltage divider bridge that couples the fourth node or the fifth node to the third node, and the other voltage divider bridge has an intermediate node connected to the base of the NPN transistor of the circuit for controlling the first metal-oxide-semiconductor transistor.

9. The interface according to claim 8, further comprising: The second circuit is configured to deliver a binary signal in a first binary state when the second power supply potential is greater than the first power supply potential, which may have an increased margin. as well as A switch is configured to couple the second node to the third node when the binary signal is in the first binary state. The circuitry for controlling the first metal-oxide-semiconductor transistor also includes a switch configured to couple the control terminal of the fifth transistor of the circuitry for controlling the first metal-oxide-semiconductor transistor to the third node when the binary signal is in the first binary state.

10. The interface of claim 4, further comprising a third P-channel metal-oxide-semiconductor transistor coupling the fourth node to the first node.

11. The interface according to claim 10, further comprising: The circuit for controlling the third P-channel metal-oxide-semiconductor transistor includes a fifth transistor and a voltage divider bridge having an intermediate node connected to the gate of the third P-channel metal-oxide-semiconductor transistor. The fifth transistor of the circuit for controlling the third P-channel metal-oxide-semiconductor transistor has a conductive terminal coupled to the third node and another conductive terminal coupled to the fourth node or the fifth node through the voltage divider bridge. The fifth transistor of the circuit for controlling the third P-channel metal-oxide-semiconductor transistor is an NPN transistor, and the interface further includes another voltage divider bridge that couples the fourth node or the fifth node to the third node, and the other voltage divider bridge has an intermediate node connected to the base of the NPN transistor of the circuit for controlling the third P-channel metal-oxide-semiconductor transistor.

12. The interface according to claim 11, further comprising: The second circuit is configured to deliver a binary signal in a first binary state when the second power supply potential is greater than the first power supply potential, which may have an increased margin. as well as A switch is configured to couple the second node to the third node when the binary signal is in the first binary state. The circuit for controlling the third P-channel metal-oxide-semiconductor transistor also includes a switch configured to couple the control terminal of the fifth transistor of the circuit for controlling the third P-channel metal-oxide-semiconductor transistor to the third node when the binary signal is in the first binary state.

13. The interface according to claim 4, further comprising: The fourth NPN transistor has an emitter connected to the fourth node or the fifth node, and a collector connected to the gate of the first metal-oxide-semiconductor transistor. Resistor; as well as A capacitor element is connected in series with the resistor between the base of the fourth NPN transistor and the third node.

14. The interface of claim 13, further comprising means for discharging the capacitor element, the means being configured to discharge the capacitor element when the second power supply potential is greater than the first power supply potential which may have increased the margin.

15. The interface of claim 14, wherein the device for discharging comprises: A diode, the anode of which is coupled to the base of the fourth NPN transistor, and the cathode of which is coupled to the emitter of the fourth NPN transistor; or The switch is connected in parallel with the capacitor.

16. The interface of claim 13, further comprising: The circuit for controlling the first metal-oxide-semiconductor transistor includes a fifth transistor and a voltage divider bridge having an intermediate node connected to the gate of the first metal-oxide-semiconductor transistor. The fifth transistor of the circuit for controlling the first metal-oxide-semiconductor transistor has a conductive terminal coupled to the third node and another conductive terminal coupled to the fourth node or the fifth node by the voltage divider bridge. as well as A resistor and a Zener diode are connected in series between the base of the fourth NPN transistor and the conductive terminal of the fifth transistor, which is part of a circuit for controlling the first metal-oxide-semiconductor transistor.

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