Signal processing method, electronic device, and computer-readable medium

Abstract

The present disclosure provides a signal processing method, comprising: determining a transform kernel matrix based on a time-frequency transform type; mapping the transform kernel matrix to multiple processing cores of a many-core chip; and mapping a time domain signal to the multiple processing cores so that the multiple processing cores determine a frequency domain signal corresponding to the time domain signal based on the transform kernel matrix and the time domain signal. The present disclosure also provides an electronic device and a computer-readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a signal processing method, an electronic device, and a computer-readable medium. Background Art

[0002] Common time-frequency transforms include discrete Fourier transform (DFT), discrete cosine transform (DCT), fast Fourier transform (FFT), and chirp Z-transform (CZT).

[0003] In some related technologies, the flexibility of implementing time-frequency conversion using traditional high-efficiency time-frequency conversion devices is relatively poor. Summary of the Invention

[0004] The present disclosure provides a signal processing method, an electronic device, and a computer-readable medium.

[0005] In a first aspect, the present disclosure provides a signal processing method, comprising:

[0006] Determine the transformation kernel matrix according to the time-frequency transformation type;

[0007] Mapping the transformation kernel matrix to multiple processing cores of a many-core chip;

[0008] The time domain signal is mapped to the plurality of processing cores, so that the plurality of processing cores determine a frequency domain signal corresponding to the time domain signal according to the transformation core matrix and the time domain signal.

[0009] In a second aspect, the present disclosure provides an electronic device, including:

[0010] multiple processing cores; and

[0011] an on-chip network configured to exchange data between the plurality of processing cores and external data;

[0012] One or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the signal processing method described in the first aspect of the embodiment of the present disclosure.

[0013] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements the signal processing method described in the first aspect of the embodiment of the present disclosure.

[0014] In the embodiment of the present disclosure, a transformation kernel matrix is ​​determined according to the time-frequency transformation type. By configuring the transformation kernel matrix to multiple processing cores of a many-core chip and inputting a time domain signal into the multiple processing cores of the many-core chip, the many-core chip can determine a frequency domain signal based on the time domain signal and the transformation kernel matrix. The time-frequency transformation types include but are not limited to DFT, DCT, FFT, and CZT, thereby enabling the many-core chip to implement a variety of time-frequency transformations. The multiple processing cores configured to the many-core chip can also be the parts of the transformation kernel matrix corresponding to any interval. The many-core chip can implement time-frequency transformation for any interval, thereby significantly saving the amount of computation and improving the efficiency of time-frequency transformation.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0017] Figure 1 is a flow chart of a signal processing method according to an embodiment of the present disclosure;

[0018] Figure 2 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0019] Figure 3 is a schematic diagram of implementing time-frequency conversion using a multi-core chip in an embodiment of the present disclosure;

[0020] Figure 4 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0021] Figure 5 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0022] Figure 6 is a schematic diagram of a time-frequency conversion pipeline operation in an embodiment of the present disclosure;

[0023] Figure 7 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0024] Figure 8 is a schematic diagram of an optional implementation of a multiplication cluster in an embodiment of the present disclosure;

[0025] Figure 9 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0026] Figure 10 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0027] Figure 11 is a flowchart of some steps in another signal processing method in an embodiment of the present disclosure;

[0028] Figure 12 A block diagram of the composition of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] To enable those skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0030] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0031] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0034] Research by the inventors of this disclosure has revealed that in some related technologies, high-efficiency time-frequency conversion devices are typically implemented using application-specific integrated circuits (ASICs). Each time-frequency conversion device can only implement a fixed time-frequency conversion algorithm, such as a time-frequency conversion device capable of implementing DCT or a time-frequency conversion device capable of implementing FFT. Furthermore, ASICs for implementing time-frequency conversion have many limitations. For example, the data input to the ASIC must be a power of 2 or the product of a prime number and 2. Therefore, the time-frequency conversion in related technologies is relatively inflexible.

[0035] In view of this, refer to Figure 1 , an embodiment of the present disclosure provides a signal processing method, including:

[0036] In step S100, a transformation kernel matrix is ​​determined according to the time-frequency transformation type;

[0037] In step S200, the transformation core matrix is ​​mapped to multiple processing cores of a many-core chip;

[0038] In step S300, the time domain signal is mapped to the plurality of processing cores, so that the plurality of processing cores determine the frequency domain signal corresponding to the time domain signal according to the transformation core matrix and the time domain signal.

[0039] The embodiment of the present disclosure aims to provide a solution for implementing time-frequency conversion based on a many-core chip. The many-core chip simulates the neural network of the human brain and can realize some of the functions of the human brain. The implementation of the present disclosure does not specifically limit the many-core chip. For example, the many-core chip can be composed of a single chip; the many-core chip can also be composed of multiple sub-chips, wherein each sub-chip has multiple computing units, and the smallest computing unit in each sub-chip that can be independently scheduled and has complete computing power is called a core. In a many-core chip, multiple cores can work together, and each core can independently run program instructions, using the power of parallel computing to speed up the running speed of the program and provide multi-tasking capabilities.

[0040] In the embodiments of the present disclosure, the type of time-frequency transform is not specifically limited. For example, the time-frequency transform type can be any one of DFT, DCT, FFT, and CZT. That is, the many-core chip in the embodiments of the present disclosure can implement multiple types of time-frequency transforms. Different time-frequency transform types correspond to different transform kernel matrices. In the embodiments of the present disclosure, the many-core chip implements reconfigurable time-frequency transforms, that is, by determining the transform kernel matrices of different time-frequency transform types and mapping the transform kernel matrices to corresponding processing cores, the corresponding type of time-frequency transform can be implemented.

[0041] In step S200 of the embodiment of the present disclosure, mapping the transformation kernel matrix to multiple processing cores of the many-core chip means configuring the transformation kernel matrix as a weight parameter in the local storage of the multiple many-core cores. The transformation kernel matrix can be obtained by dynamic calculation, static storage, or calculated based on the static storage value. The embodiment of the present disclosure does not specifically limit this. In step S300 of the embodiment of the present disclosure, mapping the time domain signal to multiple processing cores means inputting the time domain signal into the input buffer of the multiple processing cores. In the embodiment of the present disclosure, the time domain signal is stored as a one-dimensional vector. Multiple processing cores can calculate the frequency domain signal corresponding to the time domain signal based on the transformation kernel matrix and the one-dimensional vector.

[0042] It should be noted that in the embodiment of the present disclosure, in step S200, the entire transform kernel matrix can be mapped to multiple processing cores, or the transform kernel matrix corresponding to the target interval can be mapped to multiple processing cores. The embodiment of the present disclosure does not specifically limit this. In the scenario where the transform kernel matrix corresponding to the target interval is mapped to multiple processing cores, through steps S100 to S200, time-frequency conversion can be performed on the target interval to obtain a frequency domain signal corresponding to the target interval.

[0043] In the signal processing method provided by the embodiments of the present disclosure, a transformation kernel matrix is ​​determined according to the time-frequency transformation type. By configuring the transformation kernel matrix to multiple processing cores of a many-core chip and inputting a time domain signal into the multiple processing cores of the many-core chip, the many-core chip can determine a frequency domain signal based on the time domain signal and the transformation kernel matrix. The time-frequency transformation types include but are not limited to DFT, DCT, FFT, and CZT, thereby enabling the many-core chip to implement various time-frequency transformations. The multiple processing cores configured to the many-core chip can also be the parts of the transformation kernel matrix corresponding to any interval. The many-core chip can implement time-frequency transformation for any interval, thereby significantly saving the amount of computation and improving the efficiency of time-frequency transformation.

[0044] In the embodiment of the present disclosure, the frequency domain signal can be represented by a complex number, for example, the frequency domain signal X k =X k，R +jX j，I , k∈[0, N-1], that is, the frequency domain signal can be decomposed into a frequency domain real part vector and a frequency domain imaginary part vector. As an optional implementation method, when performing time-frequency transformation to determine the frequency domain signal corresponding to the time domain signal, the frequency domain real part vector and the frequency domain imaginary part vector corresponding to the frequency domain signal are determined respectively, and finally the frequency domain signal corresponding to the time domain signal is obtained. In the embodiment of the present disclosure, the many-core chip includes multiple processing cores, and the multiple processing cores can be combined into a processing core group for determining the frequency domain real part vector and a processing core group for determining the frequency domain imaginary part vector.

[0045] Accordingly, in some embodiments, the frequency domain signal can be decomposed into a frequency domain real part vector and a frequency domain imaginary part vector; Figure 2 , step S200 includes:

[0046] In step S210, a first processing core group for determining the frequency domain real part vector and a second processing core group for determining the frequency domain imaginary part vector are determined according to the transformation core matrix; the first processing core group includes at least one processing core, and the second processing core group includes at least one processing core;

[0047] In step S220 , the transformation core matrix is ​​mapped to the first processing core group and the second processing core group respectively.

[0048] It should be noted that after determining the first processing core group and the second processing core group through steps S210 to S220 and mapping the transformation core matrix to the first processing core group and the second processing core group, step S300 includes:

[0049] The time domain signals are mapped to the first processing core group and the second processing core group respectively.

[0050] In the embodiment of the present disclosure, the first processing core group and the second processing core group can run in parallel, the multiple processing cores in the first processing core group can also run in parallel, and the multiple processing cores in the second processing core group can also run in parallel, thereby enabling the massive parallel computing capabilities of the multi-core chip to be brought into play and achieving high-efficiency time-frequency conversion.

[0051] In the embodiment of the present disclosure, the time domain signal can be represented by a complex number, for example, the time domain signal x n =x n，R +jx n，I , n∈[0,N-1]. The transformation kernel can also be represented by complex numbers, for example, the transformation kernel In the embodiment of the present disclosure, the frequency domain signal X k The real part X k，R With the time domain signal x n , transformation kernel W nk Satisfy formula (1):

[0052]

[0053] Frequency domain signal X k The imaginary part X k，I With the time domain signal x n , transformation kernel W nk Satisfy formula (2):

[0054]

[0055] In the disclosed embodiment, the frequency domain signal is decomposed into a frequency domain real vector and a frequency domain imaginary vector, the transform kernel matrix is ​​decomposed into a transform real matrix and a transform kernel imaginary matrix, and the time domain signal is decomposed into a time domain real vector and a time domain imaginary vector. From formula (1), it can be seen that the frequency domain real vector = time domain real vector × transform real matrix - time domain imaginary vector × transform kernel imaginary matrix; from formula (2), it can be seen that the frequency domain imaginary vector = time domain imaginary vector × transform real matrix + time domain real vector × transform kernel imaginary matrix.

[0056] As an optional implementation, Figure 3 As shown, in the first processing core group in the many-core chip, the first multiplication cluster calculates the time-domain real part vector × the transform core matrix, the second multiplication cluster calculates the time-domain imaginary part vector × the transform core imaginary part matrix, the first addition cluster performs point-to-point subtraction, and the difference between the product vector output by the first multiplication cluster and the product vector output by the second multiplication cluster is calculated to obtain the frequency-domain real part vector. In the second processing core group in the many-core chip, the third multiplication cluster calculates the time-domain imaginary part vector × the transform core matrix, the fourth multiplication cluster calculates the time-domain real part vector × the transform core imaginary part matrix, the second addition cluster performs point-to-point addition, and the difference between the product vector output by the third multiplication cluster and the product vector output by the fourth multiplication cluster is calculated to obtain the frequency-domain imaginary part vector.

[0057] like Figure 3 As shown, the real part matrix of the transformation core is respectively configured to the processing cores in the first multiplication cluster and the third multiplication cluster, and the imaginary part matrix of the transformation core is respectively configured to the processing cores in the second multiplication cluster and the fourth multiplication cluster; accordingly, the real part vector of the time domain is respectively input into the first multiplication cluster and the fourth multiplication cluster, and the imaginary part vector of the time domain is respectively input into the second multiplication cluster and the third multiplication cluster.

[0058] It should be noted that in the embodiment of the present disclosure, the first multiplication cluster calculates the first product of the time domain real part vector × the transformation verification part matrix, and the second multiplication cluster calculates the second product of the time domain imaginary part vector × the transformation core imaginary part matrix, and transmits them to the first addition cluster through the on-chip network of the many-core chip. The first product and the second product are one-dimensional vectors. The first addition cluster can perform point-to-point subtraction to obtain the frequency domain real part vector. The third multiplication cluster calculates the third product of the time domain imaginary part vector × the transformation verification part matrix, and the fourth multiplication cluster calculates the fourth product of the time domain real part vector × the transformation core imaginary part matrix, and transmits them to the second addition cluster through the on-chip network of the many-core chip. The third product and the fourth product are one-dimensional vectors. The second addition cluster can perform point-to-point addition to obtain the frequency domain real part vector.

[0059] Accordingly, in some embodiments, the transformation kernel matrix can be decomposed into a transformation kernel real part matrix and a transformation kernel imaginary part matrix; Figure 4 , step S210 includes:

[0060] In step S211, the multiplication clusters are divided, and the multiplication clusters include a first multiplication cluster, a second multiplication cluster, a third multiplication cluster, and a fourth multiplication cluster; the first multiplication cluster and the third multiplication cluster correspond to the transformation kernel imaginary part matrix; the second multiplication cluster and the fourth multiplication cluster correspond to the transformation kernel imaginary part matrix;

[0061] In step S212, the addition clusters are divided, the addition clusters including a first addition cluster corresponding to the first multiplication cluster and the second multiplication cluster, and a second addition cluster corresponding to the third multiplication cluster and the fourth multiplication cluster; the first multiplication cluster, the second multiplication cluster, and the first addition cluster constitute a first processing core group; the third multiplication cluster, the fourth multiplication cluster, and the second addition cluster constitute a second processing core group;

[0062] Each of the multiplication clusters includes at least one processing core, and each of the addition clusters includes at least one processing core.

[0063] The embodiment of the present disclosure does not specifically limit how to decompose the transform kernel matrix into the transform kernel real part matrix and the transform kernel imaginary part matrix. For example, for DFT (or FFT), the frequency domain signal and the time domain signal satisfy formula (3):

[0064]

[0065] Therefore, the transformation verification matrix can be expressed as formula (4):

[0066]

[0067] The imaginary part matrix of the transformation kernel can be expressed by formula (5):

[0068]

[0069] For example, for DCT-II, the frequency domain signal and the time domain signal satisfy formula (6):

[0070]

[0071] The transformation verification matrix can be expressed by formula (7):

[0072]

[0073] For example, for CZT, the frequency domain signal and the time domain signal satisfy formula (8):

[0074]

[0075] The transformation kernel matrix can be expressed by formula (9):

[0076] W nk=(AW -k ) -n (9)

[0077] Accordingly, in some embodiments, reference Figure 4 , step S220 includes:

[0078] In step S221, the transformation verification part matrix is ​​loaded into the local storage of at least one processing core in the first multiplication cluster and the local storage of at least one processing core in the third multiplication cluster;

[0079] In step S222 , the transform kernel imaginary part matrix is ​​loaded into the local storage of at least one processing core in the second multiplication cluster and the local storage of at least one processing core in the fourth multiplication cluster.

[0080] Accordingly, in some embodiments, the time domain signal can be decomposed into a time domain real part vector and a time domain imaginary part vector; Figure 5 , step S300 includes:

[0081] In step S311, the time-domain real part vector is input into at least one processing core in the first multiplication cluster, so that the at least one processing core in the first multiplication cluster calculates a first product of the transformed real part matrix and the time-domain real part vector;

[0082] In step S312, the time-domain imaginary part vector is input into at least one processing core in the second multiplication cluster, so that the at least one processing core in the second multiplication cluster calculates a second product of the transform kernel imaginary part matrix and the time-domain imaginary part vector;

[0083] In step S313, the first product and the second product are transmitted to the first addition cluster, so that the first addition cluster determines the frequency domain real part vector according to the first product and the second product;

[0084] In step S321, the time-domain imaginary part vector is input to at least one processing core in the third multiplication cluster, so that the at least one processing core in the third multiplication cluster calculates a third product of the transformation matrix and the time-domain imaginary part vector;

[0085] In step S322, the time-domain real part vector is input to at least one processing core in the fourth multiplication cluster, so that the at least one processing core in the fourth multiplication cluster calculates a fourth product of the transform kernel imaginary part matrix and the time-domain real part vector;

[0086] In step S323, the third product and the fourth product are transmitted to the second addition cluster, so that the second addition cluster determines the frequency domain imaginary part vector according to the third product and the fourth product.

[0087] In an embodiment of the present disclosure, the addresses of the processing cores corresponding to the time-domain real vector and the time-domain imaginary vector can be determined within the chip, and then the time-domain real vector and the time-domain imaginary vector can be routed to the corresponding processing cores through the on-chip network; the addresses of the processing cores corresponding to the time-domain real vector and the time-domain imaginary vector can also be determined outside the chip, and after the multi-core chip receives the time-domain signal, the time-domain real vector and the time-domain imaginary vector can be routed to the corresponding processing cores through the on-chip network according to the corresponding addresses.

[0088] In the disclosed embodiment, the multi-core chip can perform pipeline operation. Figure 6 As shown, the pipeline operation means that after the first multiplication cluster outputs the first product to the first addition cluster, the first multiplication cluster can receive the new time-domain real part vector and continue to calculate the vector-matrix multiplication operation of the transformation core imaginary part matrix and the time-domain real part vector; after the second multiplication cluster outputs the second product to the first addition cluster, the second multiplication cluster can receive the new time-domain imaginary part vector and continue to calculate the vector-matrix multiplication operation of the transformation core imaginary part matrix and the time-domain imaginary part vector; after the third multiplication cluster outputs the third product to the second addition cluster, the third multiplication cluster can receive the new time-domain imaginary part vector and continue to calculate the vector-matrix multiplication operation of the transformation core imaginary part matrix and the time-domain imaginary part vector; after the fourth multiplication cluster outputs the fourth product to the second addition cluster, the fourth multiplication cluster can receive the new time-domain real part vector and continue to calculate the vector-matrix multiplication operation of the transformation core imaginary part matrix and the time-domain real part vector. Figure 6 In the example, sample 1 corresponds to the real part vector or the imaginary part vector in the time domain, and sample 2 corresponds to the imaginary part vector or the real part vector in the time domain, which is used to illustrate the flow of data in each calculation step.

[0089] In an embodiment of the present disclosure, the number of processing cores in the multiplication cluster and the number of processing cores in the addition cluster can be determined based on at least one factor, such as the local storage size of the transformation kernel matrix and a single processing core, the processing capability, and the demand for the operation rate of the time-frequency conversion. The embodiment of the present disclosure does not impose any special limitation on this. For example, when a single processing core cannot complete the vector-matrix multiplication calculation corresponding to the time domain signal and the transformation kernel matrix, the multiplication cluster includes multiple processing cores; when a single processing core can complete the vector-matrix multiplication calculation corresponding to the time domain signal and the transformation kernel matrix, the multiplication cluster includes one processing core or multiple processing cores.

[0090] Accordingly, in some embodiments, reference Figure 7 , step S211 includes:

[0091] In step S211a, a target number is determined according to the transformation kernel matrix, where the target number is the number of processing cores in the multiplication cluster;

[0092] In step S211b, the multiplication clusters are divided according to the target number.

[0093] In an embodiment of the present disclosure, when a multiplication cluster includes multiple processing cores, it is necessary to divide the transformation verification part matrix into multiple transformation verification part sub-matrices, and in the multiplication cluster, each transformation verification part sub-matrix corresponds to one processing core; and divide the transformation core imaginary part matrix into multiple transformation core imaginary part sub-matrices, and in the multiplication cluster, each transformation core imaginary part sub-matrix corresponds to one processing core.

[0094] Figure 8 FIG. 1 shows a schematic diagram of a multiplication cluster including multiple processing cores. Figure 8 As shown, the multiplication cluster includes A×B processing cores, and A×B processing cores form an A×B array. The transformation core matrix is ​​divided into A×B sub-matrices, and A×B sub-matrices form an A×B array. A×B sub-matrices correspond one-to-one to A×B processing cores. The time domain vector is divided into A sub-vectors, and each sub-vector is multicast to Figure 8 Each processing core in the same row of the array receives the same subvector. Within the same processing unit group, the calculation results of the processing cores in different multiplication clusters are added point-to-point in the addition cluster by column.

[0095] Accordingly, in some embodiments, before the step of mapping the transformation kernel matrix to the first processing core group and the second processing core group respectively, the signal processing method further includes:

[0096] dividing the transformation verification part matrix into a plurality of transformation verification part sub-matrices;

[0097] The transform kernel imaginary part matrix is ​​divided into a plurality of transform kernel imaginary part sub-matrices.

[0098] Accordingly, in some embodiments, the step of loading the transformation verification matrix into the local storage of at least one processing core in the first multiplication cluster and the local storage of at least one processing core in the third multiplication cluster includes:

[0099] Loading the plurality of transformation verification sub-matrices into local storage of a plurality of processing cores in the first multiplication cluster, wherein each processing core in the first multiplication cluster corresponds to one transformation verification sub-matrix;

[0100] Loading the plurality of transformation verification sub-matrices into local storage of a plurality of processing cores in the third multiplication cluster, each processing core in the third multiplication cluster corresponding to one transformation verification sub-matrix;

[0101] The step of loading the transform kernel imaginary part matrix into the local storage of the plurality of processing cores in the second multiplication cluster and the local storage of the plurality of processing cores in the fourth multiplication cluster comprises:

[0102] Loading a plurality of the transform kernel imaginary part sub-matrices into local storage of a plurality of processing cores in the second multiplication cluster, each processing core in the second multiplication cluster corresponding to one transform kernel imaginary part sub-matrix;

[0103] Loading a plurality of the transform kernel imaginary part sub-matrices into local storage of a plurality of processing cores in the fourth multiplication cluster, each processing core in the fourth multiplication cluster corresponds to one transform kernel imaginary part sub-matrix.

[0104] It should be noted that in the embodiment of the present disclosure, corresponding to dividing the transformation verification part matrix into multiple transformation verification part sub-matrices and dividing the transformation core imaginary part matrix into multiple transformation core imaginary part sub-matrices, it is also necessary to divide the time domain real part vector into multiple time domain real part sub-vectors and divide the time domain imaginary part vector into multiple time domain imaginary part sub-vectors.

[0105] Accordingly, before the step of mapping the time domain signal to the plurality of processing cores, the signal processing method further includes:

[0106] Dividing the time-domain real part vector into a plurality of time-domain real part sub-vectors;

[0107] The time-domain imaginary part vector is divided into a plurality of time-domain imaginary part sub-vectors.

[0108] The step of mapping the time domain signal to the plurality of processing cores specifically includes:

[0109] In each multiplication cluster, multiple time-domain real sub-vectors or multiple time-domain imaginary sub-vectors are input into multiple processing cores in the multiplication cluster according to one of the correspondences between multiple time-domain real sub-vectors and multiple transform real sub-matrices, the correspondences between multiple time-domain real sub-vectors and multiple transform core imaginary sub-matrices, the correspondences between multiple time-domain imaginary sub-vectors and multiple transform real sub-matrices, and the correspondences between multiple time-domain imaginary sub-vectors and multiple transform core imaginary sub-matrices.

[0110] In the disclosed embodiments, the transformation kernel matrix may be dynamically calculated, statically stored, or calculated based on statically stored values. The disclosed embodiments do not impose any particular limitations on this. It should be noted that different types of time-frequency transforms result in different transformation kernel matrices.

[0111] Accordingly, in some embodiments, reference Figure 9 , step S100 includes:

[0112] In step S110, the transformation kernel matrix is ​​determined according to the time-frequency transformation type and the static storage value.

[0113] The disclosed embodiments do not impose any particular restrictions on the statically stored values ​​used to calculate the transformation kernel matrix. For example, the statically stored values ​​may be Taylor series, and the transformation kernel matrix is ​​determined by calculating the Taylor expansion; the statically stored values ​​may also be rotation factors, and the transformation kernel matrix can be calculated based on the rotation factors; or Table 1 may be stored, and the transformation kernel matrix is ​​determined based on the data stored in Table 1.

[0114] Table 1

[0115] <![CDATA[W 0 ]]> <![CDATA[W 0 ]]> <![CDATA[W 0 ]]> <![CDATA[W 0 ]]> … <![CDATA[W 0 ]]> <![CDATA[W 0 ]]> <![CDATA[W 1 ]]> <![CDATA[W 2 ]]> <![CDATA[W 3 ]]> … <![CDATA[W N-1 ]]> <![CDATA[W 0 ]]> <![CDATA[W 2 ]]> <![CDATA[W 4 ]]> <![CDATA[W 6 ]]> … <![CDATA[W 2(N-1) ]]> <![CDATA[W 0 ]]> <![CDATA[W 3 ]]> <![CDATA[W 6 ]]> <![CDATA[W 9 ]]> … <![CDATA[W 3(N-1) ]]> … … … … … … <![CDATA[W 0 ]]> <![CDATA[W N-1 ]]> <![CDATA[W 2(N-1) ]]> <![CDATA[W 3(N-1) ]]> … <![CDATA[W (N-1)(N-1) ]]>

[0116] In the disclosed embodiments, the entire transform kernel matrix can be mapped to multiple processing cores, or the transform kernel matrix corresponding to the target interval can be mapped to multiple processing cores. This disclosed embodiment does not specifically limit this. In the scenario where the transform kernel matrix corresponding to the target interval is mapped to multiple processing cores, time-frequency conversion can be performed on the target interval to obtain a frequency domain signal corresponding to the target interval.

[0117] Accordingly, in some embodiments, reference Figure 10 , step S100 includes:

[0118] In step S121, a target interval is determined;

[0119] In step S122 , the transformation kernel matrix corresponding to the target interval is determined according to the time-frequency transformation type.

[0120] The embodiments of the present disclosure may also be used for window function filtering, where window function filtering includes low-pass filtering and band-pass filtering.

[0121] Accordingly, in some embodiments, reference Figure 11 , the signal processing method further includes:

[0122] In step S410, a windowing calculation is performed on the frequency domain signal corresponding to the target interval to obtain a windowing calculation result;

[0123] In step S420, a complete frequency domain signal is determined according to the windowing calculation result;

[0124] In step S430, an inverse transform is performed on the complete frequency domain signal.

[0125] In the disclosed example, after obtaining the windowing calculation result, a complete frequency domain signal is obtained by padding zeros on both sides of the target interval.

[0126] It should be noted that in the embodiment of the present disclosure, the calculation of the frequency domain signal corresponding to the target interval through steps S100 to S300, and the acquisition of the complete frequency domain signal through steps S410 to S420, are equivalent to the method of first calculating the complete frequency domain signal and then windowing it in some related technologies. The embodiment of the present disclosure can significantly save the amount of computation.

[0127] Secondly, refer to Figure 12 An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 101 and an on-chip network 102, wherein the multiple processing cores 101 are connected to the on-chip network 102, and the on-chip network 102 is used to exchange data between the multiple processing cores and external data.

[0128] One or more instructions are stored in one or more processing cores 101 , and the one or more instructions are executed by the one or more processing cores 101 , so that the one or more processing cores 101 can perform the above-mentioned signal processing method.

[0129] In some embodiments, the electronic device is a many-core chip.

[0130] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein the computer program implements the above-mentioned signal processing method when executed by a processing core.

[0131] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0132] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A signal processing method, comprising: Determining a transformation kernel matrix according to a time-frequency transformation type, wherein the transformation kernel matrix is ​​obtained by dynamic calculation; Mapping the transformation kernel matrix to multiple processing cores of a many-core chip; The time domain signal is mapped to the plurality of processing cores, so that the plurality of processing cores determine the frequency domain signal corresponding to the time domain signal according to the transformation core matrix and the time domain signal.

2. The signal processing method according to claim 1, wherein: The frequency domain signal can be decomposed into a frequency domain real part vector and a frequency domain imaginary part vector; The step of mapping the transformation core matrix to multiple processing cores of the many-core chip includes: Determine, according to the transformation kernel matrix, a first processing core group for determining the frequency domain real part vector and a second processing core group for determining the frequency domain imaginary part vector; the first processing core group includes at least one processing core, and the second processing core group includes at least one processing core; The transformation kernel matrix is ​​mapped to the first processing kernel group and the second processing kernel group respectively.

3. The signal processing method according to claim 2, wherein: The transformation kernel matrix can be decomposed into a transformation kernel real part matrix and a transformation kernel imaginary part matrix; The step of determining, according to the transformation kernel matrix, a first processing kernel group for determining the frequency domain real part vector and a second processing kernel group for determining the frequency domain imaginary part vector comprises: Dividing the multiplication clusters into a first multiplication cluster, a second multiplication cluster, a third multiplication cluster, and a fourth multiplication cluster; the first multiplication cluster and the third multiplication cluster correspond to the transformation kernel real part matrix; the second multiplication cluster and the fourth multiplication cluster correspond to the transformation kernel imaginary part matrix; Dividing the addition clusters, the addition clusters including a first addition cluster corresponding to the first multiplication cluster and the second multiplication cluster, and a second addition cluster corresponding to the third multiplication cluster and the fourth multiplication cluster; Each of the multiplication clusters includes at least one processing core, and each of the addition clusters includes at least one processing core; the first multiplication cluster, the second multiplication cluster, and the first addition cluster constitute the first processing core group; the third multiplication cluster, the fourth multiplication cluster, and the second addition cluster constitute the second processing core group. The signal processing method according to claim 3 , wherein: The step of mapping the transformation core matrix to the first processing core group and the second processing core group respectively includes: Loading the transformation verification matrix into the local memory of at least one processing core in the first multiplication cluster and into the local memory of at least one processing core in the third multiplication cluster; The transform kernel imaginary part matrix is ​​loaded into a local memory of at least one processing core in the second multiplication cluster and a local memory of at least one processing core in the fourth multiplication cluster. The signal processing method according to claim 4 , wherein: The time domain signal can be decomposed into a time domain real part vector and a time domain imaginary part vector; The step of mapping the time domain signal to the plurality of processing cores comprises: Inputting the time-domain real part vector into at least one processing core in the first multiplication cluster, so that the at least one processing core in the first multiplication cluster calculates a first product of the transformed real part matrix and the time-domain real part vector; Inputting the time-domain imaginary part vector into at least one processing core in the second multiplication cluster, so that the at least one processing core in the second multiplication cluster calculates a second product of the transform kernel imaginary part matrix and the time-domain imaginary part vector; transmitting the first product and the second product to the first addition cluster so that the first addition cluster determines the frequency domain real part vector according to the first product and the second product; Inputting the time-domain imaginary part vector into at least one processing core in the third multiplication cluster, so that the at least one processing core in the third multiplication cluster calculates a third product of the transformed real part matrix and the time-domain imaginary part vector; Inputting the time-domain real part vector into at least one processing core in the fourth multiplication cluster, so that the at least one processing core in the fourth multiplication cluster calculates a fourth product of the transform kernel imaginary part matrix and the time-domain real part vector; The third product and the fourth product are transmitted to the second addition cluster, so that the second addition cluster determines the frequency domain imaginary part vector according to the third product and the fourth product. The signal processing method according to claim 3 , wherein: The steps to partition the multiplication clusters include: determining a target number according to the transformation kernel matrix, the target number being the number of processing cores in the multiplication cluster; The multiplication clusters are divided according to the target number.

7. The signal processing method according to any one of claims 4 to 6, wherein: Before the step of mapping the transformation core matrix to the first processing core group and the second processing core group respectively, the signal processing method further includes: dividing the transformation verification part matrix into a plurality of transformation verification part sub-matrices; The transform kernel imaginary part matrix is ​​divided into a plurality of transform kernel imaginary part sub-matrices.

8. The signal processing method according to claim 4 or 5, wherein: The step of loading the transformation verification matrix into the local storage of at least one processing core in the first multiplication cluster and the local storage of at least one processing core in the third multiplication cluster comprises: Loading the plurality of transformation verification sub-matrices into local storage of a plurality of processing cores in the first multiplication cluster, wherein each processing core in the first multiplication cluster corresponds to one transformation verification sub-matrix; Loading the plurality of transformation verification sub-matrices into local storage of a plurality of processing cores in the third multiplication cluster, each processing core in the third multiplication cluster corresponding to one transformation verification sub-matrix; The step of loading the transform kernel imaginary part matrix into the local storage of the plurality of processing cores in the second multiplication cluster and the local storage of the plurality of processing cores in the fourth multiplication cluster comprises: Loading a plurality of the transform kernel imaginary part sub-matrices into local storage of a plurality of processing cores in the second multiplication cluster, each processing core in the second multiplication cluster corresponding to one transform kernel imaginary part sub-matrix; Loading a plurality of the transform kernel imaginary part sub-matrices into local storage of a plurality of processing cores in the fourth multiplication cluster, each processing core in the fourth multiplication cluster corresponds to one transform kernel imaginary part sub-matrix.

9. The signal processing method according to claim 8, wherein: The time domain signal can be decomposed into a time domain real part vector and a time domain imaginary part vector; Before the step of mapping the time domain signal to the plurality of processing cores, the signal processing method further includes: Dividing the time-domain real part vector into a plurality of time-domain real part sub-vectors; The time-domain imaginary part vector is divided into a plurality of time-domain imaginary part sub-vectors.

10. The signal processing method according to any one of claims 1 to 6, wherein: The steps of determining the transformation kernel matrix according to the time-frequency transformation type include: The transformation kernel matrix is ​​determined according to the time-frequency transformation type and the static storage value.

11. The signal processing method according to any one of claims 1 to 6, wherein: The steps of determining the transformation kernel matrix according to the time-frequency transformation type include: Determine the target range; The transformation kernel matrix corresponding to the target interval is determined according to the time-frequency transformation type.

12. The signal processing method according to claim 11, wherein: The signal processing method further includes: Performing windowing calculation on the frequency domain signal corresponding to the target interval to obtain a windowing calculation result; Determine the complete frequency domain signal according to the windowing calculation result; Perform inverse transformation on the complete frequency domain signal.

13. The signal processing method according to any one of claims 1 to 6, wherein: The time-frequency transform type is any one of discrete Fourier transform, discrete cosine transform, fast Fourier transform, and Z transform.

14. An electronic device comprising: Multiple processing cores; as well as an on-chip network configured to exchange data between the plurality of processing cores and external data; One or more instructions are stored in one or more of the processing cores, and the one or more instructions are executed by one or more of the processing cores, so that the one or more processing cores can execute the signal processing method according to any one of claims 1 to 13.

15. The electronic device according to claim 14, characterized in that The electronic device is a many-core chip.

16. A computer readable medium having a computer program stored thereon, wherein: When the computer program is executed by the processing core, the computer program implements the signal processing method according to any one of claims 1 to 13.

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