Chips arranged in a fully custom layout and electronics for hashing

Abstract

The present disclosure relates to a chip arranged in a full-custom layout and an electronic device for implementing a hash operation. A chip arranged in a full-custom layout is provided, including a pipeline structure with multiple operation stages, wherein each operation stage includes: multiple rows arranged in sequence in the X direction parallel to the substrate of the chip and having a uniform row height in the X direction, the multiple rows include a first type of rows, each first type of row includes: a first group of register modules, including a*b register modules arranged in the form of an array of a rows and b columns, wherein each register module has a first height in the X direction, the row height is a times the first height, wherein a and b are positive integers; and a first group of logic operation modules, including a*c logic operation modules arranged in the form of an array of a rows and c columns, wherein each logic operation module has a first height in the X direction, wherein c is a positive integer; wherein the first group of register modules and the first group of logic operation modules are arranged adjacent to each other in the Y direction, and the first group of logic operation modules are used to process data in the first group of register modules.

Description

Technical Field

[0001] The present disclosure generally relates to a chip arranged in a full-custom layout, and more particularly, to an electronic device for implementing a hash operation including a chip arranged in a full-custom layout. Background Art

[0002] Traditional automatic placement and routing (APR) technology usually uses electronic design automation (EDA) synthesis tools to perform cell synthesis and placement and routing (P&R). The synthesis of automatic placement and routing refers to the automatic conversion of RTL code into a netlist, which is composed of cells, and the specific cells are provided by the library; the placement and routing of automatic placement and routing (APR PR) refers to the automatic placement of cells according to rules, where the rules include but are not limited to: cells cannot overlap, data interconnection relationships are as close as possible, routing is short, round-trip routing is avoided, etc.

[0003] Although traditional automatic layout and routing technology can greatly improve design efficiency, it also brings some disadvantages. For example, if the designer uses RTL code to describe a complex, hierarchical algorithm expression, and then uses EDA synthesis tools to automatically layout and route the expression, the resulting netlist is obtained by taking the entire algorithm expression as a whole, so it does not reflect the hierarchy of the algorithm expression, and the placement relationship of each unit is also uncontrollable, which will lead to a lot of redundancy and waste in the final layout and routing, which urgently needs further optimization. Summary of the invention

[0004] The present invention realizes a chip with better performance by adopting a fully customized layout, including but not limited to making the chip area smaller, the critical path shorter, etc. The biggest feature of the chip adopting the fully customized layout is that the chip design is realized by manual code optimization and manual coding, without the need for EDA synthesis tools, so that a chip with the expected layout can be directly obtained, thereby maximizing the performance of the chip.

[0005] According to a first aspect of the present disclosure, there is provided a chip arranged in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage comprises: a plurality of rows arranged in sequence in an X direction parallel to a substrate of the chip and having a uniform row height in the X direction, the plurality of rows comprising rows of a first type, each row of the first type comprising: a first group of register modules, comprising a*b register modules arranged in an array of a rows and b columns, wherein each register module has a first height in the X direction, the row height is a times the first height, wherein a and b are positive integers; and a first group of logic operation modules, comprising a*c logic operation modules arranged in an array of a rows and c columns, wherein each logic operation module has a first height in the X direction, wherein c is a positive integer; wherein the first group of register modules and the first group of logic operation modules are adjacently arranged in a Y direction, and the first group of logic operation modules is used to process data in the first group of register modules.

[0006] According to a second aspect of the present disclosure, there is provided an electronic device for implementing a hash operation, which includes the chip arranged in a full-custom layout as described above.

[0007] The chip proposed by the present invention, which adopts a fully customized layout, has an optimization effect for chips that do not use or only use a small amount of SRAM, and is particularly suitable for use as a chip that needs to use a large number of registers, such as a chip based on hash operations. Hash operations (such as MD5, SHA-256, etc.) usually use a large number of registers to store multi-bit data. For example, MD5 is based on at least 4 32-bit data, and SHA-256 is based on at least 8 32-bit data. Taking the chip based on SHA-256 operation as an example, its operation process has multiple cycles, so a pipeline structure is usually used to implement the operation process of multiple cycles, and each operation level of the pipeline structure includes registers and combinational logic to process at least 8 32-bit data.

[0008] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0011] Figure 1A A schematic diagram of the structure of a chip 10 arranged in a full-custom layout according to an embodiment of the present disclosure is shown;

[0012] Figure 1B A schematic diagram of the structure of the first group of register modules is shown;

[0013] Figure 1C A schematic diagram showing the structure of at least part of the logic operation modules in the first group of logic operation modules;

[0014] Figure 1D shows a schematic diagram of the structure of the second group of register modules;

[0015] Figure 1E A schematic diagram showing the structure of at least part of the logic operation modules in the second group of logic operation modules;

[0016] Figure 1F shows a schematic diagram of the structure of the third group of register modules;

[0017] Figure 1G A schematic diagram showing the structure of at least part of the logic operation modules in the third group of logic operation modules;

[0018] Figure 2 The overall process of SHA-256 processing data and outputting data summary is shown;

[0019] Figure 3 The operation process of the round operation of SHA-256 is shown;

[0020] Figure 4 The mapping structure used to generate Wt is shown;

[0021] Figure 5 A schematic diagram of the operation of the t-th round of operation performed by an operation stage of a pipeline structure for performing round operations in a circuit for implementing the SHA-256 algorithm is shown;

[0022] Figure 6 The schematic diagram of the structure of a chip 20 arranged in a fully customized layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown;

[0023] Figure 7 The schematic diagram of the structure of a chip 30 arranged in a fully customized layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown;

[0024] Fig. 8A The schematic diagram of the structure of a chip 40 arranged in a fully customized layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown;

[0025] Figure 8B A schematic diagram showing the structure of two adjacent cache register modules A1 and A2 is shown;

[0026] Figure 8C shows two adjacent extended register modules R 0-1 and R 0-2 Schematic diagram of the structure;

[0027] Fig.8D A schematic diagram showing the structure of two adjacent 16-bit CH modules;

[0028] Fig. 9 The schematic diagram of the structure of a chip 50 arranged in a full custom layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown;

[0029] Fig.10 The schematic diagram of the structure of a chip 60 arranged in a full-custom layout for executing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown.

[0030] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0031] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0032] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0033] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure and its application or use. That is, the circuits and methods for implementing the hash algorithm herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in the present disclosure, and are not intended to be limiting. Those skilled in the art will appreciate that they merely illustrate exemplary ways that can be used to implement the present invention, rather than an exhaustive way.

[0034] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0035] Figure 1A FIG. 1 is a schematic diagram of a chip 10 arranged in a full custom layout according to an embodiment of the present disclosure. The chip 10 includes a pipeline structure having multiple operation stages. For the sake of clarity, Figure 1A Only one operation stage 100 in the pipeline structure is shown and other structures are omitted, but those skilled in the art will understand that the pipeline structure of the chip 10 may include any number of operation stages 100, and the chip 10 may also include any other structures.

[0036] Each operation level 100 of the pipeline structure of the chip 10 may include: a plurality of rows arranged in sequence in the X direction parallel to the substrate of the chip and having a uniform row height in the X direction. The plurality of rows may include rows of the first type, and each row of the first type may include: a first group of register modules, including a*b register modules arranged in the form of an array of a rows and b columns, wherein each register module has a first height in the X direction, and the row height is a times the first height, wherein a and b are positive integers; and a first group of logic operation modules, including a*c logic operation modules arranged in the form of an array of a rows and c columns, wherein each logic operation module has a first height in the X direction, wherein c is a positive integer. The first group of register modules and the first group of logic operation modules may be arranged adjacently in the Y direction, and the first group of logic operation modules may be used to process data in the first group of register modules. Note that the description of the size relationship of "height" mentioned in this article is not intended to represent a strict size relationship, but to represent an approximate or approximate size relationship. For example, "the row height is a times the first height" means that the row height is approximately a times the first height, that is, a difference within an acceptable range is allowed between the actual row height and a times the first height. For another example, "each logic operation module has a first height in the X direction" means that the height of the logic operation module in the X direction is approximately the first height, that is, a difference within an acceptable range is allowed between the height of the logic operation module in the X direction and the first height. The acceptable range of the difference can be a common range acceptable in the art, or a range set by a technician using the solution disclosed herein as needed.

[0037] For example, refer to Figure 1A , row 102 is one of the first type of rows, including a first group of register modules and a first group of logic operation modules. The first group of register modules in row 102 includes two register modules 112 arranged in the form of an array of 1 row and 2 columns, i.e. a=1 and b=2; the first group of logic operation modules in row 102 includes two logic operation modules 114 arranged in the form of an array of 1 row and 2 columns, i.e. c=2. Those skilled in the art will understand that Figure 1AThe row 102 shown in FIG. 1 is only one example of a first type of row and is not intended to be limiting, and other values ​​of a, b, and c may be used.

[0038] In some embodiments, each register module in the first group of register modules may be a p-bit register module, and p 1-bit data output ports arranged in sequence along the X direction are provided on the side thereof close to the first group of logic operation modules, where p is a positive integer. The first group of register modules may include q register modules arranged in sequence in the Y direction for jointly storing a p*q-bit data, where q is a positive integer, and q is not greater than the number of columns of the first group of register modules and the number of columns of the first group of logic operation modules. Accordingly, each of at least some of the logic operation modules in the first group of logic operation modules may include p 1-bit operation units arranged in sequence along the X direction, and at least some of the logic operation modules in the first group of logic operation modules may include q logic operation modules arranged in sequence in the Y direction for jointly processing one or more data of length p*q bits. Specifically, when q=1, each of the first group of register modules is used to independently store a p-bit data, and the first group of logic operation modules includes a logic operation module for independently processing one or more data with a length of p bits; when q>1, the first group of register modules includes q adjacent register modules arranged in sequence in the Y direction for jointly storing a p*q-bit data, and the first group of logic operation modules includes q adjacent logic operation modules arranged in sequence in the Y direction for jointly processing one or more data with a length of p*q bits.

[0039] Figure 1B FIG. 1 shows a schematic diagram of the structure of the first group of register modules. Figure 1B As shown, the first register module 112 is a p-bit register module, and is provided with p 1-bit data output ports Out[0] to Out[p-1] arranged in sequence along the X direction on a side thereof close to the first logic operation module.

[0040] Figure 1C FIG. 4 shows a schematic diagram of the structure of at least part of the logic operation modules in the first group of logic operation modules. Figure 1C As shown, at least part of the logic operation modules 114 in the first group of logic operation modules include p 1-bit operation units Unit[0] to Unit[p-1] sequentially arranged along the X direction.

[0041] In some embodiments, at least one of the first type of rows may further include: a fifth group of register modules, including a*m register modules arranged in an array of a rows and m columns, wherein each register module has a first height in the X direction, and m is a positive integer. The first group of logic operation modules and the fifth group of register modules may be arranged adjacent to each other in the Y direction, and the fifth group of register modules may be used to store data processed by the first group of logic operation modules.

[0042] For example, refer to Figure 1A , the row 102 may include a fifth group of register modules. The fifth group of register modules may include one register module 126 arranged in an array of one row and one column, ie, m=1.

[0043] In some embodiments, at least one of the first type of rows of the operation stage 100 may further include: a second group of register modules, including d*e register modules arranged in the form of an array of d rows and e columns, wherein each register module has a second height in the X direction, and the row height is d times the second height, wherein d and e are positive integers; and a second group of logic operation modules, including d*f logic operation modules arranged in the form of an array of d rows and f columns, wherein each logic operation module has a second height in the X direction, wherein f is a positive integer. The second group of register modules and the second group of logic operation modules are adjacently arranged in the Y direction, and the second group of logic operation modules are used to process data in the second group of register modules.

[0044] For example, refer to Figure 1A , row 102 may include a second group of register modules and a second group of logic operation modules. The second group of register modules in row 102 may include 4 register modules 116 arranged in the form of an array of 2 rows and 2 columns, i.e., d=2 and e=2; the second group of logic operation modules in row 102 may include 4 logic operation modules 118 arranged in the form of an array of 2 rows and 2 columns, i.e., f=2. Those skilled in the art will understand that Figure 1A The row 102 shown in FIG. 1 is only one example of a first type of row and is not intended to be limiting, and other values ​​of d, e, and f may be used.

[0045] In some embodiments, each register module in the second group of register modules is an r-bit register module, and r 1-bit data output ports arranged in sequence along the X direction are arranged on the side close to the second group of logic operation modules, where r is a positive integer and satisfies a*p=d*r, that is, the total number of bits that can be stored by the register modules in any column of the first group of register modules is the same as the total number of bits that can be stored by the register modules in any column of the second group of register modules, so that the row height of the first row remains consistent. The second group of register modules may include s register modules arranged in sequence in the Y direction for jointly storing an r*s bit of data, where s is a positive integer, and s is not greater than the number of columns of the second group of register modules and the number of columns of the second group of logic operation modules. Each of at least some of the logic operation modules in the second group of logic operation modules may include r 1-bit operation units arranged in sequence along the X direction, and the at least some of the logic operation modules may include s logic operation modules arranged in sequence in the Y direction for jointly processing one or more data of length r*s bits. Specifically, when s=1, each of the second group of register modules is used to independently store an r-bit data, and the second group of logic operation modules includes a logic operation module for independently processing one or more data with a length of r bits; when s>1, the second group of register modules includes s adjacent register modules arranged in sequence in the Y direction for jointly storing an r*s-bit data, and the second group of logic operation modules includes s adjacent logic operation modules arranged in sequence in the Y direction for jointly processing one or more data with a length of r*s bits.

[0046] Figure 1D FIG. 2 shows a schematic diagram of the structure of the second group of register modules. Figure 1D As shown, the second register module 116 is an r-bit register module, and is provided with r 1-bit data output ports Out[0] to Out[r-1] arranged in sequence along the X direction on a side thereof close to the second logic operation module.

[0047] Figure 1E FIG. 4 shows a schematic diagram of the structure of at least part of the logic operation modules in the second group of logic operation modules. Figure 1E As shown, at least part of the logic operation modules 118 in the second group of logic operation modules include r 1-bit operation units Unit[0] to Unit[r-1] sequentially arranged along the X direction.

[0048] In some embodiments, the plurality of rows of the operation stage 100 may further include a second type of row. Each second type of row may include: a third group of register modules, including g*h register modules arranged in an array of g rows and h columns, wherein each register module has a third height in the X direction, the row height is g times the third height, and g and h are positive integers; and a third group of logic operation modules, including g*i logic operation modules arranged in an array of g rows and i columns, wherein each logic operation module has a third height in the X direction, and i is a positive integer. The third group of register modules and the third group of logic operation modules are adjacently arranged in the Y direction, and the third group of logic operation modules is used to process data in the third group of register modules.

[0049] For example, refer to Figure 1A , row 104 is one of the rows of the second type, including a third group of register modules and a third group of logic operation modules. The third group of register modules of row 104 includes 4 register modules 122 arranged in the form of an array of 2 rows and 2 columns, i.e. g=2 and h=2; the third group of logic operation modules of row 104 includes 4 logic operation modules 124 arranged in the form of an array of 2 rows and 2 columns, i.e. i=2. Those skilled in the art will understand that Figure 1A The row 104 shown in FIG. 1 is only one example of a second type of row and is not intended to be limiting, and other values ​​of g, h, and i may be used.

[0050] In some embodiments, each register module in the third group of register modules may be a t-bit register module, and t 1-bit data output ports arranged in sequence along the X direction are arranged on the side thereof close to the third group of logic operation modules, wherein t is a positive integer and satisfies a*p=g*t, that is, the total number of bits that can be stored by the register modules in any column of the first group of register modules in the first type of row is the same as the total number of bits that can be stored by the register modules in any column of the third group of register modules in the second type of row, so that the row heights of the first type of row and the second type of row are consistent. The third group of register modules may include u register modules arranged in sequence in the Y direction for jointly storing a t*u bit of data, wherein u is a positive integer, and u is not greater than the number of columns of the third group of register modules and the number of columns of the third group of logic operation modules. Accordingly, each of at least some of the logic operation modules in the third group of logic operation modules may include t 1-bit operation units arranged in sequence along the X direction, and at least some of the logic operation modules in the third group of logic operation modules may include u logic operation modules arranged in sequence in the Y direction for jointly processing one or more data of length t*u bits. Specifically, when u=1, each of the third group of register modules is used to independently store t bits of data, and the third group of logic operation modules includes logic operation modules for independently processing one or more data with a length of t bits; when u>1, the third group of register modules may include u adjacent register modules arranged in sequence in the Y direction for jointly storing t*u bits of data, and the third group of logic operation modules includes u logic operation modules arranged in sequence in the Y direction for jointly processing one or more data with a length of t*u bits.

[0051] Figure 1F FIG. 4 shows a schematic diagram of the structure of the third group of register modules. Figure 1F As shown, the third register module 122 is a t-bit register module, and is provided with t 1-bit data output ports Out[0] to Out[t-1] arranged in sequence along the X direction on a side thereof close to the third logic operation module.

[0052] Figure 1G FIG. 4 shows a schematic diagram of the structure of at least part of the logic operation modules in the third group of logic operation modules. Figure 1G As shown, at least part of the logic operation modules 124 in the third group of logic operation modules include t 1-bit operation units Unit[0] to Unit[t-1] sequentially arranged along the X direction.

[0053] In some embodiments, at least one of the rows of the second type may further include: a sixth group of register modules, including g*n register modules arranged in an array of g rows and n columns, wherein each register module has a third height in the X direction, and n is a positive integer. The third group of logic operation modules and the sixth group of register modules may be arranged adjacent to each other in the Y direction, and the sixth group of register modules may be used to store data processed by the third group of logic operation modules.

[0054] For example, refer to Figure 1A , row 104 may include a sixth group of register modules. The sixth group of register modules may include two register modules 128 arranged in an array of two rows and one column, ie, n=1.

[0055] In some embodiments, at least one of the multiple rows of the operation stage 100 may include: a fourth group of modules, including j*k modules arranged in the form of an array of j rows and k columns, wherein each module may be a register module or a logic operation module and has a fourth height in the X direction, and the row height is j times the fourth height, wherein j and k are positive integers. That is, the first type of row, the second type of row, and the rows other than the first type of row and the second type of row may include the fourth group of modules. Each module in the fourth group of modules may be arbitrarily set to a register module or a logic operation module, and therefore, the fourth group of modules may all be register modules, may all be logic operation modules, or may be any combination of register modules and logic operation modules.

[0056] For example, refer to Figure 1A , the second type of row 104 may include a fourth group of modules. The fourth group of modules in row 104 includes 8 modules arranged in an array of 2 rows and 4 columns, i.e., j=2 and k=4. The 8 modules include register modules 130 and 136 and logic operation modules 132 and 134. Those skilled in the art will understand that Figure 1A The arrangement of the fourth group of modules shown in the figure is only for illustration and is not intended to be limiting. Other arrangements may also be used, such as alternating arrangements of register modules and logic operation modules. For example, in one embodiment, Figure 1A The two adjacent register modules 130 shown may be 16-bit registers and are used to store a 32-bit data together; Figure 1AThe two adjacent logic operation modules 132 shown may be 16-bit logic operation modules, and are used to jointly process 32-bit data stored in the two register modules 130. In another embodiment, the two 16-bit register modules 130 used to jointly store a 32-bit data and the two logic operation modules 132 used to jointly process the 32-bit data stored in the two register modules 130 may be arranged in an alternating manner, that is, in the Y direction, they are arranged in the order of one register module 130, one logic operation module 132, the second register module 130, and the second logic operation module 132.

[0057] According to the embodiments of the present disclosure, by keeping the row heights of each row of each operation level of the pipeline structure consistent and arranging the register module and the logic operation module for processing the data in the register module adjacent to each other, a very regular and neat chip layout is achieved, which effectively reduces the length and complexity of the wiring, thereby improving the area utilization of the chip, shortening the critical path, and greatly improving the overall performance.

[0058] although Figure 1A The operation level is shown to include 2 rows and the specific structure of each row (such as the number of register modules, the number of logic operation modules, the order of placement of different modules, etc.) is shown, but those skilled in the art will understand that Figure 1A The chip 10 in the figure is only used as an example and is not intended to constitute any limitation. According to the embodiment of the present disclosure, each operation stage of the pipeline structure of the chip arranged in a full-custom layout may include any number of rows with a uniform row height in the X direction, wherein the specific structure of each row may be arbitrarily set according to application requirements, and may include other structures besides the aforementioned register module and / or logic operation module. For example, the operation stage may include Figure 1A Any combination of various different rows shown in . In application, chip designers can use the above-mentioned fully customized layout structure to implement complex algorithms with multiple levels, so that the hardware implementation of the algorithm completely follows the preset hierarchical structure of the algorithm, thereby achieving optimal chip performance.

[0059] When the process for implementing the chip is determined, the height of the register module in the X direction using the structure as described above (i.e., one side of the register module is provided with a plurality of 1-bit data output ports arranged in sequence along the X direction) depends on the scale of the register module, i.e., the number of bits that can be stored. Therefore, in the process of designing the chip, the scale of the register module in each operation level of the pipeline structure can be determined according to the algorithm to be implemented, and then the height of the register module used in the X direction can be determined according to the scale, thereby determining the row height of each row of the operation level in the X direction. Afterwards, a logic operation module with the same height in the X direction is configured for each row, and finally a chip arranged using a fully customized layout as described above is realized. Those skilled in the art will understand that the width of each row of the operation level 100 in the Y direction according to the embodiment of the present disclosure can be arbitrarily set as needed, the number of register modules and the number of logic operation modules in each row can be arbitrarily set as needed, the spacing between adjacent modules in each row can be arbitrarily set as needed, and the width of the register module and the logic operation module in each row in the Y direction can be arbitrarily set as needed.

[0060] In order to present the inventive concept of the present disclosure more clearly and intuitively, the SHA-256 algorithm will be briefly introduced below and an example of implementing the SHA-256 algorithm with a chip using a full custom layout proposed in the present disclosure will be introduced in detail. Those skilled in the art will understand that the chip using a full custom layout according to an embodiment of the present disclosure can be used to implement various algorithms, including but not limited to hash algorithms (such as MD5, SHA-256, etc.), and is not limited to implementing the SHA-256 algorithm. The purpose of implementing the SHA-256 algorithm given here is only for example, and is not intended to constitute additional limitations.

[0061] The maximum length of SHA-256 input is less than 2 64 The output is a 256-bit data summary, i.e., a hash value. The input data is processed in 512-bit blocks. Figure 2 The overall process of SHA-256 processing data and outputting a data summary is shown. This process includes steps 1 to 5 as described in detail later.

[0062] Step 1: Add padding bits. Pad the original data of length L bits so that the length modulo 512 is congruent to 448, i.e., length = 448 (mod 512). Even if the original data already meets the above length requirement, padding is still required, so the number of padding bits is between 1 and 512. Padding consists of a 1 followed by a 0.

[0063] Step 2: Add the length. Add a 64-bit unsigned integer after the padded data. The 64-bit unsigned integer represents the length L of the data before the padded data.

[0064] The result of the above steps 1 and 2 is to generate an extended data with a length that is an integer multiple of 512 bits. The length of the extended data can be expressed as Q*512 bits, where Q is a positive integer greater than 1. Figure 2 As shown, the extended data is divided into Q data blocks M1, M2, and M3 with a length of 512 bits. Q .

[0065] Step 3: Initialize the hash buffer. The initial value H0, intermediate value H1, H2 of the hash algorithm until H Q-1 And the final result H Q The data are sequentially stored in a 256-bit hash buffer, which may include eight 32-bit cache register modules A, B, C, D, E, F, G, and H. At the beginning of the operation, the hash buffer is first initialized to an initial value H0, that is, the cache register modules A, B, C, D, E, F, G, and H are respectively initialized to integers (hexadecimal) as shown in the following table.

[0066] A=0X7A09E667 E=0X510E527F B = 0XBB67AE85 D=0X9B05688C C=0X3C6EF372 F=0X1F83D9AB D = 0XA54FF53A H = 0X5BE0CD19

[0067] Step 4: Process data in 512-bit blocks. The core of SHA-256 is to process data in 512-bit blocks M1, M2, and M Q Each data block in the process is subjected to 64 rounds of operations. Figure 2 Marked as f.

[0068] Figure 3 The operation process of the round operation of SHA-256 is shown. In each of the 64 rounds of round operation, the data in the cache register modules A to H of the hash cache area are used as input, and the data in the cache register modules A to H of the hash cache area are updated. i In round 0 of the round operation, the value in the hash buffer is the intermediate value H i-1 , where i is a positive integer and i≤Q. i In each round of the round operation, such as the tth round (t is an integer and satisfies 0≤t≤63), a 32-bit value W is used. t , which is composed of the current 512-bit data block M i The export algorithm is the data expansion algorithm discussed below. Each round will also use an additional constant K t , used to make each round of operations different. The output of the 63rd round and the input of the 0th round H i-1Adding them together produces H i , where the 32-bit data in each register of the cache register modules A to H in the hash cache area and H i-1 The corresponding 32 bits of data are modulo 2 32 The addition operation.

[0069] Step 5: Output. After all Q 512-bit data blocks are processed, the output from the Qth stage is a 256-bit data summary H Q , which is the hash value.

[0070] The following is a detailed discussion of the internal logic of each of the 64 rounds of SHA-256. The operation of the tth round is defined by the following operation formula (t is an integer and satisfies 0≤t≤63):

[0071] T1=H+∑1(E)+CH(E,F,G)+K t +W t

[0072] T2=∑0(A)+MAJ(A,B,C)

[0073] H=G

[0074] G=F

[0075] F = E;

[0076] E=D+T1

[0077] D=C

[0078] C=B

[0079] B=A

[0080] A=T1+T2(Calculation formula 1)

[0081] in:

[0082]

[0083] Wherein, ROTRn(x) means cyclically shifting the 32-bit variable x by n bits; t is a 32-bit word derived from the current 256-bit input data block; K t is a 32-bit additional constant; + is modulo 2 32 Add; AND is a 32-bit bitwise AND operation; NOT is a negation operation; It is an XOR operation.

[0084] Next, the 32-bit word W is described. t How to get from 512-bit data block M i Exported from . Figure 4 The method for generating W t The mapping structure of Figure 4 As shown, W t According to the following calculation formula:

[0085] For 0 ≤ t ≤ 15: W t Directly taken from data block M i ;

[0086] For 16 ≤ t ≤ 63:

[0087] W t =σ1(W t-2 )+W t-7 +σ0(W t-15 )+W t-16 (Equation 2)

[0088] in:

[0089]

[0090] Among them, ROTRn(x) means cyclically shifting the 32-bit variable x right by n bits; SHRn(x) means shifting the 32-bit variable x right by n bits and filling the left side with 0; XOR operation; + is modulo 2 32 add.

[0091] Those skilled in the art will appreciate that the above detailed description of SHA-256 is intended to more clearly present the inventive concept of the present application and is not intended to constitute any limitation. SHA-256 mentioned herein includes any known version of SHA-256 and its variants and modifications.

[0092] For multiple rounds of repeated operations in the hash algorithm, a pipeline structure can be used to parallelize multiple sets of different data to improve the operation efficiency. Taking the implementation of the SHA-256 algorithm as an example, since 64 rounds of repeated operations are required for each 512-bit data block, a 64-level pipeline structure can be used to parallelize 64 sets of data.

[0093] Figure 5 FIG. 1 shows a schematic diagram of the operation of the tth round of operation performed by an operation stage of a pipeline structure for performing round operations in a circuit for implementing the SHA-256 algorithm. Note that Figure 5 What is shown is the operation to be implemented by the operation stage (including the operation of operation formula 1 and operation formula 2), and does not represent the actual layout of the circuit.

[0094] like Figure 5 As shown, each operation stage includes eight 32-bit buffer register modules A to H for storing intermediate values ​​and two 32-bit buffer register modules A to H for storing extended data W.t To W t+15 The 16 32-bit extended register blocks R0 to R 15。 Each operation level also has multiple logic operation modules, including: full adder modules FAA1, FAA2, FAA3, FAA4, FAA5, FAA6, FAA7, FAA8, carry look-ahead adder modules CLA1 and CLA2, a MAJ module for performing the MAJ operation defined in equation 1, a CH module for performing the CH operation defined in equation 1, a ∑0 module for performing the ∑0 operation defined in equation 1, a ∑1 module for performing the ∑1 operation defined in equation 1, a σ0 module for performing the σ0 operation defined in equation 2, and a σ1 module for performing the σ1 operation defined in equation 2.

[0095] Figure 6 The schematic diagram of the structure of a chip 20 arranged in a full-custom layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown. Figure 6 The chip 20 shown is Figure 1A The chip 10 shown is a modified example, and the aforementioned description of the same or corresponding structure of the chip 10 is applicable to the chip 20. For the sake of clarity, Figure 6 Only the structure of one operation stage 200 of the pipeline structure is shown and other structures are omitted, but those skilled in the art will understand that the pipeline structure of the chip 20 may include any number of operation stages, and the chip 20 may also include any other structures.

[0096] Chip 20 is used to implement the SHA-256 algorithm, including a pipeline structure with multiple operation stages, wherein the operation stage 200 is used to implement Figure 5The operation of a single operation stage shown. The operation stage 200 includes a plurality of rows 210, 220, 230 and 240 arranged in sequence in the X direction parallel to the substrate of the chip and having a uniform row height in the X direction. Among them, the first type of row includes a first row 210, a second row 220 and a third row 230. The first row 210 includes a first group of register modules and a first group of logic operation modules. The first group of register modules of the first row 210 includes four 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns. The first group of logic operation modules of the first row 210 includes a 32-bit MAJ module, a ∑0 module, a FAA4 module, a FAA5 module and a CLA1 module arranged in the form of an array of 1 row and 5 columns. The second row 220 includes a first group of register modules and a first group of logic operation modules. The first group of register modules in the second row 220 includes four 32-bit cache register modules E, F, G and H arranged in the form of an array of 1 row and 4 columns. The first group of logic operation modules in the second row includes a 32-bit CH module, a ∑1 module, a FAA1 module, a FAA2 module, a FAA3 module, a FAA6 module and a CLA2 module arranged in the form of an array of 1 row and 7 columns. The third row 230 includes a first group of register modules, a first group of logic operation modules and a fifth group of register modules. The first group of register modules in the third row 230 includes four 32-bit extended register modules R0, R1, R9 and R10 arranged in the form of an array of 1 row and 4 columns. 14 The first group of logic operation modules in the third row includes 32-bit σ0 modules, σ1 modules, FAA7 modules, FAA8 modules, and CLA3 modules arranged in an array of 1 row and 5 columns, and the fifth group of register modules in the third row includes 1 32-bit extended register module R 15。 The plurality of rows of the operation stage 200 further includes a fourth row 240. The fourth row 240 includes a fourth group of modules, and the fourth group of modules in the fourth row includes 11 32-bit extended register modules R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R 10 , R 11 , R 12 , R 13 Each of the 32-bit cache register modules A, B, C, D, E, F, G and H is provided with 32 1-bit data output ports arranged in sequence along the X direction on its side close to the first group of logic operation modules and is used to store a 32-bit intermediate value. The 32-bit extension register modules R0 to R 15 Each of the logic operation modules has 32 1-bit data output ports arranged in sequence along the X direction on one side and is used to store a 32-bit extended data. Figure 5. At least part of the first group of logic operation modules in each row includes 32 1-bit operation units arranged in sequence along the X direction. For example, the FAA1 module includes 32 1-bit full adder units arranged in sequence along the X direction. Note that for clarity, Figure 6 The entire module of the computing stage 200 is not shown in the figure, and the computing stage 200 may also include other structures. Those skilled in the art will understand that Figure 6 The arrangement order of each module in each group of logic operation modules shown can be flexibly adjusted according to application needs, and is not limited to Figure 6 The order shown in .

[0097] Figure 7 The schematic diagram of the structure of a chip 30 arranged in a full-custom layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown. Figure 7 The chip 30 shown is Figure 1A The chip 10 shown is a modified example, and the aforementioned description of the same or corresponding structure of the chip 10 is applicable to the chip 30. For the sake of clarity, Figure 7 Only the structure of one operation stage 300 of the pipeline structure is shown and other structures are omitted, but those skilled in the art will understand that the pipeline structure of the chip 30 may include any number of operation stages 300, and the chip 30 may also include any other desired structures.

[0098] Chip 30 is used to implement the SHA-256 algorithm, including a pipeline structure with multiple operation stages, wherein the operation stage 300 is used to implement Figure 5The operation of a single operation stage shown. The operation stage 300 includes a plurality of rows 310 and 320 arranged in sequence in the X direction parallel to the substrate of the chip and having a first height in the X direction. Among them, the first type of row includes a first row 310 and a second row 320. The first row 310 includes a first group of register modules, a first group of logic operation modules, a second group of register modules, and a second group of logic operation modules. The first group of register modules in the first row 310 includes four 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns, the first group of logic operation modules in the first row 310 includes a 32-bit MAJ module, a ∑0 module, a FAA4 module, a FAA5 module and a CLA1 module arranged in the form of an array of 1 row and 5 columns, the second group of register modules in the first row 310 includes four 32-bit cache register modules E, F, G and H arranged in the form of an array of 1 row and 4 columns, the second group of logic operation modules in the first row 310 includes a 32-bit CH module, a ∑1 module, a FAA1 module, a FAA2 module, a FAA3 module, a FAA6 module and a CLA2 module arranged in the form of an array of 1 row and 7 columns. The second row 320 includes the first group of register modules, the first group of logic operation modules, the fifth group of register modules and the fourth group of modules. The first group of register modules in the second row 320 includes four 32-bit extension register modules R arranged in the form of an array of 1 row and 4 columns. o , R1, R9 and R 14 The first group of logic operation modules in the second row 320 includes 32-bit σ0 modules, σ1 modules, FAA7 modules, FAA8 modules, and CLA3 modules arranged in an array of 1 row and 5 columns, and the fifth group of register modules in the second row 320 includes a 32-bit extended register module R 15 , and the fourth group of modules in the second row includes 11 32-bit extended register modules R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29 10 , R 11 , R 12 , R 13 . Each of the 32-bit cache register modules A, B, C and D is provided with 32 1-bit data output ports arranged in sequence along the X direction on a side close to the first group of logic operation modules and is used to store a 32-bit intermediate value, each of the 32-bit cache register modules E, F, G and H is provided with 32 1-bit data output ports arranged in sequence along the X direction on a side close to the second group of logic operation modules and is used to store a 32-bit intermediate value, and the 32-bit extension register modules R0 to R 15Each of the logic operation modules has 32 1-bit data output ports arranged in sequence along the X direction on one side and is used to store a 32-bit extended data. Figure 5 . At least some of the modules in the first group of logic operation modules in each row include 32 1-bit operation units arranged in sequence along the X direction, for example, the FAA4 module includes 32 1-bit full adder units arranged in sequence along the X direction; and at least some of the modules in the second group of logic operation modules in the first row 310 include 32 1-bit operation units arranged in sequence along the X direction, for example, the FAA1 module includes 32 1-bit full adder units arranged in sequence along the X direction. Note that for clarity, Figure 7 Not all modules of the operation stage 300 are shown in the figure, and the operation stage 300 may also include other structures. Figure 7 The arrangement order of each module in each group of logic operation modules shown can be flexibly adjusted according to application needs, and is not limited to Figure 7 The order shown in .

[0099] Fig. 8A The schematic diagram of the structure of a chip 40 arranged in a full-custom layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown. Fig. 8A The chip 40 shown is Figure 1A The chip 10 shown is a modified example, and the aforementioned description of the same or corresponding structure of the chip 10 is applicable to the chip 40. For the sake of clarity, Fig. 8A Only the structure of one operation stage 400 of the pipeline structure is shown and other structures are omitted, but those skilled in the art will understand that the pipeline structure of chip 40 may include any number of operation stages 400, and chip 40 may also include any other desired structures.

[0100] Chip 40 is used to implement the SHA-256 algorithm, including a pipeline structure with multiple operation stages, wherein the operation stage 400 is used to implement Figure 5The operation of the single operation stage shown. The operation stage 400 includes a plurality of rows 410, 420, 430 and 440 arranged in sequence in the X direction parallel to the substrate of the chip and having a first height in the X direction. Among them, the first type of row includes a first row 410, a second row 420 and a third row 430. The first row 410 includes a first group of register modules and a first group of logic operation modules. The first group of register modules of the first row 410 includes 8 16-bit cache register modules A1, A2, B1, B2, C1, C2, D1, D2 (partially not shown) arranged in the form of an array of 1 row and 8 columns. The first group of logic operation modules of the first row includes two 16-bit MAJ modules, two 16-bit ∑0 modules and a 32-bit CLA1 module, etc. The second row 420 includes a first group of register modules and a first group of logic operation modules. The first group of register modules in the second row 420 includes eight 16-bit cache register modules E1, E2, F1, F2, G1, G2, H1, H2 (partially not shown) arranged in an array of 1 row and 8 columns. The first group of logic operation modules in the second row 420 includes two 16-bit CH modules, two 16-bit ∑1 modules and a 32-bit CLA2 module, etc. The third row 430 includes a first group of register modules, a first group of logic operation modules and a fifth group of register modules. The first group of register modules in the third row 430 includes eight 16-bit extended register modules R arranged in an array of 1 row and 8 columns. 0-1 , R 0-2 , R 1-1 , R 1-2 , R 9-1 , R 9-2 , R 14-1 , R 14-2 (partially not shown), the first group of logic operation modules in the third row includes two 16-bit σ0 modules, two 16-bit σ1 modules and a 32-bit CLA3 module, etc., and the fifth group of register modules in the third row includes two 16-bit extended register modules R arranged in the form of an array of 1 row and 2 columns. 15-1 and R 15-2 The plurality of rows of the operation stage 400 may further include a fourth row 440, the fourth row including a fourth group of modules, the fourth group of modules in the fourth row including 22 16-bit extended register modules R arranged in an array of 1 row and 22 columns. 2-1 , R 2-2 , R 3-1 , R 3-2 , R 4-1 , R 4-2 , R 5-1 , R 5-2 , R 6-1 , R 6-2 , R 7-1 , R7-2 , R 8-1 , R 8-2 , R 10-1 , R 10-2 , R 11-1 , R 11-2 , R 12-1 , R 12-2 , R 13-1 , R 13-2 . Note that for clarity, Fig. 8A Not all modules of the operation stage 400 are shown in the figure, and the operation stage may also include other structures. Fig. 8A The arrangement order of each module in each group of logic operation modules shown can be flexibly adjusted according to application needs, and is not limited to Fig. 8A The order shown in .

[0101] Continue to refer Fig. 8A , wherein each two adjacent 16-bit cache register modules in each of the first row 410 and the second row 420 are used to jointly store a 32-bit intermediate value, for example, the two adjacent 16-bit cache register modules A1 and A2 in the first row 410 are used to jointly store Figure 5 A 32-bit intermediate value in the round operation shown. Figure 8B A schematic structural diagram of two adjacent cache register modules A1 and A2 is shown, wherein one cache register module A1 is provided with 16 1-bit data output ports Out[0], Out[2] to Out

[30] arranged in sequence along the X direction on its side close to the first group of logic operation modules, and the other cache register module A2 is provided with 16 1-bit data output ports Out[1], Out[3] to Out

[31] arranged in sequence along the X direction on its side close to the first group of logic operation modules.

[0102] Each two adjacent 16-bit extension register modules in each of the third row 430 and the fourth row 440 are used to store a 32-bit extension data. For example, the two adjacent 16-bit extension register modules R in the third row 430 are used to store a 32-bit extension data. 0-1 and R 0-2 For storage such as Figure 5 A 32-bit extended data in the round operation shown. Figure 8C shows two adjacent extended register modules R 0-1 and R 0-2 A schematic diagram of the structure of an extended register module R 0-1 On one side, 16 1-bit data output ports Out[0], Out[2] to Out

[30] are arranged in sequence along the X direction. Another extended register module R 0-2On one side thereof, 16 1-bit data output ports Out[1], Out[3] to Out

[31] are arranged in sequence along the X direction.

[0103] The first group of logic operation modules in each of the first row 410, the second row 420 and the third row 430 may include two adjacent logic operation modules for jointly processing one or more data with a length of 32 bits. For example, two adjacent 16-bit CH modules in the second row 420 are used to jointly process three data with a length of 32 bits according to the operation defined in equation 1. Fig.8D A schematic structural diagram of two adjacent 16-bit CH modules is shown, wherein one CH module includes 16 CH operation units CH[0], CH[2] to CH

[30] for jointly processing three data with a length of 1 bit according to the operation defined in operation formula 1, and the 16 CH operation units are arranged sequentially along the X direction; the other CH module includes 16 CH operation units CH[1], CH[3] to CH

[31] for jointly processing three data with a length of 1 bit according to the operation defined in operation formula 1, and the 16 CH operation units are arranged sequentially along the X direction.

[0104] Comparison reference Figure 6 The operation stage 200 and Fig. 8A In the operation stage 400 shown, the overall structure of the operation stage 200 is tall and thin, that is, it is longer in the X direction and shorter in the Y direction, which makes the wiring across each row in the operation stage 200 along the X direction longer, and the wiring in the same row along the Y direction shorter; the overall structure of the operation stage 400 is short and fat, that is, it is shorter in the X direction and longer in the Y direction, which makes the wiring across each row in the operation stage 400 along the X direction shorter, and the wiring in the same row along the Y direction longer. When applying, a more suitable solution can be selected according to needs. For example, when there are more wirings in the same row, it can be adopted Figure 6 The structure of the operation stage 200 shown in FIG. 1 may be used when more wirings are required across rows. Fig. 8A The structure of the operation stage 400 is shown.

[0105] Fig. 9 The schematic diagram of the structure of a chip 50 arranged in a full-custom layout for performing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown. Fig. 9 The chip 50 shown is Figure 1A The chip 10 shown is a modified example, and the aforementioned description of the same or corresponding structure of the chip 10 is applicable to the chip 50. For the sake of clarity, Fig. 9Only the structure of one operation stage 500 of the pipeline structure is shown and other structures are omitted, but those skilled in the art will understand that the pipeline structure of the chip 50 may include any number of operation stages, and the chip 50 may also include any other structures. Fig. 9 The operation stage 500 shown can also be viewed as a combination of Figure 6 The operation stage 200 and Fig. 8A A variation example obtained by using the operation stage 400 shown. Those skilled in the art will understand that, under the premise of ensuring that the row heights of the rows are consistent, the various types of rows shown in the various embodiments of the present disclosure can be arbitrarily rearranged and combined according to application requirements.

[0106] Chip 50 is used to implement the SHA-256 algorithm, including a pipeline structure with multiple operation stages, wherein the operation stage 500 is used to implement Figure 5 The operation of a single operation stage shown. The operation stage 500 includes a plurality of rows 510, 520, 530 and 540 arranged in sequence in the X direction parallel to the substrate of the chip and having a uniform row height in the X direction. Among them, the first type of row includes the first row 510. The first row 510 includes a first group of register modules and a first group of logic operation modules. The first group of register modules of the first row 510 includes four 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns. The first group of logic operation modules of the first row 510 includes a 32-bit MAJ module, a ∑0 module, a FAA4 module, a FAA5 module and a CLA1 module arranged in the form of an array of 1 row and 5 columns. The second type of row includes a second row 520 and a third row 530. The second row 520 includes a third group of register modules and a third group of logic operation modules. The third group of register modules in the second row includes 8 16-bit cache register modules E1, E2, F1, F2, G1, G2, H1, H2 arranged in an array of 2 rows and 4 columns. The third group of logic operation modules in the second row includes two 16-bit CH modules, two 16-bit ∑1 modules, two 16-bit FAA1 modules, two 16-bit FAA2 modules, two 16-bit FAA3 modules and two 16-bit FAA6 modules arranged in an array of 2 rows and multiple columns. The second row 520 may also include a 32-bit CLA2 module with a row height in the X direction. The third row 430 includes a third group of register modules, a third group of logic operation modules and a sixth group of register modules. The third group of register modules in the third row 430 includes 8 16-bit extension register modules R arranged in an array of 2 rows and 4 columns. 0-1 , R 0-2 , R 1-1 , R 1-2 , R 9-1 , R 9-2 , R14-1 , R 14-2 The third group of logic operation modules in the third row includes two 16-bit σ0 modules, two 16-bit σ1 modules, two 16-bit FAA7 modules, and two 16-bit FAA8 modules arranged in an array of 2 rows and multiple columns. The third row may also include a 32-bit CLA3 module with a row height in the X direction. The sixth group of register modules in the third row includes two 16-bit extended register modules R arranged in an array of 2 rows and 1 column. 15-1 and R 15-2 The plurality of rows of the operation stage 500 further includes a fourth row 540. The fourth row 540 includes a fourth group of modules, and the fourth group of modules in the fourth row includes 11 32-bit extended register modules R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R 10 , R 11 , R 12 , R 13 .

[0107] Continue to refer Fig. 9 , wherein each 32-bit cache register module is used to store a 32-bit intermediate value, and each 32-bit extension register module is used to store a 32-bit extension data. Every two 16-bit cache register modules arranged in sequence in the Y direction in the second row 520 are used to jointly store a 32-bit intermediate value. For example, two adjacent 16-bit cache register modules E1 and E2 in the second row 520 are used to jointly store Figure 5 Each of the two 16-bit extended register modules arranged in sequence in the Y direction in the third row 530 is used to store a 32-bit extended data together. For example, two adjacent 16-bit extended register modules R in the third row 530 are used to store a 32-bit extended data. 0-1 and R 0-2 For common storage such as Figure 5 The third group of logic operation modules in each of the second row 520 and the third row 530 may include two adjacent logic operation modules for jointly processing one or more data of 32 bits in length. For example, two adjacent 16-bit CH modules in the second row 520 are used to jointly process three data of 32 bits in length according to the operation defined in the operation formula 1. Note that for clarity, Fig. 9 The entire modules of the computing stage 500 are not shown in the figure, and the computing stage 500 may also include other structures. Those skilled in the art will understand that Fig. 9 The arrangement order of each module in each group of logic operation modules shown can be flexibly adjusted according to application needs, and is not limited to Fig. 9The order shown in .

[0108] Fig.10 The schematic diagram of the structure of a chip 60 arranged in a full-custom layout for executing SHA-256 operations according to an embodiment of the present disclosure is exemplarily shown. Fig.10 The chip 60 shown is a modified example of the chip 10 shown in FIG. 1 , and the aforementioned description of the same or corresponding structure of the chip 10 is applicable to the chip 60. For the sake of clarity, Fig.10 Only the structure of one operation stage 600 of the pipeline structure is shown and other structures are omitted, but those skilled in the art will understand that the pipeline structure of chip 60 may include any number of operation stages 600, and chip 60 may also include any other desired structures.

[0109] Chip 60 is used to implement the SHA-256 algorithm, including a pipeline structure with multiple operation stages, wherein the operation stage 600 is used to implement Figure 5 The operation of a single operation stage shown. The operation stage 600 includes a plurality of rows 610 and 620 arranged in sequence in the X direction parallel to the substrate of the chip and having a first height in the X direction. Among them, the first type of row includes a first row 610 and a second row 620. The first row 610 includes a first group of register modules, a first group of logic operation modules, a second group of register modules, a second group of logic operation modules and a fourth group of modules. The first group of register modules of the first row 610 includes four 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns, the first group of logic operation modules of the first row 610 includes a 32-bit MAJ module, a ∑0 module, a FAA4 module, a FAA5 module and a CLA1 module arranged in the form of an array of 1 row and 5 columns, the second group of register modules of the first row 610 includes four 32-bit cache register modules E, F, G and H arranged in the form of an array of 1 row and 4 columns, the second group of logic operation modules of the first row 610 includes a 32-bit CH module, a ∑1 module, a FAA1 module, a FAA2 module, a FAA3 module, a FAA6 module and a CLA2 module arranged in the form of an array of 1 row and 7 columns, and the fourth group of modules of the first row 610 includes four 16-bit extension register modules R arranged in the form of an array of 2 rows and 2 columns. 4-1 , R 4-2 , R 5-1 and R 5-2 .

[0110] The second row 620 includes a first group of register modules, a first group of logic operation modules, a fifth group of register modules, and a fourth group of modules. The first group of register modules in the second row 620 includes four 32-bit extended register modules R0, R1, R9, and R10 arranged in an array of 1 row and 4 columns. 14The first group of logic operation modules in the second row 620 includes 32-bit σ0 modules, σ1 modules, FAA7 modules, FAA8 modules, and CLA3 modules arranged in the form of an array of 1 row and 5 columns, and the fifth group of register modules in the second row 620 includes a 32-bit extended register module R 15 ; and the fourth group of modules of the second row 620 includes four 16-bit extension register modules R arranged in an array of 2 rows and 2 columns 7-1 , R 7-2 , R 8-1 and R 8-2 Each row of the operation stage 600 may also include other structures besides the modules described above. For example, the second row 620 may also include 32-bit extended register modules R2-R3, R6, R 10 -R 13 . Each of the 32-bit cache register modules A, B, C and D is provided with 32 1-bit data output ports arranged in sequence along the X direction on the side close to the first group of logic operation modules and is used to store a 32-bit intermediate value; each of the 32-bit cache register modules E, F, G and H is provided with 32 1-bit data output ports arranged in sequence along the X direction on the side close to the second group of logic operation modules and is used to store a 32-bit intermediate value; the 32-bit extension register modules R0 to R3, R6, R9 to R 15 Each of the 16-bit extension register modules R is provided with 32 1-bit data output ports arranged in sequence along the X direction on one side thereof and is used to store a 32-bit extended data; 4-1 , R 4-2 , R 5-1 , R 5-2 , R 7-1 , R 7-2 , R 8-1 and R 8-2 Each of the fourth group of modules in the first row 610 and the second row 620 is provided with 16 1-bit data output ports arranged in sequence along the X direction on one side thereof, and every two adjacent 16-bit extended register modules arranged in sequence in the Y direction in the fourth group of modules in each row of the first row 610 and the second row 620 are used to store a 32-bit extended data together. For example, two 16-bit extended register modules R adjacent to each other in the Y direction in the first row 610 4-1 and R 4-2 Used to store a 32-bit extended data. Fig.10 The specific functions of each logic operation module in Figure 5, wherein at least some of the first group of logic operation modules in each of the first row 610 and the second row 620 include 32 1-bit operation units sequentially arranged along the X direction, for example, the FAA4 module includes 32 1-bit full adder units sequentially arranged along the X direction. At least some of the third group of logic operation modules in the first row 610 include 32 1-bit operation units sequentially arranged along the X direction, for example, the FAA1 module includes 32 1-bit full adder units sequentially arranged along the X direction. Note that for clarity, Fig.10 Not all modules of the operation stage 600 are shown in the figure, and the operation stage 600 may also include other structures.

[0111] Regarding the definitions of the first group of register modules, the first group of logic operation modules, the second group of register modules, the second group of logic operation modules, the third group of register modules and the third group of logic operation modules in the present disclosure, some supplementary explanations are provided here to facilitate the understanding of those skilled in the art. Note that the explanations here are only used to assist understanding and are not intended to constitute additional restrictions. In an operation level of a pipeline structure using the technical solution of the present disclosure, if a row includes a group of register modules arranged in a matrix form and a group of logic operation modules adjacent thereto, arranged in a matrix form and used to process data in the group of register modules, and the two groups of modules have the same number of rows, then the group of register modules and the group of logic operation modules can be respectively identified as the first group of register modules and the first group of logic operation modules, wherein the number of rows of the first group of register modules is identified as a, the number of columns of the first group of register modules is identified as b, the number of columns of the first group of logic operation modules is identified as c, and the row is identified as a row of the first type. In the operation level, if any other row also includes several modules that meet the definition of the first group of register modules and the first group of logic operation modules, then the row can also be identified as the first type of row, and the corresponding modules can also be identified as the first group of register modules and the first group of logic operation modules. If a first type of row of the operation level includes, in addition to the first group of register modules and the first group of logic operation modules, another group of register modules arranged in a matrix form and another group of logic operation modules adjacent thereto, arranged in a matrix form and used to process data in the group of register modules, and the two groups of modules have the same number of rows, then the other group of register modules and the other group of logic operation modules can be identified as the second group of register modules and the second group of logic operation modules, wherein the number of rows of the second group of register modules is identified as d, the number of columns of the second group of register modules is identified as e, and the number of columns of the second group of logic operation modules is identified as f. If a row of the operation level includes a group of register modules arranged in a matrix form and a group of logic operation modules adjacent to the group of register modules arranged in a matrix form and used to process data in the group of register modules, the two groups of modules have the same number of rows, but the group of register modules and the group of logic operation modules do not meet the definition of the first group of register modules and the first group of logic operation modules (for example, the group of register modules is not in row a and column b, or the group of logic operation modules is not in row a and column c, etc.), then the group of register modules and the group of logic operation modules can be respectively identified as the third group of register modules and the third group of logic operation modules, wherein the number of rows of the third group of register modules is identified as g, the number of columns of the third group of register modules is identified as h, the number of columns of the third group of logic operation modules is identified as i, and the row is identified as a row of the second type.

[0112] According to an embodiment of the present disclosure, an electronic device for implementing hash operations is also provided, which includes chips arranged in a fully customized layout as described above, including but not limited to chip 10, chip 20, chip 30, chip 40, chip 50 and chip 60.

[0113] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0114] The words "front", "rear", "top", "bottom", "over", "under", etc., if any, in the specification and claims are used for descriptive purposes and are not necessarily used to describe invariant relative positions. It is understood that the words so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0115] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background technology, summary of the invention, or detailed description.

[0116] As used herein, the term "substantially" is meant to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0117] The above description may indicate elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature, electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element / node / feature can be mechanically, electrically, logically, or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even though the two features may not be directly connected. That is, "coupled" is intended to include direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0118] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0119] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0120] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A chip arranged in a fully customized layout, characterized in that: A pipeline structure including a plurality of operation stages, wherein each operation stage includes: A plurality of rows are sequentially arranged in an X direction parallel to the substrate of the chip and have a uniform row height in the X direction, the plurality of rows comprising rows of a first type, each row of the first type comprising: A first group of register modules, comprising a*b register modules arranged in an array of a rows and b columns, wherein each register module has a first height in the X direction, the row height is a times the first height, wherein a and b are positive integers; and A first group of logic operation modules, including a*c logic operation modules arranged in an array of a rows and c columns, wherein each logic operation module has a first height in the X direction, wherein c is a positive integer; The first group of register modules and the first group of logic operation modules are arranged adjacent to each other in the Y direction, and the first group of logic operation modules is used to process data in the first group of register modules.

2. The chip according to claim 1, characterized in that: in: Each register module in the first group of register modules is a p-bit register module, and is provided with p 1-bit data output ports arranged in sequence along the X direction on a side thereof close to the first group of logic operation modules, wherein p is a positive integer; The first group of register modules includes q register modules arranged sequentially in the Y direction for jointly storing a p*q bit of data, where q is a positive integer; Each of at least some of the logic operation modules in the first group of logic operation modules includes p 1-bit operation units arranged in sequence along the X direction; as well as At least part of the logic operation modules in the first group of logic operation modules include q logic operation modules arranged sequentially in the Y direction for jointly processing one or more data with a length of p*q bits.

3. The chip according to claim 2, characterized in that: At least one of the first type of rows further comprises: A second group of register modules, comprising d*e register modules arranged in an array of d rows and e columns, wherein each register module has a second height in the X direction, the row height is d times the second height, wherein d and e are positive integers; and The second group of logic operation modules includes d*f logic operation modules arranged in an array of d rows and f columns, wherein each logic operation module has a second height in the X direction, wherein f is a positive integer, The second group of register modules and the second group of logic operation modules are arranged adjacent to each other in the Y direction, and the second group of logic operation modules are used to process data in the second group of register modules.

4. The chip according to claim 3, characterized in that: in: Each register module in the second group of register modules is an r-bit register module, and is provided with r 1-bit data output ports arranged in sequence along the X direction on a side thereof close to the second group of logic operation modules, wherein r is a positive integer and satisfies a*p=d*r; The second group of register modules includes s register modules arranged sequentially in the Y direction for jointly storing a data of r*s bits, where s is a positive integer; Each of at least some of the logic operation modules in the second group of logic operation modules includes r 1-bit operation units arranged in sequence along the X direction; and At least part of the logic operation modules in the second group of logic operation modules include s logic operation modules arranged sequentially in the Y direction for jointly processing one or more data with a length of r*s bits.

5. The chip according to claim 2, characterized in that: The plurality of rows include rows of a second type, each row of the second type including: A third group of register modules, comprising g*h register modules arranged in an array of g rows and h columns, wherein each register module has a third height in the X direction, the row height is g times the third height, wherein g and h are positive integers; and A third group of logic operation modules, including g*i logic operation modules arranged in an array of g rows and i columns, wherein each logic operation module has a third height in the X direction, wherein i is a positive integer; The third group of register modules and the third group of logic operation modules are arranged adjacent to each other in the Y direction, and the third group of logic operation modules are used to process data in the third group of register modules.

6. The chip according to claim 5, characterized in that: in: Each register module in the third group of register modules is a t-bit register module, and is provided with t 1-bit data output ports arranged in sequence along the X direction on a side thereof close to the third group of logic operation modules, wherein t is a positive integer and satisfies a*p=g*t; The third group of register modules includes u register modules sequentially arranged in the Y direction for jointly storing t*u bits of data, where u is a positive integer; Each of at least some of the logic operation modules in the third group of logic operation modules includes t 1-bit operation units arranged in sequence along the X direction; and At least part of the logic operation modules in the third group of logic operation modules include u logic operation modules sequentially arranged in the Y direction for jointly processing one or more data with a length of t*u bits.

7. The chip according to any one of claims 1 to 6, characterized in that: At least one of the plurality of rows comprises: The fourth group of modules includes j*k modules arranged in an array of j rows and k columns, wherein each module is a register module or a logic operation module and has a fourth height in the X direction, and the row height is j times the fourth height, wherein j and k are positive integers.

8. The chip according to claim 7, It is characterized in that in, At least one of the first type of rows further comprises: a fifth group of register modules, comprising a*m register modules arranged in an array of a rows and m columns, wherein each register module has a first height in the X direction, and m is a positive integer; The first group of logic operation modules and the fifth group of register modules are arranged adjacent to each other in the Y direction, and the fifth group of register modules is used to store data processed by the first group of logic operation modules; and / or Wherein, at least one of the second type of rows further comprises: a sixth group of register modules, comprising g*n register modules arranged in an array of g rows and n columns, wherein each register module has a third height in the X direction, and n is a positive integer; The third group of logic operation modules and the sixth group of register modules are arranged adjacent to each other in the Y direction, and the sixth group of register modules is used to store data processed by the third group of logic operation modules.

9. The chip according to claim 8, characterized in that: in: The chip is used to implement the SHA-256 algorithm; The first type of rows for each operation stage includes a first row, a second row, and a third row, where: The first row includes a first group of register modules and a first group of logic operation modules. The first group of register modules in the first row includes four 32-bit cache register modules A, B, C and D arranged in an array of 1 row and 4 columns. The second row includes a first group of register modules and a first group of logic operation modules, the first group of register modules in the second row includes four 32-bit cache register modules E, F, G and H arranged in an array of 1 row and 4 columns, and The third row includes a first group of register modules, a first group of logic operation modules and a fifth group of register modules. The first group of register modules in the third row includes four 32-bit extended register modules R0, R1, R9 and R11 arranged in an array of 1 row and 4 columns. 14 The fifth register module of the third row includes a 32-bit extended register module R 15 ; The plurality of rows of each operation stage further includes a fourth row, the fourth row includes a fourth group of modules, the fourth group of modules in the fourth row includes 11 32-bit extended register modules R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55 10 , R 11 , R 12 , R 13 ;as well as Each 32-bit cache register module is used to store a 32-bit intermediate value, and each 32-bit extension register module is used to store a 32-bit extension data.

10. The chip according to claim 8, characterized in that: in: The chip is used to implement the SHA-256 algorithm; and The first type of rows for each operation stage includes a first row and a second row, where: The first row includes a first group of register modules, a first group of logic operation modules, a second group of register modules and a second group of logic operation modules, wherein the first group of register modules in the first row includes four 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns, and the second group of register modules in the first row includes four 32-bit cache register modules E, F, G and H arranged in the form of an array of 1 row and 4 columns, The second row includes a first group of register modules, a first group of logic operation modules, a fifth group of register modules and a fourth group of modules, wherein the first group of register modules in the second row includes four 32-bit extended register modules R0, R1, R9 and R11 arranged in an array of 1 row and 4 columns. 14 The fifth register module of the second row includes a 32-bit extended register module R 15 , and the fourth group of modules in the second row includes 11 32-bit extended register modules R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29 10 , R 11 , R 12 , R 13 ;as well as Each 32-bit cache register module is used to store a 32-bit intermediate value, and each 32-bit extension register module is used to store a 32-bit extension data.

11. The chip according to claim 8, characterized in that: in: The chip is used to implement the SHA-256 algorithm; The first type of rows for each operation stage includes a first row, a second row, and a third row, where: The first row includes a first group of register modules and a first group of logic operation modules. The first group of register modules in the first row includes eight 16-bit cache register modules A1, A2, B1, B2, C1, C2, D1, and D2 arranged in an array of 1 row and 8 columns. The second row includes a first group of register modules and a first group of logic operation modules. The first group of register modules in the second row includes eight 16-bit cache register modules E1, E2, F1, F2, G1, G2, H1, H2 arranged in an array of 1 row and 8 columns, and The third row includes a first group of register modules, a first group of logic operation modules and a fifth group of register modules. The first group of register modules in the third row includes eight 16-bit extended register modules R arranged in an array of 1 row and 8 columns. 0-1 , R 0-2 , R 1-1 , R 1-2 , R 9-1 , R 9-2 , R 14-1 , R 14-2 The fifth group of register modules in the third row includes two 16-bit extended register modules R arranged in an array of 1 row and 2 columns. 15-1 and R 15-2 ; The plurality of rows of each operation stage further includes a fourth row, the fourth row includes a fourth group of modules, the fourth group of modules in the fourth row includes 22 16-bit extended register modules R arranged in an array of 1 row and 22 columns. 2-1 , R 2-2 , R 3-1 , R 3-2 , R 4-1 , R 4-2 , R 5-1 , R 5-2 , R 6-1 , R 6-2 , R 7-1 , R 7-2 , R 8-1 , R 8-2 , R 10-1 , R 10-2 , R 11-1 , R 11-2 , R 12-1 , R 12-2 , R 13-1 , R 13-2 ;as well as Every two adjacent 16-bit cache register modules in each of the first row and the second row are used to jointly store a 32-bit intermediate value, every two adjacent 16-bit extension register modules in each of the third row and the fourth row are used to jointly store a 32-bit extended data, and the first group of logic operation modules in each of the first row, the second row and the third row includes 2 logic operation modules adjacent in the Y direction for jointly processing one or more data with a length of 32 bits.

12. The chip according to claim 8, characterized in that: in: The chip is used to implement the SHA-256 algorithm; and The first type of rows for each operation stage comprises a first row where: The first row includes a first group of register modules and a first group of logic operation modules. The first group of register modules in the first row includes four 32-bit cache register modules A, B, C and D arranged in an array of 1 row and 4 columns. The second type of rows for each operation stage includes a second row and a third row, where: The second row includes a third group of register modules and a third group of logic operation modules, the third group of register modules in the second row includes eight 16-bit cache register modules E1, E2, F1, F2, G1, G2, H1, H2 arranged in an array of 2 rows and 4 columns; The third row includes a third group of register modules, a third group of logic operation modules and a sixth group of register modules. The third group of register modules in the third row includes eight 16-bit extended register modules R arranged in an array of 2 rows and 4 columns. 0-1 , R 0-2 , R 1-1 , R 1-2 , R 9-1 , R 9-2 , R 14-1 , R 14-2 The sixth register module of the third row includes two 16-bit extended register modules R arranged in an array of 2 rows and 1 column. 15-1 , R 15-2 ; The plurality of rows of each operation stage further includes a fourth row, the fourth row includes a fourth group of modules, the fourth group of modules in the fourth row includes 11 32-bit extended register modules R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55 10 , R 11 , R 12 , R 13 ; Each 32-bit cache register module is used to store a 32-bit intermediate value, each 32-bit extension register module is used to store a 32-bit extended data, every two adjacent 16-bit cache register modules arranged in sequence in the Y direction in the second row are used to jointly store a 32-bit intermediate value, every two adjacent 16-bit extension register modules arranged in sequence in the Y direction in the third row are used to jointly store a 32-bit extended data, and the third group of logic operation modules in each of the second and third rows includes 2 logic operation modules adjacent in the Y direction for jointly processing one or more data with a length of 32 bits.

13. The chip according to claim 8, characterized in that: in: The chip is used to implement the SHA-256 algorithm; and The first type of rows for each operation stage includes a first row and a second row, where: The first row includes a first group of register modules, a first group of logic operation modules, a second group of register modules, a second group of logic operation modules and a fourth group of modules, wherein the first group of register modules in the first row includes four 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns, the second group of register modules in the first row includes four 32-bit cache register modules E, F, G and H arranged in the form of an array of 1 row and 4 columns, and the fourth group of modules in the first row includes four 16-bit extension register modules arranged in the form of an array of 2 rows and 2 columns, The second row includes a first group of register modules, a first group of logic operation modules, a fifth group of register modules and a fourth group of modules, wherein the first group of register modules in the second row includes four 32-bit extended register modules R0, R1, R9 and R11 arranged in an array of 1 row and 4 columns. 14 The fifth register module of the second row includes a 32-bit extended register module R 15 , and the fourth group of modules in the second row includes four 16-bit extension register modules arranged in an array of 2 rows and 2 columns; and Each 32-bit cache register module is used to store a 32-bit intermediate value, each 32-bit extension register module is used to store a 32-bit extended data, and every two 16-bit extension register modules arranged sequentially in the Y direction in the fourth group of modules in each row in the first row and the second row are used to jointly store a 32-bit extended data.

14. An electronic device for implementing a hash operation, characterized in that: A chip arranged in a fully customized layout comprising any one of claims 1-13.

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