System and method for memory cell access

Abstract

The present disclosure relates to systems and methods for memory cell access. A memory device includes a plurality of memory elements. The memory device further includes a first current mirror, which selectively outputs a first current when in operation to select a target memory cell as a first memory element among the plurality of memory elements. The memory device further includes a second current mirror, which selectively outputs a second current when in operation to select the target memory cell as the first memory element among the plurality of memory elements.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to improved access to target cells in memories (eg, phase change memories). Background Art

[0002] Semiconductor memory devices such as dynamic random access memory (DRAM) can store data as bits in memory cells implemented using capacitors and transistors. For example, the charge state of a capacitor (e.g., charged or discharged) can determine whether a memory cell stores a "1" or a "0" as a binary value. A large number of memory cells can be packed into a semiconductor memory device along with additional logic that, for example, enables data to be read to the memory cells, data from the memory cells to be written, and data in the memory cells to be refreshed.

[0003] Memory device technology continues to evolve. For example, dynamic random access memory (DRAM) is a type of memory that can store data as bits in memory cells implemented using capacitors and transistors. For example, the charge state of a capacitor (e.g., charged or discharged) can determine whether a memory cell stores a "1" or a "0" as a binary value. Large numbers of memory cells can be packed into a semiconductor memory device along with additional logic that, for example, enables data to be read to the memory cells, data from the memory cells to be written, and data in the memory cells to be refreshed.

[0004] Other types of memory have been developed, such as phase change memory. Phase change memory is a non-volatile memory that typically uses a material that changes state. The change from one state to another (e.g., from a crystalline phase with relatively low resistance to an amorphous phase with relatively high resistance) can be controlled by, for example, applying heat to the material of the phase change memory. The state itself indicates whether the phase change memory cell is storing a "1" or a "0" as a binary value based on the difference in its resistivity. As the use of phase change memory continues to grow, techniques to increase the access efficiency of phase change memory are desirable. Summary of the invention

[0005] In one aspect, the present disclosure provides a memory device comprising: a memory array comprising a plurality of memory elements; a first circuit which, when in operation, selectively generates a first voltage to select a target memory cell as a first memory element among the plurality of memory elements; and a second circuit which, when in operation, selectively generates a second voltage to select the target memory cell as the first memory element among the plurality of memory elements.

[0006] In another aspect, the present disclosure further provides a memory device comprising: a memory array comprising a plurality of memory elements organized into word lines and bit lines; a snap-on detection circuit coupled to the word lines of the memory array; a first circuit which, when in operation, selectively outputs a voltage to a first word line of the word lines to select a target memory cell of the word line as a first memory element of the plurality of memory elements in combination with a selection operation; a second circuit which, when in operation, selectively outputs a second voltage to the first word line of the memory array to select the target memory cell of the word line as the first memory element of the plurality of memory elements in combination with the selection operation; and a control circuit comprising a first input coupled to the snap-on detection circuit and outputs coupled to a first current mirror and a second current mirror.

[0007] In yet another aspect, the present disclosure further provides a method comprising: determining a physical orientation of a target memory cell in a word line of a memory array; at a first time, outputting a first voltage from a first circuit to the word line to select the target memory cell in conjunction with a selection operation when the physical orientation is determined to have a first characteristic; and at a second time, outputting a second voltage from a second circuit to the word line to select the target memory cell in conjunction with the selection operation when the physical orientation is determined to have a second characteristic. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is an example of a memory device including a memory unit according to an embodiment of the present disclosure;

[0009] Figure 2 A memory cell according to an embodiment of the present disclosure Figure 1 an example of a memory array of a memory device;

[0010] Figure 3 is a method of using double-termination bit line and / or word line drive signals to obtain a Figure 2 A flowchart of a process for selecting a memory cell in a memory array;

[0011] Figure 4 According to the embodiment of the present disclosure Figure 2 A diagram of a first embodiment of a portion of a memory array;

[0012] Figure 5 Describe the embodiment according to the present disclosure Figure 4 an instance of selecting a target memory cell;

[0013] Figure 6 According to the embodiment of the present disclosure Figure 2 A diagram of a second embodiment of a portion of a memory array; and

[0014] Figure 7 is the selection and programming of the embodiments according to the present disclosure Figure 6 Flowchart of a method for storing a target memory cell in a memory cell. DETAILED DESCRIPTION

[0015] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation will be described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development efforts may be complex and time-consuming, but will be a routine of design, construction, and manufacturing undertaken by those skilled in the art who benefit from this disclosure.

[0016] Many electronic systems may employ memory devices to provide data storage functionality and / or facilitate the performance of data processing operations. Several memory devices may perform storage using electronic memory cells such as capacitors, flip-flops, latches, and / or inverter rings, among others. Examples of memory devices include random access memory (RAM) devices, dynamic RAM (DRAM) devices, static RAM (SRAM) devices, flash memory, and / or phase change memory (PCM) devices.

[0017] With respect to PCM devices, the selection of a target memory cell and its subsequent programming is important for configuring or otherwise setting up the device. However, problems may arise with the memory device itself (e.g., leakage current) that prevent proper selection of a target memory cell. Therefore, the present techniques and circuit systems are introduced to allow for more efficient and reliable memory cell selection and subsequent programming. In one embodiment, two or more selection (and / or nucleation) current mirrors may be utilized to allow for tailored current outputs. The selection of a particular current mirror may be based on characteristics of the target memory cell, such as its proximity to a column decoder and / or row decoder of the memory device. These characteristics may affect the amount of current that will be supplied to the target cell to snap the target memory cell.

[0018] In other embodiments, one or more select voltage sources may additionally be utilized to ramp the voltage output to produce a trimmed current output. One or more select voltage sources may be source followers and may be advantageous because they are less sensitive to array leakage (e.g., relative to current mirrors). Additionally, utilizing source followers as two or more select voltage sources may provide a faster ramp rate for the voltage output relative to, for example, current mirrors.

[0019] In some embodiments, a combination of one or more current mirrors and one or more voltage sources can be utilized to ramp up the voltage output more quickly and provide a trimmed current output. That is, one or more current mirrors and one or more voltage sources can provide multiple different combinations that can be used to provide current to the target cell.

[0020] In addition, in some embodiments, a word line or bit line snap detection circuit system may be utilized to allow dynamic snap detection of a target memory cell. In some embodiments, the snap detection circuit system may determine whether an appropriate voltage has been provided to induce snap in a target memory cell. The snap detection circuit system may be coupled to a plurality of memory arrays containing a plurality of memory cells. In some embodiments, the snap detection circuit system may count the amount of snap cells and use the percentage of snap cells and non-snap cells to adjust future selection current biasing. Relative to using a predetermined sensing operation at a scheduled scheduled time without feedback of the actual snap of the target memory cell, by using dynamic snap detection, the transition from a selection operation to a programming operation of the target memory cell may be accelerated. This may allow energy consumption to be reduced and may reduce the spike current in the target memory cell.

[0021] By using two or more select (and / or nucleation) current mirrors and / or select voltage sources and / or utilizing dynamic snap-on detection with a detection-based counter, the efficiency of the memory device can be improved, power consumption can be reduced (two or more select and / or nucleation current mirrors can be coupled to voltages having different values), the endurance of the memory device can be extended, and other advantages can also be achieved, for example by reducing current spikes by associating specific current mirrors and / or current levels with corresponding memory cells having specific characteristics.

[0022] Turning now to the accompanying drawings, Figure 1 An example memory apparatus 100 (or system) is shown in accordance with an embodiment of the present disclosure. The memory apparatus 100 may also be referred to as an electronic memory device. Figure 1 1 is an illustrative representation of various components and features of memory device 100. Thus, it should be understood that the components and features of memory device 100 are shown to illustrate functional interrelationships and do not necessarily represent actual physical locations within memory device 100. Figure 1 , memory device 100 includes a 3D memory array 102. 3D memory array 102 includes memory cells 105 that can be programmable to store different states. In some embodiments, each memory cell 105 can be programmable to store two states that can be labeled as logic 0 and logic 1. In some embodiments, memory cell 105 can be configured to store more than two logic states. In some embodiments, memory cell 105 can be a PCM cell (e.g., a 3D XPoint memory cell). In addition, although Figure 1 Some of the elements contained in the drawings are labeled with numerical designators, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the features depicted.

[0023] The 3D memory array 102 may include two or more two-dimensional (2D) memory arrays formed adjacent to each other (e.g., next to each other or right next to each other). This may increase the number of memory cells 105 that may be placed or formed on a single die or substrate compared to a 2D array, which in turn may reduce manufacturing costs, or increase the performance of the memory device, or both. Figure 1 , 3D memory array 102 includes two levels of memory cells 105; however, the number of levels may not be limited to two and may, for example, include a greater number of levels. Each level may be aligned or positioned so that memory cells 105 may be substantially aligned (exactly aligned, overlapping, or nearly aligned) with each other across each level, thereby forming a memory cell stack 145. In some cases, memory cell stack 145 may include two PCM cells (e.g., two 3D XPoint memory cells) disposed one above the other.

[0024] In some embodiments, each row of memory cells 105 is connected to a word line (e.g., word line 110), and each column of memory cells 105 is connected to a bit line 115. In some cases, word lines 110 and bit lines 115 can be substantially perpendicular to each other and can create an array of memory cells. Figure 1 As shown in , two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as a digit line 115. That is, the bit line 115 may be in electronic communication with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. In other embodiments, each of the memory cells 105 (e.g., upper memory cell, lower memory cell) may be configured with its own bit line. In such cases, the memory cells may be separated by an insulating layer. Other configurations are contemplated, such as a third layer may share a word line 110 with a lower layer. In general, one memory cell 105 may be located at the intersection of two conductive lines, such as a word line 110 and a bit line 115. This intersection may be referred to as the address of the memory cell 105. The target memory cell may be a memory cell 105 located at the intersection of an energized word line 110 and a bit line 115; that is, the word line 110 and the bit line 115 may be energized so as to read or write the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication (eg, connected) with the same word line 110 or bit line 115 may be referred to as non-target memory cells.

[0025] As discussed above, an electrode may be coupled to the memory cell 105 and the word line 110 or the bit line 115. The term electrode may refer to an electrical conductor, and in some cases, may serve as an electrical contact to the memory cell 105. The electrode may include a trace, a wire, a conductive line, a conductive layer, etc. that provides a conductive path between elements or components of the memory device 100. In some embodiments, the memory cell 105 may include a chalcogenide alloy positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to the word line 110, and the other side of the first electrode is coupled to the chalcogenide alloy. In addition, one side of the second electrode may be coupled to the bit line 115, and the other side of the second electrode may be coupled to the chalcogenide alloy. The first electrode and the second electrode may be the same material (e.g., carbon) or different materials. In other embodiments, the memory cell 105 may include additional electrodes to divide the chalcogenide alloy into two parts, such as Figure 2 . The first portion of the chalcogenide alloy may have a different composition than the second portion of the chalcogenide alloy. In some embodiments, the first portion of the chalcogenide alloy may have a different function than the second portion of the chalcogenide alloy. The additional electrode may have the same material (e.g., carbon) as the first electrode and / or the second electrode or be different from the first electrode and / or the second electrode.

[0026] Operations such as reading and writing can be performed on the memory cell 105 by energizing or selecting the word line 110 and the bit line 115. In some embodiments, the subline 110 may also be referred to as an access line, and the bit line 115 may also be referred to as a digital line. References to word lines and bit lines or the like are interchangeable and do not affect understanding or operation. Energizing or selecting the word line 110 or the bit line 115 may include applying a voltage to the corresponding line. The word line 110 and the bit line 115 may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds, etc.

[0027] In some architectures, the logical storage device of the memory cell 105 (e.g., a capacitor, a resistor, or a resistor of a chalcogenide material in the storage portion of the memory cell 105) can be electrically isolated from the bit line 115 by a selection component. The word line 110 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor, and the word line 110 can be connected to the gate of the transistor. Energizing the word line 110 creates an electrical connection or closed circuit between the logical storage device of the memory cell 105 and its corresponding bit line 115. The bit line 115 can then be accessed to read or write the memory cell 105. After the memory cell 105 is selected, the resulting signal can be used to determine the stored logical state. In some cases, the first logical state can correspond to no current or a negligible small current, while the second logical state can correspond to a limited amount of current. In some cases, the memory cell 105 can include a 3D XPoint memory cell or a self-select memory (SSM) cell, both of which have two terminals and may not require a separate selection component. Thus, one terminal of the 3D XPoint memory cell or SSM cell may be electrically connected to the word line 110 , and the other terminal of the 3D XPoint memory cell or SSM cell may be electrically connected to the bit line 115 .

[0028] Access to the memory cells 105 may be controlled by the row decoder 120 and the column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and energize the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 may receive a column address from the memory controller 140 and energize the appropriate bit line 115. For example, the 3D memory array 102 may include a plurality of word lines 110 labeled WL_B1 (or WL_T1) to WL_BM (or WL_TM), and a plurality of bit lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by energizing the word lines 110 and the bit lines 115 (e.g., WL_B2 and DL_3), the memory cells 105 at their intersections may be accessed.

[0029] Upon access, the sensing component 125 may read or sense the memory cell 105 to determine the stored state of the memory cell 105. For example, a voltage may be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of the resulting current may depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. In addition, if the applied voltage does not cause current to flow, other voltages may be applied until the sensing component 125 detects current. By evaluating the voltage that causes current to flow, the stored logical state of the memory cell 105 may be determined. In some cases, the magnitude of the voltage may be ramped up until current is detected (e.g., the memory cell 105 is turned on, switched on, conductive, or becomes activated). In other cases, predetermined voltages may be applied sequentially until current is detected. Likewise, current may be applied to the memory cell 105, and the magnitude of the voltage used to produce the current may depend on the resistance or threshold voltage of the memory cell 105.

[0030] The sensing component 125 may include various transistors or amplifiers to detect and amplify the signal difference, which may be referred to as a latch. The detected logic state of the memory cell 105 may then be output as output 135 by the column decoder 130. In some cases, the sensing component 125 may be part of the column decoder 130. Alternatively, the sensing component 125 may be connected or in electronic communication with the column decoder 130. Figure 1 Sense component 126 is also illustrated. As illustrated, sense component 126 is coupled to word line 110 and operates, for example, in conjunction with row decoder 120. For example, sense component 126 can operate in conjunction with row decoder 120 in a manner similar to sense component 125 as described above. Additionally, as will be described in more detail below, sense component 126 can also include circuitry that performs additional operations not performed via sense component 125, such as snap-on detection of target memory cells of 3D memory array 102. In some cases, sense component 126 can be part of column decoder 130. Alternatively, sense component 126 can be connected or in electronic communication with column decoder 130.

[0031] The memory cell 105 may be set or written by similarly energizing the associated word line 110 and bit line 115, and at least one logic value may be stored in the memory cell 105. The column decoder 130 and / or the row decoder 120 may accept data to be written to one or more memory cells 105, such as input / output 135. In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to the memory cell 105. In DRAM, for example, the capacitor of the memory cell 105 may be partially or completely discharged during a sensing operation, which may destroy the stored logic state. Therefore, the logic state may be rewritten after the sensing operation. In addition, energizing a single word line 110 may cause the memory cells 105 in the row to discharge; therefore, some or all of the memory cells 105 in the row may need to be rewritten. However, in other non-volatile memories such as SSM, PCM (eg, 3D XPoint memory), FeRAM, or 3D NAND memory, accessing memory cell 105 may not destroy the logic state, and thus rewriting memory cell 105 after access may not be required.

[0032] In operation, the memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of the memory cells 105 through various components, such as the row decoder 120, the column decoder 130, the sensing component 125, and the sensing component 126. In some cases, one or more of the row decoder 120, the column decoder 130, the sensing component 125, and the sensing component 126 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals in order to energize the desired word lines 110 and bit lines 115. The memory controller 140 may also generate and control various voltages or currents used during operation of the memory device 100.

[0033] The memory controller 140 may receive user data through the input / output 135, which may be a physical connection or path coupled to a connector of the memory device 100. In some embodiments, the memory controller 140 may read previous user data from the memory cell, and write new user data, and merge the new user data with the previous user data into a write register. Thereafter, mask register (MR) information may be generated, and wherein the mask register information may indicate bits of the previous user data stored in the memory cell whose logic values ​​are to be switched or not switched. In some embodiments, the memory controller 140 may count the number of first logic values ​​(logic "0") and second logic values ​​(logic "1") to be written respectively using the MR information, and store the number of the first logic values ​​and the second logic values ​​into a first counter and a second counter, respectively. In some embodiments, the memory controller 140 may apply a programming pulse to the memory cell 105 according to the mask register information.

[0034] In general, the amplitude, shape, polarity, and / or duration of the applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory device 100. For example, during access operations such as reset operations, set operations, and / or read operations, the current and / or voltage may be adaptively controlled. Furthermore, one, multiple, or all memory cells 105 within the memory array 102 may be accessed simultaneously; for example, multiple or all cells of the memory array 102 may be accessed simultaneously during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state.

[0035] Figure 2 An example of a memory array 200 supporting selective current mirror control according to an embodiment of the present disclosure is described. The memory array 200 may be a reference Figure 1 An example of a portion of memory array 102 is depicted. Figure 2 As depicted in FIG. 1 , memory array 200 includes a plurality of materials to construct memory cells 105 - a. Each memory cell 105 - a is stacked in a vertical direction (eg, perpendicular to a substrate) to form a memory cell stack (eg, memory cell stack 145). Memory cell 105 - a may be a reference Figure 1 1. The memory array 200 may therefore be referred to as a 3D memory array. The architecture of the memory array 200 may be referred to as a cross-point architecture. Figure 2 Some of the elements contained in the drawings are labeled with numerical designators, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the features depicted.

[0036] The memory array 200 also includes word lines 110 - a and bit lines 115 - a , which may be reference lines. Figure 1 Examples of word lines 110 and bit lines 115 are depicted. Figure 2 The description of the material between the word line 110-a and the bit line 115-a depicted in FIG. Figure 1 200. The memory array 200 includes an electrode 205, a logic storage element 210, a selector device element 220, and a substrate 225. In some examples, a single component (not shown, replacing the selector device element 220, the logic storage element 210, and the electrode 205-b) including a chalcogenide alloy can serve as both a logic storage element and a selector device. The electrode 205-a can be in electronic communication with the bit line 115-a, and the electrode 205-c can be in electronic communication with the word line 110-a.

[0037] The insulating material depicted as empty space may be electrically and thermally insulating. As described above, in PCM technology, various logic states may be stored by changing the resistance of the logic storage element 210 in the memory cell 105-a, which in turn exhibits a varying threshold voltage of the memory cell 105-a. In some cases, storing various logic states includes passing a current through the memory cell 105-a, causing the logic storage element 210 in the memory cell 105-a to generate heat, or (e.g., completely or partially) melting the material of the logic storage element 210 in the memory cell 105-a. Other storage mechanisms, such as threshold voltage modulation, may be employed in chalcogenide-based memories.

[0038] In some cases, the memory array 200 may include an array of memory cell stacks, and each memory cell stack may include a plurality of memory cells 105-a. The memory array 200 may be made by forming a stack of conductive materials, such as word lines 110-a, wherein each conductive material is separated from adjacent conductive materials by an electrically insulating material therebetween. The electrically insulating material may include an oxide or nitride material, such as silicon oxide, silicon nitride, or other electrically insulating material. These materials may be formed over a substrate 225, such as a silicon wafer, or any other semiconductor or oxide substrate. Subsequently, various process steps may be utilized to form material between the word lines 110-a and the bit lines 115-a so that each memory cell 105-a may be coupled to the word lines 110-a and the bit lines 115-a.

[0039] The selector device element 220 may be connected to the logic storage element 210 via the electrode 205-b. In some examples, the positioning of the selector device element 220 and the logic storage element 210 may be flipped. The composite stack including the selector device element 220, the electrode 205-b, and the logic storage element 210 may be connected to the word line 110-a via the electrode 205-c, and to the bit line 115-b via the electrode 205-a. The selector device element 220 may assist in selecting a particular memory cell 105-a, or may help prevent stray current from flowing through an unselected memory cell 105-a adjacent to the selected memory cell 105-a. The selector device element 220 may include an electrically nonlinear component (e.g., a non-ohmic component), such as a metal-insulator-metal (MIM) junction, a bidirectional threshold switch (OTS), or a metal-semiconductor-metal (MSM) switch, as well as other types of two-terminal selector devices, such as a diode. In some cases, the selector device element includes a chalcogenide alloy. In some examples, the selector device includes an alloy of selenium (Se), arsenic (As), silicon (Si), and germanium (Ge).

[0040] As discussed above, Figure 2 The memory cell 105-a may include a material having a variable resistance. The variable resistance material may refer to various material systems, including, for example, metal oxides, chalcogenides, etc. Chalcogenide materials are materials or alloys that include at least one of the elements sulfur (S), tellurium (Te), or selenium (Se). Many chalcogenide alloys may be possible, for example, germanium-antimony-tellurium alloy (Ge-Sb-Te) is a chalcogenide material. Other chalcogenide alloys not explicitly described herein may also be used.

[0041] To set the low resistance state, the memory cell 105-a may be heated by passing an electric current through the memory cell 105-a. The heating caused by an electric current flowing through a material having a finite resistance may be referred to as Joule or Ohmic heating. Joule heating may therefore be related to the resistance of an electrode or phase change material. Heating the phase change material to a high temperature (but below its melting temperature) may cause the phase change material to crystallize and form a low resistance state. In some cases, the memory cell 105-a may be heated by methods other than Joule heating, such as by using a laser. To set the high resistance state, the phase change material may be heated to above its melting temperature, such as by Joule heating. The amorphous structure of the molten material may be quenched or locked by suddenly removing the applied current to rapidly cool the phase change material.

[0042] Figure 32 is a flow chart of a method 250 for selecting a target memory cell from a set of memory cells 105. The memory controller 140 is described below as performing the method 250, but it should be understood that any suitable processing circuitry may additionally or alternatively perform the method 250. Furthermore, while the method 250 is described below as being performed in a particular order, it should be understood that one or more of the steps of the method 250 may be omitted or reordered, for example.

[0043] At block 252, the memory controller 140 may receive an address targeting a memory cell 105. The address may be a logical address that is converted to a physical address by the memory controller 140. The memory controller 140 may use the physical address to make certain control decisions. For example, at block 254, the memory controller 140 may use the physical address to determine which row decoders 120 and column decoders 130 to use to select a memory cell 105.

[0044] In conjunction with block 254, the memory controller 140 may look up indications of the row decoders 120 and column decoders 130 in memory, such as by using a query of a database, and / or perform address arithmetic to determine which row decoders 120 and column decoders 130 correspond to the physical address of the memory cell 105 (e.g., are located closest to the physical address of the memory cell). The database may have been populated when the memory device 100 was manufactured and / or adjusted during operation of the memory device 100 to reflect any logical to physical address assignments.

[0045] At block 256, the memory controller 140 may use the row decoder 120 and the column decoder 130 to transmit the select current to the target memory cell of the memory cell 105. The memory controller 140 may utilize the physical distance between the memory cell 105 and the row decoder 120 and the column decoder 130 to minimize the impact of the activation of the row decoder 120 and the column decoder 130 on the memory cell at the beginning (e.g., reduce the current spike). In addition, each of the memory cells 105 may correspond to two column decoders 130 for its corresponding bit line 115 and two row decoders 120 for its corresponding word line 110. The memory controller 140 may utilize the factors discussed above to determine which of the two decoders of the bit line 115 and the word line 110 may be activated.

[0046] At block 258, the memory controller 140 may employ the sensing components 125 and / or 126 to determine whether the target memory cell 105 has been properly selected by the row decoder 120 and the column decoder 130. In some embodiments, the sensing components are directly coupled to the word line 110 and the bit line 115 to ensure proper sensing of the select current being emitted to the target memory cell.

[0047] Considering the above, Figure 4 3 is a simplified array schematic diagram showing a 3D memory array 102 as part of an array 300, where a memory cell 105 is represented by a target memory cell 309 to be selected, for example, by a memory controller 140, and surrounding A-cells 301, B-cells 302, and C-cells 303. The A-cell 301 may represent a memory cell 105 located on a target word line 304 (e.g., a common or selected word line 110) with the target memory cell 309, and the B-cell 302 may represent a memory cell 105 located on a target bit line 305 (e.g., a common or selected bit line 115) with the target memory cell 309. The C-cell 303 may represent a memory cell 105 located on a different word line and bit line than the target memory cell 309. In some embodiments, the target word line 104 may be selected via a switch 310 controlled, for example, by a memory controller 140 and couple a higher voltage (e.g., 0V) through a current mirror (e.g., P1 mirror 306) to a lower voltage (e.g., -4V) as a mirror select voltage.

[0048] A set of current mirrors is coupled to the array 300, which current mirrors may be used in conjunction with operations of the array 300 (e.g., select, read, write, etc.). As illustrated, the current mirror set includes a P1 mirror 306, a P3 mirror 307, and a P4 mirror 308, which may be NFET devices in some embodiments. It may be important to note that these current mirrors may be represented as separate current mirrors, but in reality, may be a single physical current mirror with multiple different current trims as inputs into the gate. The P1 mirror 306 may operate in conjunction with a select operation (i.e., selection of a target memory cell 309), whereby the P1 mirror 306 provides a select current to the target word line 304 and the target memory cell 309. The P3 mirror 307 and the P4 mirror 308 may be programming mirrors, where, for example, the P3 mirror 307 operates with growth and the P4 mirror 308 operates with reset. Growth 307 using the P3 mirror may, for example, correspond to continued nucleation for one or more memory cells 105, which nucleation may, for example, have been initiated in a programming operation via the P1 mirror 306. Nucleation is a thermodynamic change of phase of a material, for example, starting from an amorphous state (e.g., a disordered phase of the material of the memory cell 105), raising the temperature, causing the formation of grains (e.g., an ordered phase of the material of the memory cell 105), thereby causing a phase change to the memory cell 105. Reset using the P3 mirror 307 may, for example, correspond to a reset of the memory state of the memory cell 105 to a low Vt state after growth has been completed.

[0049] In operation, when selection of target cell 309 is made, problems may arise when leakage occurs from A-cell 301. That is, the voltage difference across A-cell 301 may cause leakage current. Furthermore, the respective leakage currents of A-cell 301 are cumulative, so that the sum of the leakage currents along target word line 304 may be, for example, as much as an amount of approximately 14-20 μA or even more. This may potentially cause problems to arise because, for example, during selection of memory cell 105 (e.g., selection of target memory cell 309), P1 mirror 306 may provide the current that target memory cell 309 sees (i.e., has applied to) and the A-cell 301 leakage current may approach (or in some cases, exceed) the current provided by P1 mirror 306 to pull down target word line 304.

[0050] In addition, the A-cell 301 leakage and its strain on the P1 mirror 306 may also increase in the presence of an effect known as VSS rise. When the BL voltage is ramped to the highest voltage hpvpp to ensure a successful selection, the C-cell 303 bias from VDD (e.g., 1.2V) should also be applied to the deselected word line 110 to avoid erroneous selection on the B-cell 302. The non-transient C-cell 303 typically rises to approximately 400mV-800mV, which also pulls VSS up by approximately 200mV-400mV. The VSS rise increases the A-cell 301 sub-threshold leakage, affecting the negative word line 110 voltage delivery through the P1 mirror 306. This may otherwise cause a failure to properly select the target memory cell 309 operation.

[0051] Figure 5The selection process of the target memory cell 309 using the P1 mirror 306 is illustrated. The selection process may begin by setting the bit line voltage 320 to the default read VDM voltage vdm_int 322 for the column decoder 130. Next, the column decoder 130 may cause vdm_int 322 to ramp up. In some embodiments, the ramp up of vdm_int 322 may be divided into a mid-level ramp voltage (vdm3 323) to achieve a staircase-like pulse before reaching the bit line write voltage blwritev 324. The staircase effect has the benefit of minimizing the generation of spike currents, and the desired spike current ratio may be controlled by selecting the corresponding staircase level based on whether the target memory cell 309 is nearby (i.e., relatively close to the column decoder 130 in proximity and / or relatively close to the row decoder 120 in proximity) or whether the target memory cell 309 is far away (i.e., relatively far away from the column decoder 130 in proximity and / or relatively far away from the row decoder 120 in proximity). As used herein, inclusion of a target memory cell 309 in proximity (i.e., relatively close in proximity to a column decoder 130 and / or relatively close in proximity to a row decoder 120) is one of approximately 5%, approximately 10%, approximately 15%, approximately 20%, approximately 25%, approximately 30%, approximately 35%, or approximately 40% of the memory cells that are closest to the column decoder 130 in proximity along a bit line 115 and / or closest to the row decoder 120 along a word line 110. Likewise, as used herein, inclusion of a target memory cell 309 in proximity (i.e., relatively far in proximity to a column decoder 130 and / or relatively far in proximity to a row decoder 120) is one of approximately 5%, approximately 10%, approximately 15%, approximately 20%, approximately 25%, approximately 30%, approximately 35%, or approximately 40% of the memory cells that are farthest in proximity to a column decoder 130 along a bit line 115 and / or farthest in proximity to a row decoder 120 along a word line 110. Therefore, using a multi-step ramp (ie, staircase pulses) may increase the endurance of the memory cell 105 .

[0052] As vdm_int 322 is ramped up (e.g., via a staircase pulse), the target word line 304 drops from, for example, 0V to a mirror select voltage (i.e., a hnmirr_select voltage of, for example, approximately 4V). If the target memory cell 309 is a nearby cell, it may snap in when the bit line voltage 320 corresponds to the intermediate ramped voltage vdm3 323. This snap in may correspond to a voltage applied when the target memory cell 309 reaches a level at which the resistance across the target memory cell 309 is reduced, thus allowing current to flow through the target memory cell 309 at time 328. This snap in may be detected at time 325 in a snap in detection circuit (e.g., which may be or may include a current sensor, current detector, etc.), and the snap in detection circuit may be disposed, for example, in the sensing component 125. Likewise, if the target memory cell 309 is a far cell, it may snap in at time 329 when the bit line voltage 320 corresponds to the ramped voltage of the bit line write voltage blwritev 324. This snap-on may be detected in the snap-on detection circuit at time 325. Note that the bit line voltage 320 may be ramped back down to the mid-ramp voltage vdm3 323 to properly detect whether the target memory cell 309 has snapped at time 325 in conjunction with the sensing operation.

[0053] If the target memory cell 309 has snapped and the snapping has been detected at time 325, then programming of the target memory cell 309 may proceed. However, in some cases, the target memory cell 309 has not snapped at time 325. For example, if the target memory cell is far away and has shifted (i.e., if a resistance drift has occurred in the target memory cell 309 that causes the target memory cell 309 to prevent snapping at the bit line write voltage blwritev 324), then an additional voltage is applied to ramp the bit line voltage 320 from the mid-ramp voltage vdm3 323 to the high voltage hpvpp 326, thereby inducing snapping within the memory cell. In some embodiments, the high voltage hpvpp 326 may represent the maximum voltage that the column decoder 130 may provide as the bit line voltage 320 to snap to the target memory cell 309, as represented at time 330.

[0054] As discussed above, snap-on detection circuitry may be present on the bit line side (eg, corresponding to the positive side), such as in the sensing element 125. However, in conjunction with Figure 4 and 5, there may not be any snap detection circuitry on the word line 110 side (e.g., corresponding to the negative side) of the array 332. Therefore, any sequence on the word line 110 side is instead predetermined as an instruction (e.g., providing a predetermined trim to one or more of the P1 mirror 306, P3 mirror 307, and P4 mirror 308 at a predetermined time, where the trim (or trim signal) is an input signal (e.g., a control signal) that controls the amount of current used for the current mirrors P1 mirror 306, P3 mirror 307, and P4 mirror 308). This has the effect of turning the mirror trim into a blind one (i.e., performed at a predetermined time rather than, for example, based on the actual time when a snap occurs at the target memory cell 309). Furthermore, since the transitions of the current mirrors P1 mirror 306, P3 mirror 307, and P4 mirror 308 in response to applying a new trim take time (e.g., one or more milliseconds) to adjust to the new current, when this is coupled with the initiating trim transition at a predetermined time, additional time is consumed which may cut into other operating time periods (e.g., nucleation time) and reduce the efficiency of the 3D memory array 102. Thus, for example, if Figure 5 As illustrated in FIG. 3 , trimming 327 for P1 mirror 306 continues until after time 330 to ensure that target memory cell 309 has snapped in, which reduces the potential efficiency gain that may exist when target memory cell 309 snaps in (rather than at time 328 or 329). Finally, in conjunction with Figure 4 and Figure 5 Adjustments to the trim amount also typically utilize existing available trims, such as read or write trims, which may limit the current adjustments that may be selected for current mirrors P1 mirror 306 , P3 mirror 307 , and P4 mirror 308 .

[0055] Figure 6 A second embodiment of the 3D memory array 102 is illustrated as part of an array 332. The array 332 is similar to the array 300 in that it includes the memory cell 105 represented by a target memory cell 309 to be selected by, for example, the memory controller 140, and surrounding A-cells 301, B-cells 302, and C-cells 303. Similarly, the array 332 includes a target word line 304, a target bit line 305, and a P1 mirror 306, a P3 mirror 307, and a P4 mirror 308. The array 332 additionally includes at least one additional current mirror 334.

[0056] When different operations are implemented with different currents, for example, using a first current in conjunction with a select operation and a second current for a program operation, the array 332 can operate more efficiently. For example, due to the A-cell 301 leakage current, a relatively high current can be implemented to prevent the A-cell 301 leakage current from saturating a current mirror (e.g., current mirror 334) being utilized in selecting the target memory cell 309. Additionally, when the target memory cell 309 is far away (i.e., relatively far away in proximity from the column decoder 130 and / or relatively far away in proximity from the row decoder 120), a higher current (e.g., between approximately 45 μA and 65 μA) is utilized to snap the cell, while when the target memory cell 309 is nearby (i.e., relatively close in proximity to the column decoder 130 and / or relatively close in proximity to the row decoder 120), a lower current (e.g., between approximately 25 μA and 35 μA) is utilized to snap the target memory cell 309. This may be attributed, for example, to the voltage drop (IR drop) caused by the A-cell 301 leakage current and the resistance of the line (e.g., the target word line 304). That is, the farther along the target word line 304 the target memory cell 309 is (e.g., farther away from the row decoder 120), the greater the resistance of the target word line 304 will be, which will result in a greater voltage drop. Therefore, in this scenario, it is also advantageous to utilize a current mirror (e.g., current mirror 334) with a current higher than the currents of the current mirrors P1 mirror 306, P3 mirror 307, and P4 mirror 308.

[0057] Furthermore, the target word line 304 ramp rate is affected by the current mirror utilized. When the current mirror pulls down the voltage during a target memory cell 309 select operation, the parasitics of the tile (e.g., all memory cells 105 of the target word line 304) are also pulled down. Additionally, there is a correlation between the rate of voltage change over time (dV / dT) and the amount of current of the current mirror being utilized. Additionally, for larger values ​​of dV / dT (i.e., faster transitions), larger current spikes are achieved when the target memory cell 309 is switched on (when the target memory cell 309 is nearby), which can adversely affect the endurance of the memory device 100. Since there is no similar current spike when the target memory cell 309 is far away, it is advantageous to utilize a current mirror (e.g., current mirror 334) having a current higher than the currents of current mirrors P1 mirror 306, P3 mirror 307, and P4 mirror 308 in a select operation when the target memory cell is far away, while it is advantageous to utilize a current mirror such as current mirror P1 mirror 306 in a select operation when the target memory cell is nearby, because this can increase the useful life (endurance) of the memory device 100 (especially the 3D memory array 102). It should be noted that while current mirror 334 has been discussed, similar advantages can be provided when utilizing another additional current mirror having a current different from, for example, current mirror 334 and P1 mirror 306. This can allow for greater granularity in selecting current outputs for select and / or program operations.

[0058] Additional benefits may be obtained from using the current mirror 334 (or another additional current mirror) at the time of programming operations (e.g., nucleation). The initial programming after selecting the target memory cell 309 may be nucleation in conjunction with a set operation on the target memory cell 309. One set of operations may include crystallization of the memory cell 105 to a crystalline state (having a lower resistance), while a reset operation may return the memory cell 105 to an amorphous state (having a greater resistance). The completion of a set operation generally consumes more time than a reset operation. Therefore, a set operation may be considered time sensitive, and improvements in the start time of initiating a set operation are advantageous because this speeds up the operation of the memory device 100. For example, by being able to accurately determine the snap-in of the target memory cell 309, the set operation may be initiated after the snap-in of the target memory cell 309, rather than at a predetermined time thereafter. This may enable a faster transition to a set operation relative to initiating a set operation at a predetermined time.

[0059] For at least the reasons discussed above, it is advantageous to utilize current mirror 334 as an additional select mirror in addition to P1 mirror 306. By including a current mirror 334 having a different current than, for example, P1 mirror 306, different currents are available for use in select and program operations. Furthermore, by having the individual current mirrors each trimmed to provide different currents, delays associated with altering the current of a given current mirror (e.g., P1 mirror 306) via different trimmings may be avoided. Furthermore, to obtain additional efficiency gains, in some embodiments, an additional snap detection circuit 336 may be present on the word line 110 side (e.g., corresponding to the negative side), such as in the sense component 126. This snap detection circuit 336 (e.g., which may be or may include a current sensor, current detector, etc.) may detect snaps in the target memory cell 309 to allow for a faster transition of switching between current mirrors (e.g., between current mirror 334 and P1 mirror 306 or P3 mirror 307). The snap detection circuit 336 may emit a snap detection signal indicating that a snap has occurred.

[0060] In some embodiments, the current mirror 334, the P1 mirror 306, the P3 mirror 307, and the P4 mirror 308 are controlled by a current mirror control circuit 338. The current mirror control circuit 338 may be disposed in or be part of the memory controller 140, and may be a controller or other logic device that generates signals used to control the current mirror 334, the P1 mirror 306, the P3 mirror 307, and the P4 mirror 308. In some embodiments, current mirror control circuit 338 may be used to activate current mirror 334, P1 mirror 306, P3 mirror 307, and P4 mirror 308, and / or current mirror control circuit 338 may be used to generate and transmit trimming from output 340 along path 342 for controlling current mirror 334, P1 mirror 306, P3 mirror 307, and P4 mirror 308, e.g., thereby allowing current mirror 334, P1 mirror 306, P3 mirror 307, and P4 mirror 308 to be used in various operations (e.g., using current mirror 334 and P1 mirror in target memory cell 309 selection and subsequent nucleation). Current mirror control circuit 338 may also include input 344 coupled to snap-on detection circuit 336 via path 346 (e.g., wire). Likewise, current mirror control circuit 338 may include input 348 that receives position information of the target cell (e.g., nearby or far away).

[0061] In operation, the current mirror control circuit 338 receives information about the position of the target memory cell 309 (i.e., whether it is near or far) and can generate corresponding trimming based thereon to achieve selection of the target memory cell 309. In some embodiments, the position of the target memory cell 309 is determined during address decoding and the address (or an indication of whether it is near or far) is transmitted to the current mirror control circuit 338. Likewise, in operation, the current mirror control circuit 338 receives snap-on detection information (e.g., via a signal) from the snap-on detection circuit 336 at input 344 along path 346. This snap-on detection information is an indication that a snap-on of the target memory cell 309 has occurred. The current mirror control circuit 338 may thereafter (e.g., dynamically) transition the trimming to a programming operation trimming that is transmitted to the selected current mirror (e.g., to initiate a programming operation and corresponding nucleation).

[0062] In other embodiments, one or more voltage sources may be utilized and swapped between one or more voltage sources to ramp the voltage output to a trimmed current output produced similar to the current output of the current mirror discussed above. The type of voltage source utilized may be a source follower. The voltage source may provide a stable voltage source that does not require the same amount of time as the current mirror discussed to ramp to the voltage required for the current output, but instead, more quickly and reliably provides the voltage required to produce the correct current for selection. An example of this embodiment may be represented by source followers 349 and 350 configured to output the corresponding voltage required for the snap-in target cell 309. In some embodiments, one or more of source follower 349 and source follower 350 may be selected individually with current mirror 334, or, for example, source follower 349 or one of source followers 350 may be switched in two states for one or more clock cycles of current mirror 334 (e.g., source follower 349 may be activated and coupled to array 332 for a predetermined time period, and source control multiplexer 351 may switch from selecting source follower 349 as a voltage source to selecting current mirror 349 as a voltage source coupled to array 332).

[0063] The voltage sources and current mirrors may be directly connected to a source control multiplexer 351 that controls which current mirrors and / or voltage sources are selected. The source control multiplexer 351 may have two or more inputs 352 to determine which voltage sources and / or current mirrors are selected for use. On the paths between the source control multiplexers 351, the current mirrors and voltage sources are transmission gates 353 (e.g., switches or other transfer gates) that may be located between each node between the paths from the source control multiplexer 351 to each individual current mirror or voltage source. These transmission gates 353 may operate as switches, controlled by the output of the source control multiplexer 351, so that the corresponding voltage source (e.g., current mirror or source follower) coupled thereto is connected to the array 332. It should be noted that because two inputs 352 are illustrated, there are only four corresponding transmission gates 353 (e.g., in embodiments where the source followers 349 and source followers 350 are not connected or do not exist). However, when source follower 349 and source follower 350 are present, each of them may be coupled to source follower 349 or source follower 350 via a corresponding transmission gate 353 leading to a source control multiplexer 351, which may also include an additional input 352 for selecting up to eight voltage sources (e.g., current mirrors and source followers). Figure 7 A technique to implement a select operation and a corresponding switch to a program operation for a target memory cell 309 is described.

[0064] Figure 7 A method 350 for implementing selection and programming operations for a target memory cell 309 is described. In step 352, selection of a current mirror is performed, for example, by a current mirror control circuit 338. In certain embodiments, selection of a voltage source and / or current mirror may be performed by a source control multiplexer 351. This current mirror and / or voltage source selection (or selection of a toggle switch thereof) may be based, for example, on positional information about the target memory cell 309 (i.e., whether it is nearby or far away). For example, when the target memory cell 309 is determined to be far away, the current mirror 334 (or another additional current mirror or source follower 349 or source follower 350) may be selected in step 352, while when the target memory cell 309 is determined to be nearby, the P1 mirror 306 may be selected in step 352. This will allow a specifically tailored current to be applied to the target memory cell 309 based on its position in order to improve the durability of the device (as previously described). Additionally, step 352 may include, for example, initiating a selection operation of the target memory cell 309.

[0065] In step 354, an indication of a snap is received, for example, by the current mirror control circuit 338 or the source control multiplexer 351. In some embodiments, this snap indication is received as snap detection information from the snap detection circuit 336 along path 346 at input 344, and in other embodiments, this snap detection is received as snap detection information entering the source control multiplexer 351 at one of the inputs 352. The snap detection circuit 336 may continuously monitor the target memory cell 309 and emit an indication when detected. Alternatively, the snap detection circuit 336 may sense a snap at a predetermined time during the ramp-up of the bit line voltage 320. For example, a sensing operation may be performed, a snap detection may be performed at or about time 328, at or about time 329, at or about time 325, and / or at or about time 330, and the sensing operation is performed by the snap detection circuit 336 (e.g., also by combining Figure 5 any sensing operations performed at time 325 by the described quick connect detection circuit).

[0066] In step 356, a transition is made to a programming operation. Step 356 may include changing the trim of the current mirror selected in step 352 to initiate a programming operation. Alternatively, step 356 may include selecting a new current mirror and transmitting the programming trim to the newly selected current mirror to initiate a programming operation. In some embodiments, the determination of the current mirror to be selected may be based on whether the target memory cell 309 is nearby or far away and / or based on the current output of the corresponding current mirror.

[0067] In some embodiments, as part of method 350, an additional step 358 may be performed. If the target memory cell fails to be selected in step 354, a new current mirror or a new voltage source may be selected and step 354 may be repeated. Step 358 may be performed when a condition has occurred, such as an amount of time has passed. In step 358, current mirror control circuit 338 selects a new current mirror coupled to, for example, a more negative voltage source, because current mirror 334, P1 mirror 306, P3 mirror 307, and / or P4 mirror 308 may be driven by different voltage sources. Additionally, in step 358, source control multiplexer 351 may connect the new current mirror and / or voltage source via the selected activated switch. This will allow a larger voltage source to be used when necessary, while also providing a smaller voltage source at other times, thereby reducing overall power consumption relative to always using a larger voltage source.

[0068] As discussed above, in step 354, an indication of a snap is received. However, in some embodiments, a technique may be implemented in which the received snap indications are counted, i.e., counter-based snap detection. This step may be perpetual across multiple cells across an entire array, tiles containing multiple arrays, and partitions containing multiple tiles. The snap detection circuitry may count the amount of cells snapped in each step 354 for each cell in a defined amount of cells, and adjust the select bias using the percentage of snapped cells to unsnapped cells. That is, the additional step 358 may be affected by the percentage of snapped cells, and the subsequent selection of voltage sources (i.e., different current mirrors and / or source followers) may be affected by the percentage of snapped cells in order to correct for drift and / or other factors (i.e., increase the select bias to offset drift). By detecting the snap count (e.g., whether a threshold percentage of cells are snapped), a larger tailored select bias corresponding to the threshold percentage of snapped cells may be applied. Thus, in some embodiments, the quick connect detection in step 354 is a count detection based on a counter (eg, based on statistics).

[0069] By employing the techniques described in the present disclosure, the systems and methods described herein may allow for improved selection and programming processes for phase change memory cells in a 3D X-point architecture. Snap detection of the sense current may allow for rapid transitions between current mirrors to ensure increased nucleation time, thereby allowing for more programming time for the selected memory cell. A dedicated current mirror may overcome saturation introduced by A-cell leakage from the memory array and may allow for consistent selection currents that select the correct memory cell. In fact, enabling the current mirrors to be driven by a more negative voltage source may allow for higher levels of power efficiency across the current mirrors. The techniques described in the present disclosure may lead to further improvements in 3D X-point technology and memory architecture as a whole.

[0070] Although various modifications and alternative forms may occur in the present disclosure, specific embodiments have been shown by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. In fact, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0071] The technology presented and claimed herein is referenced and applied to substantial objects and specific examples of a practical nature that improve the art in a demonstrable manner and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is expected that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is expected that such elements will not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A memory device (100), comprising: A memory array (300) comprising a plurality of memory elements (301, 302, 303, 309); a first circuit (334, 349, 350) that, when in operation, selectively applies a first voltage to a word line (304) of the memory array (300) to select a target memory cell (309) as a first memory element of the plurality of memory elements (301, 302, 303, 309) when the target memory cell (309) is in a first orientation of the memory array (300); and A second circuit (306, 349, 350) that, when in operation, selectively applies a second voltage to the word line (304) of the memory array to select the target memory cell (309) as the first memory element of the plurality of memory elements (301, 302, 303, 309) when the target memory cell (309) is in a second orientation of the memory array.

2. The memory device of claim 1, wherein the first circuit (334, 349, 350) when in operation receives a first trim signal as a control signal to apply the first voltage at a first time.

3. The memory device of claim 2, wherein the first circuit (334, 349, 350) when in operation receives a second trim signal as a second control signal to apply a third voltage to the word line (304) of the memory array (300) at a second time after selecting the target memory cell (309).

4. The memory device of claim 2, wherein the second circuit (306, 349, 350) when in operation receives a second trim signal as a second control signal to apply a third voltage to the word line (304) of the memory array (300) at a second time after selecting the target memory cell (309).

5. The memory device of claim 1, wherein the second circuit (306, 349, 350) when in operation receives a first trim signal as a control signal to apply the second voltage at a first time.

6. The memory device of claim 5, wherein the second circuit (306, 349, 350) when in operation receives a second trim signal as a second control signal to apply a third voltage to the word line of the memory array at a second time after selecting the target memory cell.

7. The memory device of claim 5, wherein the first circuit (334, 349, 350) when in operation receives a second trim signal as a second control signal to apply a third voltage to the word line (304) of the memory array (300) at a second time after selecting the target memory cell (309).

8. The memory device of claim 1, comprising a third circuit (349, 350) that, when in operation, selectively generates a third voltage to select the target memory cell as the first memory element of the plurality of memory elements.

9. The memory device of claim 1, wherein the first circuit (334, 349, 350) when in operation generates the first voltage to select the target memory cell as the first memory element of the plurality of memory elements when the target memory cell is positioned in proximity to a row decoder of the memory device.

10. The memory device of claim 9, wherein the second circuit (306, 349, 350) when in operation generates the second voltage to select the target memory cell as the first memory element of the plurality of memory elements when the orientation of the target memory cell is away in proximity from the row decoder of the memory device.

11. A memory device comprising: a memory array comprising a plurality of memory elements organized into word lines and bit lines; a snap-in detection circuit coupled to the word line of the memory array, wherein the snap-in detection circuit is operative to detect a snap-in in a target memory cell; a first circuit that, when in operation, selectively applies a first voltage to a first one of the word lines in conjunction with a selection operation to select the target memory cell of the word line as a first one of the plurality of memory elements; a second circuit that, when in operation, selectively applies a second voltage to the first word line of the memory array in conjunction with the selection operation to select the target memory cell of the word line as the first memory element of the plurality of memory elements; and A control circuit includes a first input coupled to the snap-in detection circuit and an output coupled to the first circuit and the second circuit.

12. The memory device of claim 11, wherein the control circuit comprises a second input that, when in operation, receives orientation information of the target memory cell relative to an orientation of a row decoder coupled to the first word line.

13. The memory device of claim 12 , wherein the control circuit, when in operation, transmits a first trim signal to the first circuit to control output of a first current to the first word line of the memory array to select the target memory cell of the word line as the first memory element among the plurality of memory elements at a first time when the orientation information has a first value.

14. The memory device of claim 13 , wherein the control circuit, when in operation, transmits a second trim signal to the second circuit to control output of a second current to the first word line of the memory array to select the target memory cell of the word line as the first memory element of the plurality of memory elements at the first time when the orientation information has a second value.

15. The memory device of claim 14, wherein the control circuit, when in operation, receives a snap-on detection signal from the snap-on detection circuit at the first input in response to the snap-on detection circuit detecting a snap-on of the target memory cell when the snap-on occurs.

16. The memory device of claim 15 , wherein the control circuit, when in operation, transmits a third trim signal to the first circuit to control output of a third current to the first word line of the memory array to program the target memory cell based on the snap-in detection signal and the orientation information of the target memory cell.

17. The memory device of claim 15, wherein the control circuit, when in operation, transmits a third trim signal to the second circuit to control output of a third current to the first word line of the memory array to program the target memory cell based on the snap-in detection signal and the orientation information of the target memory cell.

18. The memory device of claim 15, wherein the quick connect detection circuit transmits the quick connect detection signal at a predetermined time.

19. A method comprising: determining a physical location of a target memory cell in a word line of a memory array; applying a first voltage from a first circuit to the word line at a first time in conjunction with a selection operation to select the target memory cell when the physical orientation is determined to have a first characteristic; applying a second voltage from a second circuit to the word line at the first time in conjunction with the selection operation to select the target memory cell when the physical orientation is determined to have a second characteristic; and When a snap-in of the target memory cell occurs, the snap-in of the target memory cell is detected.

20. The method according to claim 19, comprising: A snap-in detection signal is generated indicating the snap-in of the target memory cell.

21. The method of claim 20, comprising applying a third voltage from the first circuit to the word line to initiate nucleation of the target memory cell based on the snap-on detection signal in conjunction with a programming operation.

22. The method of claim 19, comprising determining a threshold percentage of cell snap-ins of which the snap-in of the target memory cell is a portion; and A selection bias value is determined when the threshold percentage is at or above a predetermined value.

23. A memory device comprising: a memory array comprising a plurality of memory elements; a first circuit that, when in operation, selectively generates a first voltage to select a target memory cell as a first memory element of the plurality of memory elements when the target memory cell is positioned in proximity to a row decoder of the memory device, wherein the first circuit, when in operation, receives a first trim signal as a control signal to generate the first voltage at a first time; and a second circuit that, when in operation, selectively generates a second voltage to select the target memory cell as the first memory element of the plurality of memory elements when the orientation of the target memory cell is away in proximity from the row decoder of the memory device; Wherein the second circuit, when in operation, receives a second trim signal as a second control signal to generate a third voltage at a second time after the target memory cell is selected.

24. The memory device of claim 23, comprising a third circuit that, when in operation, selectively outputs a fourth voltage to select the target memory cell as the first memory element of the plurality of memory elements.

25. The memory device of claim 23 , wherein the first circuit, when in operation, outputs the first voltage to select the target memory cell as the first memory element among the plurality of memory elements when the orientation of the target memory cell is close in proximity to the row decoder of the memory device, wherein the second circuit, when in operation, outputs the second voltage to select the target memory cell as the first memory element among the plurality of memory elements when the orientation of the target memory cell is far in proximity from the row decoder of the memory device.

26. A memory device comprising: a memory array comprising a plurality of memory elements; a second circuit that, when in operation, selectively generates a first voltage to select a target memory cell as a first memory element of the plurality of memory elements when the target memory cell is positioned in proximity to a row decoder of the memory device; and a first circuit that, when in operation, selectively generates a second voltage to select the target memory cell as the first memory element of the plurality of memory elements when the orientation of the target memory cell is proximately away from the row decoder of the memory device, wherein the first circuit, when in operation, receives a first trim signal as a control signal to generate the second voltage at a first time, wherein the The second circuit, when in operation, receives the second trim signal as a second control signal to generate a third voltage at a second time after the target memory cell is selected.

27. The memory device of claim 26, comprising a third circuit that, when in operation, selectively outputs a fourth voltage to select the target memory cell as the first memory element of the plurality of memory elements.

28. The memory device of claim 26 , wherein the second circuit, when in operation, outputs the first voltage to select the target memory cell as the first memory element among the plurality of memory elements when the orientation of the target memory cell is close in proximity to the row decoder of the memory device, wherein the first circuit, when in operation, outputs the second voltage to select the target memory cell as the first memory element among the plurality of memory elements when the orientation of the target memory cell is far in proximity from the row decoder of the memory device.

29. A memory device comprising: a memory array comprising a plurality of memory elements organized into word lines and bit lines; a snap-on detection circuit coupled to the word line of the memory array; a first circuit that, when in operation, selectively outputs a first voltage to a first word line of the word lines in conjunction with a selection operation to select a target memory cell of the first word line as a first memory element of the plurality of memory elements; a second circuit that, when in operation, selectively outputs a second voltage to the first word line of the memory array in conjunction with the selection operation to select the target memory cell of the first word line as the first memory element of the plurality of memory elements; and a control circuit comprising a first input coupled to the snap-on detection circuit and outputs coupled to the first circuit and the second circuit, wherein the control circuit comprises a second input that, when in operation, receives orientation information of the target memory cell relative to an orientation of a row decoder coupled to the first word line.

30. The memory device of claim 29, wherein the control circuit, when in operation, transmits a first trim signal to the first circuit to control output of a first current to the first word line of the memory array to select the target memory cell of the first word line as the first memory element among the plurality of memory elements at a first time when the orientation information has a first value.

31. The memory device of claim 30 , wherein the control circuit, when in operation, transmits a second trim signal to the second circuit to control output of a second current to the first word line of the memory array to select the target memory cell of the first word line as the first memory element among the plurality of memory elements at the first time when the orientation information has a second value.

32. The memory device of claim 31, wherein the control circuit, when in operation, receives a snap-in detection signal from the snap-in detection circuit at the first input in response to the snap-in detection circuit detecting the snap-in of the target memory cell.

33. The memory device of claim 32, wherein the control circuit, when in operation, transmits a third trim signal to the first circuit to control output of a third current to the first word line of the memory array to program the target memory cell based on the snap-in detection signal and the orientation information of the target memory cell.

34. The memory device of claim 32, wherein the control circuit, when in operation, transmits a third trim signal to the second circuit to control output of a third current to the first word line of the memory array to program the target memory cell based on the snap-in detection signal and the orientation information of the target memory cell.

35. The memory device of claim 32, wherein the quick connect detection circuit transmits the quick connect detection signal at a predetermined time.

36. A method comprising: determining a physical location of a target memory cell in a word line of a memory array; outputting a first voltage from a first circuit to the word line at a first time in conjunction with a selection operation to select the target memory cell when the physical location is determined to be proximate to a row decoder of a memory device including the memory array; and A second voltage is output from a second circuit to the word line at a second time in conjunction with the selection operation to select the target memory cell when the physical location is determined to be closely spaced from the row decoder of the memory device comprising the memory array.

37. The method of claim 36, comprising: When a snap connection of the target memory cell occurs, detecting the snap connection of the target memory cell; and A snap-in detection signal is generated indicating the snap-in of the target memory cell.

38. The method of claim 37, comprising outputting a third voltage from the first circuit to the word line in conjunction with a programming operation to initiate nucleation of the target memory cell based on the snap-on detection signal.

39. The method of claim 37, comprising: determining a threshold percentage of cell snap-ins of which the snap-in of the target memory cell is a portion; and A select bias voltage value is determined when the threshold percentage of cells snapping in is at or above a predetermined value.

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