Local interconnect layer with devices in second dielectric material and related methods

Abstract

The present disclosure relates to a local interconnect layer having a device within a second dielectric material and related methods. Embodiments of the present disclosure provide an integrated circuit (IC) structure including a device layer including a device on a substrate. A local interconnect layer is located above the device layer and includes a first dielectric material located above the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is located above the device and adjacent to the first dielectric material. The second dielectric material has a second effective dielectric constant that is less than the first effective dielectric constant.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to integrated circuits (ICs). More specifically, this disclosure relates to IC structures including local interconnect (LI) layers having devices and conductors within a second dielectric material and related methods for forming such layers. Background Technology

[0002] In the microelectronics industry, and in other industries involving the construction of microstructures, there has always been a desire to reduce the size of structural features and microelectronic devices and / or to provide a greater volume of circuitry for a given chip size. Miniaturization typically allows for improved performance (more processing per clock cycle and less heat generation) at lower power levels and lower costs. Current technology is at the stage of atomically scaling certain miniature devices, such as logic gates, field-effect transistors (FETs), bipolar junction transistors (BJTs), and capacitors. Circuit chips with millions of such devices are commonplace.

[0003] In devices comprising multiple transistors (e.g., FETs), the scaling of devices has been accompanied by technical setbacks due to the close proximity of device components. In particular, one variable is parasitic capacitance, which arises when a transistor exhibits capacitance across two terminals when the device is off. Parasitic capacitance reduces circuit gain, and more generally, reduces electrical isolation between nearby transistors within the device layer. Conventional methods for reducing parasitic capacitance in transistors (e.g., guard rings) may not be feasible when such components do not provide a hermetically sealed environment on the device layer. The thermal conductivity of known dielectric materials used in hermetically sealed devices may be insufficient for certain technical applications, such as amplifiers or switching circuits. Summary of the Invention

[0004] This disclosure provides an integrated circuit (IC) structure comprising: a device layer including devices located on a substrate; and a local interconnect layer located above the device layer, the local interconnect layer comprising: a first dielectric material located above the substrate and having a first effective dielectric constant, and a second dielectric material located above the devices and adjacent to the first dielectric material, the second dielectric material having a second effective dielectric constant less than the first effective dielectric constant.

[0005] Other aspects of this disclosure provide an integrated circuit (IC) structure comprising: a device layer including a first device on a substrate and a second device on the substrate horizontally away from the first device; and a local interconnect layer above the device layer, the local interconnect layer comprising: a first dielectric material having a first effective dielectric constant located above the first device; a first contact to the first device and located within the first dielectric material; a second dielectric material having a second effective dielectric constant less than the first effective dielectric constant located above the second device and adjacent to the first dielectric material; and a second contact to the second device and located within the second dielectric material.

[0006] Another aspect of this disclosure provides a method for forming an integrated circuit (IC) structure, the method comprising: forming a first dielectric material over a first device and a second device in a device layer and across a conductor over the second device, wherein the first dielectric material has a first effective dielectric constant; forming an opening within a portion of the first dielectric material to expose the second device, wherein the first opening is across the conductor; and forming a second dielectric material within the opening, across the first dielectric material and across the conductor, the second dielectric material having a second effective dielectric constant less than the first effective dielectric constant. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood in conjunction with the accompanying drawings describing various embodiments of the present disclosure, and in accordance with the following detailed description of various aspects of the present disclosure, wherein:

[0008] Figure 1 A cross-sectional view of the device layer and local interconnect layer in an initial state according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A cross-sectional view is shown of an opening formed within a portion of a first dielectric material according to an embodiment of the present disclosure.

[0010] Figure 3 A cross-sectional view of the formation of a second dielectric material according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a metal wiring layer formed above a local interconnect layer according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of an IC structure having a gas dielectric region within a local interconnect layer according to an embodiment of the present disclosure is shown.

[0013] Figure 6A cross-sectional view of an IC structure having a nitride liner between a first dielectric material and a second dielectric material is shown according to an embodiment of the present disclosure.

[0014] Figure 7 A cross-sectional view of an IC structure having a portion of a second dielectric material within a device layer, according to an embodiment of the present disclosure, is shown.

[0015] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0016] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0017] Embodiments of this disclosure provide an integrated circuit (IC) structure in which a local interconnect (LI) layer includes devices and conductors located within a second, different dielectric material. The presence of the second dielectric material can reduce parasitic capacitance across the transistor when the transistor is in an "off" state. Other portions of the LI layer may include conventional dielectric material located above other transistors in the same device layer, for example, to provide a hermetically sealed location elsewhere. Embodiments of this disclosure may include a device layer having multiple devices, one being a "first device" and another being a "second device" horizontally distant from the first device. These devices may be transistors (e.g., FETs) and / or capacitors, resistors, diodes, etc.

[0018] A first dielectric material of the LI layer is located above a first device, and a second dielectric material of the LI layer is located above a second device. The effective dielectric constant of the components of the second dielectric material is less than that of the first dielectric material. A conductor to the second device is located within the second dielectric material and electrically couples the second device to a metal wiring layer above the local interconnect layer. The second dielectric material may take the form of a dielectric pillar extending vertically through portions of the LI layer and one or more metal wiring layers thereon. In this case, the term "pillar" may refer to various vertically extending entities, including shafts, rods, obelisks, etc., which extend continuously or discontinuously through a defined space within the LI layer and / or the metal wiring layers thereon. In this case, the dielectric pillar may extend further above the device layer than the first dielectric material, and components such as conductors and / or portions of one or more devices may be located within the dielectric pillar. During operation, the second dielectric material above the second device reduces the parasitic capacitance across the second device when the second device is turned off. Therefore, the second device can be integrated into amplifiers, electrical switches, and / or similar circuits that are more likely to exhibit high parasitic capacitance, and the first device can be integrated into other types of circuits.

[0019] refer to Figure 1 The embodiments of this disclosure provide an IC structure and a method for forming an IC structure. Figure 1 An initial structure 100 (hereinafter referred to as the "structure") is provided, representing a partially fabricated IC having a device layer 102 and a local interconnect (LI) layer 104 located above the device layer 102. A portion of a metal wiring layer 106 may be located above the LI layer 104, and additional metal wiring layers may be formed above the metal wiring layer 106, as described elsewhere herein. The device layer, LI layer 104, and metal wiring layer 106 may be formed substantially according to conventional methods to form transistors and overlay conductors, such as metal wiring and / or vias. Such methods are generally understood in the art, except for various techniques related to this disclosure, and are not described in further detail herein. The device layer 102 of structure 100 may be formed on a substrate 108 comprising, for example, one or more semiconductor materials. The substrate 108 may comprise any semiconductor material now known or hereafter developed, which may include, but is not limited to, silicon, germanium, silicon carbide, and substantially composed of one or more semiconductor materials having the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4The semiconductor material is defined as a group III-V compound semiconductor, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Furthermore, the entire substrate 108 or a portion thereof may be subjected to strain.

[0020] Insulating materials can be formed at different locations within the substrate 108 to electrically isolate the active structures within the device layer 102 from each other. For example, such as Figure 1 As shown, a plurality of shallow trench isolation regions 110 can be formed within the substrate 108 to a predetermined depth. Any known method (e.g., forming trenches within the substrate 108, depositing a dielectric insulator (e.g., oxide) and polishing the deposited dielectric material) can be used to form the isolation regions 110 to the predetermined depth.

[0021] Embodiments of this disclosure may include introducing dopant into substrate 108 at selected locations. Substrate 108 may include light doping, for example, by pre-doping during fabrication or before forming isolation regions 110 therein. Where applicable, substrate 108 may be pre-doped with p-type or n-type dopant. With isolation regions 110 in place, portions of substrate 108 may be doped (e.g., by implanting dopant ions in a vertical direction) to form a set of active semiconductor regions 112 within substrate 108. The dopant used to form the active semiconductor regions 112 can significantly reduce the resistivity of the semiconductor material at the locations in substrate 108 where the dopant has been introduced. At this stage, isolation regions 110 and portions of substrate 108 may be covered with a photoresist material layer (not shown) to prevent non-target areas of substrate 108 from being doped. Portions of substrate 108 beneath isolation regions 110 and active semiconductor regions 112 may remain undoped or only lightly doped, thus substantially maintaining their doping as defined by substrate 108. After the active semiconductor region 112 is formed, any photoresist material used to form the active semiconductor region 112 can be removed by ashing or any other photoresist stripping method known in the art. In an example of forming a transistor on the substrate 108, each active semiconductor region 112 may define a source region or a drain region of a transistor in the device layer 102.

[0022] Device layer 102 may include active components located on substrate 108 and within device layer 102 in the form of at least a first device 122 and a second device 124. Each device 122, 124 may take the form of one or more active electrical elements located above and / or coupled to the active semiconductor region 112, such as field-effect transistors (FETs) or NPN transistors, as known in the art. Devices 122, 124 are illustrated in the figures as FETs by way of example, having some sub-components located above the active semiconductor region 112, but this is not required in all cases. As discussed herein, the first device 122 and / or the second device 124 may take the form of transistors or other active elements to be coupled to and / or isolated from other devices and / or elements located elsewhere within structure 100.

[0023] According to various examples, devices 122, 124 may take the form of a bipolar junction transistor (BJT), a metal-oxide-semiconductor (MOS) field-effect transistor (MOSFET), a lightly doped drain MOS (LDMOS), a diode, a capacitor, or any active or passive device known in the art. In other embodiments, devices 122, 124 may include, for example, one or more capacitors, resistors, inductors, diodes, etc., for implementing various electrical functions. In any case, devices 122, 124 may be horizontally distanced from each other across substrate 108 and / or separated by isolation region 110. As used herein, the term "horizontally distanced" means that one element is horizontally displaced relative to another element and separated from the other element by at least one other intermediate element. In this case, devices 122, 124 may be horizontally distanced from each other because portions of active semiconductor region 112, isolation region 110, and / or substrate 108 horizontally separate devices 122, 124 from each other.

[0024] As described herein, embodiments of this disclosure may include forming structure 100 substantially according to conventional methods to include a first device 122 and a second device 124 in an active layer 102 prior to further processing of structure 100. This method may include forming a LI layer 104. The LI layer 104 of the initial structure 100 may include, for example, a barrier film 126 for vertically isolating the overlying material from the underlying device layer 102. The barrier film 126 may include one or more electrically insulating materials having particularly high etch resistance. More specifically, the barrier film 126 may be formed as an “etch stop layer” configured to prevent the underlying device components from being removed or modified in subsequent processing. Thus, the barrier film 126 may, for example, include a nitrogen-doped silicon carbide (SiCN) layer or other materials with similar properties. The barrier film 126 may be formed after the formation and processing of device layer 102 are complete. In the case of conformal deposition, the barrier film 126 may also be formed on the upper surfaces and sidewalls 126A of the first device 122 and the second device 124. With the barrier film 126 in the proper position, subsequent processing can form additional conductive and insulating portions of the metal wiring layer 106 and the L1 layer 104.

[0025] Etching generally refers to the removal of material from a substrate (or a structure formed on a substrate), and is typically performed using patterned materials (e.g., one or more masks) at appropriate locations to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using solvents (e.g., acids) and has the ability to selectively dissolve a given material (e.g., oxides) while leaving another material (e.g., polycrystalline silicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged high-energy free radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching involves bombarding a wafer with high-energy ions of a rare gas. These high-energy ions approach the wafer from roughly one direction, making the process highly anisotropic. As discussed herein with respect to other figures and more generally to the various elements in structure 100, reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to produce deep, narrow features suitable for forming similar elements, such as openings at target locations.

[0026] The LI layer 104 may further include a first dielectric material 128, such as one or more oxide-based dielectric materials suitable for physically and electrically isolating various regions of the conductive material in the LI layer 104. Other types of oxide-based or nitride-based dielectric materials may also be suitable for distinguishing it from other dielectric materials, as discussed elsewhere herein. The first dielectric material 128 may include, but is not limited to: silicon dioxide-based dielectric materials, such as SiO2; doped oxides, such as phosphosilicate glass (PSG), borosilicate glass (BPSG); fluorinated silicate glass (FSG); or carbon-containing oxides, such as SiCOH. Dielectric materials formed by spin coating or CVD may be used additionally or alternatively. Regardless of the materials included therein, the first dielectric material 128 may have a higher first effective dielectric constant than other subsequently formed dielectric materials within the LI layer 104. Some portions of the first dielectric material 128 may be replaced with the subsequently formed materials, as discussed elsewhere herein. In the example setup, the first dielectric material 128 may have an effective dielectric constant between about 3 and 4. The composition of the first dielectric material 128 can be selected to hermetically seal the first device 122 located below it. In such an example, the first dielectric material 128 may include BPSG and / or similar materials and will have an effective dielectric constant of approximately 4.

[0027] A portion of layer 104 may include a conductor in the form of contact 130 (e.g., Figure 1 Four such contacts (shown in the diagram) are used to electrically couple portions of devices 122, 124 to other wiring layers located above layer 104. Contact 130 may include a set of first contacts 130a to the active semiconductor region 112 of the first device 122, and a set of second contacts 130b to the active semiconductor region 112 of the second device 124. Contact 130 may include any conductive material now known or developed later capable of forming a conductive path between multiple electroactive elements. As an example, contact 130 may include any and / or all conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), etc. Therefore, the first contacts 130a and the second contacts 130b are structurally and compositionally indistinguishable except with respect to the devices 122, 124 coupled to them. Each contact 130 may include a barrier liner 132 adjacent to the dielectric material 128 on its sidewalls.

[0028] The barrier liner 132 may comprise any barrier liner material now known or developed hereafter (e.g., a refractory metal liner), including but not limited to: tantalum nitride (TaN) and tantalum; tantalum nitride, tantalum, and cobalt; and magnesium (Mn) or combinations thereof. Similar liners may also be formed on the sidewalls of other conductive materials described herein. For example, the contact 130 may be formed by depositing conductive material within a trench in the first dielectric material 128. Such trenches within the first dielectric material 128 may be formed by forming a mask (not shown) on the first dielectric material 128 to form openings at locations where the contact 130 is desired. The barrier liner 132 may be formed in the first dielectric material 128 on the exposed surfaces and sidewalls within the formed openings. Where applicable, portions of the barrier liner 132 may be removed (e.g., by selective etching) to expose the underlying active semiconductor material 112 for silanization and / or formation of the contact 130 thereon.

[0029] The vertical conductive material of contact 130 can be formed, for example, by deposition after the barrier liner 132 is in place. The first contact 130a can be formed together with the second contact 130b, or separately. Forming material by “deposition” or “deposition” can generally include any technique now known or later developed suitable for the material to be deposited, including but not limited to: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), subatmospheric pressure CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), finite reaction process CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

[0030] To vertically separate the LI layer 104 from the metal wiring layer formed thereon and to provide an etch stop layer for the damascene wiring formed in layer 106, an additional dielectric barrier film 134 may be formed on the upper surfaces of the first dielectric material 128 and the contact 130. The additional barrier film 134 may comprise the same material as the barrier film 126 (e.g., a nitride-based layer, an etch stop layer, such as SiN, SiC, or SiCN), and / or may comprise a different material with similar properties. In some cases, the additional barrier film 134 may be omitted. When the additional barrier film 134 is formed, portions of the metal wiring layer 106 may be formed on the additional barrier film 134.

[0031] Structure 100 may include portions of a metal wiring layer 106 located on device layer 102 and / or L1 layer 104, while other portions of the metal wiring layer 106 may be formed in subsequent processing stages as discussed herein. Therefore, embodiments of the present disclosure may be implemented before, during, or after the formation of the metal wiring layer 106 on L1 layer 104. According to an example, the formation of the metal wiring layer 106 may include forming an interlayer dielectric (ILD) material 136 over L1 layer 104, specifically on an additional barrier film 134. The ILD material 136 may have the same material composition as the first dielectric material 128, and / or may include any other possible dielectric material, such as a low-k dielectric material. The ILD material 136 may have sufficient thickness to electrically isolate the conductive materials within the metal wiring layer 106 from device layer 102 and L1 layer 104 when they are not coupled to the corresponding elements in layers 102, 104. The size and composition of the ILD material 136 can also be selected to physically and electrically isolate the conductive material within the metal wiring layer 106 from the overlying conductive material.

[0032] Metal wiring layer 106 may be formed to include additional conductive material for bonding portions of device layer 102 to other metal wiring layers and / or other materials within device layer 102. For example, metal wiring layer 106 may include a set of metal wirings 138 located above I1 layer 104. Metal wirings 138 may include tungsten (W), or alternatively, other refractory materials and / or any other materials now known or later developed suitable for use as capacitor electrodes, such as aluminum (Al), tantalum (Ta), silver (Ag), etc. Metal wirings 138 may include additional portions of barrier liner 132, and these portions may also be formed prior to the formation of metal wirings 138 on portions of additional barrier film 134, ILD material 136, etc., to perform the same function described relative to contact 130. Although metal wirings 138 are exemplarily shown as located below the top of ILD material 136, metal wirings 138 may extend laterally into or out of ILD material 136. Figure 1 The page showing the cross-sectional view. In some cases, a diffusion barrier layer 140 may be formed on the metal wiring 138. The diffusion barrier layer 140 can protect the metal wiring 138 from diffusion of overlying metal (e.g., via) material into the metal wiring 138, and in some cases, also prevent vertical modifications (e.g., etching) to the metal wiring 138 in subsequent processing. In this case, the diffusion barrier layer 140 may comprise cobalt tungsten phosphide (CoWP), or any diffusion barrier material now known or developed later. As discussed herein, additional wiring, vias, etc., may be formed within the metal wiring layer 106 after further processing layers 102, 104, 106.

[0033] Turn Figure 2 Embodiments of this disclosure include removing portions of first and second dielectric materials 128, 136 at selected locations. For example, a second device 124 may be part of a circuit in which an overlying dielectric material having a second, relatively low effective dielectric constant can improve the functionality of its underlying layer. In this case, portions of the first and second dielectric materials 128, 136 located on the second device 124 may be targeted for replacement with other, different dielectric materials. In contrast, the first device 122 may be configured for use with the first dielectric material 128. Embodiments of this disclosure may allow the first dielectric material 128 to be replaced by other materials over the second device 124 while remaining intact over the first device 122. In some embodiments, the first dielectric layer 128 is removed prior to the formation of the second dielectric layer 136.

[0034] The method according to this disclosure may include removing selected portions of the first dielectric material 128 and the additional barrier film 134 and ILD material 136 thereon for replacement with another dielectric material. Reactive ion etching (RIE) of the ILD material 138 using a mask 142 is a suitable technique for forming the opening 144. The opening 144 can expose the second device 124 of the device layer 102, thereby forming an empty space in which an alternative dielectric material for use above the second device 124 can be formed. The mask 142 can therefore be configured such that the opening 144 is at least partially above the second device 124 and thus substantially vertically aligned with the second device 124. Alternatively, the mask 142 can be shaped to prevent the opening 144 from forming above the first device 122. The remaining portion of the first dielectric material 128 located below the metal wiring 138 and across the barrier liner 132 and / or the second contact 130b can remain intact as the dielectric liner 146. The dielectric liner 146 may have a higher effective dielectric constant than the dielectric material subsequently formed within the opening 144, and may remain intact as a result of forming the opening 144 by RIE or other vertical etching techniques. The dielectric liner 146 may be removed during etching. In one embodiment, the dielectric liner 146 is removed using wet etching (e.g., HF acid).

[0035] Figure 3The diagram illustrates the formation of a second dielectric material, such as any dielectric material having a second effective dielectric constant less than that of the first dielectric material 128 or the first and second dielectric materials 128, 136. The second dielectric material 150 may comprise any of several oxide-based or nitride-based dielectric materials, and in particular may comprise materials exhibiting an effective dielectric constant less than that of BPSG, SiO2, and / or similar materials. Such materials may include, for example, SiCOH insulators, carbon-doped oxides, spin-coated polymers, and / or other materials with similar properties. In the example setup, the second effective dielectric constant of the dielectric filler may be at most about 3. The second dielectric material 150 may be formed within the opening by deposition and subsequent planarization, such that the top of the second dielectric material 150 covers a portion of the adjacent ILD material 136. Planarization of the second dielectric material 150 may be achieved by chemical mechanical planarization (CMP) or other techniques for removing portions of the dielectric material to the desired depth (e.g., various types of controlled etching, such as reverse mask etch-back).

[0036] The second dielectric material 150 can extend vertically from the second device 124 over the diffusion barrier layer 140. Therefore, the second dielectric material 150 can be partially located within the L1 layer 104 and the metal wiring layer 106, and thus horizontally adjacent to the first dielectric material 128 and the ILD material 136. Furthermore, conductors such as contacts 130 (e.g., second contact 130b) and / or metal wiring 138 can be positioned within the second dielectric material 150. Thus, the second dielectric material 150 can take the form of a vertically extending dielectric pillar extending through the L1 layer 104 and the metal wiring layer 106. In the form of a dielectric pillar, the second dielectric material 150 can be horizontally adjacent to each of the first dielectric material 128, the barrier film 134, and the ILD material 136. Pre-targeted etching of the first dielectric material 128 and the additional barrier film 134 can allow the second dielectric material 150 to extend vertically through the L1 layer 104 and the metal wiring layer 106. Therefore, the additional barrier film 134 may not be present within the second dielectric material 150, and may not be above the second device 124.

[0037] Figure 4Further processing is illustrated in the formation of an additional portion of the metal wiring layer 106 according to an embodiment of the present disclosure, thereby producing an IC structure 152. The height H1 of the first dielectric material 128 above the upper surface J of the device layer 102 is substantially less than the height H2 of the second dielectric material 150 above the upper surface J of the device layer 102. In some implementations, the height H2 is approximately twice the height H1. In another example, the difference between height H1 and height H2 is approximately 1 micrometer. Therefore, the metal wiring layer 106 may include a portion of the second dielectric material 150, while also including the ILD material 136. Figure 5 Additional portions of the metal wiring layer 106 shown may be formed after the processing of the second dielectric material 150 is completed and substantially according to known techniques for forming such layers. For example, selected portions of the ILD material 136 and / or the second dielectric material 150 may be removed to form openings, and the openings may be filled with a conductive material to create a set of vias 154.

[0038] Via 154 can be formed of any conductive material and therefore can have the same composition as the contact 130 and metal wiring 138 below it. Via 154 may have additional areas of barrier liner 132 formed on its sidewalls, as described elsewhere herein. Via 154 may optionally be formed within the ILD material 136 above the first device 122 and within the second dielectric material 150 above the second device 124 before portions of the first dielectric material 128 and ILD material above the second device 124 are replaced by the second dielectric material 150.

[0039] Subsequent processing of the metal wiring layer 106 may include, for example, forming an additional ILD material layer 156 to a desired height over the ILD material 136. Although the additional ILD material 156 is indicated as different from the ILD material 136 for illustrative purposes, the additional ILD material 156 may have the same composition as the ILD material 136. In some implementations, there is no visible physical interface between the ILD materials 136 and 156. The thickness of the additional ILD material 156 over the ILD material 136 may be sufficient to form a set of additional metal wirings 158 within the additional ILD material 156. In this case, a portion of the additional ILD material 156 may be removed and replaced with additional metal wirings 158 and a barrier liner 132 in substantially the same manner as forming the metal wirings 138 within the ILD material 136. Regardless of whether additional ILD material 156 and / or additional metal wiring 158 are formed, an overlay barrier film 160 may be formed on the top surface of the metal wiring layer 106 to physically and electrically isolate components within the metal wiring layer 106 from the overlay or overlay element. The overlay barrier film 160 may have the same composition as barrier film 126 and / or additional barrier film 134 (e.g., silicon nitride), and / or may have other insulating or etch-resistant compositions (e.g., nitrogen-doped silicon carbide).

[0040] Figure 5 Other implementations of IC structure 152 are shown, wherein the second dielectric material 150 includes a gas gap or gas dielectric region 162. In this case, the structure and processing of IC structure 152 can be substantially the same as other implementations described herein, except for the techniques used to form the second dielectric material 150. The gas dielectric region 162 can be formed by any techniques now known or developed hereafter for dielectric gas gap integration. Such techniques may include, for example, forming one or more sacrificial evaporable materials within the second dielectric material 150 and subsequently evaporating the sacrificial material through pores in the second dielectric material 150. In other examples, the gas dielectric region 162 may refer to an inherently porous region in the case where the second dielectric material 150 includes a porous dielectric material (e.g., SiCOH).

[0041] Figure 6Other optional features of the IC structure 152 are shown, in which a set of nitride liners 164 can be formed transversely to the second dielectric material 150. The gas dielectric region 162 is shown in dashed lines to indicate that it can also be used in other implementations. To form the nitride liners 164, a portion of the barrier film 126 above the second device 124 can be removed and then replaced in the same location with the nitride liners 164 before forming the second dielectric material 150. The nitride liners 164 can be formed by conformal deposition. In this case, a portion of the nitride liners can be horizontally adjacent to the first dielectric material 128, the additional barrier film 134, and / or the ILD material 136. The formation of the nitride liners 164 helps to thermally and electrically isolate the second device 124 and the second dielectric material 150 above it from the first device 122 and the first dielectric material 128.

[0042] Figure 7 An IC structure 152 is shown, in which an alternative configuration of a second dielectric material 150 protrudes vertically into the device layer 102. A gas dielectric region 162 and a nitride liner 164 are present. Figure 7 The dashed lines indicate that such elements may be optionally used in this implementation. In this case, when a portion of the first dielectric material 128 is removed from a location above the second device 124, a portion of the isolation region 110 and / or the substrate 108 may be removed to form an opening. The opening can then be filled with the second dielectric material 150, as described elsewhere herein. Thus, the second dielectric material 150 may optionally include a first portion 150a located within the device layer 102 and below the bottom surface J of the first dielectric material 128. A second portion 150b of the second dielectric material may be horizontally adjacent to the first dielectric material 128 and, optionally, may be horizontally spaced from the first dielectric material 128 by a nitride liner 164, as described herein. The presence of the first portion 150a, which lies horizontally against the second device 124, allows for, for example, higher thermal conductivity in the vicinity of the second device 124, where the second dielectric material 150 has a higher thermal conductivity than the first dielectric material 128. Higher thermal conductivity may be preferred, for example, where the second device 124 forms a portion of a power amplifier circuit.

[0043] The embodiments of this disclosure provide various technical and commercial advantages, and some examples of these advantages are discussed herein. Embodiments of this disclosure allow selected active components (e.g., first device 122) in device layer 102 to be hermetically sealed with conventional dielectric materials, while allowing other active components (e.g., second device 124) to be surrounded by different dielectric materials having lower dielectric constants and / or higher thermal conductivity. The ability to form the second dielectric material 150 before or during the formation of the metal wiring layer 106 allows for the integration of multiple dielectric materials 128, 150 into a single manufacturing process. Furthermore, portions of the first dielectric material 128 can be intentionally kept intact as dielectric liner 146 against contact 130 to provide stronger electrical isolation at locations where the second dielectric material 150, having a lower effective dielectric constant, is present. These and other technical aspects of this disclosure allow for the close proximity formation of different types of devices with different technical considerations on a single substrate; for example, low-noise power amplifiers and / or switching circuits can be formed near other types of devices.

[0044] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0046] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0047] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. An integrated circuit (IC) structure, comprising: A device layer comprising a device located on a substrate, wherein the device includes a first end opposite to the second end; as well as A local interconnect layer located above the device layer, the local interconnect layer comprising: A first dielectric material located above the substrate and having a first effective dielectric constant, and A second dielectric material located above the device and adjacent to the first dielectric material, the second dielectric material having a second effective dielectric constant that is smaller than the first effective dielectric constant. The second dielectric material comprises a first portion and a second portion, the first portion having a depth extending into the substrate and passing over the first and second ends of the device, and the second portion being a dielectric pillar.

2. The IC structure according to claim 1 further includes a dielectric liner located horizontally between the conductor and the second dielectric material. The conductor is located within the second portion of the second dielectric material and is connected to the device. The dielectric liner and the first dielectric material have the same material composition.

3. The IC structure according to claim 1, wherein the second effective dielectric constant is about 3.

4. The IC structure according to claim 3, wherein the first effective dielectric constant is between about 3 and about 4.

5. The IC structure according to claim 1, further comprising: A conductor located in the second dielectric material and connected to the device; as well as A diffusion barrier layer located on the conductor and within the second dielectric material.

6. The IC structure according to claim 1 further includes a gas dielectric region located within the second portion of the second dielectric material.

7. The IC structure of claim 1 further includes a nitride liner located in the horizontal direction between the second portion of the first dielectric material and the second dielectric material.

8. The IC structure according to claim 1, wherein, The second portion is horizontally adjacent to the first dielectric material.

9. The IC structure according to claim 1, wherein the height of the second dielectric material above the device is greater than the height of the first dielectric material above the substrate.

10. The IC structure of claim 1, further comprising a metal wiring layer located above the local interconnect layer, the metal wiring layer comprising: A conductor that is connected to the device and located within the second portion of the second dielectric material; A via located above the conductor and within the second portion of the second dielectric material; as well as Metal wiring located above the via and within a portion of the first dielectric material above the second dielectric material, wherein the conductor electrically couples the device to the metal wiring above the local interconnect layer.

11. An integrated circuit (IC) structure, comprising: A device layer comprising a first device located on a substrate and a second device located on the substrate horizontally away from the first device; A local interconnect layer located above the device layer, the local interconnect layer comprising: A first dielectric material located above the first device and having a first effective dielectric constant. The first contact is located within the first dielectric material and is connected to the first device. A second dielectric material located above the second device and adjacent to the first dielectric material, the second dielectric material having a second effective dielectric constant smaller than the first effective dielectric constant, and The second contact is located within the second dielectric material and connected to the second device; and the gas dielectric region is located within the second dielectric material.

12. The IC structure of claim 11, wherein the first dielectric material comprises a silicon dioxide (SiO2) based insulator that rests across the first contact.

13. The IC structure according to claim 12, wherein the second dielectric material comprises a SiCOH insulator.

14. The IC structure of claim 11, wherein the height of the second dielectric material above the second device is greater than the height of the first dielectric material above the first device.

15. The IC structure according to claim 11, wherein, The first dielectric material defines an airtight seal above the first device.

16. A method for forming an integrated circuit (IC) structure, the method comprising: A first dielectric material is formed on a conductor above a first device and a second device in the device layer and across the second device, wherein the first dielectric material has a first effective dielectric constant; An opening is formed within a portion of the first dielectric material to expose the second device, wherein the opening is transverse to the conductor; A second dielectric material is formed within the opening, resting against the first dielectric material and the conductor, the second dielectric material having a second effective dielectric constant less than the first effective dielectric constant; and A gaseous dielectric region is formed within the second dielectric material.

17. The method of claim 16, further comprising forming a nitride liner located horizontally between the first dielectric material and the second dielectric material.

18. The method of claim 16, wherein the first dielectric material is formed to hermetically seal the first device.

19. The method of claim 16, wherein forming the second dielectric material within the opening comprises forming the second dielectric material to have a height above the second device, the height being greater than the height of the first dielectric material above the first device.

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