Semiconductor memory devices

Abstract

The semiconductor memory device of the present invention includes a semiconductor substrate. The semiconductor substrate includes a memory cell array region, an edge sealing region, and a connection region disposed therebetween. The memory cell array region includes: a plurality of first conductive layers arranged along a first direction; a first semiconductor layer facing the plurality of first conductive layers; and a second semiconductor layer connected to the first semiconductor layers. The edge sealing region includes: a third semiconductor layer and a fourth semiconductor layer arranged along the first direction, and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The connection region includes a fifth semiconductor layer and a sixth semiconductor layer continuously formed with the second semiconductor layer and the third semiconductor layer or the fourth semiconductor layer and extending in a second direction. The connection region includes a plurality of connection portions arranged along the second direction. Among these plurality of connection portions, the fifth semiconductor layer and the sixth semiconductor layer are electrically connected.

Description

[0001] Citation of relevant applications

[0002] This application is based on and asserts the priority of Japanese Patent Application No. 2021-020265, filed on February 10, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a semiconductor substrate; a plurality of first conductive layers arranged along a first direction intersecting the surface of the semiconductor substrate; a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers; and a second semiconductor layer disposed between the plurality of first conductive layers and the semiconductor substrate and connected to one end of the first semiconductor layer in the first direction. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device that can be suitably manufactured.

[0006] A semiconductor memory device according to one embodiment includes a semiconductor substrate. The semiconductor substrate includes a memory cell array region, an edge sealing region, and a connection region disposed between the memory cell array region and the edge sealing region. Furthermore, the semiconductor memory device includes a plurality of first conductive layers, a first semiconductor layer, and a second semiconductor layer disposed in the memory cell array region. The plurality of first conductive layers are arranged along a first direction intersecting the surface of the semiconductor substrate. The first semiconductor layer extends in the first direction and faces the plurality of first conductive layers. A second semiconductor layer is disposed between the plurality of first conductive layers and the semiconductor layer, and is connected to the first semiconductor layer. Furthermore, the semiconductor memory device includes a third semiconductor layer, a fourth semiconductor layer, and a second conductive layer disposed in the edge sealing region. The third and fourth semiconductor layers are arranged along the first direction. The second conductive layer is electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. Furthermore, the semiconductor memory device includes a fifth semiconductor layer and a sixth semiconductor layer disposed in the connection region. The fifth semiconductor layer extends in a second direction intersecting the first direction. Furthermore, the fifth semiconductor layer has a portion continuously formed with the second semiconductor layer and a portion continuously formed with the third semiconductor layer. The sixth semiconductor layer extends in the second direction. Furthermore, the sixth semiconductor layer has portions continuously formed with the second semiconductor layer and portions continuously formed with the fourth semiconductor layer. Additionally, the connection region includes a plurality of first regions and second regions alternately arranged along the second direction. In the plurality of first regions, the fifth and sixth semiconductor layers are separated in the first direction. In the plurality of second regions, the fifth and sixth semiconductor layers are electrically connected.

[0007] Based on the aforementioned configuration, a semiconductor memory device that can be appropriately manufactured can be provided. Attached Figure Description

[0008] Figure 1 This is a schematic circuit diagram showing the configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a schematic top view of the semiconductor memory device.

[0010] Figure 3 yes Figure 2 A schematic enlarged view of a portion.

[0011] Figure 4 yes Figure 2 A schematic enlarged view of a portion.

[0012] Figure 5 This is a schematic cross-sectional view of the semiconductor memory device.

[0013] Figure 6 This is a schematic cross-sectional view of the semiconductor memory device.

[0014] Figure 7 yes Figure 5 A schematic enlarged view of the part shown in D.

[0015] Figure 8 yes Figure 7 A schematic enlarged view of the part shown in E.

[0016] Figure 9 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0017] Figure 10 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0018] Figure 11 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0019] Figure 12 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 13 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 14 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 15 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0023] Figure 16 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 17 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 18 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 19 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 20 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 21 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 22 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 23 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 24 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 25 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 26 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 27 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0035] Figure 28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 29 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 30 This is a schematic top view showing the configuration of the semiconductor memory device of the first comparative example.

[0038] Figure 31 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0039] Figure 32 This is a schematic top view showing the configuration of the semiconductor memory device of the second comparative example.

[0040] Figure 33 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0041] Figure 34 This is a schematic top view showing the configuration of the semiconductor memory device according to the second embodiment.

[0042] Figure 35 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0043] Figure 36 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device.

[0044] Figure 37 This is a schematic top view showing the configuration of the semiconductor memory device according to the third embodiment.

[0045] Figure 38 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0046] Figure 39 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device.

[0047] Figure 40 This is a schematic top view showing the configuration of the semiconductor memory device according to the fourth embodiment.

[0048] Figure 41 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0049] Figure 42 This is a schematic top view showing the configuration of the semiconductor memory device according to the fifth embodiment.

[0050] Figure 43 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0051] Figure 44 This is a schematic top view showing the configuration of the semiconductor memory device according to the sixth embodiment.

[0052] Figure 45 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device.

[0053] Figure 46 This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to a variation of the fourth embodiment. Detailed Implementation

[0054] Next, with reference to the accompanying drawings, the semiconductor memory device according to the embodiments will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and some components may be omitted for ease of explanation. Furthermore, common parts in multiple embodiments may be labeled with the same reference numerals, and descriptions may be omitted.

[0055] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes refers to a memory die, and sometimes to a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0056] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0057] Furthermore, in this specification, when it is mentioned that the first component is "connected between" the second and third components, it is intended to mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0058] Furthermore, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0059] Furthermore, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction intersecting the first direction along the specific surface is referred to as the second direction, and the direction intersecting the specific surface is referred to as the third direction. These first, second, and third directions may or may not correspond to any one of the X, Y, and Z directions.

[0060] Furthermore, in this specification, terms such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when a component is referred to as a lower surface or lower end, it means the surface or end of the component on the substrate side; when referred to as an upper surface or upper end, it means the surface or end of the component opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0061] Furthermore, in this specification, when referring to components, parts, etc., terms such as "width," "length," or "thickness" in a specific direction are used, they sometimes mean the width, length, or thickness observed in the cross-section of the conductor by means of SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0062] [First Implementation] Figure 1 This is a schematic circuit diagram showing the configuration of the memory die MD according to the first embodiment.

[0063] The memory die MD has a memory cell array (MCA) and peripheral circuitry (PC).

[0064] The memory cell array (MCA) comprises multiple memory blocks (BLK). Each of these memory blocks (BLK) comprises multiple string cells (SU). Each of these string cells (SU) comprises multiple memory strings (MS). One end of each of these memory strings (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). Furthermore, the other end of each of these memory strings (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0065] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs), a source-side select transistor (STS), and a source-side select transistor (STSb). The STD, MCs, STS, and STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the STD, STS, and STSb are sometimes simply referred to as the select transistors (STD, STS, STSb).

[0066] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge accumulation film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. The memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to a memory string MS. These word lines WL are collectively connected to all memory strings MS in a memory block BLK.

[0067] The select transistors (STD, STS, STSb) are field-effect transistors. Each select transistor (STD, STS, STSb) has a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS, SGSb) are connected to the gate electrodes of the select transistors (STD, STS, STSb). One drain-side select gate line SGD connects to all memory strings MS in a single string cell SU. One source-side select gate line SGS connects to all memory strings MS in a single memory block BLK. One source-side select gate line SGSb connects to all memory strings MS in a single memory block BLK.

[0068] The peripheral circuit PC includes, for example: a voltage generation circuit that generates an operating voltage; a voltage transmission circuit that transmits the generated operating voltage to the selected bit line BL, word line WL, source line SL, selected gate line (SGD, SGS, SGSb), etc.; a sense amplifier module connected to the bit line BL; and a sequence generator that controls these components.

[0069] [Construction of Memory Die (MD)] Figure 2 This is a schematic top view of a memory die (MD). Figure 3 and Figure 4 yes Figure 2 A schematic enlarged view of a portion. Figure 5 and Figure 6 This is a schematic cross-sectional view of a memory die (MD). Additionally, Figure 5 Includes Figure 3 The structure shown is a schematic cross-section cut along line A-A', viewed in the direction of the arrow. Furthermore, Figure 5 Includes Figure 4 The structure shown is a schematic cross-section viewed in the direction of the arrow, cut along line B-B'. Furthermore, Figure 6 Includes Figure 3 The structure shown is a schematic cross-section cut along line A-A', viewed in the direction of the arrow. Furthermore, Figure 6 Includes Figure 4 The structure shown is a schematic cross-section cut along line C-C' and viewed in the direction of the arrow. Figure 7 yes Figure 5 A schematic enlarged view of the part shown in D. Figure 8 yes Figure 7 A schematic enlarged view of the part shown in E.

[0070] For example, memory die MD Figure 2 As shown, a semiconductor substrate 100 is provided. In the example shown, four memory cell array regions R arranged along the X and Y directions are formed on the semiconductor substrate 100. MCAFurthermore, edge sealing regions R are provided at the ends of the semiconductor substrate 100 in the X and Y directions. E Edge sealing area R E It includes: a portion extending in the Y direction from an end of the semiconductor substrate 100 in the X direction; and a portion extending in the X direction from an end of the semiconductor substrate 100 in the Y direction. Furthermore, in each memory cell array region R... MCA With edge sealing area R E At least one connection area R is set in between. C .

[0071] For example, memory die MD Figure 5 As shown, it includes: a semiconductor substrate 100; and a transistor layer L. TR The wiring layer D0 is disposed on the semiconductor substrate 100; the transistor layer L is disposed on the transistor layer L. TR Above; wiring layer D1, positioned above wiring layer D0; wiring layer D2, positioned above wiring layer D1; and memory cell array layer L. MCA It is positioned above the wiring layer D2.

[0072] [Semiconductor substrate 100 structure] The semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si) with P-type impurities such as boron (B). For example, Figure 5 As shown, an active region 100A and an insulating region 100I are disposed on the surface of a semiconductor substrate 100. The active region 100A may be an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), or a semiconductor substrate region in which neither an N-type well region nor a P-type well region is disposed.

[0073] [Transistor layer L] TR [Construction] For example, as Figure 5 As shown, a wiring layer GC is disposed on the upper surface of the semiconductor substrate 100, separated by an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc contained in the wiring layer GC are respectively connected to a contact CS.

[0074] The active region 100A of the semiconductor substrate 100 functions as a channel region for multiple transistors Tr that constitute the peripheral circuit PC, and as an electrode for multiple capacitors, etc.

[0075] The multiple electrodes gc contained in the wiring layer GC serve as the components of the peripheral circuit PC. Figure 1 The gate electrodes of multiple transistors Tr and the other electrodes of multiple capacitors function as transistors.

[0076] The contact CS extends in the Z direction and its lower end is connected to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact CS and the semiconductor substrate 100. The contact CS may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W).

[0077] [Construction of wiring layers D0, D1, D2] For example, Figure 5 As shown, the wiring layers D0, D1, and D2 contain multiple wirings that are electrically connected to at least one of the configurations in the memory cell array MCA and the peripheral circuit PC.

[0078] The wiring layers D0, D1, and D2 each contain multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may also contain stacked films of metals such as titanium nitride (TiN) barrier conductive films and tungsten (W).

[0079] [Storage cell array layer L] MCA [Construction] Next, for the memory cell array layer L MCA The structure will be explained.

[0080] [Storage cell array region R] MCA [Construction] For example, as Figure 2 As shown, in the storage cell array region R MCA This configuration includes multiple memory blocks (BLKs) arranged along the Y direction. For example, a memory block (BLK) might be... Figure 3 As shown, the device comprises multiple string cells SU arranged along the Y direction. An inter-block structure ST, such as silicon oxide (SiO2), is provided between two adjacent memory blocks BLK in the Y direction. Furthermore, an inter-string cell insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string cells SU in the Y direction.

[0081] Memory block BLK, for example Figure 7 The device includes: a plurality of conductive layers 110 arranged in the Z direction; a plurality of semiconductor layers 120 extending in the Z direction; and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0082] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0083] Below the conductive layer 110, a semiconductor layer 150 is disposed. The semiconductor layer 150 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the semiconductor layer 150 and the conductive layer 110.

[0084] Semiconductor layer 150 serves as the source line SL ( Figure 1 ) to perform its function. For example, for the memory cell array region R MCA ( Figure 2 All memory blocks BLK contained therein share a common source line SL.

[0085] Furthermore, among the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as source-side selected gate lines SGS, SGSb ( Figure 1 The gate electrodes of the multiple source-side selection transistors STS and STSb connected thereto function as well. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0086] Furthermore, multiple conductive layers 110 located above it serve as word lines WL ( Figure 1 ) and multiple storage units MC connected to it Figure 1 The gate electrode of the memory block BLK functions. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0087] Furthermore, one or more conductive layers 110 located above it serve as drain-side selected gate lines SGD and multiple drain-side selected transistors STD connected thereto. Figure 1 The gate electrode of the conductive layer 110 functions as a series cell. The width of these conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110. Furthermore, an inter-cell insulating layer SHE is disposed between two adjacent conductive layers 110 in the Y direction. Each of these conductive layers 110 is electrically independent within each series cell SU.

[0088] Semiconductor layer 120, for example Figure 3 As shown, the semiconductor layer 120 is arranged in a specific pattern in the X and Y directions. The semiconductor layer 120 serves as a memory string (MS). Figure 1 The multiple memory cells MC and the channel regions of the selection transistors (STD, STS, STSb) contained therein function. The semiconductor layer 120 is, for example, a polysilicon (Si) semiconductor layer. The semiconductor layer 120 is, for example, a... Figure 7 As shown, it has a generally bottomed cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central part. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110, which face each other.

[0089] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. Figure 7 In this example, the boundary line between the upper end of the semiconductor layer 120 and the lower end of the impurity region 121 is represented by a dashed line. The impurity region 121 is connected via junction Ch and junction Vy. Figure 5 ), connected to bit line BL.

[0090] The lower end of semiconductor layer 120 is connected to semiconductor layer 150.

[0091] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 is, for example, as shown in... Figure 8 As shown, a channel insulating film 131, a charge accumulation film 132, and a barrier insulating film 133 are deposited between the semiconductor layer 120 and the conductive layer 110. The channel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge accumulation film 132 is, for example, a film capable of accumulating charges such as silicon nitride (Si3N4). The channel insulating film 131, the charge accumulation film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, except for the contact portion between the semiconductor layer 120 and the semiconductor layer 150.

[0092] in addition, Figure 8 This example illustrates a gate insulating film 130 having a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0093] Inter-block construction ST, for example, Figure 7 As shown, the device includes a conductive layer LI and an insulating layer STSW, such as silicon oxide (SiO2), disposed on the Y-direction side of the conductive layer LI. The conductive layer LI is a generally plate-shaped conductive layer extending in the X and Z directions. The conductive layer 110 may include a multilayer film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The lower end of the conductive layer LI is connected to the semiconductor layer 150. The conductive layer LI serves as the source line SL (… Figure 1 It plays a part of the function.

[0094] [Edge sealing area R] E [Construction] as Figure 6 As shown, in the edge sealing area R EThe device comprises a semiconductor layer 161, an insulating layer 162 such as silicon nitride (Si3N4) disposed on the upper surface of the semiconductor layer 161, and a semiconductor layer 163 disposed on the upper surface of the insulating layer 162. The semiconductor layers 161 and 163 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B).

[0095] In addition, in the edge sealing area R E A conductive layer 164 is provided, extending in the Z direction through the semiconductor layer 161, the insulating layer 162, and the semiconductor layer 163. A portion of the outer peripheral surface of the conductive layer 164 is in contact with the semiconductor layers 161 and 163. The lower end of the conductive layer 164 is connected to wiring d2. The conductive layer 164 is connected to the active region 100A of the semiconductor substrate 100 via wirings d2, d1, d0 and contact CS.

[0096] In addition, such as Figure 6 As shown, in the edge sealing area R E A crack-stopping portion 180 is provided in the inner region of the substrate. The crack-stopping portion 180 may also comprise a multilayer film, such as a barrier conductive film like titanium nitride (TiN) or a metal film like tungsten (W). The lower end of the crack-stopping portion 180 is connected to wiring d2. The crack-stopping portion 180 is connected to the active region 100A of the semiconductor substrate 100 via wirings d2, d1, d0 and contact CS. Furthermore, although not shown in the figure, the upper end of the crack-stopping portion 180 is located above the bit line BL. The upper end of the crack-stopping portion 180 may also be connected, for example, to a contact electrode (not shown). Furthermore, the crack-stopping portion 180 may also be connected to a bonding pad electrode supplied with a ground voltage via the contact electrode, etc. The crack-stopping portion 180 seals the edge region R. E It extends in both the X and Y directions. However, for example, Figure 4 As shown, the crack-stopping part 180 avoids the connecting area R. C And configuration.

[0097] [Connection Area R] C [Construction] as Figure 5 As shown, in the connected region R C The device comprises a semiconductor layer 171, an insulating layer 172 such as silicon nitride (Si3N4) disposed on the upper surface of the semiconductor layer 171, and a semiconductor layer 173 disposed on the upper surface of the insulating layer 172. The semiconductor layers 171 and 173 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, Figure 5 In the diagram, the boundary line between semiconductor layer 171 and semiconductor layer 173 is represented by a dashed line. Semiconductor layer 171, insulating layer 172, and semiconductor layer 173 are as follows... Figure 4 As shown, it extends in the Y direction.

[0098] Semiconductor layer 171 has a portion continuously formed with semiconductor layer 150 and a portion continuously formed with semiconductor layer 161. The height position of the lower surface of semiconductor layer 171 may, for example, coincide with the height position of the lower surfaces of semiconductor layer 150 and semiconductor layer 161. Furthermore, for example, the height position of the upper surface of semiconductor layer 171 may coincide with the height position of the upper surface of semiconductor layer 161.

[0099] The insulating layer 172 has a portion that is continuously formed with the insulating layer 162. The height position of the lower surface of the insulating layer 172 may, for example, coincide with the height position of the lower surface of the insulating layer 162. Furthermore, for example, the height position of the upper surface of the insulating layer 172 may coincide with the height position of the upper surface of the insulating layer 162.

[0100] Semiconductor layer 173 includes a portion continuously formed with semiconductor layer 150 and a portion continuously formed with semiconductor layer 163. The height position of the lower surface of a portion of semiconductor layer 173 may, for example, coincide with the height position of the lower surface of semiconductor layer 163. Furthermore, for example, the height position of the upper surface of a portion of semiconductor layer 173 may coincide with the height position of the upper surfaces of semiconductor layers 150 and 163.

[0101] Furthermore, in the connecting region R C It is configured with multiple first regions 181 and second regions 182 arranged alternately in the Y direction.

[0102] Insulation layer 172 Figure 5 As shown, it has multiple portions 172a corresponding to multiple first regions 181, and multiple openings 172b corresponding to multiple second regions 182. Figure 4 As shown, the opening 172b reaches the end positions of the insulating layer 172 on one side and the other side in the X direction.

[0103] Semiconductor layer 173, etc. Figure 5 As shown, the device includes: multiple portions 173a corresponding to multiple first regions 181, multiple portions 173b corresponding to multiple second regions 182, and multiple portions 173c connecting these portions. Portions 173a are disposed on the upper surface of portion 172a. Portions 173b are disposed on the upper surface of semiconductor layer 171. Portions 173c are disposed on the side surface of portion 172a in the Y direction.

[0104] In addition, such as Figure 5 As shown, in the connected region R C ST is configured with a structure in which semiconductor layer 171, insulating layer 172 and semiconductor layer 173 are separated in the Y direction. C Constructing ST CIt is constructed in roughly the same way as the inter-block structure ST. However, the structure ST... C The semiconductor layer 171, insulating layer 172, and semiconductor layer 173 are connected. In other words, an ST structure is constructed. C The lower end is located below the lower surface of the semiconductor layer 171.

[0105] [Manufacturing Method] Next, refer to Figures 9 to 29 This describes the manufacturing method of the memory die (MD). Figures 9 to 29 This is a schematic cross-sectional view used to illustrate the manufacturing method. Additionally, Figures 9-11 , Figures 16-22 , Figure 24 , Figures 27-29 Indicates and Figure 5 The corresponding cross-section. Furthermore... Figures 12-15 Indicates and Figure 6 The corresponding cross-section. Furthermore... Figure 23 , Figure 25 and Figure 26 Indicates and Figure 7 The corresponding cross-section.

[0106] When manufacturing the memory die MD of this embodiment, for example, Figure 9 As shown, firstly, a transistor layer L is formed on the semiconductor substrate 100. TR Routing layer D0, routing layer D1 and routing layer D2.

[0107] Next, as Figure 9 As shown, semiconductor layers 151 and 171 and insulating layers 152 and 172 are formed above wiring layer D2. This step is performed using methods such as CVD (Chemical Vapor Deposition). Additionally, although not shown in the diagram, semiconductor layer 161 and insulating layer 162 are also formed in this step.

[0108] Next, for example, Figure 10 As shown, multiple openings 172b are formed in the insulating layer 172, dividing the insulating layer 172 into multiple portions 172a. This step is performed by methods such as wet etching.

[0109] Next, for example, Figure 11 As shown, semiconductor layers 153 and 173 are formed on the upper surfaces of insulating layers 152 and 172 and semiconductor layer 171, as well as on the side surfaces in the Y direction of a portion of 172a. This step is performed by methods such as CVD. Furthermore, as shown, semiconductor layer 173 is formed along multiple openings 172b formed in insulating layer 172. Therefore, in the connection region R... C The plurality of portions 173a, 173b, and 173c are formed. Furthermore, although not illustrated, a semiconductor layer 163 is also formed during this step.

[0110] Next, for example, Figure 12 and Figure 13 As shown, a contact hole 164A is formed at a position corresponding to the conductive layer 164. The contact hole 164A is a through-hole extending in the Z direction, penetrating the semiconductor layer 161, the insulating layer 162, and the semiconductor layer 163, exposing the upper surface of the wiring d2. This step is performed by a method such as RIE (Reactive Ion Etching).

[0111] Next, for example, Figure 14 As shown, a conductive layer 164B is formed on the inner peripheral surface of the contact hole 164A and the upper surface of the semiconductor layers 153 and 163. This step is performed by methods such as CVD.

[0112] Next, for example, Figure 15 As shown, the portion of conductive layer 164B except for the part formed inside contact hole 164A is removed. This step is performed by methods such as CMP (Chemical Mechanical Polishing). Through this step, conductive layer 164 is formed.

[0113] Next, for example, Figure 16 As shown, multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed above the semiconductor layer 153. The sacrificial layers 110A contain, for example, silicon nitride (Si3N4). The step is performed by, for example, CVD.

[0114] Next, for example, Figure 17 As shown, a plurality of memory vias (LMHs) are formed at positions corresponding to semiconductor layer 120. Each memory via (LMH) extends in the Z direction, penetrating multiple insulating layers 101, multiple sacrificial layers 110A, semiconductor layer 153, and insulating layer 152, exposing the upper surface of semiconductor layer 151. This step is performed using methods such as RIE (Residual Energy Interchange).

[0115] Next, for example, Figure 18 As shown, an amorphous silicon film 120A is formed on the inner peripheral surface of the memory hole LMH. This step is performed by methods such as CVD.

[0116] Next, for example, Figure 19 As shown, in reference Figure 18 The upper surface of the described structure is alternately formed with multiple insulating layers 101 and multiple sacrificial layers 110A. This step is performed by methods such as CVD.

[0117] Next, for example, Figure 20As shown, multiple memory vias UMH are formed at positions corresponding to the semiconductor layer 120. Each memory via UMH is a through-hole extending in the Z direction, penetrating multiple insulating layers 101 and multiple sacrificial layers 110A, exposing the upper surface of the amorphous silicon film 120A. This step is performed using methods such as RIE.

[0118] Next, for example, Figure 21 As shown, a semiconductor layer 120 is formed. Furthermore, although not shown in the diagram, a gate insulating film 130 is also formed in this step. In this step, the amorphous silicon film 120A is removed by methods such as wet etching. Additionally, the gate insulating film 130, the semiconductor layer 120, and the insulating layer 125 are formed on the inner peripheral surfaces of the memory holes LMH and UMH by methods such as CVD.

[0119] Next, for example, Figure 22 As shown, grooves STA and STA are formed. C Slot STA is located in the memory cell array area R. MCA The trench STA extends in the Z and X directions, and segments multiple insulating layers 101, multiple sacrificial layers 110A, and semiconductor layer 153 in the Y direction, exposing the upper surface of the insulating layer 152. C Set in the connection area R C STA slot C It is a trench extending in the Z and X directions, which separates the semiconductor layer 173, the insulating layer 172, and the semiconductor layer 171 in the Y direction. The step is performed by, for example, RIE (Residual Insulation).

[0120] Next, for example, Figure 23 As shown, a protective film such as silicon oxide (SiO2) STSWA is formed on the side surface of the tank STA in the Y direction. In this step, an insulating film such as silicon oxide is formed on the side surface and bottom surface of the tank STA in the Y direction using methods such as CVD. Furthermore, the portion of the insulating film covering the bottom surface of the tank STA is removed using methods such as RIE. Additionally, although not shown in the figure, this step also involves the tank STA... C A protective film, STSWA, is formed on the side in the Y direction.

[0121] Next, for example, Figures 24-26 As shown, a portion of the insulating layer 152 and the gate insulating film 130 are removed, exposing a portion of the semiconductor layer 120. This step is performed by, for example, wet etching.

[0122] Next, for example, Figure 27 As shown, a semiconductor layer 150 is formed. This step is performed by methods such as epitaxial growth.

[0123] Next, for example, Figure 28As shown, a conductive layer 110 is formed. In this step, the protective film STSWA (…) is formed using methods such as wet etching. Figure 26 The sacrificial layer 110A is removed by methods such as wet etching. Furthermore, a conductive layer 110 is formed by methods such as CVD.

[0124] Next, for example, Figure 29 As shown, an inter-block structure ST is formed within the slot STA. C Internally formed structure ST C The steps are performed using methods such as CVD and RIE.

[0125] Afterwards, a crack-stopping section 180 is formed. Figure 6 The wafer is cut into sections, such as through wiring, to form memory dies (MDs).

[0126] [Comparative Example 1] Figure 30 This is a schematic top view showing the configuration of the semiconductor memory device of the first comparative example. Figure 31 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 31 Includes Figure 30 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0127] In the semiconductor memory device of the first comparative example, in the connection region R C It comprises a semiconductor layer 171', an insulating layer 172', and a semiconductor layer 173'. The semiconductor layer 171', insulating layer 172', and semiconductor layer 173' are constructed by ST... C It is divided into two parts arranged along the Y direction. One of these two parts is continuously formed with semiconductor layer 161, insulating layer 162 and semiconductor layer 163, respectively. The other of these two parts is continuously formed with semiconductor layer 150.

[0128] In the manufacturing method of the semiconductor memory device in the first comparative example, the reference method is not performed. Figure 10 The steps are explained.

[0129] Here, in the manufacturing method of the first comparative example, in reference... Figure 17 , Figure 20In the described steps, memory vias LMH and UMH are formed. Here, to achieve high integration of the semiconductor memory device, it is desirable to form memory vias LMH and UMH with high aspect ratios. However, when forming high aspect ratio memory vias LMH and UMH using methods such as RIE, a large amount of charge may accumulate on the semiconductor layers 151 and 153 exposed in the memory vias LMH due to the influence of processing ions. If this charge exceeds a certain amount, an electric arc may occur, potentially causing wafer damage.

[0130] Therefore, in the manufacturing method of the first comparative example, before forming the memory holes LMH and UMH, in the reference... Figures 12-15 In this step, a conductive layer 164 is formed that electrically connects the semiconductor layers 151 and 153 exposed on the inner peripheral surface of the memory hole LMH to the semiconductor substrate 100. According to this configuration, the charge on the semiconductor layers 151 and 153 can escape to the semiconductor substrate 100. Therefore, the generation of electric arcs as described above can be suppressed.

[0131] However, for example, Figure 30 and Figure 31 As shown, in the first comparative example, semiconductor layer 150 and semiconductor layers 161 and 163, except for those constructed by ST... C The broken portion is formed continuously outside. Furthermore, the crack arrestor 180 avoids the connecting region R. C In this configuration, for example, during the dicing process of a memory die (MD), if cracks are generated in semiconductor layers 161 and 163, there is a concern that the cracks may propagate through semiconductor layers 171' and 173' to semiconductor layer 150.

[0132] In addition, in reference Figure 15 In some of the described steps, a portion of the semiconductor layer 163 is removed. In this case, the semiconductor layer 153 is electrically disconnected from the conductive layer 164, and an electric arc is generated due to the charge on the semiconductor layer 153.

[0133] [Comparative Example 2] Figure 32 This is a schematic top view showing the configuration of the semiconductor memory device of the second comparative example. Figure 33 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 33 Includes Figure 32 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0134] In the semiconductor memory device of the second comparative example, in the connection region R C It is provided with a semiconductor layer 171", an insulating layer 172", and a semiconductor layer 173".

[0135] Furthermore, in the semiconductor memory device of the second comparative example, in the connection region R C It is configured with multiple first regions 181” and second regions 182” arranged alternately in the Y direction.

[0136] Each of the first regions 181” has a portion of a semiconductor layer 171”, an insulating layer 172” and a semiconductor layer 173”.

[0137] Each of the second regions 182” has an insulating layer 174. The side of the insulating layer 174 in the Y direction is connected to the side of the semiconductor layer 171”, insulating layer 172” and semiconductor layer 173” contained in the two adjacent first regions 181” in the Y direction.

[0138] like Figure 32 As shown, the insulating layer 174 is arranged along the Y direction. Figure 32 In the middle, from one side of the Y direction (e.g.) Figure 32 Starting from the negative side of the Y direction, the odd-numbered insulating layer 174 is represented as insulating layer 174. O Starting from one side in the Y direction, the even-numbered insulating layer 174 is denoted as insulating layer 174. E .

[0139] Insulation layer 174 O On one side in the X direction (e.g.) Figure 32 The end of the semiconductor layer 171, insulating layer 172, and semiconductor layer 173 on one side of the X direction (negative side) reaches the end position of the semiconductor layer 171, insulating layer 172, and semiconductor layer 173 on one side of the X direction. On the other hand, insulating layer 174 O On the other side in the X direction (e.g.) Figure 32 The end of the semiconductor layer 171, insulating layer 172 and semiconductor layer 173 on the other side of the X direction (on the positive side) does not reach the end position of the semiconductor layer 171, insulating layer 172 and semiconductor layer 173 on the other side of the X direction.

[0140] Insulation layer 174 E The end on one side in the X direction reaches the connection area R. C The semiconductor layer 171, insulating layer 172, and semiconductor layer 173 are located at their ends on one side in the X direction. On the other hand, insulating layer 174... E The end on the other side in the X direction reaches the connection area R. C The semiconductor layer 171, insulating layer 172 and semiconductor layer 173 are located at the ends on the other side in the X direction.

[0141] In the manufacturing method of the semiconductor memory device in the second comparative example, the reference method is not performed. Figure 10 The steps are explained.

[0142] Furthermore, in the manufacturing method of the semiconductor memory device in the second comparative example, during the execution of the reference... Figure 12After following the steps described, and referring to the instructions. Figure 16 Before the steps described, an insulating layer 174 is formed.

[0143] Based on this configuration, for example, in the dicing process of a memory die MD, if cracks are generated in the semiconductor layers 161 and 163, multiple insulating layers 174 can be used to suppress the propagation of the cracks to the semiconductor layer 150.

[0144] However, in the configuration of the second comparative example, the wiring length between semiconductor layers 151, 153 and semiconductor layers 161, 163 is longer, resulting in increased resistance. Therefore, in the reference... Figure 17 , Figure 20 In the described steps, it is not possible to properly allow the charge on the semiconductor layers 151 and 153 to escape to the semiconductor substrate 100, which raises concerns about the generation of charge.

[0145] [Effect] In the first embodiment, for example, Figure 5 As shown, a plurality of openings 172b arranged along the Y direction are provided in the insulating layer 172. With this configuration, for example, in the dicing process of a memory die MD, if cracks are generated in the semiconductor layers 161 and 163, the propagation of the cracks to the semiconductor layer 150 can be suppressed.

[0146] Furthermore, in the first embodiment, for example, as Figure 5 As shown, in the connected region R C A second region 182 is provided to electrically connect semiconductor layer 171 and semiconductor layer 173. According to this configuration, for example in reference... Figure 15 In the described steps, if a portion of the semiconductor layer 163 is removed, the charge on the semiconductor layer 153 can also escape to the semiconductor substrate 100 via the semiconductor layer 171. This suppresses the generation of the electric arc described above.

[0147] Furthermore, in the first embodiment, compared to the structure of the second comparative example, the wiring length between semiconductor layers 151, 153 and semiconductor layers 171, 173 can be shortened. Therefore, compared to the second comparative example, arc generation can be suppressed more appropriately.

[0148] [Second Embodiment] Next, refer to Figure 34 and Figure 35 This describes the semiconductor memory device according to the second embodiment. Figure 34 This is a schematic top view showing the configuration of the semiconductor memory device according to the second embodiment. Figure 35 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 35 Includes Figure 34 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0149] The semiconductor memory device of the second embodiment is configured essentially the same as the semiconductor memory device of the first embodiment. However, in the connection region R of the semiconductor memory device of the second embodiment... C An insulating layer 272 is provided to replace the insulating layer 172. Furthermore, in the connection region R of the semiconductor memory device in the second embodiment... C It is configured with multiple first regions 281 and multiple second regions 282 arranged alternately in the Y direction.

[0150] Insulating layer 272 is constructed in essentially the same way as insulating layer 172. However, insulating layer 272 is as follows: Figure 35 As shown, it has multiple portions 272a corresponding to multiple first regions 281 and multiple openings 272b corresponding to multiple second regions 282.

[0151] like Figure 34 As shown, openings 272b are arranged along the Y direction. Figure 34 In the middle, from one side of the Y direction (e.g.) Figure 34 Starting from the negative side of the Y direction, the odd-numbered opening 272b is denoted as opening 272b. O Starting from one side in the Y direction, the even-numbered opening 272b is denoted as opening 272b. E .

[0152] Opening 272b O On one side in the X direction (e.g.) Figure 34 The end of the insulating layer 272 (on the negative side in the X direction) reaches the end position of the insulating layer 272 on one side in the X direction. On the other hand, the opening 272b O On the other side in the X direction (e.g.) Figure 34 The end of the insulating layer 272 on the other side of the X direction (positive side) does not reach the end position of the insulating layer 272 on the X direction.

[0153] Opening 272b E The end on one side in the X direction does not reach the connection area R. C The insulating layer 272 is located at one end on one side in the X direction. On the other hand, the opening 272b... E The end on the other side in the X direction reaches the connection area R. C The insulating layer 272 is located at the end position on the other side in the X direction.

[0154] The width of the opening 272b in the X direction is greater than half the width of the insulating layer 272 in the X direction. In addition, the ends of two adjacent portions 272a in the Y direction are connected to each other on the opposite side or one side of the X direction.

[0155] The manufacturing method of the second embodiment is basically the same as that of the first embodiment. However, in the manufacturing method of the first embodiment, when referring to... Figure 10 In the steps described, in the connection region R C Multiple openings 172b are formed. On the other hand, in the manufacturing method of the second embodiment, such as... Figure 36 As shown, multiple openings 272b are formed to replace multiple openings 172b.

[0156] [Third Embodiment] Next, refer to Figure 37 and Figure 38 This describes the semiconductor memory device according to the third embodiment. Figure 37 This is a schematic top view showing the configuration of the semiconductor memory device according to the third embodiment. Figure 38 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 38 Includes Figure 37 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0157] The semiconductor memory device of the third embodiment is configured in essentially the same way as the semiconductor memory device of the second embodiment. However, in the connection region R of the semiconductor memory device of the third embodiment... C An insulating layer 372 is provided to replace the insulating layer 272. Furthermore, in the connection region R of the semiconductor memory device in the third embodiment... C It is configured with multiple first regions 381 and second regions 382 arranged alternately in the Y direction.

[0158] Insulation layer 372 Figure 38 As shown, it includes a portion 372a and a plurality of openings 372b provided in the portion 372a. Figure 37 As shown, in the second region 382, ​​a plurality of openings 372b arranged along the X direction are provided. Furthermore, in the region between the plurality of openings 372b arranged along the X direction and in the first region 381, portions 372a ( Figure 38 ).like Figure 37 As shown, the width of opening 372b in the X direction is less than half the width of insulating layer 272 in the X direction.

[0159] The manufacturing method of the third embodiment is basically the same as that of the second embodiment. However, in the manufacturing method of the second embodiment, reference is made to... Figure 36 In the steps described, in the connection region R C Multiple openings 273b are formed. On the other hand, in the manufacturing method of the third embodiment, such as Figure 39 As shown, multiple openings 372b are formed to replace multiple openings 273b.

[0160] [Fourth Embodiment] Next, refer to Figure 40 and Figure 41 This describes the semiconductor memory device according to the fourth embodiment. Figure 40 This is a schematic top view showing the configuration of the semiconductor memory device according to the fourth embodiment. Figure 41 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 41 Includes Figure 40 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0161] The semiconductor memory device of the fourth embodiment is configured in the same way as the semiconductor memory device of the first embodiment.

[0162] However, in the fourth embodiment, the connection region R of the semiconductor memory device C A semiconductor layer 471, an insulating layer 472, and a semiconductor layer 473 are disposed thereto replace semiconductor layer 171, insulating layer 172, and semiconductor layer 173. Furthermore, in the connection region R of the semiconductor memory device in the fourth embodiment... C It is configured with multiple first regions 481 and multiple second regions 482 arranged alternately in the Y direction.

[0163] Semiconductor layer 471, insulating layer 472, and semiconductor layer 473 are substantially constructed in the same manner as semiconductor layer 171, insulating layer 172, and semiconductor layer 173. However, as Figure 41 As shown, the semiconductor layer 471, the insulating layer 472, and the semiconductor layer 473 have multiple portions 471a, 472a, and 473a corresponding to multiple first regions 481, and multiple openings 473b corresponding to multiple second regions 482. Figure 40 As shown, the opening 473b reaches the ends of the semiconductor layer 471, insulating layer 472, and semiconductor layer 473 on one and the other sides in the X direction.

[0164] Furthermore, in the fourth embodiment, the connection region R of the semiconductor memory device C Multiple conductive layers 486 are provided, corresponding to multiple second regions 482 arranged alternately in the Y direction. For example... Figure 41 As shown, the side surface of conductive layer 486 in the Y direction is connected to the side surface of portions 471a, 472a, and 473a in the Y direction. The lower end of conductive layer 486 is connected to wiring d2. Furthermore, as... Figure 40 As shown, the ends of the conductive layer 486 on one side and the other side in the X direction reach the ends of the semiconductor layer 471, the insulating layer 472, and the semiconductor layer 473 on one side and the other side in the X direction.

[0165] The manufacturing method of the fourth embodiment is basically the same as that of the first embodiment. However, in the manufacturing method of the first embodiment, the reference [method / procedure] is not performed. Figure 10 The steps are explained. Additionally, for example, in the reference... Figure 13 In the described steps, an opening is formed at the position corresponding to the conductive layer 486, penetrating the semiconductor layer 171, the insulating layer 172, and the semiconductor layer 173.

[0166] [Fifth Embodiment] Next, refer to Figure 42 and Figure 43 This describes the semiconductor memory device according to the fifth embodiment. Figure 42 This is a schematic top view showing the configuration of the semiconductor memory device according to the fifth embodiment. Figure 43 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 43 Includes Figure 42 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0167] The semiconductor memory device of the fifth embodiment is configured in essentially the same way as the semiconductor memory device of the fourth embodiment. However, in the connection region R of the semiconductor memory device of the fifth embodiment... C A semiconductor layer 571, an insulating layer 572, and a semiconductor layer 573 are disposed thereto replace semiconductor layer 471, insulating layer 472, and semiconductor layer 473. Furthermore, in the connection region R of the semiconductor memory device in the fifth embodiment... C ,like Figure 43 As shown, multiple first regions 581 and multiple second regions 582 are arranged alternately in the Y direction.

[0168] Semiconductor layer 571, insulating layer 572, and semiconductor layer 573 are substantially constructed in the same manner as semiconductor layer 471, insulating layer 472, and semiconductor layer 473. However, as Figure 43 As shown, the semiconductor layer 571, the insulating layer 572 and the semiconductor layer 573 have multiple portions 571a, 572a and 573a corresponding to multiple first regions 581 and multiple openings 573b corresponding to multiple second regions 582.

[0169] like Figure 42 As shown, openings 573b are arranged along the Y direction. Figure 42 In the middle, from one side of the Y direction (e.g.) Figure 42 Starting from the negative side of the Y direction, the odd-numbered opening 573b is denoted as opening 573b. O Starting from one side in the Y direction, the even-numbered opening 573b is denoted as opening 573b. E .

[0170] Opening 573b O On one side in the X direction (e.g.) Figure 42 The end of the semiconductor layer 571, insulating layer 572, and semiconductor layer 573 on one side of the X direction (negative side) reaches the end position of the semiconductor layer 571, insulating layer 572, and semiconductor layer 573 on one side of the X direction. On the other hand, the opening 573b O On the other side in the X direction (e.g.) Figure 42 The end of the semiconductor layer 571, insulating layer 572 and semiconductor layer 573 on the other side of the X direction (on the positive side) does not reach the end position of the semiconductor layer 571, insulating layer 572 and semiconductor layer 573 on the other side of the X direction.

[0171] Opening 573b E The end on one side in the X direction does not reach the connection area R. C The semiconductor layer 571, insulating layer 572, and semiconductor layer 573 are located at their ends on one side in the X direction. On the other hand, opening 573b... E The end on the other side in the X direction reaches the connection area R. C The semiconductor layer 571, insulating layer 572 and semiconductor layer 573 are located at the ends on the other side in the X direction.

[0172] The width of opening 573b in the X direction is greater than half the width of semiconductor layer 571, insulating layer 572, and semiconductor layer 573 in the X direction. In addition, the ends of two adjacent portions 571a, 572a, and 573a in the Y direction are connected to each other on the opposite side or one side of the X direction.

[0173] Furthermore, in the fifth embodiment, the connection region R of the semiconductor memory device C Multiple conductive layers 586 are provided, corresponding to multiple second regions 582 arranged alternately in the Y direction. The conductive layers 586 are basically constructed in the same way as the conductive layers 486.

[0174] like Figure 42 As shown, the conductive layer 586 is arranged along the Y direction. Figure 42 In the middle, from one side of the Y direction (e.g.) Figure 42 Starting from the negative side of the Y direction, the odd-numbered conductive layer 586 is denoted as conductive layer 586. O Starting from one side in the Y direction, the even-numbered conductive layer 586 is denoted as conductive layer 586. E .

[0175] Conductive layer 586 O On one side in the X direction (e.g.) Figure 42 The end of the semiconductor layer 571, insulating layer 572, and semiconductor layer 573 on one side of the X direction (negative side) reaches the end position of the semiconductor layer 571, insulating layer 572, and semiconductor layer 573 on one side of the X direction. On the other hand, conductive layer 586 O On the other side in the X direction (e.g.) Figure 42The end of the semiconductor layer 571, insulating layer 572 and semiconductor layer 573 on the other side of the X direction (on the positive side) does not reach the end position of the semiconductor layer 571, insulating layer 572 and semiconductor layer 573 on the other side of the X direction.

[0176] Conductive layer 586 E The end on one side in the X direction reaches the connection area R. C The semiconductor layer 571, insulating layer 572, and semiconductor layer 573 are located at their ends on one side in the X direction. On the other hand, conductive layer 586... E The end on the other side in the X direction reaches the connection area R. C The semiconductor layer 571, insulating layer 572 and semiconductor layer 573 are located at the ends on the other side in the X direction.

[0177] The width of the conductive layer 586 in the X direction is greater than half the width of the semiconductor layer 571, the insulating layer 572, and the semiconductor layer 573 in the X direction.

[0178] The manufacturing method of the fifth embodiment is basically the same as that of the fourth embodiment. However, in the manufacturing method of the fifth embodiment, when referring to... Figure 13 In the described steps, an opening is formed at the position corresponding to the conductive layer 586, penetrating the semiconductor layer 171, the insulating layer 172, and the semiconductor layer 173.

[0179] [Sixth Embodiment] Next, refer to Figure 44 and Figure 45 This describes the semiconductor memory device according to the sixth embodiment. Figure 44 This is a schematic top view showing the configuration of the semiconductor memory device according to the sixth embodiment. Figure 45 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device. Additionally, Figure 45 Includes Figure 44 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow.

[0180] The semiconductor memory device of the sixth embodiment is configured essentially the same as that of the semiconductor memory device of the fifth embodiment. However, in the connection region R of the semiconductor memory device of the sixth embodiment... C A semiconductor layer 671, an insulating layer 672, and a semiconductor layer 673 are disposed thereto replace semiconductor layer 571, insulating layer 572, and semiconductor layer 573. Furthermore, in the connection region R of the semiconductor memory device in the sixth embodiment... C ,like Figure 44 As shown, multiple first regions 681 and second regions 682 are arranged alternately in the Y direction.

[0181] Semiconductor layer 671, insulating layer 672 and semiconductor layer 673 as follows Figure 45As shown, it includes portions 671a, 672a, and 673a, and multiple openings 673b provided in portions 671a, 672a, and 673a. Figure 44 As shown, in the second region 682, a plurality of openings 673b arranged along the X direction are provided. Furthermore, portions 671a, 672a, and 673a are provided in the region between the plurality of openings 673b arranged along the X direction and in the first region 681. The width of the opening 673b in the X direction is less than half the width of the semiconductor layer 671, the insulating layer 672, and the semiconductor layer 673 in the X direction.

[0182] Furthermore, in the sixth embodiment, the connection region R of the semiconductor memory device C Multiple conductive layers 686 are provided, corresponding to multiple second regions 682. The conductive layers 686 are basically constructed in the same way as the conductive layers 586. However, the width of the conductive layer 586 in the X direction is less than half the width of the semiconductor layer 671, the insulating layer 672, and the semiconductor layer 673 in the X direction.

[0183] The manufacturing method of the sixth embodiment is basically the same as that of the fifth embodiment. However, in the manufacturing method of the fifth embodiment, when referring to... Figure 13 In the described steps, an opening is formed at the position corresponding to the conductive layer 686, penetrating the semiconductor layer 171, the insulating layer 172, and the semiconductor layer 173.

[0184] Furthermore, the lower ends of conductive layers 486, 586, and 686 in embodiments 4 to 6 are connected to wiring d2. However, this configuration is merely illustrative, and the specific configuration can be adjusted appropriately. For example, as... Figure 46 As illustrated, the lower end of conductive layer 486 may not be connected to wiring d2. The same applies to conductive layers 586 and 686.

[0185] [Other] While several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A semiconductor substrate has a memory cell array region, an edge sealing region, and a connection region disposed between the memory cell array region and the edge sealing region; Multiple first conductive layers are disposed in the memory cell array region and arranged along a first direction intersecting the surface of the semiconductor substrate; A first semiconductor layer is disposed in the memory cell array region, extends in the first direction, and faces the plurality of first conductive layers; A second semiconductor layer is disposed in the memory cell array region, between the plurality of first conductive layers and the semiconductor substrate, and connected to the first semiconductor layer; The third semiconductor layer and the fourth semiconductor layer are disposed in the edge sealing region and arranged along the first direction; A second conductive layer is disposed in the edge sealing region and electrically connected to the third semiconductor layer, the fourth semiconductor layer and the semiconductor substrate; A fifth semiconductor layer is disposed in the connection region and extends in a second direction intersecting the first direction, having a portion continuously formed with the second semiconductor layer and a portion continuously formed with the third semiconductor layer; and A sixth semiconductor layer is disposed in the connection region, extends in the second direction, and has a portion continuously formed with the second semiconductor layer and a portion continuously formed with the fourth semiconductor layer; and The connecting region comprises a plurality of first regions and second regions arranged alternately along the second direction. In the plurality of first regions, the fifth semiconductor layer and the sixth semiconductor layer are separated in the first direction. In the plurality of second regions, the fifth semiconductor layer and the sixth semiconductor layer are electrically connected.

2. The semiconductor memory device according to claim 1, comprising: A first insulating layer is disposed in the edge sealing region, located between the third semiconductor layer and the fourth semiconductor layer; and A second insulating layer is disposed in the connection region, located between the fifth semiconductor layer and the sixth semiconductor layer, and has a portion continuously formed with the first insulating layer; and The second insulating layer has a plurality of first portions corresponding to the plurality of first regions.

3. The semiconductor memory device according to claim 2, wherein... The sixth semiconductor layer comprises: A plurality of second portions are disposed in the plurality of first regions, and are disposed on one side of the plurality of first portions in the first direction; A plurality of third portions are disposed in the plurality of second regions and on the surface of the fifth semiconductor layer on one side of the first direction; and Multiple fourth parts are disposed on the side of the multiple first parts in the second direction.

4. The semiconductor memory device according to claim 3, wherein At least one of the plurality of Part 3 At one end of a third direction intersecting the first and second directions, the fifth semiconductor layer reaches the end position on one side of the third direction, and The fifth semiconductor layer reaches the end position on the other side of the third direction at the other end of the third direction.

5. The semiconductor memory device according to claim 3, wherein At least one of the plurality of Part 3 At one end of a third direction intersecting the first and second directions, the fifth semiconductor layer reaches the end position on one side of the third direction, and The fifth semiconductor layer does not reach the end position of the fifth semiconductor layer on the other side of the third direction at the other end of the third direction.

6. The semiconductor memory device according to claim 3, wherein At least one of the plurality of Part 3 At one end of the third direction, which intersects the first and second directions, the fifth semiconductor layer does not reach the end position on one side of the third direction. The fifth semiconductor layer does not reach the end position of the fifth semiconductor layer on the other side of the third direction at the other end of the third direction.

7. The semiconductor memory device according to claim 3, wherein If the width of at least one of the plurality of third parts in the third direction intersecting the first direction and the second direction is set as the first width, The width of the fifth semiconductor layer in the third direction is set as the second width. Therefore, the first width is equal to the second width.

8. The semiconductor memory device according to claim 3, wherein If the width of at least one of the plurality of third parts in the third direction intersecting the first direction and the second direction is set as the first width, The width of the fifth semiconductor layer in the third direction is set as the second width. Then the first width is smaller than the second width, and A width greater than half of the second width.

9. The semiconductor memory device according to claim 3, wherein If the width of at least one of the plurality of third parts in the third direction intersecting the first direction and the second direction is set as the first width, The width of the fifth semiconductor layer in the third direction is set as the second width. Therefore, the first width is less than half the width of the second width.

10. The semiconductor memory device according to claim 1, comprising: Multiple third conductive layers are disposed corresponding to the multiple second regions. The fifth semiconductor layer has a plurality of fifth portions disposed corresponding to the plurality of first regions. The sixth semiconductor layer has a plurality of sixth portions disposed corresponding to the plurality of first regions. The plurality of third conductive layers are respectively connected to two adjacent fifth portions and two adjacent sixth portions in the second direction.

11. The semiconductor memory device of claim 10, wherein... At least one of the plurality of third conductive layers At one end of a third direction intersecting the first and second directions, the fifth semiconductor layer reaches the end position on one side of the third direction, and The fifth semiconductor layer reaches the end position on the other side of the third direction at the other end of the third direction.

12. The semiconductor memory device of claim 10, wherein... At least one of the plurality of third conductive layers At one end of a third direction intersecting the first and second directions, the fifth semiconductor layer reaches the end position on one side of the third direction, and The fifth semiconductor layer does not reach the end position of the fifth semiconductor layer on the other side of the third direction at the other end of the third direction.

13. The semiconductor memory device of claim 10, wherein... At least one of the plurality of third conductive layers At one end of the third direction, which intersects the first and second directions, the fifth semiconductor layer does not reach the end position of the fifth semiconductor layer on one side of the third direction, and The fifth semiconductor layer does not reach the end position of the fifth semiconductor layer on the other side of the third direction at the other end of the third direction.

14. The semiconductor memory device of claim 10, wherein... If the width of at least one of the plurality of third conductive layers in the third direction, which intersects the first direction and the second direction, is set as the first width, The width of the fifth semiconductor layer in the third direction is set as the second width. Therefore, the first width is equal to the second width.

15. The semiconductor memory device according to claim 10, wherein If the width of at least one of the plurality of third conductive layers in the third direction, which intersects the first direction and the second direction, is set as the first width, The width of the fifth semiconductor layer in the third direction is set as the second width. Then the first width is smaller than the second width, and A width greater than half of the second width.

16. The semiconductor memory device of claim 10, wherein... If the width of at least one of the plurality of third conductive layers in the third direction, which intersects the first direction and the second direction, is set as the first width, The width of the fifth semiconductor layer in the third direction is set as the second width. Therefore, the first width is less than half the width of the second width.

17. The semiconductor memory device according to claim 1, wherein The third semiconductor layer and the fourth semiconductor layer are electrically insulated from the second semiconductor layer.

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