semiconductor devices

Abstract

The present invention discloses a semiconductor device comprising a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate, and the source region and the drain region are disposed in the semiconductor substrate and are located on two opposite sides of the gate structure in a first direction. A plurality of field plates are disposed on the semiconductor substrate, with each field plate being partially located above the gate structure and partially located between the gate structure and the drain region. The gate structure is electrically connected to at least one of the plurality of field plates, and the source region is electrically connected to at least one of the plurality of field plates.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a semiconductor device with a field plate. Background Art

[0002] Among power devices with high-voltage handling capabilities, double-diffused MOS (DMOS) transistors continue to gain attention. Common DMOS transistors include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. LDMOS transistors, due to their high operating bandwidth and efficiency, as well as their planar structure that allows for easy integration with other integrated circuits, are now widely used in high-voltage operating environments, such as CPU power supplies, power management systems, DC / AC converters, and high-power or high-frequency power amplifiers. The main feature of LDMOS transistors is that they utilize a large, low-doping lateral diffusion drift region to mitigate the high voltage between the source and drain terminals, thereby enabling LDMOS transistors to achieve a higher breakdown voltage. However, as the requirements for related products become increasingly stringent, how to improve the electrical performance, voltage resistance, and / or power loss of power devices through design adjustments in structure and / or manufacturing process remains a continuous effort of researchers in related fields. Summary of the Invention

[0003] The present invention provides a semiconductor device that utilizes a gate structure electrically connected to at least one field plate and a source region electrically connected to at least one field plate to adjust characteristics such as on-resistance (Ron) and gate charge (Qg) of the semiconductor device, thereby achieving the effect of improving specific electrical performance of the semiconductor device and / or reducing power consumption.

[0004] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and are located on opposite sides of the gate structure in a first direction. A plurality of field plates are disposed on the semiconductor substrate, each field plate being partially located above the gate structure and partially located between the gate structure and the drain region. The gate structure is electrically connected to at least one of the plurality of field plates, and the source region is electrically connected to at least one of the plurality of field plates.

[0005] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a first gate structure, a second gate structure, a first source region, a first drain region, a second source region, a second drain region, a plurality of first field plates, and a plurality of second field plates. The first gate structure and the second gate structure are disposed on the semiconductor substrate. The first source region and the first drain region are disposed in the semiconductor substrate and are respectively located on two opposite sides of the first gate structure in a first direction. The second source region and the second drain region are disposed in the semiconductor substrate and are respectively located on two opposite sides of the second gate structure in the first direction. The first field plate and the second field plate are disposed on the semiconductor substrate. Each first field plate is partially located above the first gate structure and partially located between the first gate structure and the first drain region, and the first gate structure is electrically connected to at least one of the plurality of first field plates. Each second field plate is partially located above the second gate structure and partially located between the second gate structure and the second drain region, and the second source region is electrically connected to at least one of the plurality of second field plates.

[0006] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and are respectively located on two opposite sides of the gate structure in a first direction. A plurality of field plates are disposed on the semiconductor substrate, each field plate being partially located above the gate structure and partially located between the gate structure and the drain region, the gate structure being electrically connected to a plurality of the plurality of field plates, and the source region being electrically connected to a plurality of the plurality of field plates. The plurality of field plates electrically connected to the gate structure and the plurality of field plates electrically connected to the source region are alternately arranged along a second direction, and the second direction is orthogonal to the first direction.

[0007] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and are respectively located on two opposite sides of the gate structure in a first direction. A plurality of field plates are disposed on the semiconductor substrate, each field plate being partially located above the gate structure and partially located between the gate structure and the drain region. The gate structure is electrically connected to at least one of the plurality of field plates, and the source region is electrically connected to at least one of the plurality of field plates. The size of the field plate electrically connected to the gate structure is different from the size of the field plate electrically connected to the source region.

[0008] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a first gate structure, a second gate structure, a first source region, a first drain region, a second source region, a second drain region, a plurality of first field plates, and a plurality of second field plates. The first gate structure and the second gate structure are disposed on the semiconductor substrate. The first source region and the first drain region are disposed in the semiconductor substrate and are located on two opposite sides of the first gate structure in a first direction. The second source region and the second drain region are disposed in the semiconductor substrate and are located on two opposite sides of the second gate structure in the first direction. The first field plates and the second field plates are disposed on the semiconductor substrate. Each first field plate is partially located above the first gate structure and partially located between the first gate structure and the first drain region, and the first gate structure is electrically connected to at least one of the plurality of first field plates. Each second field plate is partially located above the second gate structure and partially located between the second gate structure and the second drain region, and the second source region is electrically connected to at least one of the plurality of second field plates. The number of first field plates is different from the number of second field plates.

[0009] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a first gate structure, a second gate structure, a first source region, a first drain region, a second source region, a second drain region, a plurality of first field plates, and a plurality of second field plates. The first gate structure and the second gate structure are disposed on the semiconductor substrate. The first source region and the first drain region are disposed in the semiconductor substrate and are located on opposite sides of the first gate structure in a first direction. The second source region and the second drain region are disposed in the semiconductor substrate and are located on opposite sides of the second gate structure in the first direction. The first field plates and the second field plates are disposed on the semiconductor substrate. Each first field plate is partially located above the first gate structure and partially located between the first gate structure and the first drain region, and the first gate structure is electrically connected to at least one of the plurality of first field plates. Each second field plate is partially located above the second gate structure and partially located between the second gate structure and the second drain region, and the second source region is electrically connected to at least one of the plurality of second field plates. At least one of the plurality of first field plates has a different size than at least one of the plurality of second field plates. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0011] Figure 2 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

[0012] Figure 3 is another cross-sectional schematic diagram of the semiconductor device according to the first embodiment of the present invention;

[0013] Figure 4 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0014] Figure 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

[0015] Figure 6 is another cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0016] Figure 7 is a schematic diagram of a semiconductor device according to a third embodiment of the present invention;

[0017] Figure 8 is a schematic diagram of a semiconductor device according to a fourth embodiment of the present invention;

[0018] Figure 9 is a schematic diagram of a semiconductor device according to a fifth embodiment of the present invention;

[0019] Figure 10 is a schematic diagram of a semiconductor device according to a sixth embodiment of the present invention;

[0020] Figure 11 is a schematic diagram of a semiconductor device according to a seventh embodiment of the present invention;

[0021] Figure 12 is a schematic diagram of a semiconductor device according to an eighth embodiment of the present invention;

[0022] Figure 13 is a schematic diagram of a semiconductor device according to a ninth embodiment of the present invention;

[0023] Figure 14 FIG. 1 is a schematic diagram of a semiconductor device according to a tenth embodiment of the present invention.

[0024] Description of main component symbols

[0025] 10 Semiconductor substrate

[0026] 10A active area

[0027] 12 Isolation Structure

[0028] 22 First well region

[0029] 24 Second well region

[0030] 24A Part 1

[0031] 24B Part 2

[0032] 32 Gate dielectric layer

[0033] 32A first gate dielectric layer

[0034] 32B second gate dielectric layer

[0035] 34 Gate structure

[0036] 36 Spacer

[0037] 38 Insulation Pattern

[0038] 38A First insulation pattern

[0039] 38B Second insulation pattern

[0040] 42 Lightly doped region

[0041] 42A first lightly doped region

[0042] 42B Second lightly doped region

[0043] 44D drain region

[0044] 44S source region

[0045] 46 doping region

[0046] 101 Semiconductor Devices

[0047] 102 Semiconductor devices

[0048] 103 Semiconductor devices

[0049] 104 Semiconductor devices

[0050] 105 Semiconductor devices

[0051] 106 Semiconductor devices

[0052] 107 Semiconductor devices

[0053] 108 Semiconductor devices

[0054] 109 Semiconductor devices

[0055] 110 Semiconductor devices

[0056] CS1 first connection structure

[0057] CS2 Second connection structure

[0058] CS3 third connection structure

[0059] D1 First direction

[0060] D2 Second direction

[0061] D3 third direction

[0062] DE1 first drain region

[0063] DE2 Second drain region

[0064] DS distance

[0065] DS1 distance

[0066] DS2 distance

[0067] F11 Field Plate

[0068] F12 Field Plate

[0069] F21 Field Plate

[0070] F22 Field Plate

[0071] FP1 First round board

[0072] FP2 Second board

[0073] GS1 first gate structure

[0074] GS2 second gate structure

[0075] L length

[0076] L1 length

[0077] L2 length

[0078] SE1 first source region

[0079] SE2 second source region

[0080] V1 contact structure

[0081] V2 contact structure

[0082] V3 contact structure

[0083] V4 contact structure

[0084] V5 contact structure

[0085] W Width

[0086] W1 width

[0087] W2 width DETAILED DESCRIPTION

[0088] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

[0089] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0090] The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0091] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify claim elements. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0092] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0093] See also Figures 1 to 3 . Figure 1 FIG. 1 is a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 2 FIG. 1 is a cross-sectional view of the semiconductor device 101 of this embodiment. Figure 3 FIG. 1 is another cross-sectional view of the semiconductor device 101 of this embodiment. Figure 1 It can be regarded as a top view or / and a layout diagram of the semiconductor device 101 of this embodiment, and some components of the semiconductor device 101 (such as the source region, the drain region, the doped region, the well region, the isolation structure, the spacer and the gate dielectric layer, etc.) are not shown. Figure 1 middle. Figure 2 Can be considered as Figure 1 The sectional view shown by the A-A' section line is Figure 3 Can be considered as Figure 1 The cross-sectional view is shown along the BB' section line, but is not limited thereto. Figures 1 to 3 As shown, semiconductor device 101 includes a semiconductor substrate 10, a gate structure 34, a source region 44S, a drain region 44D, and a plurality of field plates (e.g., a plurality of first field plates FP1). Gate structure 34 is disposed on semiconductor substrate 10. Source region 44S and drain region 44D are disposed in semiconductor substrate 10 and are located on opposite sides of gate structure 34 in a first direction D1. A plurality of first field plates FP1 are disposed on semiconductor substrate 10, each of which is partially located above gate structure 34 and partially located between gate structure 34 and drain region 44D. Gate structure 34 is electrically connected to at least one of the plurality of first field plates FP1, and source region 44S is electrically connected to at least one of the plurality of first field plates FP1. By electrically connecting at least one first field plate FP1 to the gate structure 34 and to the source region 44S, the on-resistance (Ron) and gate charge (Qg) of the semiconductor device 101 can be adjusted, thereby reducing power consumption.

[0094] In some embodiments, the first direction D1 may be considered as a horizontal direction, and the first direction D1 may be aligned with another horizontal direction (eg Figures 1 to 3 ) and a vertical direction (e.g. Figures 1 to 3The third direction D3 shown in FIG. 1 is substantially orthogonal to the third direction D3 shown in FIG. Furthermore, the third direction D3 can be considered the thickness direction of the semiconductor substrate 10. The semiconductor substrate 10 may have an upper surface and a bottom surface opposite each other in the third direction D3. The gate structure 34 and the first field plate FP1 may be disposed on one side of the upper surface, but are not limited thereto. The second direction D2 and the third direction D3 may be substantially parallel to the upper surface and / or the bottom surface of the semiconductor substrate 10, but are not limited thereto. In addition, the relatively higher position in the vertical direction (e.g., the third direction D3) or / and the distance between the component and the bottom surface of the semiconductor substrate 10 in the third direction D3 described in this article is greater than the relatively lower position in the third direction D3 or / and the distance between the component and the bottom surface of the semiconductor substrate 10 in the third direction D3. The lower part or bottom of each component may be closer to the bottom surface of the semiconductor substrate 10 in the third direction D3 than the upper part or top of this component. Another component above a certain component may be regarded as relatively far away from the bottom surface of the semiconductor substrate 10 in the third direction D3, and another component below a certain component may be regarded as relatively close to the bottom surface of the semiconductor substrate 10 in the third direction D3.

[0095] Furthermore, in some embodiments, the semiconductor device 101 may further include an isolation structure 12, a first well region 22, a second well region 24, a gate dielectric layer 32, a spacer 36, a plurality of insulating patterns 38, a lightly doped region 42, a doped region 46, a plurality of contact structures (e.g., contact structure V1, contact structure V2, contact structure V3, contact structure V4, and contact structure V5), a first connection structure CS1, a second connection structure CS2, and a third connection structure CS3, but the present invention is not limited thereto. The isolation structure 12 may be at least partially disposed in the semiconductor substrate 10 to define a plurality of active regions 10A in the semiconductor substrate 10. The first well region 22 and the second well region 24 may be disposed in the semiconductor substrate 10. A portion of the first well region 22 and a portion of the second well region 24 may be located on opposite sides of the gate structure 34 in the first direction D1. The source region 44S may be located in the first well region 22, and the drain region 44D may be located in the second well region 24. In addition, the lightly doped region 42 and the doped region 46 may be disposed in the semiconductor substrate 10 and located in the first well region 22 , and the source region 44S may be disposed adjacent to the lightly doped region 42 and the doped region 46 , respectively.

[0096] In some embodiments, the conductivity type of the first well region 22 may be complementary to the conductivity type of the second well region 24. The conductivity type of the source region 44S, the drain region 44D, and the lightly doped region 42 may be the same as the conductivity type of the second well region 24, and the conductivity type of the doped region 46 may be the same as the conductivity type of the first well region 22, but the present invention is not limited thereto. For example, when the semiconductor substrate 10 is a p-type semiconductor substrate or a semiconductor substrate having a p-type doped region, the first well region 22 may be a p-type doped well region, the second well region 24 may be an n-type doped well region, the lightly doped region 42 may be a lightly n-type doped region, the source region 44S and the drain region 44D may each be a heavily n-type doped region, and the doped region 46 may be a heavily p-type doped region, but the present invention is not limited thereto. In some embodiments, the doped region 46 can be used to adjust the potential of the first well region 22, and the doped region 46 and the source region 44S can be considered as a source doped region in the semiconductor device 101, but the present invention is not limited thereto. In addition, in some embodiments, the second well region 24 can be considered as a drift region in the semiconductor device, and the semiconductor device can be considered as a double-diffused metal oxide semiconductor (DMOS) device, such as a DMOS device in a bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor (Bipolar-CMOS-DMOS, BCD) structure, but the present invention is not limited thereto.

[0097] A gate dielectric layer 32 is disposed on the semiconductor substrate 10, and at least a portion of the gate dielectric layer 32 may be located between the gate structure 34 and the semiconductor substrate 10 in the third direction D3. Spacers 36 are disposed on the semiconductor substrate 10 and may be disposed on the sidewalls of the gate structure 34 and, but are not limited to, the lightly doped region 42 in the third direction D3. A plurality of insulating patterns 38 may be disposed on the semiconductor substrate 10, each insulating pattern 38 may be partially located above the gate structure 34 and partially located between the gate structure 34 and the drain region 44D. Each insulating pattern 38 may be disposed between the semiconductor substrate 10 and one of the plurality of first field plates FP1. In some embodiments, each insulating pattern 38 may correspond to a corresponding first field plate FP1 in the third direction D3, and the projection of each insulating pattern 38 in the third direction D3 may overlap with the projection of the corresponding first field plate FP1 in the third direction D3, thereby having substantially the same pattern and area, but this is not limited to this.

[0098] Furthermore, contact structures V1, V2, V3, V4, and V5 may be disposed in an interlayer dielectric layer (not shown) covering the first field plate FP1, the source region 44S, the drain region 44D, and the gate structure 34. Contact structures V1 and V2 may be disposed on and electrically connected to the corresponding first field plate FP1, respectively. Contact structure V3 may be disposed on and electrically connected to the source region 44S, contact structure V4 may be disposed on and electrically connected to the drain region 44D, and contact structure V5 may be disposed on and electrically connected to the gate structure 34. In some embodiments, each of the aforementioned contact structures may directly contact the corresponding component to form an electrical connection. Alternatively, a conductive auxiliary structure (such as, but not limited to, a conductive metal silicide) may be formed between each contact structure and the corresponding component, depending on design requirements, thereby reducing contact resistance, but the present invention is not limited thereto.

[0099] In some embodiments, the first connection structure CS1, the second connection structure CS2, and the third connection structure CS3 may be disposed on the interlayer dielectric layer. The first connection structure CS1, the second connection structure CS2, and the third connection structure CS3 may be disposed separately from each other (e.g., electrically separated and / or not directly connected), and the first connection structure CS1, the second connection structure CS2, and the third connection structure CS3 may be connected to corresponding contact structures to form an electrical connection. For example, the gate structure 34 may be electrically connected to at least one of the plurality of first field plates FP1 via the contact structure V5, the first connection structure CS1, and the contact structure V1. The source region 44S may be electrically connected to at least one of the plurality of first field plates FP1 via the contact structure V3, the second connection structure CS2, and the contact structure V2. The third connection structure CS3 may be electrically connected to the drain region 44D via the contact structure V4.

[0100] In some embodiments, each first field plate FP1 may extend along a first direction D1 and be repeatedly arranged along a second direction D2. Each first field plate FP1 may be separated from each other, and the gate structure 34 may extend generally along the second direction D2, but is not limited thereto. Furthermore, in some embodiments, the first field plate FP1 electrically connected to the gate structure 34 may be electrically separated from the first field plate FP1 electrically connected to the source region 44S. For example, the first field plate FP1 electrically connected to the gate structure 34 may be referred to as field plate F11, and the first field plate FP1 electrically connected to the source region 44S may be referred to as field plate F12, with field plate F11 and field plate F12 being electrically separated. In some embodiments, the gate structure 34 may be electrically connected to multiple first field plates FP1 (e.g., multiple field plates F11) among the plurality of first field plates FP1, and the source region 44S may be electrically connected to multiple first field plates FP1 (e.g., multiple field plates F12) among the plurality of first field plates FP1, with field plates F11 and field plates F12 being electrically separated. In some embodiments, each field plate F11 in the first field plates FP1 may be electrically connected to the gate structure 34 via the contact structure V1, the first connection structure CS1, and the contact structure V5, and each field plate F12 in the first field plates FP1 may be electrically connected to the source region 44S via the contact structure V2, the second connection structure CS2, and the contact structure V3. Furthermore, the first connection structure CS1 and a portion of the first field plate FP1 electrically connected to the source region 44S (e.g., the field plate F12) may overlap and be electrically separated from each other in a thickness direction (e.g., the third direction D3) of the semiconductor substrate 10, while the second connection structure CS2 and a portion of the first field plate FP1 electrically connected to the gate structure 34 (e.g., the field plate F11) may overlap and be electrically separated from each other in the third direction D3, but the present invention is not limited thereto. In other words, when viewing the semiconductor device 101 along the third direction D3, the first connection structure CS1 and the field plate F12 may partially overlap and be electrically separated from each other, while the second connection structure CS2 and the field plate F11 may partially overlap and be electrically separated from each other, but the present invention is not limited thereto.

[0101] In some embodiments, the field plate F11 electrically connected to the gate structure 34 can be used to increase accumulated charge, thereby reducing the on-resistance of the semiconductor device 101 and improving the electric field-induced safe operating area (E-SOA). The field plate F12 electrically connected to the source region 44S can be used to improve the gate-drain capacitance (Cgd), thereby reducing the gate charge of the semiconductor device 101 and improving the figure of merit (FOM) of the semiconductor device 101. Therefore, the effect of the first field plates FP1 in the semiconductor device 101 can be adjusted by adjusting the number, arrangement density (e.g., the distance DS between adjacent first field plates FP1 in the second direction D2), and / or dimension (e.g., the width W and / or length L of each first field plate FP1). In some embodiments, each first field plate FP1 may have substantially the same size (for example, substantially the same width W and / or length L), and multiple first field plates FP1 may be repeatedly arranged and aligned with each other along the second direction D2 at substantially the same pitch. In this case, the contribution of the field plate F11 electrically connected to the gate structure 34 and the field plate F12 electrically connected to the source region 44S to the characteristics of the semiconductor device can be adjusted by adjusting the number and / or setting position of the first contact structure V1 and the second contact structure V2. Therefore, there is no need to adjust the layout design of the first field plate FP1 to achieve the effect of simplifying the design process and / or reducing production costs, but the present invention is not limited to this.

[0102] Furthermore, power loss in a semiconductor device may include conduction loss, switching loss, and drive loss. Switching loss is affected by both on-resistance and gate charge, drive loss is affected by gate charge, and conduction loss is affected by on-resistance. Under relatively low switching frequency operation, the power loss of a semiconductor device primarily comes from conduction loss. Under relatively high switching frequency operation, the proportion of drive loss and switching loss in the overall power loss gradually increases with increasing frequency. In some embodiments, the field plate F11 electrically connected to the gate structure 34 can reduce on-resistance but also increases gate charge, thereby worsening drive loss and switching loss. Furthermore, the field plate F12 electrically connected to the source region 44S can reduce gate charge but also increases on-resistance, thereby worsening conduction loss and switching loss. Therefore, the number, arrangement density and / or size of the field plates F11 electrically connected to the gate structure 34 and the field plates F12 electrically connected to the source region 44S can be adjusted respectively according to the product requirements of the semiconductor device (such as requirements for different characteristics and / or requirements for operating switching frequency), so that the semiconductor device can meet the specification requirements.

[0103] For example, under conditions of relatively low switching frequency operation or / and greater emphasis on the safe operating area caused by the electric field, the number, arrangement density, and / or size of the field plates F11 electrically connected to the gate structure 34 may be increased; under conditions of relatively high switching frequency operation or / and greater emphasis on the quality factor, the number, arrangement density, and / or size of the field plates F12 electrically connected to the source region 44S may be increased; and under conditions of relatively intermediate switching frequency operation, the number, arrangement density, and / or size of the field plates F11 electrically connected to the gate structure 34 and the field plates F12 electrically connected to the source region 44S may be similar, but the present invention is not limited thereto. Therefore, the number of field plates F11 electrically connected to the gate structure 34 may be equal to or different from the number of field plates F12 electrically connected to the source region 44S, and the size of the field plates F11 electrically connected to the gate structure 34 may be equal to or different from the size of the field plates F12 electrically connected to the source region 44S. In some embodiments, the number of field plates F11 electrically connected to the gate structure 34 may be equal to the number of field plates F12 electrically connected to the source region 44S, and the multiple field plates F11 electrically connected to the gate structure 34 and the multiple field plates F12 electrically connected to the source region 44S may be alternately arranged along the second direction D2, so that the effects generated by the field plates F11 and the field plates F12 respectively can be evenly distributed in the semiconductor device.

[0104] In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or other semiconductor substrates formed of suitable semiconductor materials and / or structures. In some embodiments, the first well region 22, the second well region 24, the lightly doped region 42, the drain region 44D, the source region 44S, and the doped region 46 may each include a doped region formed in the semiconductor substrate 10 using a doping process (e.g., an implantation process). In other words, the first well region 22, the second well region 24, the lightly doped region 42, the drain region 44D, the source region 44S, and the doped region 46 may each include a portion of the semiconductor substrate 10 (i.e., the same material as the semiconductor substrate 10) and dopants formed in the semiconductor substrate 10. In addition, the isolation structure 12 may include a single layer or multiple layers of insulating material, such as an oxide insulating material or other suitable insulating material. The gate dielectric layer 32 may include a high-k dielectric material or other suitable dielectric material (e.g., silicon oxide). The gate structure 34 may comprise a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, but is not limited thereto. The spacer 36 may comprise a single layer or multiple layers of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The insulating pattern 38 may comprise an oxide insulating material (e.g., silicon oxide) or other suitable insulating material, and the first field plate FP1 may comprise a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material. Furthermore, the first connection structure CS1, the second connection structure CS2, the third connection structure CS3, the contact structure V1, the contact structure V2, the contact structure V3, the contact structure V4, and the contact structure V5 may each comprise a barrier layer (not shown) and a conductive material (not shown) located on the barrier layer, but is not limited thereto. The barrier layer may include titanium nitride, tantalum nitride, or other suitable barrier materials, and the conductive material may include a material with relatively low resistivity such as tungsten, aluminum, copper, titanium aluminide, titanium, etc., but is not limited thereto.

[0105] The following describes various embodiments of the present invention. To simplify the description, the following description focuses on the differences between the embodiments and does not repeat the similarities. In addition, the same elements in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the various embodiments.

[0106] See also Figures 4 to 6 . Figure 4 FIG. 1 is a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 5 FIG. 1 is a cross-sectional view of the semiconductor device 102 of this embodiment. Figure 6FIG. 1 is another cross-sectional view of the semiconductor device 102 of this embodiment. Figure 4 It can be regarded as a top view or / and a layout diagram of the semiconductor device 102 of this embodiment, and some components of the semiconductor device 102 (such as the source region, the drain region, the doped region, the well region, the isolation structure, the spacer and the gate dielectric layer, etc.) are not shown. Figure 4 middle. Figure 5 Can be considered as Figure 4 The cross-sectional view shown by the C-C' section line is Figure 6 Can be considered as Figure 4 The cross-sectional view is shown along the D-D' section line, but is not limited thereto. Figures 4 to 6 As shown, the semiconductor device 102 includes a semiconductor substrate 10, a first gate structure GS1, a second gate structure GS2, a first source region SE1, a first drain region DE1, a second source region SE2, a second drain region DE2, a plurality of first field plates FP1, and a plurality of second field plates FP2. The first gate structure GS1 and the second gate structure GS2 are disposed on the semiconductor substrate 10. The first source region SE1 and the first drain region DE1 are disposed in the semiconductor substrate 10 and are located on opposite sides of the first gate structure GS1 in a first direction D1. The second source region SE2 and the second drain region DE2 are disposed in the semiconductor substrate 10 and are located on opposite sides of the second gate structure GS2 in the first direction D1. The first field plates FP1 and the second field plates FP2 are disposed on the semiconductor substrate 10. Each first field plate FP1 is partially located above the first gate structure GS1 and partially located between the first gate structure GS1 and the first drain region DE1. The first gate structure GS1 is electrically connected to at least one of the plurality of first field plates FP1. Each second field plate FP2 is partially located on the second gate structure GS2 and partially located between the second gate structure GS2 and the second drain region DE2 , and the second source region SE2 is electrically connected to at least one of the plurality of second field plates FP2 .

[0107] In some embodiments, the semiconductor device 102 can be considered to be formed by two semiconductor devices of the first embodiment arranged in a substantially mirror-symmetrical manner, but the present invention is not limited thereto. In some embodiments, the semiconductor device 102 may further include an isolation structure 12, a first well region 22, a second well region 24, a first gate dielectric layer 32A, a second gate dielectric layer 32B, spacers 36, a plurality of first insulating patterns 38A, a plurality of second insulating patterns 38B, a first lightly doped region 42A, a second lightly doped region 42B, a doped region 46, a plurality of contact structures (such as the contact structure V1, contact structure V2, contact structure V3, contact structure V4, and contact structure V5 described above), two first connection structures CS1, a second connection structure CS2, and two third connection structures CS3, but the present invention is not limited thereto. The isolation structure 12, the first well region 22, the second well region 24, a first lightly doped region 42A, a second lightly doped region 42B and the doped region 46 are arranged in the semiconductor substrate 10, and the first gate dielectric layer 32A, the second gate dielectric layer 32B, the spacer 36, the first insulating pattern 38A, the second insulating pattern 38B, each contact structure and each connection structure are arranged on the semiconductor substrate 10.

[0108] A portion of the first well region 22 and the first portion 24A of the second well region 24 may be located on opposite sides of the first gate structure GS1 in the first direction D1, respectively. A portion of the first well region 22 and the second portion 24B of the second well region 24 may be located on opposite sides of the second gate structure GS2 in the first direction D1, respectively. Doped region 46, first source region SE1, second source region SE2, first lightly doped region 42A, and second lightly doped region 42B may be located in the first well region 22. The first portion 24A and the second portion 24B of the second well region 24 may be at least partially located on opposite sides of the first well region 22 in the first direction D1, respectively. The first drain region DE1 and the second drain region DE2 may be located in the first portion 24A and the second portion 24B, respectively. In some embodiments, when the semiconductor device 102 is viewed along the third direction D3, the first gate structure GS1 and the second gate structure GS2 may extend along the second direction D2 and be arranged parallel to each other, the doped region 46, the first source region SE1 and the second source region SE2 may be located between the first gate structure GS1 and the second gate structure GS2 in the first direction D1, and the doped region 46 may be located between the first source region SE1 and the second source region SE2 in the first direction D1.

[0109] At least a portion of the first gate dielectric layer 32A may be located between the first gate structure GS1 and the semiconductor substrate 10 in the third direction D3, and at least a portion of the second gate dielectric layer 32B may be located between the second gate structure GS2 and the semiconductor substrate 10 in the third direction D3. A portion of the spacer 36 may be disposed on the sidewall of the first gate structure GS1 and above the first lightly doped region 42A in the third direction D3, and another portion of the spacer 36 may be disposed on the sidewall of the second gate structure GS2 and above the second lightly doped region 42B in the third direction D3, but the present invention is not limited thereto. Each first insulating pattern 38A may be partially located above the first gate structure GS1 and partially located between the first gate structure GS1 and the first drain region DE1, and each first insulating pattern 38A may be disposed between the semiconductor substrate 10 and one of the plurality of first field plates FP1. Each second insulating pattern 38B may be partially located on the second gate structure GS2 and partially located between the second gate structure GS2 and the second drain region DE2 , and each second insulating pattern 38B may be disposed between the semiconductor substrate 10 and one of the plurality of second field plates FP2 .

[0110] Each first field plate FP1 may extend along the first direction D1 and be repeatedly arranged along the second direction D2, and each second field plate FP2 may also extend along the first direction D1 and be repeatedly arranged along the second direction D2. In some embodiments, the plurality of first field plates FP1 and the plurality of second field plates FP2 may be substantially mirror-symmetrical with respect to the doped region 46 as the central axis, the plurality of first insulation patterns 38A and the plurality of second insulation patterns 38B may be substantially mirror-symmetrical with respect to the doped region 46 as the central axis, the first gate structure GS1 and the second gate structure GS2 may be substantially mirror-symmetrical with respect to the doped region 46 as the central axis, the first source region SE1 and the second source region SE2 may be substantially mirror-symmetrical with respect to the doped region 46 as the central axis, and the first drain region DE1 and the second drain region DE2 may be substantially mirror-symmetrical with respect to the doped region 46 as the central axis, but the present invention is not limited thereto.

[0111] In addition, contact structure V1, contact structure V2, contact structure V3, contact structure V4 and contact structure V5 can be arranged in an interlayer dielectric layer (not shown) covering the first field plate FP1, the second field plate FP2, the first source region SE1, the first drain region DE1, the second source region SE2, the second drain region DE2, the first gate structure GS1 and the second gate structure GS2. Contact structure V1 and contact structure V2 may be respectively disposed on the corresponding first field plate FP1 or second field plate FP2 and electrically connected thereto. Contact structure V3 may be disposed on the first source region SE1 or second source region SE2 and electrically connected thereto. Contact structure V4 may be disposed on the first drain region DE1 or second drain region DE2 and electrically connected thereto. Contact structure V5 may be disposed on the first gate structure GS1 or second gate structure GS2 and electrically connected thereto. First, second, and third connection structures CS1, CS2, and CS3 may be disposed on the aforementioned interlayer dielectric layer and may be connected to the corresponding contact structures to form an electrical connection.

[0112] Similar to the first embodiment described above, each first field plate FP1 may be electrically connected to the first gate structure GS1 or the first source region SE1, and each second field plate FP2 may be electrically connected to the second gate structure GS2 or the second source region SE2. For example, the first field plate FP1 electrically connected to the first gate structure GS1 may be considered as field plate F11, the first field plate FP1 electrically connected to the first source region SE1 may be considered as field plate F12, the second field plate FP2 electrically connected to the second gate structure GS2 may be considered as field plate F21, and the second field plate FP2 electrically connected to the second source region SE2 may be considered as field plate F22. In some embodiments, field plate F11 may be electrically separated from field plate F12, field plate F21 may be electrically separated from field plate F22, and field plate F12 may be electrically connected to field plate F22, but this is not limiting. In other words, the first source region SE1 can be electrically connected to at least one of the multiple first field plates FP1, the second gate structure GS2 can be electrically connected to at least one of the multiple second field plates FP2, the first field plate FP1 (for example, field plate F11) electrically connected to the first gate structure GS1 is electrically separated from the first field plate FP1 (for example, field plate F12) electrically connected to the first source region SE1, the second field plate FP2 (for example, field plate F21) electrically connected to the second gate structure GS2 is electrically separated from the second field plate FP2 (for example, field plate F22) electrically connected to the second source region SE2, and the field plate F12 electrically connected to the first source region SE1 can be electrically connected to the field plate F22 electrically connected to the second source region SE2, but is not limited to this.

[0113] In some embodiments, the first gate structure GS1 may be electrically connected to at least one of the plurality of first field plates FP1 via the contact structure V5, the first connection structure CS1, and the contact structure V1; the first source region SE1 may be electrically connected to at least one of the plurality of first field plates FP1 via the contact structure V3, the second connection structure CS2, and the contact structure V2; the second gate structure GS2 may be electrically connected to at least one of the plurality of second field plates FP2 via the contact structure V5, the first connection structure CS1, and the contact structure V1; the second source region SE2 may be electrically connected to at least one of the plurality of second field plates FP2 via the contact structure V3, the second connection structure CS2, and the contact structure V2; and the third connection structure CS3 may be electrically connected to the first drain region DE1 or the second drain region DE2 via the contact structure V4, but the present invention is not limited thereto. In some embodiments, all of the first field plates FP1 may be electrically connected to the first gate structure GS1, and all of the second field plates FP2 may be electrically connected to the second source region SE2, depending on design requirements.

[0114] In some embodiments, the first source region SE1 and the second source region SE2 can be electrically connected to each other. For example, the first source region SE1 and the second source region SE2 can be electrically connected through the doped region 46 and the field plate F12 and the field plate F22 can be electrically connected. The doped region 46, the first source region SE1 and the second source region SE2 can be regarded as a common source structure, but is not limited to this. In addition, the material composition of the first gate structure GS1 and the second gate structure GS2 may be the same as or similar to the material composition of the above-mentioned gate structure 34, the material composition of the first gate dielectric layer 32A and the second gate dielectric layer 32B may be the same as or similar to the material composition of the above-mentioned gate dielectric layer 32, the material composition of the first source region SE1, the second source region SE2, the first drain region DE1 and the second drain region DE2 may be the same as or similar to the material composition of the above-mentioned source region 44S and the drain region 44D, the material composition of the second field plate FP2 may be the same as or similar to the material composition of the first field plate FP1, and the material composition of the first insulating pattern 38A and the second insulating pattern 38B may be the same as or similar to the material composition of the above-mentioned insulating pattern 38, but is not limited to this.

[0115] Similar to the first embodiment described above, the degree of effect produced by the first field plates FP1 and the second field plates FP2 in the semiconductor device 102 can be adjusted by adjusting the number, arrangement density, and / or size of each first field plate FP1 and each second field plate FP2. In other words, depending on design requirements, the number of first field plates FP1 can be made equal to or different from the number of second field plates FP2, the arrangement density of first field plates FP1 can be made equal to or different from the arrangement density of second field plates FP2, or the size of first field plates FP1 can be made equal to or different from the size of second field plates FP2. Furthermore, the number, arrangement density, and / or size of the field plates F11 electrically connected to the first gate structure GS1, the field plates F12 electrically connected to the first source region SE1, the field plates F21 electrically connected to the second gate structure GS2, and the field plates F22 electrically connected to the second source region SE2 can also be adjusted based on product requirements of the semiconductor device, thereby ensuring that the semiconductor device meets specification requirements. In other words, the number, arrangement density, and / or size of the field plates F11 may be the same as or different from those of the field plates F12 , and the number, arrangement density, and / or size of the field plates F21 may be the same as or different from those of the field plates F22 .

[0116] In some embodiments, the number of field plates F11 electrically connected to the first gate structure GS1 may be equal to the number of field plates F12 electrically connected to the first source region SE1, the number of field plates F21 electrically connected to the second gate structure GS2 may be equal to the number of field plates F22 electrically connected to the second source region SE2, and multiple field plates F11 and multiple field plates F12 may be alternately arranged along the second direction D2, and multiple field plates F21 and multiple field plates F22 may be alternately arranged along the second direction D2, so that the effects generated by the field plates F11, F12, F21 and F22 respectively can be evenly distributed in the semiconductor device.

[0117] See also Figure 7 . Figure 7 FIG. 1 is a schematic diagram of a semiconductor device 103 according to a third embodiment of the present invention. Figure 7 As shown, the difference from the first embodiment described above is that the insulating pattern 38 of this embodiment can be arranged corresponding to multiple first field plates FP1, and multiple first field plates FP1 can be arranged on the same insulating pattern 38. The insulating pattern 38 located between adjacent first field plates FP1 in the second direction D2 can further adjust the influence of the first field plates FP1 on the electric field distribution and / or reduce the negative impact of the patterning process for forming the first field plates FP1 on the gate structure 34. In addition, the arrangement of the insulating pattern 38 of this embodiment can also be applied to other embodiments of the present invention according to design requirements. For example, in the second embodiment described above, multiple first field plates can be arranged on the same first insulating pattern and / or multiple second field plates can be arranged on the same second insulating pattern.

[0118] See also Figure 8 . Figure 8 FIG. 1 is a schematic diagram of a semiconductor device 104 according to a fourth embodiment of the present invention. Figure 8 As shown, in some embodiments, the number of field plates F11 electrically connected to the gate structure 34 may be different from the number of field plates F12 electrically connected to the source region, and the arrangement density of the field plates F11 electrically connected to the gate structure 34 may be different from the arrangement density of the field plates F12 electrically connected to the source region. In addition, the minimum distance in the second direction D2 between two adjacent field plates F11 among the plurality of field plates F11 electrically connected to the gate structure 34 (e.g., Figure 8 The distance DS1 shown in FIG. 5 may be different from the minimum distance in the second direction D2 between two adjacent field plates F12 among the plurality of field plates F12 electrically connected to the source region (eg, Figure 8 For example, the number of field plates F11 electrically connected to the gate structure 34 may be less than the number of field plates F12 electrically connected to the source region, and the arrangement density of the field plates F11 electrically connected to the gate structure 34 may be lower than the arrangement density of the field plates F12 electrically connected to the source region. Moreover, the minimum distance between two adjacent field plates F11 in the second direction D2 may be greater than the minimum distance between two adjacent field plates F12 in the second direction D2, thereby relatively increasing the electrical influence of the field plates F12 electrically connected to the source region on the semiconductor device.

[0119] See also Figure 9 . Figure 9 FIG. 1 is a schematic diagram of a semiconductor device 105 according to a fifth embodiment of the present invention. Figure 9 As shown, in the semiconductor device 105, the number of field plates F11 electrically connected to the gate structure 34 may be greater than the number of field plates F12 electrically connected to the source region, and the arrangement density of the field plates F11 electrically connected to the gate structure 34 may be higher than the arrangement density of the field plates F12 electrically connected to the source region, and the minimum distance between two adjacent field plates F11 in the second direction D2 (for example, the distance DS1) may be smaller than the minimum distance between two adjacent field plates F12 in the second direction D2 (for example, the distance DS2), thereby relatively increasing the electrical influence of the field plates F11 electrically connected to the gate structure 34 on the semiconductor device.

[0120] See also Figure 10 . Figure 10 FIG. 1 is a schematic diagram of a semiconductor device 106 according to a sixth embodiment of the present invention. Figure 10As shown, in semiconductor device 106, the dimensions of field plates F11 electrically connected to gate structure 34 may differ from the dimensions of field plates F12 electrically connected to the source region. For example, the width W1 of field plates F11 electrically connected to gate structure 34 may differ from the width W2 of field plates F12 electrically connected to the source region, but the present invention is not limited thereto. For example, the width W1 of field plates F11 electrically connected to gate structure 34 may be greater than the width W2 of field plates F12 electrically connected to the source region, and the length of field plates F11 electrically connected to gate structure 34 may be substantially equal to the length of field plates F12 electrically connected to the source region. This can reduce the electrical impact of field plates F11 electrically connected to gate structure 34 on the semiconductor device when the number of field plates F11 and F12 is equal. Furthermore, the width of the field plates described above may also be considered as the length of the field plates in the second direction D2, but the present invention is not limited thereto.

[0121] See also Figure 11 . Figure 11 FIG. 1 is a schematic diagram of a semiconductor device 107 according to a seventh embodiment of the present invention. Figure 11 As shown, in the semiconductor device 107, the size of the field plate F11 electrically connected to the gate structure 34 may be different from the size of the field plate F12 electrically connected to the source region. For example, the length L1 of the field plate F11 electrically connected to the gate structure 34 may be different from the length L2 of the field plate F12 electrically connected to the source region, but the present invention is not limited to this. For example, the length L1 of the field plate F11 electrically connected to the gate structure 34 in the first direction D1 may be smaller than the length L2 of the field plate F12 electrically connected to the source region in the first direction D1. In this way, when the number of field plates F11 and F12 is equal, the electrical impact of the field plate F12 electrically connected to the source region on the semiconductor device can be relatively reduced.

[0122] See also Figure 12 . Figure 12 FIG. 1 is a schematic diagram of a semiconductor device 108 according to an eighth embodiment of the present invention. Figure 12 As shown, in the semiconductor device 108, all first field plates FP1 may be electrically connected to the first gate structure GS1, and all second field plates FP2 may be electrically connected to the second source region ( Figure 12 In other words, each first field plate FP1 can be a field plate F11 electrically connected to the first gate structure GS1, and each second field plate FP2 can be a field plate F22 electrically connected to the second source region. This prevents the first connection structure CS1 and the second connection structure CS2 from overlapping with field plates that are not electrically connected thereto, thereby preventing negative effects.

[0123] See also Figure 13 . Figure 13 FIG. 1 is a schematic diagram of a semiconductor device 109 according to a ninth embodiment of the present invention. Figure 13 As shown, in the semiconductor device 109, the number of the first field plates FP1 may be different from the number of the second field plates FP2, and the arrangement density of the first field plates FP1 may be different from the arrangement density of the second field plates FP2, thereby adjusting the effect of the field plates on the first gate structure GS1 and the second gate structure GS2. For example, the number of the first field plates FP1 may be greater than the number of the second field plates FP2, and the arrangement density of the first field plates FP1 may be higher than the arrangement density of the second field plates FP2, but the present invention is not limited thereto. In this case, if all the first field plates FP1 are electrically connected to the first gate structure GS1, and all the second field plates FP2 are electrically connected to the second source region ( Figure 12 By electrically connecting the field plate electrically connected to the gate structure (not shown), the electrical influence of the field plate electrically connected to the gate structure on the semiconductor device can be relatively increased or / and the electrical influence of the field plate electrically connected to the source region on the semiconductor device can be relatively reduced.

[0124] See also Figure 14 . Figure 14 FIG. 1 is a schematic diagram of a semiconductor device 110 according to a tenth embodiment of the present invention. Figure 14 As shown, in the semiconductor device 110, the size of at least one of the plurality of first field plates FP1 may be different from the size of at least one of the plurality of second field plates FP2, thereby adjusting the effect of the field plates on the first gate structure GS1 and the second gate structure GS2. For example, the projected area of each second field plate FP2 in the third direction D3 may be larger than the projected area of each first field plate FP1 in the third direction D3, but the present invention is not limited thereto.

[0125] In summary, in the semiconductor device of the present invention, the gate structure can be electrically connected to at least one field plate, and the source region can be electrically connected to at least one field plate, thereby adjusting the on-resistance, gate charge and other characteristics of the semiconductor device, thereby achieving the effect of improving the specific electrical performance of the semiconductor device and / or reducing power consumption.

[0126] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates; A gate structure is disposed on the semiconductor substrate; a source region and a drain region, the source region and the drain region being disposed in the semiconductor substrate and respectively located at two opposite sides of the gate structure in the first direction; as well as A plurality of field plates are disposed on the semiconductor substrate, wherein each of the field plates is partially located above the gate structure and partially located between the gate structure and the drain region, the gate structure is electrically connected to at least one of the plurality of field plates, and the source region is electrically connected to at least one of the plurality of field plates, The plurality of field plates are arranged along a direction parallel to the semiconductor substrate. 2 . The semiconductor device of claim 1 , wherein the field plate electrically connected to the gate structure is electrically separated from the field plate electrically connected to the source region. The semiconductor device as claimed in claim 1 , wherein each of the field plates extends along the first direction. 4 . The semiconductor device as claimed in claim 1 , wherein the plurality of field plates are repeatedly arranged along a second direction, and the second direction is orthogonal to the first direction. The semiconductor device as claimed in claim 4 , wherein the gate structure extends along the second direction. 6 . The semiconductor device of claim 1 , wherein the gate structure is electrically connected to a plurality of the plurality of field plates, and the source region is electrically connected to a plurality of the plurality of field plates.

7. A semiconductor device as described in claim 6, wherein the multiple field plates electrically connected to the gate structure and the multiple field plates electrically connected to the source region are arranged along a second direction, the second direction is orthogonal to the first direction, and the minimum distance between two adjacent ones of the multiple field plates electrically connected to the gate structure in the second direction is different from the minimum distance between two adjacent ones of the multiple field plates electrically connected to the source region in the second direction. 8 . The semiconductor device of claim 6 , wherein the number of the field plates electrically connected to the gate structure is equal to the number of the field plates electrically connected to the source region. 9 . The semiconductor device of claim 6 , wherein the number of the plurality of field plates electrically connected to the gate structure is less than the number of the plurality of field plates electrically connected to the source region. 10 . The semiconductor device of claim 6 , wherein the number of the field plates electrically connected to the gate structure is greater than the number of the field plates electrically connected to the source region. 11 . The semiconductor device of claim 1 , wherein a size of the field plate electrically connected to the gate structure is equal to a size of the field plate electrically connected to the source region. 12 . The semiconductor device of claim 1 , wherein a width of the field plate electrically connected to the gate structure is different from a width of the field plate electrically connected to the source region. 13 . The semiconductor device of claim 1 , wherein a length of the field plate electrically connected to the gate structure is different from a length of the field plate electrically connected to the source region.

14. The semiconductor device according to claim 1, further comprising: An insulating pattern is disposed on the semiconductor substrate, wherein the insulating pattern is partially located above the gate structure and partially located between the gate structure and the drain region, and the plurality of field plates are disposed on the insulating pattern.

15. The semiconductor device according to claim 1, further comprising: A plurality of insulating patterns are arranged on the semiconductor substrate, wherein each of the insulating patterns is partially located on the gate structure and partially located between the gate structure and the drain region, and each of the insulating patterns is arranged between the semiconductor substrate and one of the plurality of field plates.

16. The semiconductor device according to claim 1, further comprising: a first connection structure, wherein the gate structure is electrically connected to at least one of the plurality of field plates through the first connection structure; as well as A second connection structure is provided, wherein the source region is electrically connected to at least one of the plurality of field plates through the second connection structure, and the first connection structure and the second connection structure are separated from each other. 17 . The semiconductor device of claim 16 , wherein the first connection structure and a portion of the field plate electrically connected to the source region overlap in a thickness direction of the semiconductor substrate. 18 . The semiconductor device of claim 16 , wherein the second connection structure and a portion of the field plate electrically connected to the gate structure overlap in a thickness direction of the semiconductor substrate.

19. A semiconductor device, characterized in that: include: semiconductor substrates; A first gate structure is disposed on the semiconductor substrate; a first source region and a first drain region, wherein the first source region and the first drain region are disposed in the semiconductor substrate and are respectively located at two opposite sides of the first gate structure in a first direction; A second gate structure is disposed on the semiconductor substrate; a second source region and a second drain region, wherein the second source region and the second drain region are disposed in the semiconductor substrate and are respectively located at two opposite sides of the second gate structure in the first direction; a plurality of first field plates disposed on the semiconductor substrate, wherein each of the first field plates is partially located above the first gate structure and partially located between the first gate structure and the first drain region, and the first gate structure is electrically connected to at least one of the plurality of first field plates; as well as A plurality of second field plates are disposed on the semiconductor substrate, wherein each second field plate is partially located above the second gate structure and partially located between the second gate structure and the second drain region, and the second source region is electrically connected to at least one of the plurality of second field plates. 20 . The semiconductor device of claim 19 , wherein the first source region and the second source region are located between the first gate structure and the second gate structure in the first direction. 21 . The semiconductor device of claim 19 , wherein the first source region is electrically connected to the second source region.

22. A semiconductor device as described in claim 19, wherein the first source region is electrically connected to at least one of the multiple first field plates, the second gate structure is electrically connected to at least one of the multiple second field plates, the first field plate electrically connected to the first gate structure is electrically separated from the first field plate electrically connected to the first source region, and the second field plate electrically connected to the second gate structure is electrically separated from the second field plate electrically connected to the second source region. 23 . The semiconductor device of claim 22 , wherein the first field plate electrically connected to the first source region is electrically connected to the second field plate electrically connected to the second source region.

24. The semiconductor device according to claim 19, further comprising: The doped region is disposed in the semiconductor substrate and is located between the first source region and the second source region in the first direction. 25 . The semiconductor device of claim 24 , wherein the plurality of first field plates and the plurality of second field plates are mirror-symmetrical with respect to the doped region as a central axis. 26 . The semiconductor device of claim 19 , wherein the plurality of first field plates are repeatedly arranged along a second direction, the plurality of second field plates are repeatedly arranged along the second direction, and the second direction is orthogonal to the first direction.

27. A semiconductor device, characterized in that: include: semiconductor substrates; A gate structure is disposed on the semiconductor substrate; a source region and a drain region, the source region and the drain region being disposed in the semiconductor substrate and respectively located at two opposite sides of the gate structure in the first direction; as well as A plurality of field plates are disposed on the semiconductor substrate, wherein each of the field plates is partially located above the gate structure and partially located between the gate structure and the drain region, the gate structure is electrically connected to a plurality of the plurality of field plates, and the source region is electrically connected to a plurality of the plurality of field plates, the plurality of field plates electrically connected to the gate structure and the plurality of field plates electrically connected to the source region are alternately arranged along a second direction, and the second direction is orthogonal to the first direction. The plurality of field plates are arranged along a direction parallel to the semiconductor substrate.

28. A semiconductor device, characterized in that include: semiconductor substrates; A gate structure is disposed on the semiconductor substrate; a source region and a drain region, the source region and the drain region being disposed in the semiconductor substrate and respectively located at two opposite sides of the gate structure in the first direction; as well as A plurality of field plates are disposed on the semiconductor substrate, wherein each of the field plates is partially located above the gate structure and partially located between the gate structure and the drain region, the gate structure is electrically connected to at least one of the plurality of field plates, and the source region is electrically connected to at least one of the plurality of field plates, wherein the size of the field plate electrically connected to the gate structure is different from the size of the field plate electrically connected to the source region, The plurality of field plates are arranged along a direction parallel to the semiconductor substrate.

29. A semiconductor device, characterized in that include: semiconductor substrates; A first gate structure is disposed on the semiconductor substrate; a first source region and a first drain region, wherein the first source region and the first drain region are disposed in the semiconductor substrate and are respectively located at two opposite sides of the first gate structure in a first direction; A second gate structure is disposed on the semiconductor substrate; a second source region and a second drain region, wherein the second source region and the second drain region are disposed in the semiconductor substrate and are respectively located at two opposite sides of the second gate structure in the first direction; a plurality of first field plates disposed on the semiconductor substrate, wherein each of the first field plates is partially located above the first gate structure and partially located between the first gate structure and the first drain region, and the first gate structure is electrically connected to at least one of the plurality of first field plates; as well as A plurality of second field plates are disposed on the semiconductor substrate, wherein each of the second field plates is partially located above the second gate structure and partially located between the second gate structure and the second drain region, the second source region is electrically connected to at least one of the plurality of second field plates, and the number of the plurality of first field plates is different from the number of the plurality of second field plates.

30. A semiconductor device, characterized in that: include: semiconductor substrates; A first gate structure is disposed on the semiconductor substrate; a first source region and a first drain region, wherein the first source region and the first drain region are disposed in the semiconductor substrate and are respectively located at two opposite sides of the first gate structure in a first direction; A second gate structure is disposed on the semiconductor substrate; a second source region and a second drain region, wherein the second source region and the second drain region are disposed in the semiconductor substrate and are respectively located at two opposite sides of the second gate structure in the first direction; a plurality of first field plates disposed on the semiconductor substrate, wherein each of the first field plates is partially located above the first gate structure and partially located between the first gate structure and the first drain region, and the first gate structure is electrically connected to at least one of the plurality of first field plates; as well as A plurality of second field plates are disposed on the semiconductor substrate, wherein each of the second field plates is partially located above the second gate structure and partially located between the second gate structure and the second drain region, the second source region is electrically connected to at least one of the plurality of second field plates, and the size of at least one of the plurality of first field plates is different from the size of at least one of the plurality of second field plates.

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