Stacked switch unit and method for use in a stacked switch unit

Abstract

A stackable switch unit and a method for using a stackable switch unit, comprising: the stackable switch unit has a plurality of signal ports, and the plurality of signal ports include a master / slave control port; and during a power-on startup program of the stackable switch unit, automatically determine whether the stackable switch unit is a master switch unit or a slave switch unit according to the signal level of the master / slave control port and / or the content of the data obtained from the master / slave control port.

Description

Technical Field

[0001] The present invention relates to a switch mechanism, and more particularly to a stackable switch unit and a method for using the stackable switch unit. Background Art

[0002] Generally speaking, traditional switch units can only allow the transmission of switch packets at the bottom layer of their systems. In addition, if a user needs to control multiple switch units, correspondingly, multiple sets of connection interfaces are required to control the multiple switch units respectively. However, this traditional approach wastes the number of ports and also occupies a relatively large circuit area. Summary of the Invention

[0003] Therefore, one of the objectives of the present invention is to provide a stackable switch unit and a corresponding method to solve the problems of the prior art.

[0004] According to an embodiment of the present invention, there is disclosed a method for using a stackable switch unit, which can be stacked with at least one other stackable switch unit. The method includes: providing the stackable switch unit, which has a plurality of signal ports, and the plurality of signal ports include at least one master / slave control port; during a startup program of the stackable switch unit, automatically determining whether the stackable switch unit is a master switch unit or a slave switch unit according to at least one signal level of the at least one master / slave control port and / or the content of at least one bit of the data obtained from the at least one master / slave control port; and when the stackable switch unit is the master switch unit, generating a stack configuration setting, and transmitting the stack configuration setting to the at least one other stackable switch unit connected to the stackable switch unit through at least one of the plurality of signal ports of the stackable switch unit, so that the stackable switch unit and the at least one other switch unit complete a stack connection.

[0005] According to an embodiment of the present invention, there is further disclosed a method for using a stackable switch unit, which can be stacked with at least one other stackable switch unit, and the method includes: providing the stackable switch unit, which has a plurality of signal ports, and the plurality of signal ports include at least one master / slave control port; during a power-on startup program of the stackable switch unit, automatically determining whether the stackable switch unit is a master switch unit or a slave switch unit according to at least one signal level of the at least one master / slave control port and / or the content of at least one bit of data obtained from the at least one master / slave control port; and when the stackable switch unit is the slave switch unit, receiving, through at least one of a first signal port and a second signal port of the stackable switch unit, a stack configuration setting generated by a specific master switch unit and / or relayed by another slave switch unit, so that the stackable switch unit completes a stack connection with the specific master switch unit or the other slave switch unit, wherein the at least one other stackable switch unit includes the specific master switch unit and the other slave switch unit.

[0006] According to an embodiment of the present invention, there is further disclosed a stackable switch unit, which can be stacked with at least one other stackable switch unit, and the stackable switch unit includes a plurality of signal ports and a processing circuit. The plurality of signal ports include at least one master / slave control port. The processing circuit is coupled to the plurality of signal ports and is used to: during a power-on startup program of the stackable switch unit, automatically determine whether the stackable switch unit is a master switch unit or a slave switch unit according to at least one signal level of the at least one master / slave control port and / or the content of at least one bit of data obtained from the at least one master / slave control port. Brief Description of the Drawings

[0007] Figure 1 Schematic diagram of one or more switch units according to an embodiment of the present application.

[0008] Figure 2 Exemplary schematic diagram of a switch device according to an embodiment of the present invention.

[0009] Figure 3 Schematic diagram of the method flow for generating and storing a stack file and a program into a flash memory according to an embodiment of the present invention.

[0010] Figure 4 Schematic diagram of the method flow for determining a switch unit as a master / slave switch unit during system startup according to an embodiment of the present invention.

[0011] Figure 5Schematic diagram of the operation and communication of two switch units in the stack for the embodiments of the present invention during system startup.

[0012]

Symbol Description

[0013] 100, 100A~100C: Switch device

[0014] 101, 101A~101D: Switch unit

[0015] 102A~102D: Processing circuit

[0016] 105: Flash memory

[0017] 110: Control device

[0018] SA0, SA1, SB0, SB1, SC0, SC1, SD0: Signal port

[0019] S305~S320, S405~S445, S505A~S540A, S505B~S540B: Steps Detailed implementation

[0020] The present invention aims to provide a stacking / stackable switch unit, such as a network switch unit, which can fully and independently perform the operation of a network switch and can also be set to cooperate with one or more switch units. A group of stacked switch units has the characteristics of a single switch unit / device but has a larger number of input / output ports (or pin numbers).

[0021] The switch unit of the embodiment of the present invention has multiple signal ports, such as a network switch unit with N ports (N is, for example, 16, but not limited). Among them, multiple, for example, M switch units can be stacked to form a single switch unit. And the user can directly determine the stacking topology of the M switch units according to the circuit design of one or more signal ports / pins of the M switch units or other external circuit designs. After that, the user can achieve the purpose of automatic connection of all switch units, automatic determination of the master / slave unit, realization of the stacking topology, and update of the same software / firmware program for all switch units under the condition of only setting data for one switch unit / device.

[0022] Please refer to Figure 1 , Figure 1 The figure shows a schematic diagram of one or more switch units of the embodiment of the present application. As Figure 1As shown, the switch device 100 includes a single switch unit, while the switch device 100A includes M stacked switch units (M is 2 for example), and the switch device 100B includes M stacked switch units (M is 4 for example). It should be noted that the dashed boxes of the switch devices 100A and 100B indicate that when accessed externally by the user, the stack of multiple switch units can be regarded as a single switch device (or unit). That is, the user's operation behavior is similar to that of only a single switch unit, and its actual operation is, for example, carried out by the 2 switch units 101 in the switch device 100A (or the 4 switch units 101 in the switch device 100B) working together to automatically connect, determine the master / slave unit relationship, implement the stack topology, update the software / firmware programs of all switch units, and process network switching packets, etc.

[0023] In addition, a switch unit 101 has N signal ports (or pins), and when stacked, it will stack-connect (stacking connection) with a signal port of at least another switch unit 101 through at least one signal port. The communication connection interface between the signal ports uses, for example, the USXGMII interface, but is not limited to this. For the overall switch device 100A, since the switch unit 101 with N signal ports uses one signal port to stack-connect with a signal port of another switch unit 101, therefore, the switch device 100A can have at most (2N - 2) signal ports as input / output; for the overall switch device 100B, since 6 signal ports are used for stack connection (two switch units 101 that are only connected to one switch unit 101 use one signal port, and the other two switch units 101 that are connected to two switch units 101 use two signal ports), therefore, the switch device 100B can have at most (4N - 6) signal ports as input / output. In addition, it should be noted that the part of the dashed squares shown in the switch devices 100A and 100B is used to indicate that it is, for example, formed by stacking the chip circuits of multiple switch units on a circuit board. However, this is not a limitation of this case. In possible embodiments, multiple switch units can also be circuit-packaged after stacking to form a chip circuit of a switch device.

[0024] Please refer to Figure 2 , Figure 2 which is a schematic diagram of an example of the switch device 100C in the first embodiment of the present invention. As Figure 2As shown, multiple switch units (e.g., four, but this number is not limiting) 101A to 101D form a stacked topology to form the switch device 100C. Each switch unit 101A to 101D includes a plurality of signal ports ( / or pins) and a processing circuit. For example, a switch unit 101A as the main switch unit includes a processing circuit 102A and includes a serial peripheral interface (SPI) formed by using a signal port to connect to a flash memory 105 (which can be an external memory), a data transfer interface formed by using another signal port to receive data from a control device 110, a buffer access interface formed by a signal port to receive instructions (or commands) from the control device 110, at least one signal port SA0 and SA1 for stack connection, and other signal ports. One of the signal port SA0 and the signal port SA1 (e.g., SA1, but not limited) is connected to another switch unit (e.g., 101B) through, for example, a USXGMII interface (but not limited); the control device 110 is, for example, an external electronic control unit or a single-chip device, used to send commands and data to the main switch unit 101A to control the data transfer and operation behavior of the main switch unit 101A and all other slave switch units 101B to 101D.

[0025] In addition, a switch unit 101B as a slave switch unit, for example, includes a processing circuit 102B, at least one signal port SB0 and SB1 for stack connection, and other signal ports. The signal port SB0 is connected to the signal port SA1 of the main switch unit 101A, and the signal port SA1 is connected to the signal port SC0 of another switch unit 101C through, for example, a USXGMII interface (but not limited). In addition, a switch unit 101C as another slave switch unit, for example, includes a processing circuit 102C, at least one signal port SC0 and SC1 for stack connection, and other signal ports. The signal port SC0 is connected to the signal port SB1 of the switch unit 101B, and the signal port SC1 is connected to the signal port SD0 of yet another switch unit 101D through, for example, a USXGMII interface (but not limited). In addition, a switch unit 101D as yet another slave switch unit, for example, includes a processing circuit 102D, at least one signal port SD0 for stack connection, and other signal ports.

[0026] It should be noted that in this embodiment, the switch units 101A to 101D are all switch units having the same number of signal ports (or pins). During system startup (during the startup of the switch units 101A to 101D), when the processing circuits 102A to 102D of each switch unit 101A to 101D enter the stack mode, they will respectively determine whether they are a master switch unit or a slave switch unit in the stack mode according to the signal levels on one or more of their signal ports (or pins) and / or the data stored in a memory (such as the flash memory 105) connected to at least one signal port (or pin). If it is a master switch unit, then as Figure 2 shown, the two signal ports of the master switch unit 101A are respectively connected to the control device 110 to form the data transmission interface and the buffer access interface, and one of its signal ports is connected to the flash memory 105 as an SPI interface; if it is a slave switch unit, then as Figure 2 shown by the slave switch units 101B to 101D, these slave switch units are not connected to the control device 110 and the flash memory 105. Therefore, each slave switch unit 101B to 101D has three more idle signal ports than the master switch unit 101A and can be used as other input / outputs. It should be noted that Figure 2 the different placement positions of the signal ports inside the switch units 101A to 101D shown are only for conveniently and concisely depicting their stack connection structure relationship and are not a limitation of this case.

[0027] In practice, among the N signal ports of each switch unit, there are also one or more master / slave control ports (or pins). Each switch unit can determine its role as a master / slave switch unit through the signal levels and / or the received data bits on the above-mentioned one or more master / slave control ports, and automatically connect to one or more other switch units and automatically complete the update of the stack topology structure and the software / firmware program. When the user performs the stack topology of N switch units, it can enable the user to directly set the signal levels and / or the received data bits on one or more master / slave control ports of each switch unit according to an external control circuit or a simple external circuit, so as to achieve the purpose of automatically connecting all switch units and automatically completing the update of the stack topology structure and the software / firmware program during system startup.

[0028] In an embodiment of the present invention, the above one or more master / slave control ports (or pins) include at least one strapping pin and / or at least one control pin coupled to a circuit such as a one-time programmable (OTP) circuit. It should be noted that one-time programmable is only for illustrative purposes and not a limitation of this case; the data in the flash memory 105 can be written and burned only once, or it can also be repeatedly read and written. The at least one strapping pin corresponds to at least one specific operation function of a stackable switch unit, and the one-time programmable circuit is, for example, the aforementioned flash memory 105. Embodiments of at least one strapping pin and at least one control pin of a switch unit in an embodiment of the present invention are shown in the following table. For example, it includes four strapping pins and an OTP pin connected to the one-time programmable circuit:

[0029]

[0030]

[0031] As shown in the above table, the four strapping pins P5_TXD[3], P4_TXD[0], P4_TXD[1], and P4_TXD[2] of a switch unit respectively indicate whether to use the strapping pin to determine the master / slave role of the switch unit during stacking, whether to use the first signal port (denoted as S0, such as Figure 2 the signal ports SA0, SB0, SC0, SD0, etc. among the switch units shown) for stacking connection, whether to use the second signal port (denoted as S1, such as Figure 2 the signal ports SA1, SB1, SC1, etc. among the switch units shown) for stacking connection, and determine the master / slave role during stacking. For example, when the signal level of the strapping pin P5_TXD[3] is the first level (such as logic level "0", but not limited), it indicates disabled, that is, the strapping pin is not used to determine the master / slave switch unit, and when the signal level of the strapping pin P5_TXD[3] is the second level (such as logic level "1", but not limited), it indicates enabled, that is, the strapping pin is used to determine the master / slave switch unit.

[0032] When the signal level of the strapping pin P4_TXD[0] is the first level (such as logic level "0", but not limited), it indicates disabling the first signal port S0 for stacking connection, and when the signal level of the strapping pin P4_TXD[0] is the second level (such as logic level "1", but not limited), it indicates enabling the first signal port S0 for stacking connection. For example Figure 2The first signal port SA0 of the main switch unit 101A shown does not perform stack connection. Therefore, the signal level of the multiplexed pin P4_TXD[0] of the main switch unit 101A will be at the first level "0" to indicate disable, and for example Figure 2 The first signal port SB0 of the slave switch unit 101B shown performs stack connection. Therefore, the signal level of the multiplexed pin P4_TXD[0] of the slave switch unit 101B will be at the second level "1" to indicate enable.

[0033] When the signal level of the multiplexed pin P4_TXD[1] is at the first level (such as logic level "0", but not limited), it indicates that the first signal port S1 is disabled for stack connection. When the signal level of the multiplexed pin P4_TXD[1] is at the second level (such as logic level "1", but not limited), it indicates that the second signal port S1 is enabled for stack connection. For example, as Figure 2 The second signal port SA1 of the main switch unit 101A shown performs stack connection. Therefore, the signal level of the multiplexed pin P4_TXD[1] of the main switch unit 101A will be at the second level "1" to indicate enable, and for example Figure 2 The second signal port SD1 of the slave switch unit 101D shown does not perform stack connection. Therefore, the signal level of the multiplexed pin P4_TXD[1] of the slave switch unit 101D will be at the first level "0" to indicate disable.

[0034] When the signal level of the multiplexed pin P4_TXD[2] is at the first level (such as logic level "0", but not limited), it indicates that the switch unit is a main switch unit. When the signal level of the multiplexed pin P4_TXD[2] is at the second level (such as logic level "1", but not limited), it indicates that the switch unit is a slave switch unit. For example, if the above multiplexed pins are used to define the main / slave switch units, then for example Figure 2 The signal level of the multiplexed pin P4_TXD[2] of the main switch unit 101A shown will be at the first level "0" to indicate that the switch unit is set as a main switch unit, and for example Figure 2 The signal level of the multiplexed pin P4_TXD[2] of the slave switch unit 101D shown will be at the second level "1" to indicate that the switch unit is set as a slave switch unit.

[0035] And for the OTP pin, the OTP pin is, for example, through Figure 2is connected to the flash memory 105 through the SPI interface shown. In the flash memory 105, for example, four bits at a specific address 0xC4 (but not limited to this) are used to represent the information in the above embodiments (for example, master / slave role, signal port enable / disable, etc.). For example, bit 0xC4[7] at the specific address 0xC4 represents which pin is selected to determine the master / slave role of the switch unit. When the content of bit 0xC4[7] is the first data content (for example, "1", but not limited to this), it means that the multiplexed pin is selected to determine the master / slave role. On the contrary, when the content of bit 0xC4[7] is the second data content (for example, "0", but not limited to this), it means that the OTP pin is selected to determine the master / slave role; in addition, bit 0xC4[2] at the specific address 0xC4 represents whether to use the first signal port S0 for stack connection. For example, when the content of bit 0xC4[2] is "1", it means that the first signal port S0 is disabled for stack connection. On the contrary, when the content of bit 0xC4[2] is "0", it means that the first signal port S0 is enabled for stack connection; in addition, bit 0xC4[3] at the specific address 0xC4 represents whether to use the second signal port S1 for stack connection. For example, when the content of bit 0xC4[3] is "1", it means that the second signal port S1 is disabled for stack connection. On the contrary, when the content of bit 0xC4[3] is "0", it means that the second signal port S1 is enabled for stack connection. For example, Figure 2 the content of bit 0xC4[2] at address 0xC4 connected to the OTP pin of the switch unit 101A shown is "1", indicating that the first signal port SA0 is not used for stack connection, and the content of bit 0xC4[3] at its address 0xC4 is "0", indicating that the second signal port SA1 is enabled for stack connection. Furthermore, bit 0xC4[6] at address 0xC4 is used to determine the master / slave role during stacking. When the content of bit 0xC4[6] is "0", it means that the switch unit is set as a master switch unit. On the contrary, when the content of bit 0xC4[6] is "1", it means that the switch unit is set as a slave switch unit. For example, Figure 2 the content of bit 0xC4[6] at address 0xC4 connected to the OTP pin of the switch unit 101A shown is "1", indicating that the switch unit 101A is set as a master switch unit.

[0036] In this way, through the above-mentioned one or more control pins (multiplexing pins and / or OTP pins) of each switch unit, the user can design a system-on-chip on the circuit board and set the signal level of the multiplexing pins through an input / output interface, such as a general-purpose input / output interface (GPIO interface), to set the master / slave role relationship of the above-mentioned switch units 101A to 101D, or can also directly initialize and set the signal level of the multiplexing pins by means of a method of grounding through a resistor. Therefore, for example, in terms of the use of the multiplexing pins, when the group of switch units 101A to 101D is in a system startup program, each switch unit 101A to 101D can automatically determine whether it is a master unit or a slave unit according to the signal level on its multiple multiplexing pins after entering the stack mode, and determine the enabling or disabling of the signal ports for stack connection. After the master / slave role of the switch unit is determined, the processing circuit 102A of the master switch unit 101A can transmit data or program code to the processing circuit 102B of the next slave switch unit 101B, and then the processing circuit 102B of the slave switch unit 101B transmits the data or program code to the processing circuit 102C of the next slave switch unit 101C, and finally the processing circuit 102C of the slave switch unit 101C transmits the data or program code to the processing circuit 102D of the last slave switch unit 101D.

[0037] Furthermore, in terms of the OTP pins, the switch unit 101A can, for example, obtain the bits at address 0xC4 through the OTP pins to determine whether it is the master switch unit and determine which signal port to use for stack connection, and can also obtain the stacking binary file and other related software / firmware programs from the flash memory 105 through the OTP pins. After that, the master switch unit 101A can transfer the obtained binary file and other related software / firmware programs to the slave switch unit connected to it, such as 101B, and then sequentially transfer them to other slave switch units 101C to 101D, so that all master / slave switch units can obtain the corresponding stack configuration settings and related software / firmware programs during the system startup program.

[0038] Please refer to FIG. 3. Figure 3 It is a schematic flowchart of the method for the embodiment of the present invention to generate and store stack files and programs in the flash memory 105. It should be noted that the steps of this method flowchart can be executed by the manufacturer of the switch unit or can also be executed by the user of the switch unit. In other words, the generation of stack files and programs can be executed at the factory end of the manufacturer or at the client end, which is not a limitation of this case. As Figure 3As shown, in step S305, the manufacturer or user can determine the stacking topology through an electronic device such as a computer device or other control device. For example, the manufacturer can customize the stacking topology according to the needs of its customers. For example, it is a stacking topology of three switch units, including the main switch unit 101A and the slave switch units 101B-101C. Or in another embodiment, the user can determine the stacking topology by himself and design the signal levels of the foregoing control ports on the circuit board. For example, the main switch unit is 101A and the slave switch units are 101B and 101C. In step S310, the manufacturer or user uses an electronic device such as a computer device to generate the setting of the stacking configuration. Then, in step S315, the manufacturer or user uses an electronic device such as a computer device to set the settings of other configurations, such as patch code, the configuration of the main switch unit 101A, the configuration of the slave switch unit 101B, the configuration of the slave switch unit 101C, data settings such as software / firmware programs, etc. Finally, in step S320, the manufacturer or user uses an electronic device such as a computer device to generate and write the stacking file and related programs into the flash memory 105. The stacking file and related programs include data such as the setting of the stacking configuration, patch code, and the settings of other main / slave switch unit configurations, etc.

[0039] Please refer to Figure 4 , Figure 4It is a schematic flowchart of a method for determining a switch unit as a master / slave switch unit during the startup of the system in an embodiment of the present invention. In step S405, when the switch unit enters the stacking mode, the steps of this method flowchart start. In step S410, the switch unit first obtains the data content of the bit at an address in an external memory device, such as 0xC4, from the OTP pin. If bit 0xC4[7] indicates "0" (refer to the pin setting / definition table and explanation described in the previous paragraph, and the same applies to the following description), it means that the OTP pin is selected to determine the master / slave role, and then step S420 will be executed; conversely, if bit 0xC4[7] indicates "1", it means that the multiplexed pin is selected to determine the master / slave role, and then step S415 will be executed. In step S415, the switch unit determines which level the signal level on the multiplexed pin P5_TXD[3] is. If the signal level on the multiplexed pin P5_TXD[3] is the logic level "0", it means that the multiplexed pin is disabled; conversely, if the signal level on the multiplexed pin P5_TXD[3] is the logic level "1", it means that the multiplexed pin is enabled. In other words, if bit 0xC4[7] indicates "1" and the signal level on the multiplexed pin P5_TXD[3] is the logic level "0", it means that neither the OTP pin nor the multiplexed pin is used to determine the stacking structure. That is, in this case, the stacking structure is disabled during startup, and the process enters step S445.

[0040] In step S420, if both bits 0xC4[3:2] obtained from the OTP pin indicate "1", it means that both the first signal port S0 and the second signal port S1 are disabled for stacking connection. In other words, if bit 0xC4[7] indicates "0" but both bits 0xC4[3:2] indicate "1", it means that the stacking structure is disabled during startup in this case, and the process enters step S445. If any one of the two bits 0xC4[3:2] does not indicate "1", the process proceeds to step S430, and the data on the OTP pin is used to set the stacking configuration. Then the process will enter step S440, enable the stacking structure and complete the stacking mode.

[0041] In step S425, if the signal levels on both multiplexed pins P4_TXD[1:0] are logic level "0", it means that both the first signal port S0 and the second signal port S1 are disabled for stack connection. In other words, if the signal level of multiplexed pin P5_TXD[3] is logic level "1" while the signal levels on both multiplexed pins P4_TXD[1:0] are logic level "0", it indicates that the stack structure is disabled during startup in this case, and the process proceeds to step S445. If any of the signal levels on the two multiplexed pins P4_TXD[1:0] is not logic level "0", the process goes to step S435, where the signal level on the multiplexed pin is used to set the stack configuration. Then the process proceeds to step S440 to enable the stack structure and complete the stack mode. It should be noted that Figure 4 The flow steps shown are executed by a processing circuit in a switch unit.

[0042] Please refer to Figure 5 , Figure 5 which is a schematic diagram of the operations and communications of two switch units performing stacking during system startup in an embodiment of the present invention. As Figure 5 shown, taking the switch unit 101A and the switch unit 101B shown in Figure 2 as an example, during the execution of the system startup program, both the switch unit 101A and the switch unit 101B enter the stack mode. At this time, the flow operation of the switch unit 101A enters step S505A, and the flow operation of the switch unit 101B enters step S505B. In step S505A, the switch unit 101A performs startup stack setting and is set as a master switch unit in this example. If successful, it proceeds to step S510A; otherwise, if the setting fails, it enters step S540A to end the process. In step S505B, the switch unit 101B also performs startup stack setting and is set as a slave switch unit in this example. If successful, it proceeds to step S510B; otherwise, if the setting fails, it enters step S540B to end the process.

[0043] In step S510A, the main switch unit 101A performs the connection and communication of the stack interface. Similarly, in step S510B, the slave switch unit 101B also performs the connection and communication of the stack interface. Therefore, in steps S515A and S515B that follow, the main switch unit 101A transmits the stack configuration settings to at least one connected slave switch unit (i.e., including the slave switch unit 101B), and correspondingly, the slave switch unit 101B receives the stack configuration settings from at least one connected switch unit (which can be a main / slave switch unit, and in this embodiment is the main switch unit 101A). It should be noted that the main switch unit 101A can generate the stack configuration settings based on the data stored in the flash memory 105, or directly download the stack configuration settings from the flash memory 105.

[0044] In steps S520A and S520B that follow, the main switch unit 101A and the slave switch unit 101B determine whether to perform transmission with encryption / decryption operations. If it is determined to perform transmission with encryption / decryption operations, then in steps S525A and S525B, the main switch unit 101A generates an encryption key and sends the encryption key to at least one connected slave switch unit, such as the slave switch unit 101B, and the slave switch unit 101B receives the encryption key from at least one connected switch unit (which can be a main / slave switch unit) to perform subsequent decryption operations. Subsequently, the process proceeds to steps S530A and S530B. If it is determined in steps S520A and S520B not to perform transmission in an encrypted manner, the process can directly proceed to steps S530A and S530B.

[0045] The main switch unit 101A transmits a firmware program (such as obtained from the flash memory 105) to at least one connected slave switch unit, such as the slave switch unit 101B, in step S530A, and the slave switch unit 101B receives the firmware program from at least one connected switch unit (main / slave switch unit) and updates its firmware program in step S530B. It should be understood that if the main switch unit 101A determines to perform transmission in an encrypted manner in step S520A, the main switch unit 101A encrypts the firmware program with the encryption key and then transmits it to the slave switch unit in step S530A; if the main switch unit 101A determines not to perform transmission in an encrypted manner in step S520A, the main switch unit 101A can directly transmit the unencrypted firmware program to the slave switch unit in step S530A.

[0046] Next, the main switch unit 101A transmits other configuration settings to at least one connected slave switch unit, such as the slave switch unit 101B, in step S535A, and the slave switch unit 101B receives other configuration settings from at least one connected switch unit (which can be a main / slave switch unit) in step S535B and applies and implements the other configuration settings. If in steps S520A and S520B, the main switch unit 101A and the slave switch unit 101B determine to perform transmission with encryption operations, the exchange of other configuration settings in steps S535A and S535B is also performed with corresponding encryption / decryption operations; if it is determined in steps S520A and S520B not to perform transmission with encryption operations, the exchange of other configuration settings in steps S535A and S535B is performed with unencrypted operations.

[0047] The main switch unit 101A completes the process steps of its stacking mode at step S540A. The slave switch unit 101B can further determine whether the firmware program is encrypted at step S536. If it is determined that the firmware program is encrypted, the process proceeds to step S537, and in step S537, the firmware program is decrypted according to the previously received encryption key so that the decrypted firmware program can be applied to the slave switch unit 101B (for example, updating the firmware program of the slave switch unit 101B). Conversely, if it is determined that the firmware program is not encrypted, step S540B is performed, and the slave switch unit 101B completes the process steps of its stacking mode at step S540B. In an embodiment, a default firmware program is included on each switch unit, and when updating the firmware program, if the updated firmware program from the main switch unit is encrypted, the updated firmware program will be decrypted according to the encryption key in step S537.

[0048] It should be noted that Figure 5 the shown process steps are respectively executed by the processing circuit 102A in the switch unit 101A and the processing circuit 102B in the switch unit 101B.

[0049] It should be understood that the foregoing embodiments are merely examples and are not intended to limit the present invention. In some embodiments, the main switch unit 101A and the individual slave switch units 101B to 101D can perform one-to-one key exchanges, enabling the individual slave switch units 101B to 101D to hold different keys, so that the data transmissions from the main switch unit 101A to the individual slave switch units 101B to 101D cannot be decrypted by other slave switch units. For example, it can prevent other slave switch units from obtaining the information of a specific switch unit. It should be noted that in one embodiment, the information of the firmware program can be obtained by other slave switch units. Therefore, the encryption / decryption of the firmware program by the main switch unit 101A and other slave switch units 101B to 101D can also be based on the same key.

[0050] The foregoing are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims

1. A method for use in a stack of switch units, the stack of switch units being capable of stacking with at least one other stack of switch units, characterized in that, The method includes: providing the stackable switch unit, which has a plurality of signal ports, and the plurality of signal ports include at least one master / slave control port; during a startup program of the stackable switch unit, automatically determining whether the stackable switch unit is a master switch unit or a slave switch unit according to at least one signal level of the at least one master / slave control port and / or at least one bit content of data obtained from the at least one master / slave control port; and when the stackable switch unit is the master switch unit, generating a stack configuration setting, and transmitting the stack configuration setting to at least one other stackable switch unit connected to the stackable switch unit through at least one signal port among the plurality of signal ports of the stackable switch unit, so that the stackable switch unit and the at least one other stackable switch unit complete stack connection; wherein, the at least one master / slave control port includes a plurality of multiplexed pins: a first multiplexed pin, used to determine whether to determine whether the stackable switch unit is the master switch unit or the slave switch unit from the plurality of multiplexed pins. When the first multiplexed pin is at a first level, it means not to use the plurality of multiplexed pins, and when the first multiplexed pin is at a second level, it means to use the plurality of multiplexed pins; a second multiplexed pin, used to determine whether a first signal port of the stackable switch unit is enabled. When the second multiplexed pin is at the first level, it means not to enable or disable, and when the second multiplexed pin is at the second level, it means to enable; a third multiplexed pin, used to determine whether a second signal port of the stackable switch unit is enabled. When the third multiplexed pin is at the first level, it means not to enable or disable, and when the third multiplexed pin is at the second level, it means to enable; and a fourth multiplexed pin, used to determine the master / slave role of the stackable switch unit. When the fourth multiplexed pin is at the first level, it means the role of a master switch unit, and when the fourth multiplexed pin is at the second level, it means the role of a slave switch unit; wherein, the stackable switch unit is externally coupled to a flash memory device, and the at least one master / slave control port includes at least one control pin coupled to the flash memory device, and the at least one control pin is used to read a specific data stored at a specific address in the flash memory device, and the specific data includes: a first bit, used to determine whether to determine whether the stackable switch unit is the master switch unit or the slave switch unit from the plurality of multiplexed pins included in the at least one master / slave control port. When the first bit indicates a first data content, it means to use the plurality of multiplexed pins, and when the first bit indicates a second data content, it means to use the at least one control pin; a second bit, used to determine whether a first signal port of the stackable switch unit is enabled. When the second bit indicates the first data content, it means not to enable or disable, and when the second bit indicates the second data content, it means to enable; A third bit, for determining whether a second signal port of the stackable switch unit is enabled. When the third bit indicates the first data content, it represents non - enabling or disabling, and when the third bit indicates the second data content, it represents enabling; and A fourth bit, for determining the master / slave role of the stackable switch unit. When the fourth bit indicates the first data content, it represents the role of a master switch unit, and when the fourth bit indicates the second data content, it represents the role of a slave switch unit.

2. The method according to claim 1, wherein It further includes: During the power - on startup program of the stackable switch unit, determine whether to use a first signal port and a second signal port of the stackable switch unit as stack connections according to at least one signal level of the at least one master / slave control port and / or the content of at least one bit of data obtained from the at least one master / slave control port.

3. The method according to claim 1, wherein It further includes: When the stackable switch unit is the slave switch unit, receive a stack configuration setting generated by a specific master switch unit or relayed by another slave switch unit through a first signal port of the stackable switch unit, so that the stackable switch unit completes a stack connection with the specific master switch unit or the other slave switch unit.

4. The method according to claim 1, wherein It further includes: When the stackable switch unit completes a stack connection with at least one other stackable switch unit, transmit a firmware program of a switch unit to the at least one other stackable switch unit through the at least one signal port of the stackable switch unit, so that the stackable switch unit and the at least one other stackable switch unit have the same firmware program.

5. A method for use in a stack of switch units, the stackable switch units being capable of stacking with at least one other stackable switch unit, characterized in that, The method includes: Provide the stackable switch unit, which has a plurality of signal ports, and the plurality of signal ports include at least one master / slave control port; During a power - on startup program of the stackable switch unit, automatically determine whether the stackable switch unit is a master switch unit or a slave switch unit according to at least one signal level of the at least one master / slave control port and / or the content of at least one bit of data obtained from the at least one master / slave control port; and When the stackable switch unit is the slave switch unit, receive a stack configuration setting generated by a specific master switch unit and / or relayed by another slave switch unit through at least one of a first signal port and a second signal port of the stackable switch unit, so that the stackable switch unit completes a stack connection with the specific master switch unit or the other slave switch unit, where the at least one other stackable switch unit includes the specific master switch unit and the other slave switch unit; Wherein, the at least one master / slave control port includes a plurality of multiplexed pins: A first multiplexed pin, for determining whether to determine whether the stackable switch unit is the master switch unit or the slave switch unit from the plurality of multiplexed pins. When the first multiplexed pin is at a first electrical level, it represents not using the plurality of multiplexed pins, and when the first multiplexed pin is at a second electrical level, it represents using the plurality of multiplexed pins; A second multiplexing pin for determining whether a first signal port of the stackable switch unit is enabled. When the second multiplexing pin is at the first level, it indicates non - enabling or disabling, and when the second multiplexing pin is at the second level, it indicates enabling; A third multiplexing pin for determining whether a second signal port of the stackable switch unit is enabled. When the third multiplexing pin is at the first level, it indicates non - enabling or disabling, and when the third multiplexing pin is at the second level, it indicates enabling; and A fourth multiplexing pin for determining a master / slave role of the stackable switch unit. When the fourth multiplexing pin is at the first level, it indicates a master switch unit role, and when the fourth multiplexing pin is at the second level, it indicates a slave switch unit role; Wherein, the stackable switch unit is externally coupled to a flash memory device, and the at least one master / slave control port includes at least one control pin coupled to the flash memory device. The at least one control pin is used to read a specific data stored at a specific address in the flash memory device. The specific data includes: A first bit for determining whether to determine whether the stackable switch unit is the master switch unit or the slave switch unit from a plurality of multiplexing pins included in the at least one master / slave control port. When the first bit indicates a first data content, it means using the plurality of multiplexing pins, and when the first bit indicates a second data content, it means using the at least one control pin; A second bit for determining whether a first signal port of the stackable switch unit is enabled. When the second bit indicates the first data content, it means non - enabling or disabling, and when the second bit indicates the second data content, it means enabling; A third bit for determining whether a second signal port of the stackable switch unit is enabled. When the third bit indicates the first data content, it means non - enabling or disabling, and when the third bit indicates the second data content, it means enabling; and A fourth bit for determining a master / slave role of the stackable switch unit. When the fourth bit indicates the first data content, it means a master switch unit role, and when the fourth bit indicates the second data content, it means a slave switch unit role.

6. A stackable switch unit that can be stacked with at least one other stackable switch unit, characterized in that, The stackable switch unit includes: A plurality of signal ports, the plurality of signal ports including at least one master / slave control port; and A processing circuit coupled to the plurality of signal ports for: During a power - on startup program of the stackable switch unit, automatically determine whether the stackable switch unit is a master switch unit or a slave switch unit according to at least one signal level of the at least one master / slave control port and / or the content of at least one bit of the data obtained from the at least one master / slave control port; Wherein, the at least one master / slave control port includes a plurality of multiplexing pins: A first multiplexing pin for determining whether to determine whether the stackable switch unit is the master switch unit or the slave switch unit from the plurality of multiplexing pins. When the first multiplexing pin is at a first level, it means not using the plurality of multiplexing pins, and when the first multiplexing pin is at a second level, it means using the plurality of multiplexing pins; A second multiplexing pin for determining whether a first signal port of the stackable switch unit is enabled. When the second multiplexing pin is at the first level, it indicates non-enabling or disabling, and when the second multiplexing pin is at the second level, it indicates enabling; A third multiplexing pin for determining whether a second signal port of the stackable switch unit is enabled. When the third multiplexing pin is at the first level, it indicates non-enabling or disabling, and when the third multiplexing pin is at the second level, it indicates enabling; and A fourth multiplexing pin for determining the master / slave role of the stackable switch unit. When the fourth multiplexing pin is at the first level, it indicates a master switch unit role, and when the fourth multiplexing pin is at the second level, it indicates a slave switch unit role; Wherein, the stackable switch unit is externally coupled to a flash memory device, and the at least one master / slave control port includes at least one control pin coupled to the flash memory device. The at least one control pin is used to read a specific data stored at a specific address in the flash memory device. The specific data includes: A first bit for determining whether to determine whether the stackable switch unit is the master switch unit or the slave switch unit from the multiple multiplexing pins included in the at least one master / slave control port. When the first bit indicates a first data content, it means using the multiple multiplexing pins, and when the first bit indicates a second data content, it means using the at least one control pin; A second bit for determining whether a first signal port of the stackable switch unit is enabled. When the second bit indicates the first data content, it means non-enabling or disabling, and when the second bit indicates the second data content, it means enabling; A third bit for determining whether a second signal port of the stackable switch unit is enabled. When the third bit indicates the first data content, it means non-enabling or disabling, and when the third bit indicates the second data content, it means enabling; and A fourth bit for determining the master / slave role of the stackable switch unit. When the fourth bit indicates the first data content, it means a master switch unit role, and when the fourth bit indicates the second data content, it means a slave switch unit role.

7. The stackable switch unit according to claim 6, wherein When the stackable switch unit is the master switch unit, the processing circuit is used to generate a stack configuration setting and transmit the stack configuration setting to at least one other stackable switch unit connected to the stackable switch unit through at least one signal port among the multiple signal ports of the stackable switch unit, so that the stackable switch unit and the at least one other stackable switch unit complete stack connection.

8. The stackable switch unit according to claim 6, wherein When the stackable switch unit is the slave switch unit, the processing circuit receives a stack configuration setting generated by a specific master switch unit and / or relayed by another slave switch unit through at least one of a first signal port and a second signal port of the stackable switch unit, so that the stackable switch unit completes a stack connection with the specific master switch unit or the another slave switch unit, wherein the at least one other stackable switch unit includes the specific master switch unit and the another slave switch unit.

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