Encapsulated devices, packages, and methods for forming packages

Abstract

Embodiments include a package and a method for forming a package that includes an interposer having a substrate made of a dielectric material. The interposer can also include a redistribution structure located above the substrate that includes metallization patterns stitched together in a patterning process that includes multiple laterally overlapping patterning exposures. Embodiments of the present application also relate to packaged devices.

Description

Technical Field

[0001] Embodiments of this application relate to packaging devices, packages, and methods for forming packages. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density comes from the iterative reduction in the size of the smallest component, which allows more components to be integrated into a given area.

[0003] With the growing demand for miniaturized electronic devices, there is a need for smaller and more innovative packaging technologies for semiconductor dies. An example of such a packaging system is the stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is the chip-on-wafer (CoWoS) structure. In some embodiments, to form a CoWoS structure, multiple semiconductor chips are attached to a wafer, and a dicing process is then performed to separate the wafer into multiple interposers, each of which has one or more semiconductor chips attached thereto. The interposer with the attached semiconductor chips is called a chip-on-wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form the CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and small coverage areas. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a package, comprising: attaching a first interposer to a package structure, the first interposer including a dielectric filler formed on a carrier substrate; laterally sealing the first interposer in a first sealant; attaching a first device to the package structure; laterally sealing the first device in a second sealant; removing a portion of the first sealant and removing the carrier substrate of the first interposer to expose the dielectric filler; and forming an external connector on the package structure, one or more of the external connectors being electrically coupled to the first device through the first interposer.

[0005] Other embodiments of this application provide a package comprising: a first device, the first device being laterally sealed by a first sealant; a first interposer including a dielectric filler layer, the first interposer having no silicon layer, the first interposer being laterally sealed by a second sealant; and an external connector, one or more of the external connectors being electrically coupled to the first device through the first interposer.

[0006] Further embodiments of this application provide a packaging device comprising: one or more embedded devices; a first sealant layer sealing the one or more embedded devices; one or more chiplet interposers, each of the one or more chiplet interposers having a substrate, the substrate comprising a first material having a Young's modulus between 50 GPa and 100 GPa; a second sealant layer sealing the one or more chiplet interposers; a first redistribution structure disposed between the first sealant layer and the second sealant layer; and external connectors, wherein one or more of the external connectors are electrically coupled to the one or more embedded devices and electrically coupled to the one or more chiplet interposers. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figures 1 to 22 Cross-sectional and top views are shown of intermediate steps during a process for forming a chiplet interposer, according to some embodiments.

[0009] Figures 23 to 34 A cross-sectional view is shown during an intermediate step in the process of forming a packaged device using a chiplet interposer, according to some embodiments.

[0010] Figures 35 to 45 A cross-sectional view is shown during an intermediate step in the process of forming a packaged device using a chiplet interposer, according to some embodiments.

[0011] Figures 46 to 51 A top view is shown showing various configurations of the utilization of one or more chiplet intermediary layers according to various embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] According to some embodiments, a chiplet interposer is formed, comprising a dielectric filler layer serving as a substrate layer, rather than, for example, a silicon layer or a pre-formed substrate core layer. Using a dielectric filler layer as a substrate layer is cost-effective and advantageously provides lower stress concentration than using a silicon substrate layer, etc. The chiplet interposer is attached to a carrier substrate, which can be removed after the chiplet interposer has been placed in a packaged device. The chiplet interposer may also be incorporated into a redistribution structure, and in some embodiments, the redistribution structure may be formed by multiple side-by-side patterning processes in a stitching process, which provides the ability to combine several patterns side-by-side within a larger metallization pattern of a specific layer of the redistribution structure.

[0015] Figures 1 to 21 Cross-sectional and top-view views of intermediate steps in the process of forming a dielectric interposer are shown. Advantageously, the dielectric interposer does not utilize a silicon substrate, but rather a dielectric substrate. Therefore, the dielectric interposer can be manufactured in a more cost-effective manner than silicon-based interposers. Furthermore, the dielectric interposer can exhibit a more desirable stress concentration effect, thereby reducing the stress in the resulting package.

[0016] exist Figure 1 A carrier substrate 110 is provided. In some embodiments, a release layer 112 is formed on the carrier substrate 110 (omitted in further figures for simplicity). In other embodiments, the release layer 112 may be omitted. The carrier substrate 110 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 110 may be a silicon-based substrate, such as a silicon ingot. The carrier substrate 110 will be removed in subsequent steps, such as by decomposing the release layer 112 or by grinding away the carrier substrate 110. The carrier substrate 110 may be a wafer, such as... Figure 1 As shown, this allows multiple interposer layers to be formed simultaneously on the carrier substrate 110. It should be understood that, although... Figure 1 Three locations are shown, corresponding to interposer regions 100A, 100B, and 100C, but any number of locations can be used simultaneously above the carrier substrate 110.

[0017] Release layer 112 (if used) may be formed of a polymer-based material that can be removed from the above structure along with the carrier substrate 110, to be formed in subsequent steps. In some embodiments, release layer 112 is a thermally release material based on epoxy resin that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 112 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Release layer 112 may be dispensed as a liquid and cured, may be a laminated film laminated onto the carrier substrate 110, or may be the like. The top surface of release layer 112 may be flush and may have a high degree of planarity.

[0018] A via 125 is formed above and extends away from the carrier substrate 110. As an example of forming the via 125, a seed layer (not shown) is formed above the carrier substrate 110 (e.g., on the release layer 112 or directly on the carrier substrate 110). In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to a conductive via. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating (such as electroplating, electroless plating, etc.). The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Remove the photoresist and the portion of the seed layer where no conductive material has formed. The photoresist can be removed using an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, remove the exposed portion of the seed layer, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and conductive material forms the via 125.

[0019] exist Figure 2 In this process, a dielectric filler 120 is formed above and around the via 125. In some embodiments, the dielectric filler 120 may comprise a non-polymer, such as silicon dioxide, silicon nitride, or another oxide or nitride or other insulating material, deposited using any suitable process. For example, the dielectric filler 120 may be formed by CVD, PECVD or ALD deposition processes, FCVD or spin-coating glass processes. However, any suitable material and any suitable deposition process may be utilized. The dielectric filler 120 may be formed to have a thickness, for example, between about 1 μm and about 30 μm. In the completed chiplet interposer, the dielectric filler 120 will be the thickest layer of the chiplet interposer when the carrier substrate 110 is removed.

[0020] exist Figure 3 In this process, a planarization process is performed on the dielectric filler 120 to expose the via 125. The top surfaces of the via 125 and the dielectric filler 120 are substantially coplanar after the planarization process within a process variation. The planarization process can be, for example, chemical mechanical polishing (CMP), grinding, etc. In some embodiments, planarization may be omitted, for example, if the via 125 has already been exposed. The via 125 can be used to route signals from one side of the dielectric filler 120 to the opposite side of the dielectric filler 120. Because the via 125 passes through the dielectric filler 120, they can be referred to as dielectric vias or TDVs.

[0021] Still referencing Figure 3 In another embodiment, the dielectric filler 120 may be deposited prior to the formation of the via 125. In such an embodiment, once the dielectric filler 120 has been placed, photolithography masking and etching processes may be used to form an opening through the dielectric filler 120 to expose the underlying release layer 112 or carrier substrate 110. Once the opening has been formed, it may be filled with a conductive material, which in some embodiments includes a pad layer and / or a barrier layer. The remaining portion of the opening may then be filled with the conductive material. The conductive material may include any of those discussed above for the via 125. The conductive material may be formed by electroplating copper onto a seed layer, filling and overfilling the opening. Once the opening has been filled, excess pad, barrier layer, seed layer and conductive material outside the opening may be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process may be used. In such an embodiment, the via 125 may have a tapered shape, wider at the top than at the bottom (closer to the carrier substrate 110).

[0022] Figure 4 Illustrations are shown according to some embodiments Figure 3 An exemplary top view of the structure. (e.g.) Figure 4 The diagram shows the top of the dielectric filler 120 and the via 125. Although the vias 125 are shown as circular, they can also be other shapes. For example, they can be circular, square, rectangular, elliptical, rectangular, rectangular with rounded ends, and / or combinations thereof.

[0023] Figures 5 to 21 This shows a redistribution structure 128 formed above the through-hole 125 (see...). Figure 20 Views of the intermediate steps in the process. Brief reference. Figure 20 The redistribution structure 128 includes dielectric layers 130 and 140, optional metallization patterns 132, 138 and 148, and vias 136 and 146.

[0024] exist Figure 5In this process, an optional metallization pattern 132 may be formed on the dielectric filler 120. As an example of forming the metallization pattern 132, a seed layer is formed over the dielectric filler 120. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). A photoresist (not shown) is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 132. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating (such as electroplating, electroless plating, etc.). The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist and portions of the seed layer on which no conductive material is formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example by using an acceptable etching process, such as wet etching or dry etching. The remaining portion of the seed layer and conductive material forms a metallization pattern 132.

[0025] A dielectric layer 130 may be formed on a dielectric filler 120 and an optional metallization pattern 132. The bottom surface of the dielectric layer 130 may contact the top surface of the dielectric filler 120, the upper surface of the optional metallization pattern 132, and the upper surface of the via 125. In some embodiments, the dielectric layer 130 is formed of a polymer, which may be a photosensitive material that can be patterned using a photomask, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layer 130 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; etc. The dielectric layer 130 may be formed by spin coating, lamination, CVD, or a combination thereof.

[0026] The dielectric layer 130 is then patterned to form via openings 131 that expose portions of optional metallization patterns 132 and / or vias 125. Patterning can be performed using acceptable processes, such as exposing the dielectric layer 130 to light when it is a photosensitive material, or by using etching, for example, anisotropic etching. If the dielectric layer 130 is a photosensitive material, it can be developed after exposure.

[0027] exist Figure 6 In the process, after forming the via opening 131, the dielectric layer 130 can be patterned to form the opening 156 therein. Figure 8A metallization pattern will be formed therein. In an example of forming opening 156, a photomask 150 is formed over dielectric layer 130 and in via opening 131. Photomask 150 is exposed in exposure process 162, which allows light to pass through photomask 160 (such as an intermediate mask). In the exemplary embodiment shown, the exposed portion of photomask 150 creates an exposed area 152 that is removed by a development process of photomask 150. Other embodiments may use a negative photomask 150, which results in the preservation of the exposed area 152 of the photomask.

[0028] exist Figure 7 In the process, after the photomask 150 has been exposed in each of the interposer regions 100A, 100B, and 100C by the exposure process 162, the photomask 150 is developed and the exposed areas 152 are removed, leaving an opening 154 in the photomask 150. The opening 154 may expose the opening 131 and the underlying optional metallization pattern 132 and / or via 125.

[0029] exist Figure 8 In this process, photomask 150 is used as an etching mask and opening 154 is transferred to the underlying dielectric layer 130 by a suitable etching process to form opening 156 in the dielectric layer 130.

[0030] exist Figure 9 In the next step, photomask 150 is removed by an acceptable ashing or stripping process, such as by using oxygen plasma. Next, conductive material 134 is deposited into the opening 156 to form a metallization pattern 138. Figure 10 As an example of forming the metallization pattern 138, an optional barrier layer may be formed over the dielectric layer 130 and in the openings 156 and 131. The optional barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof, and may be formed using any suitable method, including PVD, CVD, etc. The optional barrier layer may line the openings 131 and 156 and may cover the upper surface of the dielectric layer 130. Next, a seed layer may be formed over the dielectric layer 130 and in the openings 156 and 131. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). Next, a conductive material 134 is formed in the openings 131 and 156 and over the dielectric layer 130. The conductive material 134 can be formed by any suitable process, such as PVD, CVD, plating (such as electroplating or electroless plating), etc. The conductive material 134 may include metals such as copper, titanium, tungsten, aluminum, etc.

[0031] exist Figure 10In the planarization process, conductive material 134 is planarized to form a metallization pattern 138. During the planarization process, excess material of conductive material 134 is removed, and the upper surface of the conductive material becomes flush with the upper surface of dielectric layer 130. The conductive pattern 138 appears where the dielectric layer 130 separates portions of the conductive material 134. The planarization process can include any suitable process, such as chemical mechanical polishing (CMP), etching back, or combinations thereof.

[0032] Figure 11 Illustrations are shown according to some embodiments Figure 10 A top view of the structure. Figure 11 The metallization pattern 138, via 136, and dielectric layer 130 are shown. It should be understood that... Figure 11 For illustrative purposes only and not intended to be limiting. The metallization pattern 138 may extend primarily horizontally, vertically, or in a hybrid direction between horizontal and vertical (as shown). The via 136 may be the same size as, less than, or greater than the width w1 of the metallization pattern 138. The width w1 of the metallization pattern 138 may be between 0.05 μm and 5 μm. The spacing p1 of the metallization pattern 138 may be between 0.1 μm and 10 μm. In some embodiments, the width w1 may be the same as the spacing p1.

[0033] Figures 12 to 19A to Figure 19D A stitching process is illustrated to form a single metallization pattern across multiple packaging regions, such as across a first interposer region 100A, a second interposer region 100B, and a third interposer region 100C. Thus, the superchip interposer 100' can include multiple interposer regions. In such embodiments, these may also be referred to as patterned regions or interposer / patterned regions. Stitching or merging multiple interposer regions or patterned regions together to form the superchip interposer 100' provides the ability to form a metallization having a coverage area larger than that available for use in a photomask used to expose the photomask. For example, multiple photomask patterns can be stitched together to form a conductor as part of a metallization pattern extending from the first interposer / patterned region 100A to the second interposer / patterned region 100B. The stitching process provides the formation of a metallization pattern larger than the photomask used to fabricate it. The size of the photomask is determined by the exposure tool (e.g., an ultraviolet or extreme ultraviolet light source). The stitching process combines multiple exposures into a single continuous pattern without modifying the exposure tool to accommodate a larger photomask.

[0034] exist Figure 12 In the middle, in forming the through hole opening 131 (see Figure 5 After that, the dielectric layer 130 can be patterned to form openings 156 therein. Figure 16), which will be used to form metallic patterns. Figures 12 to 15 An exemplary use of the stitching process is illustrated. A photomask 150 is formed over a dielectric layer 130 and in a via opening 131. The photomask 150 is exposed in an exposure process 162, which allows light to pass through the photomask 160A, such as an intermediate mask. In the example shown, the exposed portion of the photomask 150 creates an exposed region 152A, which is subsequently removed by a development process of the photomask 150. Other embodiments may use a negative photomask 150, which results in the exposed region 152A of the photomask 150 being retained. It should be noted that the photomask 150 is exposed only in the first interposer region 100A.

[0035] exist Figure 13 In this process, photomask 150 is exposed in another exposure process 162 through which light passes through photomask 160B. Photomask 160B may be the same photomask as photomask 160A or it may be a different photomask. In the example shown, the exposed portion of photomask 150 produces a double-exposed region 152B and an exposed region 152C that are subsequently removed by a development process of photomask 150. Other embodiments may use a negative photomask 150, which results in the retention of the double-exposed region 152B and the exposed region 152C of photomask 150. The double-exposed region 152B has already been exposed twice in exposure process 162. It is first exposed through photomask 160A and then second exposed through photomask 160B. The overlapping area between the two exposures is the double-exposed region 152B.

[0036] exist Figure 14 In this process, photomask 150 is exposed in another exposure process 162, through which light passes through photomask 160C. Photomask 160C may be the same photomask as photomask 160A and / or photomask 160B, or it may be a different photomask. In the example shown, the exposed portion of photomask 150 produces a double-exposed region 152D and an exposed region 152E, which are subsequently removed by a development process of photomask 150. Other embodiments may use a negative photomask 150, which results in the retention of the double-exposed region 152D and exposed region 152E of photomask 150. The double-exposed region 152D has already been exposed twice in exposure process 162. It is first exposed through photomask 160B and then second exposed through photomask 160C. The overlapping area between the two exposures is the double-exposed region 152D.

[0037] exist Figure 15In the process of exposure process 162, after photomask 150 has been exposed in each of the interposer regions 100A, 100B, and 100C, photomask 150 is developed and exposed regions 152A, 152C, and 152E, as well as double-exposed regions 152B and 152D, are removed, leaving an opening 154 in photomask 150. Opening 154 may expose opening 131 and the underlying optional metallization pattern 132 and / or via 125.

[0038] exist Figure 16 In this process, photomask 150 is used as an etching mask and opening 154 is transferred to the underlying dielectric layer 130 by a suitable etching process to form opening 156 in the dielectric layer 130.

[0039] exist Figure 17 In the next step, photomask 150 is removed by an acceptable ashing or stripping process, such as by using oxygen plasma. A conductive material is then deposited into the opening 156 to form a metallization pattern 138 and an overlapping region 138o. These can be similar to those described above. Figure 9 and Figure 10 The processes and materials discussed are formed. It should be noted that the overlapping regions 138o of the metallization pattern 138 can be bridged between package regions, for example, between interposer regions 100A and 100B, to form a superchiplet interposer 100'.

[0040] Figure 18 Illustrations are shown according to some embodiments Figure 17 A top view of the structure. Figure 18 The metallization pattern 138, via 136, and dielectric layer 130 are shown. Figure 18 The overlapping area of ​​138° is also shown. It should be understood that... Figure 18 For illustrative purposes only and not intended to be limiting. The metallized pattern 138 may extend primarily horizontally, vertically, or in a hybrid direction between horizontal and vertical (as shown). The via 136 may be the same size as, less than, or greater than the width w1 of the metallized pattern 138. The width w1 of the metallized pattern 138 may be between 0.05 μm and 5 μm. The spacing p1 of the metallized pattern 138 may be between 0.05 μm and 5 μm. In some embodiments, the width w1 may be the same as the spacing p1. The width w2 of the lines in the overlapping region 138o may be the same size as the width w1 or slightly larger than the width w1. The width w2 may be greater than the width w1.

[0041] Figures 19A to 19D This shows the effect when using a stitching process. Figure 17 and Figure 18 Top views of different embodiments of the overlapping area 138o. Figures 19A to 19DEach of the embodiments can exist in a single metallization pattern 138. Figure 19A In this process, the linewidth d1 of the metallized pattern 138a from the first patterning process can be the same as the linewidth d2 of the metallized pattern 138b from the second patterning process. The overlapping region 138o can have a linewidth d3 that is about 5% to 50% wider than the linewidth d2 and / or the linewidth d3. This increase in linewidth d3 may be due to the double-exposed photomask (e.g., Figure 12 The double exposure (150) is caused by the overlapping region of the photomask 130 used for patterning the underlying dielectric layer 130. Double exposure can affect a larger portion of the photomask width compared to normal exposure by the photomask. For example, light diffusion in the exposed region can affect the surrounding area. In other embodiments, the overlapping region 138o may have a linewidth d3 that is approximately 10% to 30% smaller than the linewidth d2 and / or linewidth d3. This reduction in linewidth d3 may be due to a negative photomask in the double-exposed overlapping region. In a negative photomask, the retained areas of the photomask are exposed, while the removed areas are protected. Double exposure can affect a larger portion of the photomask compared to normal exposure by the photomask. For example, light diffusion in the exposed region can affect the surrounding area, including into the overlapping region.

[0042] exist Figure 19B In this process, the linewidth d1 of the metallized pattern 138a from the first patterning process can be the same as the linewidth d2 of the metallized pattern 138b from the second patterning process. The overlapping region 138o can have a linewidth d3 that is approximately the same as the linewidth d1 and / or the linewidth d2. Although the double exposure of the photomask leads to Figure 19A The width is increased, but in Figure 19B In this case, double exposure can be performed without causing widening. For example, the exposure intensity in the overlapping area can be controlled to prevent widening, or the photomask used can be adjusted to have a narrower exposure in the overlapping area to compensate for the double exposure.

[0043] exist Figure 19C In this process, the linewidth d1 of the metallized pattern 138a from the first patterning process can be the same as the linewidth d2 of the metallized pattern 138b from the second patterning process. The overlapping region 138o can have a linewidth d3 that is up to about 100% wider than linewidth d2 and / or linewidth d3. The offset represented by distance d4 shows a slight pattern misalignment of up to about 50% of linewidth d1 and / or linewidth d2 (whichever is smaller). When linewidth d1 is equal to linewidth d2, the corresponding offset represented by distance d5 is equal to distance d4.

[0044] exist Figure 19DIn this process, the linewidth d1 of the metallized pattern 138a from the first patterning process can be smaller than the linewidth d2 of the metallized pattern 138b from the second patterning process. The overlapping region 138o can have a linewidth d3 that is approximately the same as the wider of the linewidths d1 and d2. An offset d4 is created between the metallized patterns 138a and 138b. Figure 19C and Figure 19D The embodiments can also be combined. In such embodiments, Figure 19C The corresponding width d5 ​​is not equal to the width d4.

[0045] exist Figure 20 In this process, the process of forming dielectric layer 130, via 136, and metallization pattern 138 can be repeated multiple times as needed to include additional layers of redistribution structure 128. For example, as shown, dielectric layer 140 can be deposited using materials and processes similar to those used for depositing dielectric layer 130. Dielectric layer 140 can then be patterned using processes and materials similar to those described for dielectric layer 130, e.g., regarding... Figures 5 to 8 or Figures 12 to 16 Then, the via 146 and the metallization pattern 148 can be deposited using processes and materials similar to those discussed above regarding the via 136 and the metallization pattern 138.

[0046] It should be understood that the redistribution structure 128 can be formed using other suitable processes. For example, the process described above conforms to a dual damascene process, wherein trenches and via openings are formed in dielectric layer 130, with the via openings located below and connected to the trenches. Conductive material is then filled into the trenches and via openings to form metal lines (e.g., metallized pattern 138) and vias (e.g., vias 136), respectively. A single damascene process can also be used, wherein trenches are first formed in dielectric layer (e.g., dielectric layer 130), and then the trenches are filled with conductive material. A planarization process, such as CMP, is then performed to remove excess conductive material above the top surface of the dielectric layer, leaving metal lines in the trenches. The vias are then formed separately in a manner similar to forming the metal lines. Other suitable processes can still be used to form the redistribution structure 128. All such processes can utilize stitching processes, such as those described above. Figures 12 to 16 The described area is patterned to be larger than the photomask used for light patterning.

[0047] Still referencing Figure 20An insulating layer 170 can be deposited over the redistribution structure 128, and conductive connections 172 can be formed through the insulating layer 170 to contact the top metal parts of the redistribution structure 128. The insulating layer 170 can be any suitable insulating material that can be patterned using a photolithographic mask, such as PBO, polyimide, BCB, etc. In other embodiments, the insulating layer 170 is formed of nitrides, such as silicon nitride; oxides, such as silicon oxide, PSG, BSG, BPSG; etc. The insulating layer 170 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. The insulating layer 170 is then patterned to form openings that expose portions of the uppermost metallized pattern (e.g., metallized pattern 148) of the redistribution structure 128. Patterning can be performed by acceptable processes, such as exposing the insulating layer 170 to light when the insulating layer 170 is a photosensitive material, or by etching, for example, anisotropic etching. If the insulating layer 170 is a photosensitive material, the insulating layer 170 can be developed after exposure.

[0048] Conductive connector 172 is formed in an opening in insulating layer 170. In some embodiments, conductive connector 172 may include an optional under-bump metal (UBM) extending through insulating layer 170 to physically and electrically couple metallization pattern 148. UBM may be formed of the same material as metallization pattern 148. Conductive connector 172 may include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium-immersion gold (ENEPIG) technology, etc. Conductive connector 172 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. Conductive connector 172 may be formed by sputtering, printing, electroplating, electroless plating, CVD, etc. Conductive connector 172 may be solderless and have substantially vertical sidewalls. In some embodiments, conductive connector 172 includes metal pillars and a metal overlay formed on top of the metal pillars. The metallic coating may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0049] Figure 21 It shows Figure 20 A top view of the structure. The conductive connector 172 is shown as being arranged in a regular pattern; however, it should be understood that the conductive connector 172 may be arranged randomly or in a varying pattern. Figure 20 and Figure 21 The resulting structure shown may include separate intermediate layer regions 100A, 100B, 100C, etc. (such as regarding...) Figure 10 (as shown) and / or may include two or more patterned regions (such as those shown) Figure 17 The super-small chip interposer layer 100' is made as shown.

[0050] exist Figure 22 middle, Figure 20 The structure can be divided into small chips, such as a chip interposer 100, which may correspond to interposer regions 100A, 100B, or 100C (etc.), or a superchip interposer 100' (corresponding to one or more stitched interposer / pattern regions 100A, 100B, and / or 100C (etc.)). In some embodiments, forming the chip interposer 100 may include using a slitting process that includes sawing along, for example, a scribe line region between a first interposer region 100A and a second interposer region 100B. The sawing separates the first interposer region 100A from the second interposer region 100B. In other embodiments, the sawing may occur between the superchip interposer 100' and an adjacent superpackage 100' produced by the stitching process described above. The resulting chiplet interposer 100 is provided as an example and may originate from the first interposer region 100A, or may include each of the first interposer / pattern region 100A, the second interposer / pattern region 100B, and the third interposer / pattern region 100C in the superchiplet interposer 100' discussed above. However, it should be understood that the superchiplet interposer 100' shown is merely an example, and any number of interposer / pattern regions can be combined into a superchiplet interposer 100' that is horizontally and / or vertically adjacent to each other in the stitching process described above.

[0051] exist Figure 23 In the middle, a chiplet interposer 100 is mounted to a carrier substrate 202. Each chiplet interposer 100 corresponds to... Figure 22 A chiplet interposer 100 is shown. Although two chiplet interposers 100 are shown, fewer or more additional chiplet interposers 100 can be placed. Furthermore, the chiplet interposers 100 can be identical or different. For example, one of the shown chiplet interposers 100 can correspond to package region 100B, while another shown chiplet interposer 100 can correspond to super chiplet interposer 100', and so on. Pick-up and placement processes can be used to pick up and place the chiplet interposers 100 onto the carrier substrate 202. A release layer can be formed on the carrier substrate 202, which serves both as an adhesive and can be easily removed in subsequent steps of removing the carrier substrate 202. The carrier substrate 202 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 202 can be a wafer, thereby allowing multiple packages to be formed simultaneously on the carrier substrate 202.

[0052] The release layer can be formed of a polymer-based material that can be removed from the structure above, along with the carrier substrate 202, in subsequent steps. In some embodiments, the release layer is a thermally release material based on epoxy resin that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer can be a UV adhesive that loses its adhesiveness upon exposure to UV light. The release layer can be dispensed and cured as a liquid, can be a laminated film laminated onto the carrier substrate, or can be the like. The top surface of the release layer can be flush and can have a high degree of planarity.

[0053] Figure 23 Optional vias 210 are also shown. Vias 210 can be formed before or after the chip interposer 100 is placed. Vias 210 are formed on the carrier substrate 202 and extend away from the carrier substrate 202 in a direction perpendicular to the main surface of the carrier substrate 202. As an example of forming vias 210, a seed layer (not shown) can be formed above the carrier substrate 202. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to a conductive via. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating (such as electroplating, electroless plating, etc.). The conductive material can include metals such as copper, titanium, tungsten, and aluminum. Remove the portion of the photoresist and seed layer where no conductive material has formed. The photoresist can be removed using an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, remove the exposed portion of the seed layer, such as by using an acceptable etching process, such as wet etching or dry etching. The remaining portion of the seed layer and conductive material forms the via 210.

[0054] exist Figure 24 In this process, a sealant 214 can be deposited over and between the chiplet interposer 100 and the via 210. After formation, the sealant 214 seals the via 210 and the chiplet interposer 100. The sealant 214 can be a molding compound, epoxy resin, etc. The sealant 214 can be applied by compression molding, transfer molding, etc., and can be formed over the carrier substrate 202, thereby burying or covering the via 210 and / or the chiplet interposer 100. The sealant 214 is further formed in the gap regions between the chiplet interposers 100 and between the chiplet interposers 100 and the via 210. The sealant 214 can be applied in liquid or semi-liquid form and then subsequently cured.

[0055] exist Figure 25 In this process, a planarization process is performed on the sealant 214 to expose the through-hole 210 and the conductive connector 172. The planarization process may also remove material from the through-hole 210 and the conductive connector 172 until the conductive connector 172 and the through-hole 210 are exposed. The top surfaces of the through-hole 210, the conductive connector 172, and the sealant 214 are substantially coplanar after the planarization process within a process variation. In some embodiments, the sealant 214 may continue to surround the conductive connector 172, while in other embodiments, the conductive connector 172 may be flush with the upper surface of the insulating layer 170, some of which may also be removed by the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), grinding, etc. In some embodiments, planarization may be omitted, for example, if the through-hole 210 and / or the conductive connector 172 have already been exposed.

[0056] exist Figure 26 In this process, a front redistribution structure 228 is formed over the sealant 214, the via 210, and the chip interposer 100. The front redistribution structure 228 includes a dielectric layer 228-d and a metallization pattern 228-m. The front redistribution structure 228 can be formed using similar processes and materials to the redistribution structure 128 described above, including the use of optional stitching processes to implement multiple stitched patterning steps, as described above.

[0057] A sealant 230 may be deposited over the redistribution structure 228. In some embodiments, such as Figure 26 As shown, the redistribution structure 228 may have a smaller lateral extent than the lateral extent of the carrier substrate 202. In such embodiments, the sealant may be located on the sidewalls of the redistribution structure 228. In other embodiments, the redistribution structure 228 may extend into the lateral extent of the carrier substrate 202. The sealant 230 may be formed using processes and materials similar to those described above with respect to sealant 214. The material composition of the sealant 230 may be the same as or different from that of the sealant 214. In some embodiments, the sealant 230 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof, and may be deposited by spin coating or the like. In some embodiments, the sealant 230 may be formed first, then an opening may be made in the sealant 230, the redistribution structure 228 may be formed in the opening, and an additional layer of the sealant 230 may be formed over the redistribution structure 228.

[0058] An opening can then be formed in the sealant 230 to expose the top metallized pattern 228-m of the redistribution structure 228. A conductive connector 235 can be formed in the opening on the top metallized pattern 228-m. The conductive connector 235 can be formed using processes and materials similar to those described above with respect to conductive connector 172, including optional under-bump metallization (UBM). In embodiments where the conductive connector 235 does not include solder bumps, solder bumps 237 can also be formed on the conductive connector 235. The solder bumps 237 can be formed by any suitable process, such as by solder printing or plating followed by a reflow process.

[0059] exist Figure 27 In this configuration, device 250 can be mounted to conductive connector 172 via solder bumps 237. Device 250 may include device 250A, device 250B, and device 250C. Device 250 may include integrated circuit dies, system-on-integrated circuit (SOIC) devices, chiplet devices, etc. For example, device 250 may include logic devices (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), application processor (AP), microcontroller, etc.), memory devices (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management devices (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) devices, sensor devices, microelectromechanical systems (MEMS) devices, signal processing devices (e.g., digital signal processing (DSP) dies), front-end devices (e.g., analog front-end (AFE) dies), etc., or combinations thereof.

[0060] Each of the devices 250 (e.g., devices 250A, 250B, and 250C) can be of the same or different types, such as those types listed above. Device 250 may include a front-side connector 255. Pick-and-place processes may be used to pick up and place the devices 250 to align the front-side connector 255 with the conductive connector 235, and bonding processes may occur, for example, by reflowing solder bumps 237 to physically and electrically couple the devices 250 to the conductive connector 235.

[0061] After device 250 is mounted to conductive connector 235, optional underfill 260 may be deposited under device 250, between device 250 and redistribution structure 228, and around the joint between conductive connector 235 and front connector 255. In some embodiments, underfill 260 may extend upward between mounted devices 250, or even to the upper surface of mounted device 250. Underfill 260 may reduce stress and protect the joint from reflow of solder bumps 237. Underfill may be formed by capillary flow process after device 250 is attached, or by suitable deposition method prior to device 250 attachment.

[0062] After depositing the optional underfill, a sealant 265 can be deposited over the redistribution structure 228 and between the device 250. The sealant 265 can be deposited using processes and materials similar to those used for depositing sealant 214, as described above. Figure 24 The discussion focuses on the following. Specifically, sealant 265 can be deposited to completely cover the thickness of device 250, followed by a planarization process such as CMP to flush the upper surface of sealant 265 with the upper surface of device 250. In some embodiments, device 250 can be thinned using a planarization process. In some embodiments, underfill 260 can be omitted, and sealant 265 can be used simultaneously as both underfill 260 and sealant 265.

[0063] exist Figure 28 In this process, the carrier substrate 202 can be removed by a peeling process, and the structure can be flipped and attached to the mounting platform 204. The mounting platform 204 can be another carrier substrate similar to the carrier substrate 202, tape, mounting frame, etc. In an exemplary peeling process, peeling involves projecting light, such as laser or UV light, onto a release layer, causing the release layer to decompose under the heat of the light, and the carrier substrate 202 can be removed. The structure is then flipped and placed on tape (not shown). If a release layer is not used, the structure can be flipped and placed on the mounting platform 204, and the carrier substrate 202 can then be mechanically removed by upward pressure or by grinding the carrier substrate 202 in a polishing process. The removal of the carrier substrate 202 exposes the carrier substrate 110 of the chiplet interposer 100.

[0064] exist Figure 29In this process, the chiplet interposer 100 is modified by removing the carrier substrate 110. The carrier substrate 110 of the chiplet interposer 100 can be removed by a planarization process that removes the carrier substrate 110 and makes the (now) upper surface of the via 210 flush with the sealant 214 and the upper surface of the chiplet interposer 100. The planarization process can include planarization processes such as polishing, CMP, etching, or combinations thereof. In some embodiments, a release layer 112 can be used between the dielectric filler 120 and the carrier substrate 110. In such embodiments, the release layer 104 can be used to more easily release the carrier substrate 110, for example by performing a back etch of the sealant 214 and the via 210 until the carrier substrate 110 is exposed. The carrier substrate 110 can then be removed by projecting light, such as laser or UV light, onto the release layer 112, causing the release layer 112 to decompose under the heat of the light, and the carrier substrate 110 can be removed. After removing the carrier substrate 110 in this manner, the CMP process can still be used to flush the upper surfaces of the sealant 214, via 210, dielectric filler 120, and via 125. After removing the carrier substrate 110, the thickest layer of the chiplet interposer 100 is the dielectric filler 120, which serves as the substrate of the chiplet interposer 100. In some embodiments, one main surface of the chiplet interposer 100 may include the dielectric filler 120, and the other main surface of the chiplet interposer 100 may include the redistribution structure 128.

[0065] exist Figure 30 In this process, an optional redistribution structure 278 can be formed above the chiplet interposer layer 100. The redistribution structure 278 can use methods similar to those described above. Figure 26 The redistribution structure 228 is discussed in terms of the processes and materials used in its formation. A sealant 280 may be deposited on and / or around the redistribution structure 278. The sealant 280 may be similar to that discussed above. Figure 26 The sealant 230 is formed using the processes and materials discussed above. An opening can then be formed in the sealant 280 to expose the top metallization pattern of the redistribution structure 278. Conductive connectors 285 can be formed in the openings in the top metallization pattern of the redistribution structure 278. Conductive connectors 285 can be formed using processes and materials similar to those described above with respect to conductive connector 172, including optional under-bump metallization (UBM). In embodiments where conductive connector 285 does not include solder bumps, solder bumps 287 can also be formed on conductive connector 285. Solder bumps 287 can be formed by any suitable process, such as by solder printing or plating followed by a reflow process.

[0066] exist Figure 31In this process, the mounting platform 204 can be removed and the structure flipped. The completed structure can be a package device 300, which includes multiple devices 250 and one or more chip interposers 100, which help redistribute signals from devices 250 to conductive connectors 285 or from conductive connectors 285 to devices 250. Optional stitching processes can be used to form a superpackage including a metallized pattern that extends beyond the lateral boundaries of a photomask (e.g., an intermediate mask) used for optical patterning.

[0067] Figure 32 A packaged device 300 according to another embodiment is shown. Figure 32 In this embodiment, the via 210 is omitted. In such an embodiment, the process of forming the via 210 can be omitted, and the sealant 214 can be formed laterally around the chiplet interposer 100 (see...). Figure 24 ).

[0068] Figure 33 A packaged device 300 according to another embodiment is shown. Figure 33 In this case, the via 125 within the small chip interposer layer 100 can be omitted (see...). Figure 2 In such an embodiment, the formation of through hole 125 can be omitted (see...). Figure 1 The process (and its accompanying description) and the dielectric filler 120 can be deposited on the carrier substrate 110.

[0069] Figure 34 A packaged device 300 according to another embodiment is shown. Figure 34 In this embodiment, the redistribution structure 278 can be omitted. (See [link to example]). Figure 30 The process (and its accompanying description) and the sealant 280 can be directly formed on the through hole 125, through hole 210, sealant 214 and dielectric filler 120.

[0070] Figures 31 to 34Each of the packaged devices 300 shown utilizes a chiplet interposer 100 without a silicon substrate such as a carrier substrate 110. Instead, the interposer 100 acts as a “substrate” of dielectric filler 120, which may also have optional vias 125. Because the chiplet interposer 100 does not have a silicon substrate, the stress concentration of the chiplet interposer 100 is less than that of other interposer technologies. For example, the Young's modulus of a silicon substrate can be between about 130 and 180 GPa, depending on the thickness, crystal orientation, and axial direction. In contrast, the Young's modulus of dielectric filler 120 can be between about 50 and about 100 GPa, such as between about 65 and 75 GPa. Therefore, the chiplet interposer 100 exhibits significantly less stress concentration than other interposer technologies. The reduced stress modulus also allows for the successful use of interposers with larger coverage areas and the stitching processes described above.

[0071] Figures 35 to 45 Intermediate steps in the process of forming a packaged device according to some embodiments are shown. In the illustrated process, the same references refer to the same components previously described. Figures 35 to 45 In the process, device 250 is first attached to the carrier and then attached to chiplet interposer 100 during subsequent processes.

[0072] exist Figure 35 In this embodiment, a carrier substrate 302 is provided. Devices 250 (such as devices 250A and 250B) are attached to the carrier substrate 302. The carrier substrate 302 may be made of a material similar to that of the carrier substrate 110, and the devices 250 may be attached to the carrier substrate 302 using a release layer similar to the release layer 112 discussed above.

[0073] exist Figure 36 In this process, a sealant 265 is deposited laterally around the device 250. In some embodiments, the sealant 265 may cover the connector 255 of the device 250, such as... Figure 36 As shown in the diagram. In some embodiments, connector 255 may not protrude from device 250 and sealant may be disposed on the upper surface of device 250, but not laterally around connector 255. Sealant 265 may be formed using a process and materials similar to sealant 214, as described above. Figure 24 As described.

[0074] exist Figure 37 In this process, a planarization process, such as CMP, is used to flush the upper surfaces of the sealant 265 and the connector 255. In embodiments where the connector 255 is embedded in the device 250, the planarization process may also flush the sealant 265 with the upper surface of the remaining portion of the device 250. In such embodiments, the planarization process can expose the connector 255 from the sealant 265.

[0075] Next step Figure 37 In this embodiment, a redistribution structure 228 is formed above the sealed device 250. The redistribution structure 228 is used for routing signals to and from the connectors 255 of the device 250. The redistribution structure 228 is similar to the redistribution structure 228 described above and can be formed using similar processes and materials. In some embodiments, a sealant 230 laterally seals the redistribution structure 228. Conductive connectors 235 and solder bumps 237 are formed above the redistribution structure 228. The conductive connectors 235 and solder bumps 237 can be formed using processes and materials similar to those described above. A via 210 is also formed above the redistribution structure 228. The via 210 can be formed using processes and materials similar to those discussed above. However, it should be noted that the via 210 can be deposited on the metallization pattern 228-m (or on the underlying bump structure formed on the metallization pattern 228-m). The deposition of the through-hole 210 can be accomplished, for example, by a plating process, such as electroplating or electroless plating.

[0076] exist Figure 38 In this configuration, the chiplet interposer 100 is attached to the conductive connector 235 via solder bumps 237. The chiplet interposer 100 may have a carrier (such as a carrier substrate 110, as described above) attached thereto for processing purposes. It should be understood that while one chiplet interposer 100 is shown, any number of such chiplet interposers 100 can be used. Furthermore, the chiplet interposer 100 can be any chiplet interposer 100 discussed above, including a super chiplet interposer 100' which contains multiple patterned regions disposed therein and bonded together by a stitching process.

[0077] exist Figure 39 Optionally, an underfill 260 can be deposited or implanted between the chiplet interposer 100 and the redistribution structure 228 via a capillary flow process to surround and support the connection between the conductive connectors 235 and 172. A sealant 265 is deposited over the via 210 and the chiplet interposer 100, laterally surrounding them. In embodiments where the underfill 260 is omitted, the sealant 265 may also be used as the underfill.

[0078] exist Figure 40In this process, a planarization process can be implemented to flush the upper surface of the dielectric filler 120 of the chiplet interposer 100 with the sealant 265 and vias 210. The chiplet interposer 100 is also modified by removing the carrier substrate 110 of the chiplet interposer. For example, the carrier substrate 110 can be removed as part of a planarization process or as part of a separation process. The planarization process can include polishing, etching, CMP processes, or combinations thereof. In some embodiments, a release layer 112 can be used between the dielectric filler 120 and the carrier substrate 110. In such embodiments, the release layer 104 can be used to more easily release the carrier substrate 110, for example by performing a back etch of the sealant 214 and vias 210 until the carrier substrate 110 is exposed. The carrier substrate 110 can then be removed by projecting light, such as laser or UV light, onto the release layer 112, causing the release layer 112 to decompose under the heat of the light, and the carrier substrate 110 can be removed. After removing the carrier substrate 110 in this manner, the CMP process can still be used to flush the upper surfaces of the sealant 214, via 210, dielectric filler 120, and via 125. After removing the carrier substrate 110, the thickest layer of the chiplet interposer 100 is the dielectric filler 120, which serves as the substrate of the chiplet interposer 100. In some embodiments, one main surface of the chiplet interposer 100 may include the dielectric filler 120, and the other main surface of the chiplet interposer 100 may include the redistribution structure 128.

[0079] exist Figure 41 In this process, an optional redistribution structure 278 can be formed above the chiplet interposer layer 100. The redistribution structure 278 can use methods similar to those described above. Figure 26 The redistribution structure 228 is discussed in terms of the processes and materials used in its formation. A sealant 280 may be deposited on and / or around the redistribution structure 278. The sealant 280 may be similar to that discussed above. Figure 26 The sealant 230 is formed using the processes and materials discussed above. An opening can then be formed in the sealant 280 to expose the top metallization pattern of the redistribution structure 278. Conductive connectors 285 can be formed in the openings in the top metallization pattern of the redistribution structure 278. Conductive connectors 285 can be formed using processes and materials similar to those described above with respect to conductive connector 172, including optional under-bump metallization (UBM). In embodiments where conductive connector 285 does not include solder bumps, solder bumps 287 can also be formed on conductive connector 285. Solder bumps 287 can be formed by any suitable process, such as by solder printing or plating followed by a reflow process.

[0080] exist Figure 42In this process, the carrier substrate 302 can be removed and the structure flipped using a peeling process. In an exemplary peeling process, peeling involves projecting light, such as laser or UV light, onto the release layer, causing the release layer to decompose under the heat of the light, and thus removing the carrier substrate 302. If the release layer is not used, the structure can be flipped, and the carrier substrate 302 can then be mechanically removed by applying upward pressure or by grinding the carrier substrate 302 in a polishing process.

[0081] Figure 42 The completed structure shown can be a packaged device 400 comprising a plurality of devices 250 and one or more chiplet interposers 100, which facilitates the redistribution of signals from devices 250 to conductive connectors 285 or from conductive connectors 285 to devices 250. An optional stitching process can be used to form the superchiplet interposer 100'. As the chiplet interposer 100, it includes a metallization pattern that extends beyond the lateral boundary of a photomask (e.g., an intermediate mask) used for optical patterning.

[0082] Figure 43 A packaged device 400 according to another embodiment is shown. Figure 43 In this embodiment, the via 210 is omitted. In such an embodiment, the process of forming the via 210 can be omitted, and the sealant 214 can be formed laterally around the chiplet interposer 100 (see...). Figure 39 ).

[0083] Figure 44 A packaged device 400 according to another embodiment is shown. Figure 44 In this case, the via 125 within the small chip interposer layer 100 can be omitted (see...). Figure 2 In such an embodiment, the formation of through hole 125 can be omitted (see...). Figure 1 The process (and its accompanying description) and the dielectric filler 120 can be deposited on the carrier substrate 110.

[0084] Figure 45 A packaged device 400 according to another embodiment is shown. Figure 45 In this embodiment, the redistribution structure 278 can be omitted. (See [link to example]). Figure 41 The process (and its accompanying description) and the sealant 280 can be directly formed on the through hole 125, through hole 210, sealant 214 and dielectric filler 120.

[0085] Figures 35 to 45Each of the packaged devices 400 shown utilizes a chiplet interposer 100 without a silicon substrate such as a carrier substrate 110. Instead, the interposer 100 acts as a “substrate” of dielectric filler 120, which may also have optional vias 125. Because the chiplet interposer 100 does not have a silicon substrate, the stress concentration of the chiplet interposer 100 is less than that of other interposer technologies. For example, the Young's modulus of a silicon substrate can be between about 130 and 180 GPa, depending on the thickness, crystal orientation, and axial direction. In contrast, the Young's modulus of dielectric filler 120 can be between about 50 and about 100 GPa, such as between about 65 and 75 GPa. Therefore, the chiplet interposer 100 exhibits significantly less stress concentration than other interposer technologies. The reduced stress modulus also allows for the successful use of interposers with larger coverage areas and the stitching processes described above.

[0086] Other components and processes may also be included with packaged devices 300 and 400. For example, test structures may be included to aid in the verification testing of packaged devices 300 and 400. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow for testing of packaged devices 300 and 400, the use of probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods incorporating intermediate verification of known good dies to increase yield and reduce cost. Subsequent processes can mount packaged devices 300 and / or 400 to a device substrate.

[0087] Figures 46 to 51 It is a horizontal cross-sectional view through the chip interposer layer 100 of package device 300 and package device 400. Figure 46 It is along Figure 31 An exemplary cross-sectional view taken by line A-A' (for packaged device 300), and Figure 47 It is along Figure 42 An exemplary cross-sectional view taken by line B-B' in the diagram (for packaged device 400). Figures 46 to 51 Each of the diagrams illustrates various configurations for chiplet interposers 100 in similar structures along similar horizontal cross-sections. It should be understood that the cross-sectional diagrams are merely examples and they can be combined in any suitable manner to achieve a particular layout or configuration. For example, more or fewer chiplet interposers 100 than those depicted can be combined. Furthermore, super-chiplet interposers 100' can be used and combined with other chiplet interposers, such as… Figures 46 to 51 As shown in the image.

[0088] exist Figure 46 In some embodiments, a horizontal cross-sectional view through the chiplet interposer layer 100 is shown. Figure 46As indicated in the document, devices 300 / 400 may have multiple chiplet interposer layers 100. Figure 46 In this example, four chiplet interposers 100 are disposed within a layer of sealant 214. More or fewer chiplet interposers 100 may be used. Because the chiplet interposers 100 consist of dielectric filler 120 instead of a silicon substrate layer (e.g., carrier substrate 110), the stress concentration of each of the multiple chiplet interposers 100 is small, resulting in higher reliability due to reduced risk of warpage and delamination. The chiplet interposers 100 may each have the same interposer design, different interposer designs, or a combination of the same and different interposer designs. The chiplet interposers 100 may also comprise an interposer with a patterned region or a mixture of super-chiplet interposers 100' with multiple patterned regions (side-by-side).

[0089] exist Figure 47 In some embodiments, a horizontal cross-sectional view through the chiplet interposer layer 100 is shown. Figure 47 In the illustrated embodiment, a superchiplet interposer 100' is included as a chiplet interposer 100. The superchiplet interposer 100' may have multiple patterned regions, such as patterned regions 100A and 100B. Devices 300 / 400 may have multiple chiplet interposers 100, including multiple superchiplet interposers 100', chiplet interposers 100, or combinations thereof. Figure 47 In one example, a superchippery interposer 100' is disposed within a layer of sealant 214. More or fewer chippery interposers 100 can be used. Because the superchippery interposer 100' consists of a dielectric fill layer 120 instead of a silicon substrate layer (e.g., a carrier substrate 110), each superchippery interposer 100' has low stress concentration, resulting in higher reliability due to reduced warpage and delamination risk. When using multiple chippery interposers 100 (including the superchippery interposer 100'), each chippery interposer 100 can have the same interposer design, different interposer designs, or a combination of the same and different interposer designs.

[0090] exist Figure 48 In some embodiments, a horizontal cross-sectional view through the chiplet interposer layer 100 is shown. Figure 48 The illustrated embodiment includes a hybrid of a chiplet interposer 100 and a super-chiplet interposer 100'. The super-chiplet interposer 100' may have multiple patterned regions, such as patterned regions 100A and 100B. Figure 48In this example, two superchip interposers 100' are disposed within a layer of sealant 214, and two chiplet interposers 100 are disposed within a layer of sealant 214. More or fewer chiplet interposers 100 (and / or superchiplet interposers 100') can be used. Because the chiplet interposers 100 and / or superchiplet interposers 100' consist of dielectric filler 120 instead of a silicon substrate layer (e.g., carrier substrate 110), each of the chiplet interposers 100 and / or superchiplet interposers 100' has low stress concentration, resulting in higher reliability due to reduced warpage and delamination risk. Multiple chiplet interposers 100 and / or superchiplet interposers 100' can each have the same interposer design, different interposer designs, or a combination of the same and different interposer designs.

[0091] exist Figure 49 In some embodiments, a horizontal cross-sectional view through the chiplet interposer layer 100 is shown. Figure 49 In the illustrated embodiment, two superchiplet interposers 100' are included. Each superchiplet interposer 100' may have multiple patterned regions, such as patterned regions 100A, 100B, and 100C. Devices 300 / 400 may have multiple chiplet interposers 100, including multiple superchiplet interposers 100', chiplet interposers 100, or combinations thereof. Figure 49 In this example, two superchiplet interposers 100' are disposed within a layer of sealant 214. More or fewer chiplet interposers 100 and / or superchiplet interposers 100' can be used. Because the superchiplet interposers 100' consist of a dielectric fill layer 120 instead of a silicon substrate layer (e.g., a carrier substrate 110), each superchiplet interposer 100' has low stress concentration, resulting in higher reliability due to reduced warpage and delamination risk. When using multiple chiplet interposers 100 and / or superchiplet interposers 100', each chiplet interposer 100 can have the same interposer design, different interposer designs, or a combination of the same and different interposer designs.

[0092] exist Figure 50 and Figure 51 In some embodiments, a horizontal cross-sectional view through the chiplet interposer layer 100 is shown. Figure 50 and Figure 51 In the illustrated embodiment, a superchiplet interposer 100' is included as the chiplet interposer 100. Figure 50 In the superchip interposer layer 100', multiple patterned regions may be present, such as patterned regions 100A, 100B, 100C, 100D, 100E, and 100F. Figure 51In this context, the superchiplet interposer 100' may have multiple patterned regions, such as patterned regions 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 100H. Devices 300 / 400 may have multiple chiplet interposers 100, including multiple superchiplet interposers 100', chiplet interposers 100, or combinations thereof. Figure 50 and Figure 51 In the example shown, a superchippery interposer 100' is disposed within a layer of sealant 214. More or fewer chippery interposers 100 can be used. Because the superchippery interposers 100' consist of dielectric filler 120 instead of a silicon substrate layer (e.g., carrier substrate 110), each of the superchippery interposers 100' has low stress concentration, resulting in higher reliability due to reduced warpage and delamination risk. When using multiple chippery interposers 100 (including superchippery interposers 100'), each chippery interposer 100 can have the same interposer design, different interposer designs, or a combination of the same and different interposer designs.

[0093] Figures 46 to 51 The examples provided are intended as non-limiting examples. They can be combined to form different configurations and layouts using chiplet interposer 100 and / or superchiplet interposer 100'. For superchiplet interposer 100', any number of patterned areas can be stitched together. Although superchiplet interposer 100' is shown as a rectangle, the patterned areas can be stitched together to form other shapes, such as el shapes, tee shapes, plus sign shapes, rectangular ring shapes, etc.

[0094] The embodiments advantageously utilize one or more chiplet interposers for signal routing in packaged devices. Chiplet interposers offer significant advantages over other interposer technologies. In particular, chiplet interposers do not have a silicon substrate portion. Instead, the functional "substrate" of the chiplet interposer is a dielectric filler material formed over a carrier substrate that is subsequently removed. Redistribution structures can be formed on either side of the dielectric filler "substrate" to provide signal routing capabilities, and vias disposed in the dielectric filler can transmit signals from one side of the interposer to the opposite side. By removing the silicon substrate portion of the interposer and relying solely on the dielectric filler as the "substrate," stress concentration in the interposer is reduced. Consequently, warpage in the finished package is reduced, and the likelihood of delamination of the sealant around the chiplet interposer is decreased. The embodiments further provide advantages regarding the patterning of the chiplet interposer. When a redistribution structure is formed over the dielectric filler, two or more adjacent regions of the metallization pattern of the redistribution structure can be stitched together to provide a metallization pattern with a coverage area larger than typically possible for a given photomask size.

[0095] One embodiment is a method including attaching a first interposer to a package structure, the first interposer including a dielectric filler formed on a carrier substrate. The method also includes laterally sealing the first interposer in a first sealant. The method also includes attaching a first device to the package structure. The method also includes laterally sealing the first device in a second sealant. The method also includes removing a portion of the first sealant and removing the carrier substrate of the first interposer to expose the dielectric filler. The method also includes forming external connectors on the package structure, one or more of the external connectors being electrically coupled to the first device through the first interposer. In one embodiment, a via extending through the dielectric filler of the first interposer is formed. In one embodiment, a via extending through the first sealant is formed. In one embodiment, a redistribution structure is formed over the first interposer, the redistribution structure being wider than the first interposer and situated between the first interposer and the external connector. In one embodiment, a first portion of a first photopatternable material is exposed to a first photomask pattern; a second portion of the first photopatternable material is exposed to a second photomask pattern, wherein the first portion overlaps with the second portion, and the first and second portions together form a first pattern; and a metallization pattern is formed based on the first pattern. In one embodiment, the metallization pattern in the overlapping region of the first and second portions has a wider linewidth than the metallization pattern in either the first or second portion. In one embodiment, a second interposer is attached to the package structure, the second interposer being adjacent to the first interposer, the second interposer including a second dielectric filler formed on a second carrier substrate, and the second carrier substrate is removed to expose the second dielectric filler. In one embodiment, the first interposer is attached to the package structure after the first device is attached to the package structure.

[0096] Another embodiment is a package including a first device, the first device being laterally sealed by a first sealant. The package also includes a first interposer, the first interposer including a dielectric filler layer, the first interposer having no silicon layer, and the first interposer being laterally sealed by a second sealant. The package also includes external connectors, one or more of which are electrically coupled to the first device through the first interposer. In one embodiment, the dielectric filler layer of the first interposer includes a group of vias disposed in the dielectric filler layer. In one embodiment, the first interposer includes a first redistribution structure and a second redistribution structure disposed on opposite sides of the dielectric filler layer. In one embodiment, the package includes vias extending through a second sealant. In one embodiment, the first interposer includes a redistribution structure including a first metallization pattern, the first metallization pattern including an overlapping conductor having a first width, a first metal line of the first metallization pattern having a second width, the first metal line continuously extending into the overlapping conductor, the first width being greater than the second width. In one embodiment, the second metal line of the first metallization pattern extends continuously into the overlapping conductor on the side opposite to the first metal line, the first metal line being offset from the second metal line and parallel to the second metal line.

[0097] Another embodiment is a packaged device including one or more embedded devices. The packaged device also includes a first sealant layer that seals the one or more embedded devices. The packaged device also includes one or more chiplet interposers, each of the one or more chiplet interposers having a substrate comprising a first material having a Young's modulus between 50 GPa and 100 GPa. The packaged device also includes a second sealant layer that seals the one or more chiplet interposers. The packaged device also includes a first redistribution structure disposed between the first and second sealant layers. The packaged device also includes external connectors, wherein one or more of the external connectors are electrically coupled to the one or more embedded devices and electrically coupled to the one or more chiplet interposers. In an embodiment, each of the one or more chiplet interposers includes a dielectric fill layer. In an embodiment, at least one of the one or more chiplet interposers has a dielectric fill layer comprising a via through the thickness of the dielectric fill layer. In an embodiment, the packaged device further includes a second redistribution structure disposed between the external connectors and the one or more chiplet interposers, the second redistribution structure electrically coupling a first chiplet interposer of the one or more chiplet interposers to a second chiplet interposer of the one or more chiplet interposers. In one embodiment, the packaging device further includes a via extending through a second sealant layer, the via directly physically and electrically coupling the first redistribution structure to the second redistribution structure. In another embodiment, the first interposer of one or more chiplet interposers includes a stitched redistribution structure comprising a first metallization pattern having a first portion, a second portion, and an overlapping portion corresponding to the overlapping areas of the first and second portions, wherein a first metal linewidth of the first metallization pattern in the first portion is smaller than a second metal linewidth of the first metallization pattern in the overlapping portion.

[0098] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a package, comprising: A dielectric filler is deposited on a carrier substrate, and one or more metallization patterns are formed on the dielectric filler to form an interlayer structure; A first interposer layer is separated from the interposer structure, the first interposer layer comprising a first carrier substrate separated from the carrier substrate and a first dielectric filler separated from the dielectric filler; Attach the first intermediary layer to the packaging structure; The first intermediate layer is laterally sealed in the first sealant; Attach the first device to the package structure; The first device is laterally sealed in the second sealant; After sealing the first device, a portion of the first sealant is removed and the first carrier substrate of the first interlayer is removed to expose the first dielectric filler; as well as An external connector is formed on the package structure, and one or more of the external connectors are electrically coupled to the first device through the first interposer layer.

2. The method according to claim 1, further comprising: A via is formed that extends through the first dielectric filler of the first interlayer.

3. The method according to claim 1, further comprising: A through-hole is formed extending through the first sealant.

4. The method according to claim 1, further comprising: A redistribution structure is formed above the first intermediary layer, the redistribution structure being wider than the first intermediary layer, and the redistribution structure being located between the first intermediary layer and the external connector.

5. The method according to claim 1, further comprising: A first portion of a first photometic patternable material is exposed to a first photomask pattern; A second portion of the first photopatternable material is exposed to a second photomask pattern, the first portion and the second portion overlap, and the first portion and the second portion together form a first pattern; as well as A metallized pattern is formed based on the first pattern.

6. The method according to claim 5, wherein, The metallized pattern in the overlapping area of ​​the first and second portions has a wider linewidth than the metallized pattern in either the first or second portion.

7. The method according to claim 1, further comprising: A second interposer is separated from the interposer structure and attached to the package structure. The second interposer is adjacent to the first interposer and includes a second dielectric filler formed on a second carrier substrate. as well as Remove the second carrier substrate to expose the second dielectric filler.

8. The method according to claim 1, wherein, After the first device is attached to the package structure, the first interposer is attached to the package structure.

9. A package comprising: A first device, wherein the first device is laterally sealed by a first sealant; A first interposer layer, the first interposer layer including a dielectric filling layer, the first interposer layer having no silicon layer, the first interposer layer being laterally sealed by a second sealant; A first redistribution structure connects the first interposer to the first device, the first redistribution structure is located between the first interposer and the first device, and the first redistribution structure is laterally sealed by a third sealant layer; and An external connector, one or more of the external connectors, is electrically coupled to the first device through the first intermediary layer.

10. The package according to claim 9, wherein, The dielectric filling layer of the first interposer layer includes a group of vias disposed in the dielectric filling layer.

11. The package according to claim 9, wherein, The first interposer layer includes a second redistribution structure and a third redistribution structure located on the dielectric filling layer, the second redistribution structure and the third redistribution structure being disposed on opposite sides of the dielectric filling layer.

12. The package of claim 9, further comprising a through-hole extending through the second sealant.

13. The package according to claim 9, wherein, The first interposer layer includes a second redistribution structure, the second redistribution structure includes a first metallization pattern, the first metallization pattern includes an overlapping conductor having a first width, a first metal line of the first metallization pattern having a second width, the first metal line extending continuously into the overlapping conductor, and the first width being greater than the second width.

14. The package according to claim 13, wherein, The second metal line of the first metallized pattern extends continuously into the overlapping conductor on the side opposite to the first metal line, the first metal line being offset from the second metal line and parallel to the second metal line.

15. A packaged device, comprising: One or more embedded devices; A first sealant layer seals the one or more embedded devices; One or more chiplet interposers, each of the one or more chiplet interposers having a substrate, the substrate comprising a first material having a Young's modulus between 50 GPa and 100 GPa; A second sealant layer seals the one or more chip interposer layers; A first redistribution structure is disposed between the first sealant layer and the second sealant layer; A third sealant layer laterally seals the first redistribution structure; as well as External connectors, wherein one or more of the external connectors are electrically coupled to the one or more embedded devices and electrically coupled to the one or more chip interposers.

16. The packaging device according to claim 15, wherein, Each of the one or more chip interposers includes a dielectric filling layer.

17. The packaging device according to claim 16, wherein, The dielectric filling layer of at least one of the one or more chip interposers includes a via through the thickness of the dielectric filling layer.

18. The packaging device of claim 15, further comprising: A second redistribution structure is disposed between the external connector and the one or more chiplet interposers, wherein the second redistribution structure electrically couples the first chiplet interposer of the one or more chiplet interposers to the second chiplet interposer of the one or more chiplet interposers.

19. The packaging device of claim 18, further comprising: A through-hole extends through the second sealant layer, the through-hole directly physically and electrically coupling the first redistribution structure to the second redistribution structure.

20. The packaging device according to claim 15, wherein, The first interposer of the one or more chip interposers includes a stitched redistribution structure, the stitched redistribution structure including a first metallization pattern having a first portion, a second portion, and an overlapping portion corresponding to the overlapping regions of the first portion and the second portion, wherein a first metal linewidth of the first metallization pattern in the first portion is smaller than a second metal linewidth of the first metallization pattern in the overlapping portion.

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