Shielded-Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor

Abstract

The present disclosure relates to a shielded gate trench (SGT) metal oxide semiconductor field effect transistor (MOSFET). The SGT MOSFET according to the present disclosure includes: a substrate; a first epitaxial layer, disposed above the substrate; a second epitaxial layer, disposed above the first epitaxial layer; a channel region, disposed above the second epitaxial layer; a source region, disposed above the channel region; a trench, extending through the source region, the channel region, and the second epitaxial layer into the first epitaxial layer in a longitudinal direction, the trench being filled with a dielectric layer, in which a control gate and a shield gate are disposed; and a buffer region, disposed below the trench in the first epitaxial layer, the size of the buffer region being larger than the size of the trench in a lateral direction. According to the SGT MOSFET according to the present disclosure, by introducing a buffer region having a size larger than the trench below the trench, a peak-valley distribution can be formed in the longitudinal electric field of the SGT MOSFET, thereby effectively improving the voltage withstand capability of the SGT MOSFET and reducing the specific on-resistance.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductors, and in particular, to a shielded gate trench (SGT) metal oxide semiconductor field effect transistor (MOSFET). Background Art

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in power converters and power supplies due to their simple structure, ease of manufacturing, and excellent performance. Power MOSFETs are categorized into high-voltage, medium-voltage, and low-voltage types based on their withstand voltage capabilities. Among low-voltage power MOSFETs, shielded-gate trench (SGT) MOSFETs have garnered widespread attention due to their low specific on-resistance, minimal static and dynamic losses, and high switching speed. Summary of the Invention

[0003] The following is a brief overview of the present disclosure to provide a basic understanding of certain aspects of the present disclosure. However, it should be understood that this overview is not an exhaustive overview of the present disclosure, nor is it intended to identify the key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. The purpose of this overview is simply to present certain inventive concepts of the present disclosure in a simplified form as a prelude to the more detailed description that will be given later.

[0004] An object of the present disclosure is to provide a shielded gate trench (SGT) metal oxide semiconductor field effect transistor (MOSFET) capable of further improving withstand voltage capability and reducing specific on-resistance.

[0005] According to one aspect of the present disclosure, an SGT MOSFET is provided, which may include: a substrate; a first epitaxial layer, arranged above the substrate; a second epitaxial layer, arranged above the first epitaxial layer; a channel region, arranged above the second epitaxial layer; a source region, arranged above the channel region; a trench, extending through the source region, the channel region, and the second epitaxial layer into the first epitaxial layer in a longitudinal direction, the trench being filled with a dielectric layer, a control gate and a shield gate being arranged in the dielectric layer; and a buffer region, which is arranged below the trench in the first epitaxial layer, and the size of the buffer region in a lateral direction is larger than the size of the trench.

[0006] According to an embodiment of the present disclosure, the buffer region may have an elliptical, rectangular, or trapezoidal cross-section.

[0007] According to an embodiment of the present disclosure, the buffer region may be formed by an ion implantation process.

[0008] According to an embodiment of the present disclosure, the buffer region may not be in contact with the substrate.

[0009] According to an embodiment of the present disclosure, the control gate may be disposed above the shielding gate.

[0010] According to an embodiment of the present disclosure, the control gate may be disposed on both sides of the shielding gate.

[0011] According to an embodiment of the present disclosure, the substrate, the first epitaxial layer, the second epitaxial layer and the buffer region can be doped with impurities of the first conductive type, the doping concentration of the substrate can be greater than the doping concentration of the first epitaxial layer, the doping concentration of the first epitaxial layer can be greater than the doping concentration of the second epitaxial layer, and the doping concentration of the second epitaxial layer can be greater than the doping concentration of the buffer region.

[0012] According to an embodiment of the present disclosure, the channel region may be doped with impurities of the second conductivity type, and the source region may be doped with impurities of the first conductivity type.

[0013] According to an embodiment of the present disclosure, the first conductive type may be an N type, and the second conductive type may be a P type.

[0014] According to an embodiment of the present disclosure, the dielectric layer filled in the trench may include a first dielectric layer disposed at a lower portion of the trench and a second dielectric layer disposed at an upper portion of the trench.

[0015] According to an embodiment of the present disclosure, the first dielectric layer and the second dielectric layer may be formed of different materials.

[0016] According to an embodiment of the present disclosure, the first dielectric layer and the second dielectric layer may include silicon oxide or silicon nitride.

[0017] According to an embodiment of the present disclosure, the control gate and the shield gate may include polysilicon or amorphous silicon.

[0018] According to an embodiment of the present disclosure, the SGT MOSFET may further include: an insulating layer disposed above the source region and the trench; a first metal layer disposed below the substrate; and a second metal layer disposed above the insulating layer.

[0019] According to an embodiment of the present disclosure, the first metal layer and the second metal layer may include at least one of W, Pt, PtNi, Ti, and TiN.

[0020] According to the SGT MOSFET disclosed herein, by introducing a buffer region larger than the trench below the trench, a peak-valley distribution can be formed in the longitudinal electric field of the SGT MOSFET, thereby effectively improving the withstand voltage capability of the SGT MOSFET and reducing the specific on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and, together with the following description, serve to explain the principles of the present disclosure. In the drawings:

[0022] Figure 1A A cross-sectional view of an SGT MOSFET according to the prior art is shown.

[0023] Figure 1B FIG. 1 is a schematic diagram showing the longitudinal electric field distribution of an SGT MOSFET according to the prior art.

[0024] Figure 2A A cross-sectional view of an SGT MOSFET according to a first embodiment of the present disclosure is shown.

[0025] Figure 2B A schematic diagram showing the longitudinal electric field distribution of the SGT MOSFET according to the first embodiment of the present disclosure is shown.

[0026] Figure 2C A schematic diagram showing a doping concentration distribution in the longitudinal direction of the SGT MOSFET according to the first embodiment of the present disclosure.

[0027] Figure 3 A cross-sectional view of an SGT MOSFET according to a second embodiment of the present disclosure is shown.

[0028] Figure 4 A cross-sectional view of an SGT MOSFET according to a third embodiment of the present disclosure is shown.

[0029] Figure 5 A cross-sectional view of an SGT MOSFET according to a fourth embodiment of the present disclosure is shown.

[0030] Figure 6 A cross-sectional view of an SGT MOSFET according to a fifth embodiment of the present disclosure is shown.

[0031] Figure 7 A cross-sectional view of an SGT MOSFET according to a sixth embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] In this specification, it will be understood that when a component (or region, layer, portion, etc.) is referred to as being “on,” “connected to,” or “coupled to” another component, the component may be directly disposed on / directly connected to / directly coupled to the component, or a third component may be present in between. In contrast, when a component (or region, layer, portion, etc.) is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another component, no intervening component is provided therebetween.

[0033] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present disclosure can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, the same reference numerals represent the same components. Furthermore, in the drawings, the thicknesses, ratios, and sizes of components are exaggerated for clarity.

[0034] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, "a," "an," "the," and "at least one" do not represent a limitation on quantity, but are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "a component" has the same meaning as "at least one component." "At least one" should not be interpreted as limiting "one" or "an." "Or" means "and / or." The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It will be understood that although terms such as "first" and "second" are used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first component referred to as a first component in one embodiment may be referred to as a second component in other embodiments without departing from the scope of the appended claims.

[0036] Furthermore, “below,” “below,” “above,” and “upper” are used to describe the relationship between components shown in the drawings. These terms may be relative concepts and are described based on the directions presented in the drawings.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art. Terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the relevant technical context, and unless explicitly defined in the specification, these terms should not be interpreted as having formal meanings in an idealized or overly formal sense.

[0038] The meaning of “include” or “comprising” specifies properties, quantities, steps, operations, elements, parts or their combinations, but does not exclude other properties, quantities, steps, operations, elements, parts or their combinations.

[0039] Embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, variations in shape relative to the illustrated embodiment are anticipated as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather should include deviations in shape that result from, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0040] Hereinafter, exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.

[0041] Figure 1A A cross-sectional view of an SGT MOSFET according to the prior art is shown. Figure 1B FIG. 1 is a schematic diagram showing the longitudinal electric field distribution of an SGT MOSFET according to the prior art.

[0042] like Figure 1A As shown, an SGT MOSFET according to the prior art includes an epitaxial layer (also referred to herein as a "drift region") stacked on a substrate, a channel region, and a source region. Furthermore, the SGT MOSFET according to the prior art also includes a trench extending through the channel region and the source region into the epitaxial layer. The trench is filled with a dielectric layer, and a control gate and a shield gate are disposed in the dielectric layer. The control gate is disposed above the shield gate and has a larger dimension than the shield gate in a lateral direction (also referred to herein as a "horizontal direction").

[0043] According to the SGT MOSFET of the prior art, the opening of the channel in the longitudinal direction (also referred to as the "vertical direction" in this article) is controlled by applying a voltage to the control gate, and the reverse voltage is withstood by the PN junction formed by the channel region and the epitaxial layer. In addition, according to the SGT MOSFET of the prior art, the shielded gate can be connected to the same potential as the source, acting as a field plate to reduce the electric field in the drift region, thereby increasing the carrier concentration in the drift region to reduce its resistance, and thus being able to obtain a lower on-resistance at the same breakdown voltage. In addition, according to the SGT MOSFET of the prior art, the shielded gate can greatly reduce the area facing the control gate and the drain (connected to the substrate), so that the Miller capacitance (Cgd) can be reduced, thereby improving the ability to resist drain voltage oscillations.

[0044] Therefore, if Figure 1B As shown, the SGT MOSFET according to the prior art can achieve an electric field distribution that is approximately trapezoidal in the longitudinal direction.

[0045] However, there is still a need to further increase the withstand voltage capability and reduce the specific on-resistance of the SGT MOSFET according to the prior art.

[0046] In order to address the above requirements, the present disclosure proposes a novel SGT MOSFET structure.

[0047] Figure 2A A cross-sectional view of an SGT MOSFET 100 according to a first embodiment of the present disclosure is shown. Figure 2B A schematic diagram showing a longitudinal electric field distribution of the SGT MOSFET 100 according to the first embodiment of the present disclosure is shown. Figure 2C A schematic diagram showing a doping concentration distribution in the longitudinal direction of the SGT MOSFET 100 according to the first embodiment of the present disclosure is shown.

[0048] The SGT MOSFET 100 according to the first embodiment of the present disclosure may include:

[0049] Substrate 1;

[0050] A first epitaxial layer 2 is provided on the substrate 1;

[0051] A second epitaxial layer 4 is provided above the first epitaxial layer 2;

[0052] a channel region 9, disposed above the second epitaxial layer 4;

[0053] a source region 10 , disposed above the channel region 9 ;

[0054] a trench 11 extending longitudinally through the source region 10, the channel region 9, the second epitaxial layer 4 and into the first epitaxial layer 2, the trench 11 being filled with a dielectric layer in which a control gate 8 and a shield gate 6 are disposed; and

[0055] The buffer region 3 is provided below the trench 11 in the first epitaxial layer 2 , and the size of the buffer region 3 is larger than the size of the trench 11 in the lateral direction.

[0056] According to an embodiment of the present disclosure, substrate 1 may be composed of a heavily doped semiconductor material. According to an embodiment of the present disclosure, substrate 1 may be a heavily doped region doped with N-type impurities as the first conductivity type. According to an embodiment of the present disclosure, substrate 1 may include, but is not limited to, a silicon substrate, a gallium nitride substrate, a silicon carbide substrate, a diamond substrate, a gallium oxide substrate, or a silicon germanium substrate.

[0057] Those skilled in the art will appreciate that although the embodiments of the present disclosure are described herein with the first conductivity type being N-type and the second conductivity type being P-type as an example, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first conductivity type may also be P-type and the second conductivity type may be N-type.

[0058] In addition, those skilled in the art will recognize that the term “heavily doped region” in this context generally refers to a region with a doping concentration greater than or equal to 10 18 cm -3 In addition, the term "lightly doped region" in this article refers to a region with a doping concentration of less than 10 18 cm -3 For example, "N+" means that the doping concentration is greater than or equal to 10 18 cm -3 N-type heavily doped region, “N-” means the doping concentration is less than 10 18 cm -3 N-type lightly doped region.

[0059] According to an embodiment of the present disclosure, the first epitaxial layer 2 and the second epitaxial layer 4 can be epitaxial layers of the first conductivity type, i.e., N-type, disposed on the substrate 1 by, for example, an epitaxial process. Herein, the first epitaxial layer 2 and the second epitaxial layer 4 can also be collectively referred to as a "drift region." According to an embodiment of the present disclosure, the first epitaxial layer 2 and the second epitaxial layer 4 can be N-lightly doped regions. That is, according to an embodiment of the present disclosure, the doping concentration of the substrate 1 is higher than the doping concentration of the first epitaxial layer 2 and the second epitaxial layer 4.

[0060] Furthermore, according to an embodiment of the present disclosure, the doping concentration of the first epitaxial layer 2 may be higher than the doping concentration of the fourth epitaxial layer 4 .

[0061] According to an embodiment of the present disclosure, the channel region 9 may be a P-type doped region formed on the second epitaxial layer 4 by, for example, a deposition process. In addition, according to an embodiment of the present disclosure, the source region 10 may be an N+ heavily doped region formed on the channel region 9 by, for example, a deposition process.

[0062] like Figure 2A As shown, the trench 11 can be formed by, for example, a photolithography process to extend through the source region 10, the channel region 9, the second epitaxial layer 4 and into the first epitaxial layer 2 in the longitudinal direction. Figure 2A As shown, according to an embodiment of the present disclosure, the bottom of the groove 11 is formed into a rounded structure to reduce physical damage and defects on the groove surface. In other words, the groove 11 can be a U-shaped groove.

[0063] In addition, if Figure 2A As shown, according to an embodiment of the present disclosure, a buffer region 3 extending from the bottom of the trench 11 into the first epitaxial layer 2 is formed at the bottom of the trench 11 by, for example, an ion implantation process. The ion implantation process is the process of doping silicon materials and adjusting the doping concentration. In actual application, the power device is placed at one end of the ion implanter, and the doping ion source is set at the other end of the ion implanter. At one end of the doping ion source, the doping body atoms are ionized, thereby carrying a certain charge. They are then accelerated to ultra-high speed by the electric field, pass through the surface of the device, and use the momentum of the atoms to inject the doping atoms into the power device, thereby forming a doped region.

[0064] According to an embodiment of the present disclosure, the buffer region 3 may be a lightly N-doped region, for example, but not limited to, formed by adjusting the doping concentration of a portion of the first epitaxial layer 2 through ion implantation. Furthermore, according to an embodiment of the present disclosure, the doping concentration of the buffer region 3 may be lower than the doping concentration of the second epitaxial layer 4.

[0065] Therefore, the substrate 1, the first epitaxial layer 2, the second epitaxial layer 4 and the buffer region 3 may all be doped regions doped with N-type impurities and may have the following characteristics: Figure 2C As shown in the longitudinal doping concentration distribution. Figure 2C As shown, according to an embodiment of the present disclosure, the doping concentration of the substrate 1 can be greater than the doping concentration of the first epitaxial layer 2, the doping concentration of the first epitaxial layer 2 can be greater than the doping concentration of the second epitaxial layer 4, and the doping concentration of the second epitaxial layer 4 can be greater than the doping concentration of the buffer region 3.

[0066] According to an embodiment of the present disclosure, the buffer region 3 may be completely disposed in the first epitaxial layer 2 , that is, the upper portion of the buffer region 3 does not contact the second epitaxial layer 4 , and the lower portion of the buffer region 3 does not contact the substrate 1 .

[0067] According to an embodiment of the present disclosure, in the horizontal direction, the buffer region 3 may have a size larger than the groove 11. Figure 2A As shown, according to the first embodiment of the present disclosure, the buffer region 3 may have an elliptical cross-section.

[0068] In addition, according to an embodiment of the present disclosure, a dielectric layer may be filled in the trench 11 by, for example, a deposition process. According to an embodiment of the present disclosure, the dielectric layer filled in the trench 11 may include a first dielectric layer 5 disposed at a lower portion of the trench 11 and a second dielectric layer 7 disposed at an upper portion of the trench 11. In this document, the first dielectric layer 5 may also be referred to as a field oxide layer, and the second dielectric layer may also be referred to as a gate oxide layer. According to an embodiment of the present disclosure, the first dielectric layer 5 and the second dielectric layer 7 may be formed of different materials. In addition, according to an embodiment of the present disclosure, since the first dielectric layer 5 and the second dielectric layer 7 need to withstand a certain degree of high voltage during the operation of the SGT MOSFET 100, they need to be thin films with good density, such as insulating films of silicon oxide or silicon nitride formed by, for example, a chemical vapor deposition (CVD) process.

[0069] According to an embodiment of the present disclosure, the control gate 8 and the shielding gate 6 can be formed in the dielectric layer by, for example, a deposition process. Figure 2A As shown, according to the first embodiment of the present disclosure, the control gate 8 may be disposed above the shield gate 6, and in the horizontal direction, the control gate 8 may have a size larger than the shield gate 6. According to an embodiment of the present disclosure, each of the control gate 8 and the shield gate 6 may be formed of polysilicon or amorphous silicon.

[0070] In addition, despite Figure 2A Although not shown, according to an embodiment of the present disclosure, SGT MOSFET 100 may further include an insulating layer formed on the upper surface of source region 10 and trench 11 by, for example, a deposition process, and a second metal layer formed on the upper surface of the insulating layer by, for example, a sputtering process. According to an embodiment of the present disclosure, metal patterns electrically connected to control gate 8, shield gate 6, and source region 9, respectively, may be formed in the second metal layer to serve as a control gate electrode, a shield gate electrode, and a source electrode, respectively.

[0071] In addition, despite Figure 2A Although not shown, according to an embodiment of the present disclosure, SGT MOSFET 100 may further include a first metal layer formed on the lower surface of substrate 1 by, for example, a sputtering process. According to an embodiment of the present disclosure, a metal pattern electrically connected to substrate 1 may be formed in the first metal layer to serve as a drain electrode.

[0072] According to an embodiment of the present disclosure, the first metal layer and the second metal layer may include at least one of tungsten (W), platinum (Pt), platinum nitride (PtNi), titanium (Ti), and titanium nitride (TiN).

[0073] According to an embodiment of the present disclosure, by forming a lightly doped buffer region 3 in the first epitaxial layer 2 at the lower portion of the trench 11, the SGT MOSFET 100 can have the following characteristics: Figure 2B The longitudinal electric field E (unit: V / cm) shown has a peak-valley distribution, thereby effectively improving the withstand voltage capability of the SGT MOSFET 100 and reducing the specific on-resistance.

[0074] Figure 3 A cross-sectional view of an SGT MOSFET 200 according to a second embodiment of the present disclosure is shown.

[0075] exist Figure 3 2, the same reference numerals as in FIG. 2 are used to denote the same components as in FIG. Figure 3 As shown, except for the configuration of the buffer region 3 , the constituent components of the SGT MOSFET 200 are identical to the corresponding constituent components shown in FIG. 2 , and thus detailed descriptions of these constituent components will be omitted.

[0076] like Figure 3 As shown, according to the second embodiment of the present disclosure, the buffer region 3 may be formed to have a rectangular cross section. According to the second embodiment of the present disclosure, in the horizontal direction, the size of the buffer region 3 having a rectangular cross section is larger than the size of the groove 11.

[0077] Figure 4 A cross-sectional view of an SGT MOSFET 300 according to a third embodiment of the present disclosure is shown.

[0078] exist Figure 4 2, the same reference numerals as in FIG. 2 are used to denote the same components as in FIG. Figure 4 As shown, except for the configuration of the buffer region 3 , the constituent components of the SGT MOSFET 300 are identical to the corresponding constituent components shown in FIG. 2 , and thus detailed descriptions of these constituent components will be omitted.

[0079] like Figure 4 As shown, according to the third embodiment of the present disclosure, the buffer region 3 may be formed to have a trapezoidal cross section. According to the third embodiment of the present disclosure, in the horizontal direction, the size of the buffer region 3 having the trapezoidal cross section is larger than the size of the groove 11 .

[0080] Figure 5A cross-sectional view of an SGT MOSFET 400 according to a fourth embodiment of the present disclosure is shown.

[0081] exist Figure 5 2, the same reference numerals as in FIG. 2 are used to denote the same components as in FIG. Figure 5 As shown, except for the configurations of the control gate 8 and the shield gate 6, the constituent components of the SGT MOSFET 400 are identical to the corresponding constituent components shown in FIG. 2 , and thus detailed descriptions of these constituent components will be omitted.

[0082] like Figure 5 As shown, according to the fourth embodiment of the present disclosure, the control gate 8 may be provided on both sides of the shielding gate 6. In addition, according to the embodiment of the present disclosure, the size of the shielding gate 6 may be larger than that of the control gate 8 in the vertical direction.

[0083] Figure 6 A cross-sectional view of an SGT MOSFET 500 according to a fifth embodiment of the present disclosure is shown.

[0084] exist Figure 6 In, with Figure 3 The same reference numerals are used to denote Figure 3 In addition, as Figure 6 As shown in FIG. 1 , except for the configuration of the control gate 8 and the shield gate 6, the components of the SGT MOSFET 500 are similar to those of FIG. Figure 3 The corresponding constituent components shown are identical, and thus detailed descriptions of these constituent components will be omitted.

[0085] like Figure 6 As shown, according to the fifth embodiment of the present disclosure, the control gate 8 may be provided on both sides of the shielding gate 6. In addition, according to the embodiment of the present disclosure, the shielding gate 6 may be larger than the control gate 8 in the vertical direction.

[0086] Figure 7 A cross-sectional view of an SGT MOSFET 600 according to a sixth embodiment of the present disclosure is shown.

[0087] exist Figure 7 In, with Figure 4 The same reference numerals are used to denote Figure 4 In addition, as Figure 7 As shown, except for the configuration of the control gate 8 and the shield gate 6, the components of the SGT MOSFET 600 are the same as those of the Figure 4 The corresponding constituent components shown are identical, and thus detailed descriptions of these constituent components will be omitted.

[0088] like Figure 7 As shown, according to the sixth embodiment of the present disclosure, the control gate 8 may be provided on both sides of the shielding gate 6. In addition, according to the embodiment of the present disclosure, the size of the shielding gate 6 may be larger than that of the control gate 8 in the vertical direction.

[0089] Those skilled in the art will recognize that although the semiconductor manufacturing processes used to form the various components of SGT MOSFETs 100-600 are exemplified above, such as photolithography, epitaxy, deposition, implantation, sputtering, etc., the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may use other semiconductor processes to obtain the same structure as the SGT MOSFETs 100-600 described herein, and all such variations are intended to be within the scope of the present disclosure.

[0090] According to the SGT MOSFET disclosed herein, by introducing a buffer region larger than the trench below the trench, a peak-valley distribution can be formed in the longitudinal electric field of the SGT MOSFET, thereby effectively improving the withstand voltage capability of the SGT MOSFET and reducing the specific on-resistance.

[0091] While the present disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A shielded gate trench metal oxide semiconductor field effect transistor comprising: substrate; a first epitaxial layer disposed above the substrate; a second epitaxial layer, disposed above the first epitaxial layer; a channel region, disposed above the second epitaxial layer; a source region, disposed above the channel region; a trench extending longitudinally through the source region, the channel region, the second epitaxial layer and into the first epitaxial layer, the trench being filled with a dielectric layer, and a control gate and a shield gate being disposed in the dielectric layer; as well as a buffer region, which is provided in the first epitaxial layer below the trench, and has a size larger than that of the trench in a lateral direction; The substrate, the first epitaxial layer, the second epitaxial layer and the buffer region are doped with impurities of a first conductivity type. The doping concentration of the substrate is greater than the doping concentration of the first epitaxial layer. wherein the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer, and The doping concentration of the second epitaxial layer is greater than the doping concentration of the buffer region.

2. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, in, The buffer area has an elliptical, rectangular or trapezoidal cross section.

3. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, in, The buffer region is formed by an ion implantation process.

4. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, in, The buffer region does not contact the substrate.

5. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, in, The control gate is disposed above the shielding gate.

6. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, in, The control gate is arranged on both sides of the shielding gate.

7. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, in, The channel region is doped with impurities of the second conductivity type, and the source region is doped with impurities of the first conductivity type.

8. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 7, in, The first conductivity type is N type, and the second conductivity type is P type.

9. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, in, The dielectric layer filled in the trench includes a first dielectric layer disposed at a lower portion of the trench and a second dielectric layer disposed at an upper portion of the trench.

10. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 9, in, The first dielectric layer and the second dielectric layer are formed of different materials.

11. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 9, in, The first dielectric layer and the second dielectric layer include silicon oxide or silicon nitride.

12. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, in, The control gate and the shield gate include polysilicon or amorphous silicon.

13. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 1 or 2, further comprising: an insulating layer, disposed above the source region and the trench; a first metal layer, disposed below the substrate; as well as The second metal layer is disposed above the insulating layer.

14. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 13, in, The first metal layer and the second metal layer include at least one of W, Pt, PtNi, Ti, and TiN.

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