A RF programmable gain amplifier with large dynamic range and low additional phase shift

Abstract

The present invention belongs to the field of semiconductor integrated circuit design, and specifically relates to a large dynamic low additional phase shift radio frequency programmable gain amplifier, comprising a bias voltage, transistors M1-M5, resistors R1-R4, inductors L1-L2, two current control arrays, and two phase compensation arrays, wherein the transistors M1 and M2 form a common source differential pair tube, the resistors R1 and R2 provide gate voltage bias for the transistors M1 and M2 respectively; the transistors M3 and M4 form a common gate amplifier stage; the transistor M5 is a tail current source, which is used to ensure that the overall current of the amplifier remains unchanged; the current control array is used to realize programming control of the amplifier gain; the phase compensation array is used to eliminate the influence of the feedforward capacitor and reduce the additional phase shift caused by the gain change. The present invention improves the gain change range of the CMOS radio frequency programmable gain amplifier and reduces the signal additional phase shift introduced in the gain change process.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit design, and in particular relates to a large dynamic low additional phase shift radio frequency programmable gain amplifier. Background Art

[0002] The programmable gain amplifier (PGA) is a key component of the automatic gain control (AGC) loop in wireless transceivers, which is used to control the signal amplitude. In analog phased array systems, gain control is usually required in the RF link, which requires the programmable gain amplifier to operate at the RF frequency. The gain control range of the RF programmable gain amplifier directly determines the dynamic range of the system; at the same time, the additional phase shift of the signal introduced by the RF programmable gain amplifier during the gain change process will affect the beamforming of the phased array system.

[0003] Traditional analog phased array systems mostly use digitally controlled attenuators based on III-V compound semiconductor technology as gain control units, which have disadvantages such as high loss and high cost. With the development of semiconductor technology, the cutoff frequency (f T ) is constantly improving, and shows significant advantages such as high integration and low cost. It is particularly suitable for making multi-channel integrated RF transceiver chips, thereby realizing ultra-large-scale MIMO. However, compared with III-V processes, the current CMOS process still has disadvantages such as poor linearity and large high-frequency parasitics, which leads to low dynamic range and large additional phase shift of existing CMOS RF programmable gain amplifiers. Therefore, in order to meet the requirements of system applications, it is of great engineering value to design and invent a RF programmable gain amplifier with large dynamic range and low additional phase shift based on CMOS process. Summary of the invention

[0004] In order to improve the gain variation range of a CMOS radio frequency programmable gain amplifier and reduce the additional phase shift of a signal introduced during the gain variation process, the present invention provides a large dynamic and low additional phase shift radio frequency programmable gain amplifier based on CMOS technology, comprising:

[0005] Bias voltage, transistors M1-M5, resistors R1-R4, inductors L1-L2, two current control arrays, two phase compensation arrays, the current control array includes terminals 1 and 2, the phase compensation array includes terminals 1 and 2, wherein:

[0006] The drain of transistor M1 is connected to the source of transistor M3, the drain of transistor M2 is connected to the source of transistor M4, the sources of transistor M1 and transistor M2 are connected to the drain of transistor M5, the gate of transistor M5 is connected to bias voltage terminal 2, the bias voltage terminal 1 is connected to resistor R1 and resistor R2, and resistor R3, inductor L1, inductor L2 and resistor R4 are connected in series in sequence;

[0007] The 1 ends of the two current control arrays are connected to the source of the transistor M3 and the transistor M4 respectively, and the corresponding 2 ends are connected to the drain of the transistor M3 and the transistor M4 respectively;

[0008] The 1 ends of the two phase compensation arrays are respectively connected to the source of the transistor M3 and the source of the transistor M4, and the corresponding 2 ends are respectively connected to the drain of the transistor M4 and the drain of the transistor M3;

[0009] The transistor M1 and the transistor M2 form a common-source differential pair transistor, and the resistor R1 and the resistor R2 provide gate voltage bias for the transistor M1 and the transistor M2 respectively;

[0010] The transistor M3 and the transistor M4 form a common gate amplifier stage of a programmable gain amplifier, the resistor R3 and the inductor L1 serve as the load of the transistor M3, and the resistor R4 and the inductor L2 serve as the load of the transistor M4;

[0011] The differential cascode structure formed by transistors M1 to M4 can provide high gain for the amplifier;

[0012] Transistor M5 is a tail current source, which is used to ensure that the overall current of the amplifier remains unchanged;

[0013] The current control array is used to implement programmable control of the amplifier gain;

[0014] The phase compensation array is used to eliminate the effect of the feedforward capacitor and reduce the additional phase shift caused by gain changes.

[0015] Furthermore, the current control array includes several current channels and several control voltages, each current channel is provided with port 1, port 2 and port 3, port 1 of all current channels is connected to end 1 of the current control array, port 2 of all current channels is connected to end 2 of the current control array, and port 3 of each current channel is connected to a corresponding control voltage.

[0016] Furthermore, the current channel includes transistor Mg1, transistor Mg2 and inverter INV1, the source, drain and gate of transistor Mg1 are respectively connected to port 1, port 2 and port 3; the gate, source and drain of transistor Mg2 are respectively connected to the inverter output end, port 1 and the power supply end; the input end of the inverter is connected to port 3.

[0017] Furthermore, when the control voltage output of the 3-port connection of any current channel is at a high level, the transistor Mg1 in the current channel is turned on, the transistor Mg2 is turned off, and the branch current of the transistor Mg1 output of the current channel flows through the output + end or the output - end; when the output voltage is at a low level, the transistor Mg1 in the current channel is turned off, the transistor Mg2 is turned on, and the branch current of the transistor Mg2 output of the current channel flows into the power supply.

[0018] Furthermore, the phase compensation array includes transistors Mc1-Mcn, the sources of the transistors Mc1-Mcn are connected to terminal 1 of the phase compensation array; the drains of the transistors Mc1-Mcn are connected to terminal 2 of the phase compensation array; and the gate of each transistor is grounded.

[0019] Furthermore, the transistor M1 and the transistor M2 have the same size; the transistor M3 and the transistor M4 have the same size.

[0020] Furthermore, in any current channel, the transistor Mg1 and the transistor Mg2 have the same size.

[0021] Beneficial effects of the present invention:

[0022] The present invention provides a large dynamic low additional phase shift radio frequency programmable gain amplifier based on CMOS technology, which adopts a differential common source and common gate amplifier structure and benefits from a current discharge tube ( Figure 3 Mg2 tube in the current control array), so that the static operating point of the amplifier remains consistent in each gain state, thereby obtaining a large gain adjustment range by increasing the ratio of the total size of the transistors in the current control array to the size of the normally-on common-gate transistors.

[0023] The present invention effectively reduces the additional phase shift caused by gain change by adding a cross-coupled phase compensation array to offset the feedforward capacitance. At the same time, the programmable gain amplifier of the present invention can achieve a gain dynamic range of more than 25dB within a frequency range of 10GHz to 18GHz, and the gain control accuracy is better than 0.5dB, and the root mean square additional phase shift introduced by the gain change is less than 3°. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The schematic diagram of the high dynamic and low additional phase shift radio frequency programmable gain amplifier of the present invention;

[0025] Figure 2 The schematic diagram of the current control array of the present invention;

[0026] Figure 3 It is the principle diagram of the current channel of the present invention;

[0027] Figure 4 This is a schematic diagram of the phase compensation array of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The present invention provides a large dynamic low additional phase shift radio frequency programmable gain amplifier, comprising: a bias voltage, transistors M1-M5, resistors R1-R4, inductors L1-L2, a current control array 1, a current control array 2, a phase compensation array 1 and a phase compensation array 2, each current control array comprises a 1 end and a 2 end, each phase compensation array comprises a 1 end and a 2 end, and the connection mode between each component is as follows Figure 1 As shown, specifically:

[0030] The gate of the transistor M1 is connected to the input + terminal, and the source and drain of the transistor M1 are connected to the drain of the transistor M5 and the source of the transistor M3 respectively; the gate of the transistor M3 is connected to the power supply, and the drain of the transistor M3 is connected to the output + terminal; the gate of the transistor M5 is connected to the bias voltage 2 terminal, the source of the transistor M5 is grounded, the gate of the transistor M2 is connected to the input - terminal, and the source and drain of the transistor M2 are connected to the drain of the transistor M5 and the source of the transistor M4 respectively; the gate of the transistor M4 is connected to the power supply terminal, and the drain of the transistor M4 is connected to the output - terminal;

[0031] The two ends of the resistor R1 are connected to the input + end and the bias voltage 1 end respectively; the two ends of the resistor R2 are connected to the input - end and the bias voltage 1 end respectively; the two ends of the resistor R3 are connected to the output + end and the inductor L1 respectively, and the end of the inductor L1 not connected to the resistor R3 is connected to the power supply end; the two ends of the resistor R4 are connected to the output - end and the inductor L2 respectively, and the end of the inductor L2 not connected to the resistor R4 is connected to the power supply end;

[0032] The terminal 1 of the current control array 1 is connected to the source of the transistor M3, and the terminal 2 of the current control array 1 is connected to the drain of the transistor M3; the terminal 1 of the current control array 2 is connected to the source of the transistor M4, and the terminal 2 of the current control array 2 is connected to the drain of the transistor M4;

[0033] End 1 of the phase compensation array 1 is connected to the source of the transistor M3, and end 2 of the phase compensation array 1 is connected to the drain of the transistor M4; end 1 of the phase compensation array 2 is connected to the source of the transistor M4, and end 2 of the phase compensation array 2 is connected to the drain of the transistor M3.

[0034] In one embodiment, the current control array 1 and the current control array 2 have the same structure. Figure 2As shown, it includes current channels 1 to n, each current channel is provided with port 1, port 2 and port 3, port 1 of current channel 1 to n is connected to end 1 of the current control array, port 2 of current channel 1 to n is connected to end 2 of the current control array, and port 3 of each current channel is connected to a control voltage. The number of current channels directly determines the gain control accuracy of the programmable gain amplifier. The more current channels, the higher the gain control accuracy of the amplifier, but the control complexity and chip area increase accordingly. Therefore, it can be said that the larger the number of current channels n, the better within the acceptable complexity and area range.

[0035] Specifically, the more current channels n, the more gain states the amplifier has, and the easier it is to find a state close to the required gain state among these gain states, but at the same time there are more redundant states. For example, the required gain adjustment range is 16dB and the step is 0.5dB, there are a total of 32 required gain states. When n=5, the amplifier also has 2 5 = 32 gain states. There is no redundant state at this time. However, since the gain control of the amplifier is not logarithmic linear, there will be a large error between the gain of these 32 states and the required gain state. Therefore, n must be set to be greater than 5 so that the amplifier has more gain states. Then, the 32 states closest to the required gain state are found among these states, and the corresponding relationship is made into a lookup table to achieve precise numerical control of the corresponding number of bits. When the required gain adjustment range is 16dB and the step is 0.5dB, n is 8 to control the gain error within 0.1dB. At this time, the amplifier has a total of 2 8 =256 gain states, of which there are 256-32=224 redundant states.

[0036] Preferably, all current channels in the current control array have the same structure, such as Figure 3 As shown, the current channel includes transistor Mg1, transistor Mg2 and inverter INV1, the source, drain and gate of transistor Mg1 are connected to port 1, port 2 and port 3 respectively; the gate, source and drain of transistor Mg2 are connected to the inverter output terminal, port 1 and the power supply respectively; the input terminal of the inverter is connected to port 3.

[0037] Specifically, the size of the transistor Mg1 and the transistor Mg2 in any current channel is the same.

[0038] In one embodiment, the phase compensation array 1 and the phase compensation array 2 have the same structure. Figure 4As shown, the phase compensation array includes transistors Mc1~Mcn, and the number n of transistors in the phase compensation array must be consistent with the number n of current channels in the connected current control array to offset the additional phase shift introduced by the transistors in the current channel. The source of the transistors Mc1~Mcn is connected to the end 1 of the phase compensation array; the drain of the transistors Mc1~Mcn is connected to the end 2 of the phase compensation array; the gate of each transistor is grounded.

[0039] Specifically, all transistors involved in the present invention are field effect transistors, among which M1 and M2 form a differential pair of transistors, and M3 and M4 form a differential pair of transistors. Therefore, it is necessary to ensure that their sizes are consistent and the layout is symmetrical to reduce mismatch. Therefore, transistor M1 and transistor M2 have the same size, and transistor M3 and transistor M4 have the same size.

[0040] Specifically, the transistor Mc1 in the phase compensation array has the same size as the transistor in the corresponding current channel in the connected current control array, that is, the size of the transistor Mc1 in the phase compensation array is the same as the size of the transistor (Mg1 or Mg2) in the current channel 1, the size of the transistor Mc2 is the same as the size of the transistor in the current channel 2... The size of the transistor Mcn is the same as the size of the transistor in the current channel n. The programmable gain amplifier designed by the present invention adopts a differential common source and common gate amplifier structure, the transistor M1 and the transistor M2 form a common source differential pair, the transistor M1 and the transistor M2 are respectively connected to the resistor R1 and the resistor R2 to provide gate voltage bias for themselves, the transistor M5 is a tail current source, and its function is to keep the overall current of the programmable gain amplifier unchanged, thereby keeping the transconductance of the transistors in the current control array constant; the transistor M3 and the transistor M4 are used as the common gate amplifier stage of the amplifier, and the current control array 1 and the current control array 2 are respectively connected in parallel with the transistor M3 and the transistor M4.

[0041] Preferably, the current control array contains n current channels, and the sizes of transistors in different current channels may be different. The number and size of transistors connected to the amplifier are selected through digital control signals to achieve programmable control of the amplifier gain.

[0042] In one embodiment, constructing Figure 1The programmable gain amplifier shown in the figure has a bilaterally symmetrical structure. The control voltage of each current channel in the current control array determines the conduction state of Mg1 or Mg2 in the current channel, that is, when the control voltage output is a high level, Mg1 in the current channel is turned on and Mg2 is turned off; when the control voltage output is a low level, Mg1 in the current channel is turned off and Mg2 is turned on. For the case where the current control array contains n current channels, all the corresponding control voltages are combined into a parallel n-bit binary logic code, and all the control voltage states in a current control array are not completely consistent. Taking n=3 as an example, the three control voltages in the current control array can be any one of the eight states of 000 to 111. Different logic codes correspond to different gain states of the programmable amplifier. When n=3, the control voltage 111 corresponds to the maximum gain state, and the control voltage 000 corresponds to the minimum gain state. At the same time, the gain changes monotonically and progressively with the binary code, and because the gain of the MOS tube does not change logarithmically with the voltage, the difference between two adjacent states is different. By increasing the number of current channels n and introducing redundant gain states, the gain state of the amplifier is made greater than the required gain state, and the required gain accuracy is obtained by screening out states close to the required gain.

[0043] Specifically, considering the left half of the circuit, when the control voltage i (i=1,2,3,…,n) in the current control array 1 is at a high level, the transistor Mg1 in the current channel i is turned on and the transistor Mg2 is turned off. At this time, the current channel i outputs the transistor Mg1 branch current and the transistor M3 branch current and flows through the output + terminal together. When the control voltage i (i=1,2,3,…,n) in the current control array 1 is at a low level, the transistor Mg1 in the current channel i is turned off and the transistor Mg2 is turned on. At this time, the current channel i outputs the transistor Mg2 branch current and flows into the power supply, and the current flowing through the output + terminal is only the transistor M3 branch current. By controlling the current state of the n current channels through digital control signals, the size of the output current can be controlled.

[0044] Specifically, considering the right half of the circuit, when the control voltage i (i=1, 2, 3, ..., n) in the current control array 2 is at a high level, the transistor Mg1 in the current channel i is turned on and the transistor Mg2 is turned off. At this time, the current channel i outputs the branch current of the transistor Mg1 and the branch current of the transistor M4 and flows through the output - end together. When the control voltage i (i=1, 2, 3, ..., n) in the current control array 2 is at a low level, the transistor Mg1 in the current channel i is turned off and the transistor Mg2 is turned on. At this time, the current channel i outputs the branch current of the transistor Mg2 and flows into the power supply, and the current flowing through the output - end is only the branch current of the transistor M4.

[0045] Preferably, assuming that the branch current of transistor M is Im, the current when all n current channels in the current control array 1 are turned on is Ic, and the maximum output current and the minimum output current can be expressed as:

[0046] Iout_max=Im+Ic;

[0047] Iout_min = Im;

[0048] Therefore, the adjustable range that can be achieved by the programmable gain amplifier is expressed as The minimum gain of the programmable gain amplifier depends on Iout_min, that is, the size of the transistors M3 and M4, and the larger the number n of current channels in the current control array, the higher the gain control resolution.

[0049] Specifically, the right half of the circuit is completely symmetrical with the left half, and the sizes of transistors M3 and M4 are the same. The control voltages in the current control array 2 are consistent with the corresponding control voltages in the current control array 1. The currents of the left half of the circuit and the right half of the circuit change at the same time, so the total gain adjustment range of the amplifier is

[0050] Preferably, the transistors in the phase compensation array are connected in parallel with transistors of the same size in the current control array, which are connected across the source and drain of the transistor M3 and the transistor M4 in a cross-coupling manner. The function of the phase compensation array is to eliminate the influence of the feedforward capacitor and reduce the additional phase shift caused by the gain change.

[0051] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "rotation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0052] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high dynamic range low additional phase shift radio frequency programmable gain amplifier, characterized in that: include: Bias voltage, transistors M1-M5, resistors R1-R4, inductors L1-L2, two current control arrays, two phase compensation arrays, the current control array includes terminals 1 and 2, the phase compensation array includes terminals 1 and 2, wherein: The drain of transistor M1 is connected to the source of transistor M3, the drain of transistor M2 is connected to the source of transistor M4, the sources of transistor M1 and transistor M2 are connected to the drain of transistor M5, the gate of transistor M5 is connected to bias voltage terminal 2, the bias voltage terminal 1 is connected to resistor R1 and resistor R2, and resistor R3, inductor L1, inductor L2 and resistor R4 are connected in series in sequence; The 1 ends of the two current control arrays are connected to the source of the transistor M3 and the transistor M4 respectively, and the corresponding 2 ends are connected to the drain of the transistor M3 and the transistor M4 respectively; The 1 ends of the two phase compensation arrays are respectively connected to the source of the transistor M3 and the source of the transistor M4, and the corresponding 2 ends are respectively connected to the drain of the transistor M4 and the drain of the transistor M3; The transistor M1 and the transistor M2 form a common-source differential pair transistor, and the resistor R1 and the resistor R2 provide gate voltage bias for the transistor M1 and the transistor M2 respectively; The transistor M3 and the transistor M4 form a common gate amplifier stage of a programmable gain amplifier, the resistor R3 and the inductor L1 serve as the load of the transistor M3, and the resistor R4 and the inductor L2 serve as the load of the transistor M4; Transistor M5 is a tail current source, which is used to ensure that the overall current of the amplifier remains unchanged; The current control array is used to implement programmable control of the amplifier gain; The phase compensation array is used to eliminate the influence of the feedforward capacitor and reduce the additional phase shift caused by gain changes; The current control array includes a plurality of current channels and a plurality of control voltages. Each current channel is provided with port 1, port 2 and port 3. The ports 1 of all current channels are connected to the terminal 1 of the current control array, the ports 2 of all current channels are connected to the terminal 2 of the current control array, and the port 3 of each current channel is connected to a corresponding control voltage. The current channel includes transistor Mg1, transistor Mg2 and inverter INV1, the source, drain and gate of transistor Mg1 are connected to port 1, port 2 and port 3 respectively; the gate, source and drain of transistor Mg2 are connected to the inverter output end, port 1 and the power supply end respectively; the input end of the inverter is connected to port 3.

2. A high dynamic range low additional phase shift radio frequency programmable gain amplifier according to claim 1, characterized in that: In any current channel, the transistor Mg1 and the transistor Mg2 have the same size.

3. A high dynamic range low additional phase shift radio frequency programmable gain amplifier according to claim 1, characterized in that: When the control voltage output of the 3-port connection of any current channel is at a high level, the transistor Mg1 in the current channel is turned on, the transistor Mg2 is turned off, and the branch current of the output transistor Mg1 of the current channel flows through the output + terminal or the output - terminal; When the output voltage is at a low level, the transistor Mg1 in the current channel is turned off, the transistor Mg2 is turned on, and the branch current of the output transistor Mg2 of the current channel flows into the power supply.

4. The high dynamic range low additional phase shift RF programmable gain amplifier according to claim 1, characterized in that: The phase compensation array includes transistors Mc1 to Mcn, and the sources of the transistors Mc1 to Mcn are connected to terminal 1 of the phase compensation array; The drains of transistors Mc1 to Mcn are connected to two terminals of the phase compensation array; the gate of each transistor is grounded.

5. The large dynamic low additional phase shift radio frequency programmable gain amplifier according to claim 1, characterized in that: The transistor M1 and the transistor M2 have the same size; the transistor M3 and the transistor M4 have the same size.

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