Third order integrator cascade feedforward delta sigma-adc for mems gyro interface chip

Abstract

The application relates to a third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip, relates to the technical field of micro-electro-mechanical system (MEMS) gyro interfaces and integrated circuits, and generally provides a discrete-time delta-sigma ADC with a local negative feedback-free cascade integrator feedforward structure. The discrete-time delta-sigma ADC adopts a full-differential input, small-signal output single-loop single-bit quantization discrete third-order integrator cascade feedforward delta-sigma ADC structure, can improve the precision and linearity of the delta-sigma ADC, discards the traditional input-to-quantizer channel, simplifies the circuit, reduces the circuit area overhead and the negative influence of nonlinearity on SNR under the premise of ensuring high precision and stability, effectively realizes noise shaping, and the local negative feedback-free cascade integrator feedforward structure can also reduce the power consumption and design difficulty of the operational amplifier in the integrator.

Description

TECHNICAL FIELD

[0001] The application relates to a third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface special chip, and belongs to the technical field of micro-electro-mechanical system (MEMS) gyro interface and integrated circuits. BACKGROUND

[0002] A micro-electro-mechanical system (MEMS) gyroscope is a sensor for detecting and measuring angular velocity by using inertial power principle, and is often combined with an accelerometer to form an inertial navigation system, has low dependence on the outside world, is good in concealment, and has the characteristics of small size, light weight, low price and easy batch production, and thus has wide practical and potential application prospects. Among the numerous MEMS gyroscopes, a gyro with a capacitive sensing interface has better stability, more optimal sensitivity and lower temperature dependence. At present, analysis and calculation of a gyro signal tend to be digitalized, however, the signal is transmitted in physical and digital forms in the gyro and a digital chip respectively, and thus a gyro interface application specific integrated circuit (ASIC) is needed for connection. The delta-sigma ADC has the advantages of high precision and easy implementation, and is an indispensable part of the gyro interface ASIC.

[0003] At present, the delta-sigma ADC applied to the gyro interface ASIC is mostly sensitive to non-ideal effects such as process deviation, loop delay and clock phase noise, needs to be additionally designed with digital noise elimination logic to eliminate quantization errors between cascades, has a relatively complex circuit structure, and the circuit nonlinearity has a negative impact on the signal-to-noise ratio (SNR), local negative feedback is difficult to be accurately implemented, and the circuit has large power consumption. SUMMARY

[0004] In view of the deficiencies of the prior art, the application provides a third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface special chip, which reduces the complexity, power consumption and area overhead of the circuit while ensuring the precision and linearity of the ADC in the MEMS gyro interface special chip.

[0005] In order to achieve the above-mentioned purpose, the application adopts the following technical scheme: a third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip, which adopts a discrete third-order integrator cascade feedforward delta-sigma ADC structure with full-differential input, small-signal output, single-loop and single-bit quantization, and includes a first summation node, a feedforward factor a1, a feedforward factor a2, a feedforward factor a3, a second summation node, a quantizer and a DAC module.

[0006] A first integrator composed of a gain factor c1 and a switch and an operational amplifier corresponding to the gain factor c1;

[0007] A second integrator composed of a gain factor c2 and a switch and an operational amplifier corresponding to the gain factor c2;

[0008] a third integrator composed of a gain factor c3 and a switch and an operational amplifier corresponding to the gain factor c3;

[0009] a first feedforward factor a1, a second feedforward factor a2, and a third feedforward factor a3 and a second summing node constitute an adder;

[0010] a first summing node, a first integrator, a second integrator, a third integrator, a second summing node, and a quantizer are sequentially connected;

[0011] an output of the quantizer is connected to a DAC module, an output of the DAC module is connected to the first summing node, an output of the first integrator is connected to the first feedforward factor a1, an output of the second integrator is connected to the second feedforward factor a2, an output of the third integrator is connected to the third feedforward factor a3, and outputs of the first feedforward factor a1, the second feedforward factor a2, and the third feedforward factor a3 are connected to the second summing node;

[0012] an analog input signal is input into the first integrator after being sampled and being subtracted from a single-bit stream output of the quantizer fed back by the DAC module, and then is integrated by the first integrator, the second integrator, and the third integrator in sequence, and the integration result of the first integrator is added to the integration result of the second integrator through the first feedforward factor a1 and the integration result of the third integrator through the third feedforward factor a3, and then is quantized by the quantizer and outputted.

[0013] In an embodiment of the present application, the discrete third-order integrator cascade feedforward delta-sigma-ADC structure comprises a first SC integrator module, a second SC integrator module, a third SC integrator module, an adder module, a quantizer module, a DAC module, and two DAC sampling capacitors C dac ;

[0014] a positive input end V ip1 and a negative input end V in1 of the first SC integrator module are respectively connected to positive and negative ends of an input V i , positive and negative output ends V op1 and V on1 of the first SC integrator module are respectively connected to positive and negative input ends V ip2 and V in2 of the second SC integrator module, positive and negative output ends V op2 and V on2 of the second SC integrator module are respectively connected to positive and negative input ends V ip3 and V in3 of the third SC integrator module, and positive and negative output ends V op1 and V op2, the positive output terminal V of the third-stage SC integrator module op3 Also connected to the positive input terminal V ipa1 、V ipa2 、V ipa3 , the negative output terminal V of the first stage SC integrator module on1 , the negative output terminal V of the second stage SC integrator module on2 、The negative output terminal V of the third-stage SC integrator module on3 Also connected to the negative input terminal V ina1 、V ina2 、V ina3 , the positive output terminal of the adder module V opa Connect the negative input terminal V qn , the negative output terminal V of the adder module ona Connect the positive input terminal of the quantizer module V qp The output terminals Q and Qn of the quantizer module are connected to the NAND gate of the DAC module, and the output of the DAC module is connected to two DAC sampling capacitors C dac The lower plate of the two DAC sampling capacitors C dac The upper plate output V dacp and V dacn Connect the two sampling capacitors C to the positive and negative input terminals of the first-stage SC integrator module respectively. s The upper plate.

[0015] In one embodiment of the present invention, the first stage SC integrator module includes two timing Φ1 control switches, two timing Φ 1a Control switch, two timing Φ2 Control switch, two timing Φ 2a Control switch, two sampling capacitors C s , two integrating capacitors C f , an operational amplifier OP;

[0016] One end of the timing Φ1 control switch is connected to the positive input terminal V ip1 , another timing Φ1 control switch is connected to the negative input terminal V in1 The other end of each timing Φ1 control switch is connected to a sampling capacitor C s The lower plate and one end of a timing Φ2 control switch, the other ends of the two timing Φ2 control switches are connected and then connected to the power supply V CM terminal, each sampling capacitor C s The upper plate is connected to a timing Φ 2a Control switch and a timing Φ 1a One end of the control switch, two timing Φ 1a The other end of the control switch is connected to the power supply V CMone end of each of the two timing Φ 2a control switches is connected to the positive input terminal V f and the other end of each of the two timing Φ f control switches is connected to the negative input terminal V op1 and the other end of each of the two timing Φ on1 control switches is connected to the negative input terminal V ip2 and the other end of each of the two timing Φ in2 control switches is connected to the negative input terminal V op1 and the other end of each of the two timing Φ on1 control switches is connected to the negative input terminal V ipa1 and the other end of each of the two timing Φ ina1 control switches is connected to the negative input terminal V

[0017] In one embodiment, the second stage SC integrator module also includes two timing Φ 1a control switches, two timing Φ 2a control switches, two timing Φ s control switches, two sampling capacitors C f , two integrating capacitors C

[0018] one end of each of the two timing Φ ip2 control switches is connected to the positive input terminal V in2 and the other end of each of the two timing Φ s control switches is connected to the negative input terminal V CM and the other end of each of the two timing Φ s control switches is connected to the negative input terminal V 2a and the other end of each of the two timing Φ 1a control switches is connected to the negative input terminal V 1a and the other end of each of the two timing Φ CM control switches is connected to the negative input terminal V 2a and the other end of each of the two timing Φ f control switches is connected to the negative input terminal V f and the other end of each of the two timing Φ op2 control switches is connected to the negative input terminal V on2 and the other end of each of the two timing Φ ip3 control switches is connected to the negative input terminal V in3; The positive output terminal V of the second-stage SC integrator module op2 With the negative output terminal V on2 Connect to the positive input terminal V of the adder module respectively ipa2 With the negative input terminal V ina2 .

[0019] In one embodiment, the third stage SC integrator module also includes two timing Φ1 control switches, two timing Φ 1a Control switch, two timing Φ2 Control switch, two timing Φ 2a Control switch, two sampling capacitors C s , two integrating capacitors C f , an operational amplifier OP;

[0020] One end of the timing Φ1 control switch is connected to the positive input terminal V ip3 , one end of the other timing Φ1 control switch is connected to the negative input terminal V in3 The other end of each timing Φ1 control switch is connected to a sampling capacitor C s The lower plate and one end of a timing Φ2 control switch, the other ends of the two timing Φ2 control switches are connected and then connected to the power supply V CM terminal, each sampling capacitor C s The upper plate is connected to a timing Φ 2a Control switch and a timing Φ 1a One end of the control switch, two timing Φ 1a The other end of the control switch is connected to the power supply V CM end, two time series Φ 2a The other end of the control switch is connected to an integral capacitor C f The upper plate is connected to the negative input voltage terminal and the positive input voltage terminal of the operational amplifier OP respectively, and the two integrating capacitors C f The lower plate of the operational amplifier OP is connected to the positive output terminal V op3 With the negative output terminal V on3 Connected and connected to the positive input terminal V of the adder module ipa3 With the negative input terminal V ina3 .

[0021] In one embodiment, the adder module includes a power supply terminal V CM , positive input terminal V ipa1 、V ipa2 、V ipa3 and the negative input terminal V ina1 、V ina2 、V ina3, two feedforward path timing Φ1 control switches corresponding to the first-stage SC integrator module, two feedforward path timing Φ1 control switches corresponding to the second-stage SC integrator module, two feedforward path timing Φ1 control switches corresponding to the third-stage SC integrator module, two timing Φ1 control switches corresponding to the first-stage SC integrator module 2a Control switch, corresponding to the two timing Φ of the second stage SC integrator module 2a Control switch, corresponding to the two timing Φ of the third-stage SC integrator module 2a Control switch, corresponding to the two timing Φ at the output of the adder 2a Control switch, two first-stage SC integrator modules, feedforward path sampling capacitor C a1 、Two second-stage SC integrator modules feedforward path sampling capacitors C a2 , two third-stage SC integrator modules feedforward path sampling capacitors C a3 ;

[0022] The two feedforward path timing Φ1 control switches corresponding to the first stage SC integrator module are connected to the positive input terminal V ipa1 and the negative input terminal V ina1 The other end is connected to the two first-stage SC integrator module feedforward path sampling capacitors C a1 The lower plate and the two timing Φ corresponding to the first stage SC integrator module 2a One end of the control switch is connected, corresponding to the two timing Φ of the first stage SC integrator module 2a The other end of the control switch is connected to the power supply V CM The two feedforward path sampling capacitors C corresponding to the first stage SC integrator module a1 The upper plates are connected to the positive output terminal V opa and the negative output terminal V ona ;

[0023] The two feedforward path timing Φ1 control switches corresponding to the second-stage SC integrator module are connected to the positive input terminal V ipa2 and the negative input terminal V ina2 The other end is connected to the two second-stage SC integrator module feedforward path sampling capacitors C a2 The lower plate and the two timing Φ corresponding to the second stage SC integrator module 2a One end of the control switch is connected, corresponding to the two timing Φ of the second-stage SC integrator module 2a The other end of the control switch is connected to the power supply V CM The two feedforward path sampling capacitors C corresponding to the second-stage SC integrator module a2 The upper plates are connected to the positive output terminal V opa and the negative output terminal Vona ;

[0024] The one end of the two feedforward path timing Φ1 control switches corresponding to the third stage SC integrator module is connected to the positive input terminal V ipa3 and the negative input terminal V ina3 respectively, and the other end is connected to the lower plate of the two third stage SC integrator module feedforward path sampling capacitors C a3 respectively, and the one end of the two timing Φ 2a control switches corresponding to the third stage SC integrator module is connected to the positive input terminal V 2a and the other end is connected to the power supply V CM terminal, and the other end of the two feedforward path sampling capacitors C a3 corresponding to the third stage SC integrator module is connected to the positive output terminal V opa and the negative output terminal V ona respectively.

[0025] The one end of the two timing Φ 2a control switches corresponding to the adder output terminal is connected to the power supply V CM terminal, and the other end is connected to the positive output terminal V opa and the negative output terminal V ona of the adder respectively.

[0026] The positive output terminal V opa and the negative output terminal V ona are connected to the negative input terminal V qn and the positive input terminal V qp of the quantizer module respectively.

[0027] In an embodiment, the quantizer module includes a positive input terminal V qp , a negative input terminal V qn , and an enable terminal, the positive input terminal V qp and the negative input terminal V qn are connected to the negative output terminal V ona and the positive output terminal V opa of the adder module respectively, and the enable terminal is connected to the clock signal clk.

[0028] In an embodiment, one end of the two NAND gates of the DAC module is connected to the output Q terminal and the Qn terminal of the quantizer module respectively, and the other end of the NAND gate is connected to the clock signal clk; the output voltage terminal of the DAC module is connected to the lower plate of one DAC sampling capacitor C dac respectively, and the upper plate of the two DAC sampling capacitors C dac outputs V dacp , V dacn and is connected to the upper plate of the two sampling capacitors C s of the first stage SC integrator module respectively.

[0029] The operational amplifier OP adopts a two-stage cascade structure, the first stage of the operational amplifier OP adopts a gain-enhanced folded cascode structure, and the second stage of the operational amplifier OP adopts a common source structure and takes PMOS as input and NMOS as an independent bias current source load structure.

[0030] Finally, it should be pointed out that the MEMS gyro interface chip containing the above-mentioned third-order integrator cascade feedforward delta-sigma ADC also belongs to the content range of the present application.

[0031] Unlike the existing delta-sigma ADC for a gyro interface ASIC, the present application provides a discrete-time type delta-sigma ADC with a local negative feedback-free cascade integrator feedforward structure, which adopts a full-differential input, small-signal output single-loop single-bit quantization discrete third-order integrator cascade feedforward delta-sigma ADC structure, can improve the precision and linearity of the delta-sigma ADC, and discards the traditional input-to-quantizer path, simplifies the circuit, reduces the circuit area overhead and the negative impact of nonlinearity on SNR under the premise of ensuring high precision and stability, effectively realizes noise shaping, and the local negative feedback-free cascade integrator feedforward structure can also reduce the power consumption and design difficulty of the operational amplifier in the integrator. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 and Figure 2 Two different architectures of the third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip.

[0033] Figure 3 The amplitude-frequency characteristics of the STF and NTF of the third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip in the embodiment.

[0034] Figure 4 The simulation output signal PSD analysis result of the third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip in the embodiment.

[0035] Figure 5 The circuit structure and switch timing of the third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip in the embodiment.

[0036] Figure 6 The charge transfer state diagram of the first integrator of the third-order integrator cascade feedforward delta-sigma ADC for a MEMS gyro interface chip in the embodiment.

[0037] Figure 7This is an operational amplifier transistor-level circuit structure of a third-order integrator cascade feedforward ΔΣ-ADC for a MEMS gyroscope interface chip in an embodiment.

[0038] Figure 8 Layout of a third-order integrator cascade feedforward ΔΣ-ADC for a MEMS gyroscope interface chip in an embodiment. DETAILED DESCRIPTION

[0039] In order to facilitate those skilled in the art to better understand the improvements of the present invention relative to the prior art, the present invention is further described below with reference to the accompanying drawings and embodiments.

[0040] Figure 1 and Figure 2 Two different discrete-time third-order integrator cascaded feedforward ΔΣ-ADC architectures are shown. Figure 2 In, a i 、b i , g and c i (i = 1, 2, 3, is the order of the integrator) are the feedforward factor, input factor, local negative feedback factor and gain factor, which together determine the performance of the ΔΣ-ADC. These factors can be automatically calculated using the synthesizeNTF and realizeNTF functions in DSToolbox. The architecture of the third-order integrator cascade feedforward ΔΣ-ADC used in the MEMS gyroscope interface chip in this embodiment is shown in the figure. Figure 1 Compared to Figure 2 , Figure 1 The input to the quantizer path (i.e. the path where b3 is located) is discarded. Figure 1The shown third-order integrator cascade feedforward delta-sigma-ADC mainly comprises a first summing node 2, a first integrator 3 composed of a gain factor c1 and a switch and an operational amplifier corresponding thereto, a second integrator 4 composed of a gain factor c2 and a switch and an operational amplifier corresponding thereto, a third integrator 5 composed of a gain factor c2 and a switch and an operational amplifier corresponding thereto, a feedforward factor a1 6, a feedforward factor a2 7, a feedforward factor a3 8, a second summing node 9, a quantizer 10 and a digital-to-analog conversion (DAC) module 11. The feedforward factor a1 6, the feedforward factor a2 7, the feedforward factor a3 8 and the second summing node 9 constitute an adder. The first summing node 2, the first integrator 3, the second integrator 4, the third integrator 5, the second summing node 9 and the quantizer 10 are sequentially connected. The output of the quantizer 10 is transmitted to the digital-to-analog conversion module 11, and the output of the digital-to-analog conversion module 11 is connected to the first summing node 2. The output of the first integrator 3 is connected to the feedforward factor a1 6. The output of the second integrator 4 is connected to the feedforward factor a2 7. The output of the third integrator 5 is connected to the feedforward factor a3 8. The outputs of the feedforward factor a1 6, the feedforward factor a2 7 and the feedforward factor a3 8 are connected to the second summing node 9.

[0041] The working process of the above-mentioned discrete-time third-order integrator cascade feedforward delta-sigma-ADC is as follows: after the sampling switch, the analog input signal X is sent to the first integrator 3 to be subtracted and then integrated, and then integrated by the second integrator 4 and the third integrator 5. The integration result of the first integrator 3 is added to the integration result of the second integrator 4 through the feedforward factor a1 6 and the integration result of the third integrator 5 through the feedforward factor a3 8, and then sent to the quantizer for quantization to obtain the quantization result Y.

[0042] Since the gyroscope is a mechanical vibration device, the resonant frequency is low, and the MEMS gyroscope requires a high-resolution small-signal ADC, and Figure 1 The shown delta-sigma-ADC is a discrete-time delta-sigma-ADC with a local negative feedback-free cascade integrator feedforward structure. Since it adopts a full-differential input, small-signal output single-loop single-bit quantization discrete third-order integrator cascade feedforward delta-sigma-ADC structure, the precision and linearity of the delta-sigma-ADC can be improved. The traditional input-to-quantizer path is abandoned, the circuit is simplified, the circuit area overhead and the negative impact of nonlinearity on SNR are reduced under the premise of ensuring high precision and stability, noise shaping is effectively realized, and the power consumption and design difficulty of the operational amplifier in the integrator are also reduced.

[0043] Next, by analyzing the amplitude-frequency characteristics of STF and NTF and the stability of the system, the feasibility of the discrete-time third-order integrator cascade feedforward ΔΣ-ADC is verified. In order to make the integrator work properly and reduce the design difficulty, the scaling principle is followed (that is, to ensure that A in formula (1) i Almost unchanged), manually reduce c j , zoom in i , and finally make a i and c j Only one decimal place is retained and listed in Table 1. The simplified a i and c i Make A i There is a slight deviation.

[0044]

[0045] Table 1 Values ​​of various factors in the ΔΣ-ADC system

[0046] Factor [a1] [a2] [a3] ​ [ca2] [c3 <!-- 5 -->]]> Value 0.4 0.4 0.4 2 1.8 0.7

[0047] Assumptions Figure 1 The quantizer and DAC are both in unity gain, and the open-loop system function of the ΔΣ-ADC can be calculated as shown in formula (2). The STF and NTF are defined as formula (3) and formula (4). i and c i Substitute A i , and draw as Figure 3 The amplitude-frequency characteristic curves of STF and NTF are shown in Figure 1. This figure shows that STF has a low-pass characteristic and NTF has a high-pass characteristic, so the system has a very high SNR in the low-frequency domain.

[0048]

[0049]

[0050]

[0051] By analyzing the zero-pole distribution of NTF and the root locus of the system under ideal conditions, when the gain K of the quantizer satisfies 0.363≤K≤2.97, all poles are within the circle and the system is stable. According to the system structure, a Simulink model is established and simulated. When the input is a sine wave with a frequency of 7kHz and an amplitude of 0.6V, the sampling frequency f s When the frequency is 8MHz, 8000000 points are taken from the output signal, and a Hanning window is added, and then a fast Fourier transform (FFT) is performed to obtain Figure 4The output signal power spectral density (PSD) analysis diagram is shown. For an oversampling ratio (OSR) of 128, the bandwidth (BW) of the ΔΣ-ADC is 31.25kHz. Figure 4 It shows that in the model simulation, the factor-optimized ΔΣ-ADC system can effectively achieve noise shaping, and the signal-to-noise ratio (SNR) within the BW is 102dB, the effective number of bits (ENOB) is 16.6 bits, and the spurious-free dynamic range (SFDR) is 108.463dB.

[0052] Next, we introduce the specific circuit structure of the discrete-time third-order integrator cascade feedforward ΔΣ-ADC. Figure 5 As shown, its circuit structure is similar to Figure 1 The ΔΣ-ADC architecture shown in the following will focus on combining Figure 5 Explain it in detail. Figure 5 The ΔΣ-ADC circuit structure shown mainly includes three in-phase SC integrators that are insensitive to parasitic capacitance, such as the first-stage SC integrator module 101, the second-stage SC integrator module 102, the third-stage SC integrator module 103, the adder module 201, the quantizer module 301, the DAC module 401, and the DAC sampling capacitor C dac 501. The positive input terminal V of the first stage SC integrator module 101 is ip1 With the negative input terminal V in1 Connect to input V i The “+” and “-” terminals of the first stage SC integrator module 101 are connected to the positive output terminal V op1 With the negative output terminal V on1 are respectively connected to the positive input terminal V ip2 With the negative input terminal V in2 ; The positive output terminal V of the second stage SC integrator module 102 op2 With the negative output terminal V on2 are respectively connected to the positive input terminal V ip3 With the negative input terminal V in3 The positive output terminal V of the first stage SC integrator module 101 op1 , the positive output terminal V of the second stage SC integrator module 102 op2 , the positive output terminal V of the third-stage SC integrator module 103 op3 are connected to the positive input terminal V ipa1 、V ipa2 、V ipa3 , the negative output terminal V of the first stage SC integrator module 101 on1 , the negative output terminal V of the second stage SC integrator module 102on2 , the third stage SC integrator module 103 negative output end V on3 adder module 201 negative input end V ina1 , V ina2 , V ina3 adder module 201 positive output end V opa quantizer negative input end V qn adder module 201 negative output end V ona quantizer module 301 positive input end V qp ; the output Q, Qn of quantizer module 301 respectively connects to the NAND gate of DAC module 401, and the output of DAC module 401 respectively connects to the lower plate of two DAC sampling capacitors C dac 501, the upper plate output V dac of two DAC sampling capacitors C dacp 501. dacn respectively connects to the positive and negative input ends of the first stage SC integrator module 101 two sampling capacitors C s upper plate.

[0053] The first stage SC integrator module 101 comprises: the "+" end and "-" end of input V i , two timing Φ1 control switches, two timing Φ 1a control switches, two timing Φ2 control switches, two timing Φ 2a control switches, two sampling capacitors C s , two integration capacitors C f , an operational amplifier OP, the upper plate output V dacp of two DAC sampling capacitors 501, V dacn . The positive input end V ip1 and the negative input end V in1 of the first stage SC integrator module 101 are connected to the "+" end and "-" end of input V i respectively, one end of two timing Φ1 control switches is connected to the positive input end V ip1 and the negative input end V in1 respectively, the other end is connected to the lower plate of two sampling capacitors C s and then connected to one end of two timing Φ2 control switches, the other end of two timing Φ2 control switches is connected and then connected to the power supply V CM end, the upper plate of two sampling capacitors C s is connected to one end of two timing Φ 2a control switches and then connected to one end of two timing Φ 1a control switches, the other end of two timing Φ 1a control switches is connected and then connected to the power supply V CM end, two timing Φ2a The other end of the control switch is connected to the integral capacitor C f The upper plate is connected to the negative input voltage terminal and the positive input voltage terminal of the operational amplifier OP, and the integrating capacitor C f The lower plate of the operational amplifier OP is connected to the positive output terminal V op1 With the negative output terminal V on1 Then connected to the positive input terminal V of the second stage SC integrator module 102 ip2 With the negative input terminal V in2 ; The positive output terminal V of the first stage SC integrator module 101 op1 With the negative output terminal V on1 are connected to the positive input terminal V ipa1 With the negative input terminal V ina1 .

[0054] The second-stage SC integrator module 102 includes: a positive input terminal V ip2 With the negative input terminal V in2 , two timing Φ1 control switches, two timing Φ 1a Control switch, two timing Φ2 Control switch, two timing Φ 2a Control switch, two sampling capacitors C s , two integrating capacitors C f , an operational amplifier OP. The positive input terminal V ip2 With the negative input terminal V in2 are respectively connected to the positive output terminal V op1 With the negative output terminal V on1 , one end of the two timing Φ1 control switches is connected to the positive input terminal V ip2 With the negative input terminal V in2 The other end is connected to two sampling capacitors C s The lower plate is connected to one end of the two sequential Φ2 control switches, and the other ends of the two sequential Φ2 control switches are connected to the power supply V CM end, two sampling capacitors C s The upper plate is respectively connected to the two timing Φ 2a One end of the control switch is connected to two timing Φ 1a One end of the control switch, two timing Φ 1a The other end of the control switch is connected to the power supply V CM end, two time series Φ 2a The other end of the control switch is connected to the integral capacitor C f The upper plate is connected to the negative input voltage terminal and the positive input voltage terminal of the operational amplifier OP, and the integrating capacitor C f The lower plate of the operational amplifier OP is connected to the positive output terminal Vop2 With the negative output terminal V on2 Then connected to the positive input terminal V of the third stage SC integrator module 103 ip3 With the negative input terminal V in3 ; The positive output terminal V of the second stage SC integrator module 102 op2 With the negative output terminal V on2 are connected to the positive input terminal V ipa2 With the negative input terminal V ina2 .

[0055] The third stage SC integrator module 103 includes: a positive input terminal V ip3 With the negative input terminal V in3 , two timing Φ1 control switches, two timing Φ 1a Control switch, two timing Φ2 Control switch, two timing Φ 2a Control switch, two sampling capacitors C s , two integrating capacitors C f , an operational amplifier OP. The positive input terminal V ip3 With the negative input terminal V in3 are respectively connected to the positive output terminal V op2 With the negative output terminal V on2 , one end of the two timing Φ1 control switches is connected to the positive input terminal V ip3 With the negative input terminal V in3 The other end is connected to two sampling capacitors C s The lower plate is connected to one end of the two sequential Φ2 control switches, and the other ends of the two sequential Φ2 control switches are connected to the power supply V CM end, two sampling capacitors C s The upper plate is respectively connected to the two timing Φ 2a One end of the control switch is connected to two timing Φ 1a One end of the control switch, two timing Φ 1a The other end of the control switch is connected to the power supply V CM end, two time series Φ 2a The other end of the control switch is connected to the integral capacitor C f The upper plate is connected to the negative input voltage terminal and the positive input voltage terminal of the operational amplifier OP, and the integrating capacitor C f The lower plate of the operational amplifier OP is connected to the positive output terminal V op3 With the negative output terminal V on3 Then connected to the positive input terminal V of the adder module 201 ipa3 With the negative input terminal V ina3 .

[0056] The adder module 201 includes a power terminal V CM , a positive input terminal V ipa1 , a V ipa2 , a V ipa3 and a negative input terminal V ina1 , a V ina2 , a V ina3 , six feedforward path timing Φ1 control switches, eight timing Φ 2a control switches, two first-stage SC integrator module 101 feedforward path sampling capacitors C a1 , two second-stage SC integrator module 102 feedforward path sampling capacitors C a2 , and two third-stage SC integrator module 102 feedforward path sampling capacitors C a3 . The positive input terminal V ipa1 and the negative input terminal V ina1 of the adder module 201 are connected to the positive output terminal V op1 and the negative output terminal V on1 of the first-stage SC integrator module 101 respectively, the positive input terminal V ipa2 and the negative input terminal V ina2 of the adder module 201 are connected to the positive output terminal V op2 and the negative output terminal V on2 of the second-stage SC integrator module 102 respectively, and the positive input terminal V ipa3 and the negative input terminal V ina3 of the adder module 201 are connected to the positive output terminal V op3 and the negative output terminal V on3 of the third-stage SC integrator module 103 respectively; one end of the two feedforward path timing Φ1 control switches of the first-stage SC integrator module 101 is connected to the positive input terminal V ipa1 and the negative input terminal V ina1 of the addor module 201 respectively, and the other end is connected to the lower plate of the two first-stage SC integrator module 101 feedforward path sampling capacitors C a1 respectively and then connected to one end of the two timing Φ 2a control switches, and the other end of the timing Φ 2a control switches is connected to the power terminal V CM , and the upper plate of the two feedforward path sampling capacitors C a1 is connected to the positive output terminal V opa and the negative output terminal V ona of the adder module 201 respectively; one end of the two feedforward path timing Φ1 control switches of the second-stage SC integrator module 102 is connected to the positive input terminal V ipa2 and the negative input terminal V ina2 of the adder module 201 respectively, and the other end is connected to the lower plate of the two second-stage SC integrator module 102 feedforward path sampling capacitors C a2The lower plate is connected to the two timing Φ 2a One end of the control switch, timing Φ 2a The other end of the control switch is connected to the power supply V CM end, two feedforward path sampling capacitors C a2 The upper plates are connected to the positive output terminals V opa and the negative output terminal V ona The two feedforward path timing Φ1 control switches of the third stage SC integrator module 103 are connected to the positive input terminal V of the adder module 201 respectively. ipa3 and the negative input terminal V ina3 , and the other end is connected to the two third-stage SC integrator module 103 feedforward path sampling capacitors C a3 The lower plate is connected to the two timing Φ 2a One end of the control switch, timing Φ 2a The other end of the control switch is connected to the power supply V CM end, two feedforward path sampling capacitors C a3 The upper plates are connected to the positive output terminals V opa and the negative output terminal V ona , the two timing sequences Φ of the adder output edge 2a One end of the control switch is connected to the power supply V CM The other end is connected to the positive output terminal V opa and the negative output terminal V ona , the positive output terminal V of the adder module 201 opa and the negative output terminal V ona are respectively connected to the negative input terminal V qn and the positive input terminal V qp .

[0057] The positive input terminal V of the quantizer module 301 qp , negative input terminal V qn are connected to the negative output terminal V of the adder module 201 ona and the positive output terminal V opa , the enable terminal clk of the quantizer module 301 is connected to the clock signal clk.

[0058] The NAND gate of the DAC module 401 is connected to the output Q terminal and Qn terminal of the quantizer module 301, and the other end of the NAND gate is connected to the clock signal clk; the DAC output voltage is connected to two DAC sampling capacitors C dac The lower plate of 501, two DAC sampling capacitors C dac The upper plate of 501 outputs V dacp 、V dacn Two sampling capacitors C connected to the positive and negative input terminals of the first stage SC integrator module 101 respectively sthe upper plate of the upper pole.

[0059] In Figure 5 The full differential is used in the ΔΣ-ADC circuit structure shown in the figure to eliminate the even harmonic of the signal, reduce the noise interference in the input signal and power supply, and avoid the clock feedthrough effect of the MOS switch. Under the premise of meeting the performance and stability of the MEMS gyroscope, the circuit is simplified, the circuit area is reduced, the operational amplifier in the SC integrator adopts a two-stage cascade structure and a gain-enhanced folded cascode structure to realize high gain, the second stage of the operational amplifier adopts a new bias current source load cascode structure, and a large overdrive voltage is used to significantly reduce the transistor size, thereby greatly reducing the area overhead.

[0060] The following examples verify whether the ΔΣ-ADC structure described above can reduce the area overhead under the premise of meeting the performance and stability of the MEMS gyroscope and make a detailed description of its technical principles.

[0061] Figure 5 In the figure, the timing Φ1, Φ 2a The switch controlled by Φ1 and the capacitor C ai (i = 1, 2, 3, indicating which order integrator output is connected to) constitute an analog adder. When Φ1 is valid, C ai The output voltage of the i-th integrator is sampled. When Φ 2a is valid, C ai The charge stored in C ai is cleared. In order to make the quantizer quantize only after the capacitor C 1a is fully charged, the duty cycle of the quantizer enable terminal clk is only half of Φ 1a and rises on the latter half of the high level of Φ

[0062] The quantizer adopts the traditional latch comparator and SR buffer circuit structure, and its input signal is formula (5). In the formula, V q is the input of the quantizer, and V oi is the output of the i-th integrator. In order to match the ΔΣ-ADC circuit with the system in Figure 1 , C a1 ∶C a2 ∶C a3 = b1∶b2∶b3. This design makes the quantizer input shrink by 4.5 times, ensuring that the input signal does not exceed the input range. The quantizer output is a single-bit stream. It and clk control the DAC output voltage to be high (V ref+ = 3.5V) or low (V ref- = 1.5V) through an AND gate. V ref+ or V ref- is fed back to the input terminal of the ΔΣ-ADC circuit through the DAC sampling capacitor C dac .

[0063]

[0064] Time series Φ1 and Φ 1a , Φ2 and Φ 2a The controlled switch and sampling capacitor C s , operational amplifier OP, integrating capacitor C f Together they form an integrator. Φ1 and Φ 1a Control sampling, Φ2 and Φ 2a Control integral. Φ 1(2)a and Φ 1(2) Rising at the same time, but before Φ 1(2) The first-order integrator is different from other integrators in that it needs to accumulate the difference between the input signal and the DAC signal and has two inputs. Figure 6 The positive terminal of the first-order integrator (subscript " p ” indicates the charge transfer state. Φ1 and Φ 1a When valid, C s and C dac The input voltage V ip and V refp Sampling is performed, and C f Maintain the integration end state of the previous cycle. Φ2 and Φ 2a When valid, it is stored in C s and C dac All the charges in the f Therefore, in one clock cycle T s The charge transfer equation of the positive terminal of the first-order integrator is (6). Similarly, the negative terminal (subscript “ n " represents) The charge transfer equation is equation (7). The differential charge transfer equation is equation (8), and the input-output relationship in the z domain is equation (9). The input V i2(3) Output V o2(3) The relationship is as follows: (10). Design C s / C f =a i , C dac =C s The input-output relationship of the signal after SC sampling is (11), R on is the switch on-resistance. The signal transmission error through SC is given by equation (12). Assume that the maximum input signal amplitude that the ΔΣ-ADC can process is |V in,max |, ENOB is N, then its least significant bit (LSB) is as follows (13). Assuming that at 1 / 4T s (T s= 1 / fs = 125 ns) by C s , C adc or C ai The transmission error AV of SC composed of C in,max | = 0.6V. Referring to formula (12), (13), it can be calculated that LSB = 18.3uV, R on C < 2.54 x 10 -9 Thus, the value of C is listed in Table 2, and R on is 500Ω. For the sampling switch of the first stage integrator, a traditional single-capacitor gate voltage bootstrap switch is used, which has Ron not varying with input voltage, can reduce harmonics, and improve signal-to-noise ratio. The others are CMOS switches.

[0065] (V op [n] - V CM ) · C f = (V ip [n-1] - V CM ) · C s + (V dacp [n-1] - V CM ) · C dac + (V op [n-1] - V CM ) · C f (6);

[0066] (V on [n] - V CM ) · C f = (V in [n-1] - V CM ) · C s + (V dacn [n-1] - V CM ) · C dac + (V on [n-1] - V CM ) · C f (7);

[0067] V o [n] · C f = V i [n-1] · C s + V dac [n-1] · C b + V o [n-1] · C f (8);

[0068]

[0069]

[0070]

[0071]

[0072]

[0073] Table 2 Capacitance values in ΔΣ-ADC circuit

[0074] Name C s ]]> C f ]]> C b ]]> C a1 ]]> C a2 ]]> C a3 <!-- 9 -->]]> Value (pF) 0.8 2 0.8 4 3.6 1.4

[0075] An operational amplifier is the basis of the integrator, whose DC gain A0, unity gain bandwidth (UGB) and slew rate (SR) are related to the accuracy, small signal settling time t UGB and large signal settling time t SR of the ΔΣ-ADC, respectively. The relationship between A0and ENOB is formula (14). Formula (15) is the small signal settling equation. Since the integration duration of the integrator is 1 / 2T s , t UGB + t SR <1 / 2T s . Assuming t UGB = 3 / 8T s , the output error is less than 1 / 2LSB, then UGB needs to be greater than 40MHz. Assuming t SR = 1 / 8T s , and the input signal amplitude does not exceed 0.6V, the closed loop gain is 0.4, then SR≥15.36V / us.

[0076] A o > 20log(2 N )≈6.02N (14);

[0077] V out (t)=V step (1-e -t·2πUGB ) (15);

[0078] Figure 7The transistor level circuit diagram of the operational amplifier OP can be divided into three parts in general: the leftmost side is a bias voltage generating circuit, the rightmost side is an output common mode feedback circuit, and the middle is a main circuit, and Ap and An in the figure are auxiliary amplifiers of P-type common source common gate and N-type common source common gate respectively. The main circuit adopts common source common gate technology, gain enhancement technology and multi-stage cascade technology to improve the gain. The FD structure is adopted to eliminate even harmonics, suppress noise / interference in the input signal and power supply, output double signal swing, and the operational amplifier OP has a gain as high as 129dB and a unit gain bandwidth of 35MHz; the first stage of the operational amplifier OP adopts the gain-enhanced FC structure, and the second stage of the operational amplifier adopts a new common source structure, with PMOS as the input and NMOS as an independent bias current source load structure, and a large overdrive voltage is applied to reduce the transistor size, so as to further reduce the area overhead.

[0079] The entire ΔΣ-ADC layout in the embodiment is shown in Figure 8 The layout area is calculated to be 379.4umx755.5um, and thus the person skilled in the art should understand that the application of the above ΔΣ-ADC can make the structure of the MEMS gyroscope interface special chip more simple, smaller in size, and lower in power consumption to a certain extent.

[0080] In summary, the embodiment provides a discrete-time ΔΣ-ADC with a local negative feedback cascaded integrator feedforward structure, which adopts a full-differential input, small-signal output single-loop single-bit quantization discrete three-order integrator cascaded feedforward ΔΣ-ADC structure, improves the accuracy and linearity of the ΔΣ-ADC, discards the traditional input-to-quantizer path, simplifies the circuit, reduces the circuit area overhead and the negative influence of nonlinearity on SNR under the premise of ensuring high accuracy and stability, effectively realizes noise shaping, and the local negative feedback cascaded integrator feedforward structure also reduces the power consumption and design difficulty of the operational amplifier in the integrator.

[0081] The above embodiment is a preferred implementation scheme of the present application, and in addition thereto, the present application can be implemented in other manners, and any obvious replacement without departing from the technical scheme concept of the present application is within the protection scope of the present application.

[0082] In order for the person skilled in the art to more conveniently understand the improvements of the present application over the prior art, some drawings and descriptions of the present application have been simplified, and some other elements have also been omitted in the present application file for the sake of clarity, and the person skilled in the art should realize that these omitted elements can also constitute the content of the present application.

Claims

1. A third order integrator cascade feedforward delta sigma - ADC for a MEMS gyroscope interface chip, characterized by: A feedforward factor a 1 A feedforward factor a 2 A feedforward factor a 3 A second summing node, quantizer and DAC module; a first integrator composed of a gain factor c 1 and switches and operational amplifiers corresponding thereto; a second integrator composed of a gain factor c 2 and switches and operational amplifiers corresponding thereto; a third integrator composed of a gain factor c 3 and switches and operational amplifiers corresponding thereto; a feedforward factor a 1 , a feedforward factor a 2 , a feedforward factor a 3 and the second summing node constitute an adder; The first summing node, the first stage integrator, the second stage integrator, the third stage integrator, the second summing node, the quantizer are connected in sequence. The output of the quantizer is connected to a DAC module, the output of the DAC module is connected to a first summing node, the output of the first integrator is connected to a feedforward factor a 1, the output of the second integrator is connected to a feedforward factor a 2, the output of the third integrator is connected to a feedforward factor a 3, the output of the feedforward factor a 1, the output of the feedforward factor a 2, the output of the feedforward factor a 3 is connected to a second summing node; After the analog input signal is sampled, the quantizer single-bit stream output fed back by the DAC module is sent to the first-stage integrator for difference and integration, and then integrated by the second-stage integrator and the third-stage integrator in sequence. The integration result of the first-stage integrator is fed back by the feedforward factor. a 1 and the second-stage integrator integration result are fed forward by the factor a 2 and the third-stage integrator integration results are fed forward by the factor a 3, then add and sum, send to the quantizer for quantization and output the quantization result; And the discrete third-order integrator cascade feedforward delta-sigma-ADC structure comprises a first-stage SC integrator module, a second-stage SC integrator module, a third-stage SC integrator module, an adder module, a quantizer module, a DAC module and two DAC sampling capacitors C dac ; a positive input of the first stage SC integrator module V ip1 a negative input V in1 a positive output of the first stage SC integrator module V i a negative output of the first stage SC integrator module V op1 a positive input of the second stage SC integrator module V on1 a negative input V ip2 a positive output of the second stage SC integrator module V in2 a negative output V op2 a positive input of the third stage SC integrator module V on2 a negative input V ip3 a positive output of the third stage SC integrator module V in3 a negative output V op1 a positive output of the first stage SC integrator module V op2 a positive output of the second stage SC integrator module V op3 a positive output of the third stage SC integrator module V ipa1 a negative output of the first stage SC integrator module V ipa2 a negative output of the second stage SC integrator module V ipa3 a negative output of the third stage SC integrator module V on1 a negative input of the adder module V on2 a negative output of the adder module V on3 a positive input of the quantizer module V ina1 a positive output of the quantizer module V ina2 a negative input of the quantizer module V ina3 a negative output of the quantizer module V opa a positive input of the quantizer module V qn a negative output of the quantizer module V ona a positive output of the quantizer module V qp ; output terminal of the quantizer module Q , Q n respectively NAND gate of the DAC module, output of the DAC module respectively corresponds to connect two DAC sampling capacitors C dac lower plate of the two DAC sampling capacitors C dac upper plate output of the two DAC sampling capacitors V dacp and V dacn respectively connect two sampling capacitors of the first stage SC integrator module positive and negative input terminals C s upper plate of the two sampling capacitors The first stage SC integrator module includes two timing Φ 1 control switch, two timing Φ 1a control switch, two timing Φ 2 control switch, two timing Φ 2a control switch, two sampling capacitors C s , two integration capacitors C f , one operational amplifier OP; one of the time sequences Φ 1 control switch one end connected to the positive input V ip1 , the other time sequence Φ 1 control switch one end connected to the negative input V in1 , each time sequence Φ 1 control switch the other end connected to a sampling capacitor C s lower plate and a time sequence Φ 2 control switch one end, two time sequences Φ 2 control switch the other end connected to the power supply V CM end, each sampling capacitor C s upper plate connected to a time sequence Φ 2a control switch and a time sequence Φ 1a control switch one end, two time sequences Φ 1a control switch the other end connected to the power supply V CM end, two time sequences Φ 2a control switch the other end of each connected to an integral capacitor C f upper plate and respectively connected to the negative input voltage and positive input voltage of the operational amplifier OP, two integral capacitor C f lower plate and the positive output of the operational amplifier OP V op1 and the negative output V on1 connected and each connected to the positive input of the second SC integrator module V ip2 and the negative input V in2 , the positive output of the first SC integrator module V op1 and the negative output V on1 respectively connected to the positive input of the adder module V ipa1 and the negative input V ina1 ; The quantizer module includes a positive input end V qp , a negative input end V qn , an enable end ， The positive input end V qp , the negative input end V qn respectively connect the negative output end and the positive output end of the adder module V ona V opa , the enable end connects a clock signal clk ; the duty cycle of the clock signal clk connected by the enable end is only half of the time sequence Φ 1a and rises in the latter half of the time sequence Φ 1a when it is high, the quantizer module outputs a single-bit stream and its and clock signal clk is controlled by an AND gate to make the DAC module output voltage high or low, and the DAC module output voltage is fed back to the input end of the ΔΣ-ADC circuit through a DAC sampling capacitor C dac ​​ The first stage SC integrator module accumulates the difference between the input signal and the DAC signal and has two inputs, when timing Φ 1 and timing Φ 2 are active, the sampling capacitors 1a C s and the DAC sampling capacitors C dac sample the integrator module input voltage V ip and the DAC output voltage V refp respectively, while the integration capacitors C f are held at the end of integration state of the previous cycle; when timing Φ 2 and timing Φ 2a are active, the charges stored in the sampling capacitors C s C dac and the DAC sampling capacitors C f are all transferred to the integration capacitors.​ 2. The third-order integrator cascaded feed-forward delta sigma ADC of claim 1, wherein: The second stage SC integrator module also includes two timing Φ 1 control switches, two timing Φ 1a control switches, two timing Φ 2 control switches, two timing Φ 2a control switches, two sampling capacitors C s 、 two integration capacitors C f , one operational amplifier OP; one of the time sequences Φ 1 control switch one end connected to the positive input V ip2 , the other time sequence Φ 1 control switch one end connected to the negative input V in2 , each time sequence Φ 1 control switch the other end connected to a sampling capacitor C s , the lower plate and a time sequence Φ 2 control switch one end, two time sequences Φ 2 control switch the other end connected to the power supply V CM end, each sampling capacitor C s , the upper plate connected to a time sequence Φ 2a control switch and a time sequence Φ 1a control switch one end, two time sequences Φ 1a control switch the other end connected to the power supply V CM end, two time sequences Φ 2a control switch the other end connected to an integral capacitor C f , the upper plate and the negative input voltage end and the positive input voltage end of the operational amplifier OP are connected respectively, two integral capacitors C f , the lower plate and the positive output end V op2 and the negative output end V on2 of the operational amplifier OP are connected respectively and each connected to the positive input end V ip3 and the negative input end V in3 of the third SC integrator module; the positive output end V op2 and the negative output end V on2 of the second SC integrator module are connected to the positive input end V ipa2 and the negative input end V ina2 of the adder module respectively.

3. The third order integrator cascade feed forward delta sigma - ADC of claim 2, characterized in that: The third stage SC integrator module also includes two timing Φ 1 control switches, two timing Φ 1a control switches, two timing Φ 2 control switches, two timing Φ 2a control switches, two sampling capacitors C s 、 two integration capacitors C f , one operational amplifier OP; one of the time sequences Φ 1 control switch one end connected to the positive input V ip3 , the other time sequence Φ 1 control switch one end connected to the negative input V in3 , each time sequence Φ 1 control switch the other end connected to a sampling capacitor C s lower plate and a time sequence Φ 2 control switch one end, two time sequences Φ 2 control switch the other end connected to the power supply V CM end, each sampling capacitor C s upper plate connected to a time sequence Φ 2a control switch and a time sequence Φ 1a control switch one end, two time sequences Φ 1a control switch the other end connected to the power supply V CM end, two time sequences Φ 2a control switch the other end connected to an integral capacitor C f upper plate and connected to the negative input voltage and positive input voltage of the operational amplifier OP, respectively, two integral capacitor C f lower plate is connected to the positive output V op3 and negative output V on3 of the operational amplifier OP, respectively, and connected to the positive input of the adder module V ipa3 and negative input V ina3 .

4. Third order integrator cascade feed forward delta sigma - ADC according to any of the claims 1-3, characterized in that: The adder module includes a power terminal V CM , a positive input terminal V ipa1 , V ipa2 , V ipa3 and a negative input terminal V ina1 , V ina2 , V ina3 , two feedforward path timings corresponding to the first-stage SC integrator module Φ 1 control switches, two feedforward path timings corresponding to the second-stage SC integrator module Φ 1 control switches, two feedforward path timings corresponding to the third-stage SC integrator module Φ 1 control switches, two timings corresponding to the first-stage SC integrator module Φ 2a control switches, two timings corresponding to the second-stage SC integrator module Φ 2a control switches, two timings corresponding to the third-stage SC integrator module Φ 2a control switches, two timings corresponding to the adder output terminal Φ 2a control switches, two first-stage SC integrator module feedforward path sampling capacitors C a1 、 two second-stage SC integrator module feedforward path sampling capacitors C a2 , two third-stage SC integrator module feedforward path sampling capacitors C a3 ; two feedforward path timings corresponding to the first stage SC integrator modules Φ 1 control switches having one end connected to the positive input V ipa1 and negative input V ina1 respectively, and the other end connected to the lower plate of the two feedforward path sampling capacitors C a1 corresponding to the first stage SC integrator modules and the two timing Φ 2a corresponding to the first stage SC integrator modules Φ 2a respectively, and the other end connected to the power supply V CM end, the upper plate of the two feedforward path sampling capacitors C a1 corresponding to the first stage SC integrator modules are connected to the positive output V opa and negative output V ona respectively The timing of the two feedforward paths corresponding to the second-stage SC integrator module Φ 1. One end of the control switch is connected to the positive input terminal V ipa2 and the negative input V ina2 The other end is connected to the two second-stage SC integrator module feedforward path sampling capacitors C a2 The lower plate and the two timings corresponding to the second stage SC integrator module Φ 2a One end of the control switch is connected, corresponding to the two timing of the second stage SC integrator module Φ 2a The other end of the control switch is connected to the power supply V CM The two feedforward path sampling capacitors corresponding to the second-stage SC integrator module C a2 The upper plates are connected to the positive output terminals V opa and negative output terminal V ona ; Two feedforward path timings corresponding to the third-stage SC integrator module Φ 1. One end of the control switch is connected to the positive input terminal V ipa3 and the negative input V ina3 The other end is connected to the two third-stage SC integrator module feedforward path sampling capacitors C a3 The lower plate and the two timings corresponding to the third-stage SC integrator module Φ 2a One end of the control switch is connected, corresponding to the two timing of the third-stage SC integrator module Φ 2a The other end of the control switch is connected to the power supply V CM The two feedforward path sampling capacitors corresponding to the third-stage SC integrator module C a3 The upper plates are connected to the positive output terminals V opa and negative output terminal V ona ; Two time sequences corresponding to the adder output end clk 2a One end of the control switch is connected to the power supply V CM The other end is connected to the positive output end of the adder V opa And the negative output end of the adder V ona ​ the positive output V opa and the negative output V ona corresponding to the negative input V qn and the positive input V qp respectively 5. The third order integrator cascade feed forward delta sigma ADC of claim 1, wherein: One end of the two NAND gates of the DAC module respectively corresponds to the output of the quantizer module Q The end with Q The n end, the other end of the NAND gate is connected with the clock signal The operational amplifier OP adopts a two-stage cascade structure, the first stage of the operational amplifier OP adopts a gain-enhanced folded cascode structure, and the second stage of the operational amplifier OP adopts a common source structure and takes PMOS as input and NMOS as an independent bias current source load structure. The output voltage end of the DAC module is respectively connected with one DAC sampling capacitor C dac The lower plate of the two DAC sampling capacitors C dac The upper plate output V dacp 、 V dacn Respectively corresponds to the two sampling capacitors of the first stage SC integrator module C s The upper plate.

6. A third order integrator cascade feed forward delta sigma - ADC according to any of the claims 1-3, characterized in that:

7. A MEMS gyroscope interface chip comprising a third order integrator cascade feedforward ΔΣ-ADC according to any one of claims 1-6. ​

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