Indium gallium nitride structures and devices

Abstract

The present disclosure relates to an InGaN layer characterized by an in-plane lattice parameter in the range of to. The InGaN layer is grown by coalescing InGaN grown on a plurality of GaN seed regions. The InGaN layer can be used to fabricate optical and electronic devices in light sources for lighting and display applications.

Description

[0001] This application claims the priority of U.S. Application No. 16 / 689,064, filed on November 19, 2019. Technical Field

[0002] The present disclosure relates to an indium gallium nitride (InGaN) layer having a substantially relaxed region and a device fabricated on the InGaN layer. The substantially relaxed wurtzite (0001) InGaN region has an in-plane or "a" lattice parameter greater than or equal to . The substantially relaxed InGaN region is grown on a plurality of group III nitride seed regions, such as GaN, InGaN, AlGaN, or AlN seed regions. During growth, the InGaN grown on the seed region relaxes and coalesces to provide a substantially relaxed InGaN region that can be used as a growth surface for other semiconductor materials. The InGaN layer can be used to fabricate optical and electronic devices that are used as light sources in lighting and display application systems. Background Art

[0003] Compound semiconductor materials are typically deposited or grown on a growth substrate in an atomically lattice-matched manner to avoid the generation of growth defects such as dislocations. In some cases, it is desirable to modify the lattice parameter of the compound semiconductor material to provide a material and / or device and / or system having specific properties.

[0004] InGaN is currently the material of choice for the active layer of GaN-based optoelectronic devices, such as light-emitting diodes (LEDs) that emit blue or violet light and laser diodes (LDs) that emit violet light. The LEDs are currently the basis of most commercially available LED-based lighting and display systems, and the violet-emitting LDs are the basis of the blue TM industry. Today, such devices are fabricated using a pseudomorphic InGaN active layer grown on a gallium-nitride (GaN) epitaxial layer. Unfortunately, the crystal atomic lattice parameter of InGaN is greater than that of GaN, resulting in severe strain, and as the InN mole fraction or thickness of InGaN grown on GaN (InGaN / GaN) increases, the material quality deteriorates. This limits the performance of InGaN / GaN-based optoelectronic devices, such as LEDs and LDs.

[0005] To date, attempts to grow high-quality, planar, relaxed InGaN for device applications have not been successfully commercialized. The graded layer approach used in some III-V material systems has been attempted for InGaN using low-temperature molecular beam epitaxy (MBE). However, the relaxation mechanism is associated with the emergence of high densities of misfit dislocations, stacking faults, and threading dislocations, resulting in poor material quality. Similar approaches using the commercially preferred metalorganic chemical vapor deposition (MOCVD) for c-plane InGaN are compromised by the lack of a slip system for (polar) c-plane growth, and attempts to utilize nonpolar and semipolar growth planes result in materials with high defect densities. Hydride vapor phase epitaxy (HVPE) has been used to grow thick InGaN layers with the aim of reducing crystal defects, but this method is limited in terms of the achievable InN mole fraction and is only applicable to N-polar surfaces, and thus is not ideal for low-cost manufacturing. Attempts have been made to grow strained InGaN layers that can be peeled off and bonded to compliant substrates to facilitate relaxation, but this method results in limited lattice expansion and non-planar trench surfaces. Using nanocolumn or nanorod device structures designed to avoid the strain limits of conventional heteroepitaxy results in non-planar device geometries that are not suitable for manufacturing and may exhibit low optical quality.

[0006] The use of patterning and regrowth has been used to grow high-quality, lattice-mismatched heteroepitaxies for single-element (e.g., Ge on Si) and binary III-V (e.g., GaAs on Si) zinc blende semiconductors. However, similar approaches for wurtzite semiconductors and / or ternary alloys such as InGaN have not been successful. Summary of the Invention

[0007] According to the present invention, a group III nitride semiconductor structure comprises (a) a seed region comprising In x Ga 1-x N (0 ≤ x < 1) and having a wurtzite group III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite group III nitride structure and intersecting the seed region; wherein the intersection of the first plane with a first edge of the seed region locates an In x Ga 1-x N / In y Ga 1-y N heterojunction, where 0 < y ≤ 1 and y > x; the In x Ga 1-x N / In y Ga 1-yThe N heterojunction is coplanar with a first crystal plane of the seed region; (c) any second plane that is parallel to the (0001) plane of the wurtzite group-III nitride crystal structure and intersects a second edge of the seed region positions a group-III nitride heterojunction, wherein the group-III nitride heterojunction is coplanar with a second crystal plane of the seed region; and (d) a (0001) InGaN region covering the seed region, wherein the (0001) InGaN region is characterized by an in-plane a lattice parameter greater than and wherein each of the first crystal plane and the second crystal plane is crystallographically equivalent.

[0008] According to the present invention, a semiconductor device includes a III-V semiconductor structure according to the present invention.

[0009] According to the present invention, an illumination system includes a semiconductor device according to the present invention.

[0010] According to the present invention, a display system includes a semiconductor device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Those skilled in the art will understand that the drawings described herein are for illustrative purposes only. The drawings are not intended to limit the scope of the present disclosure.

[0012] Figures 1A to 1E An example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure is shown.

[0013] Figures 2A to 2E An example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure is shown.

[0014] Figures 3A to 3E An example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure is shown.

[0015] Figures 4A to 4E An example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by the present disclosure is shown.

[0016] Figure 5 Examples of positive etch masks having various shapes, sizes, and orientations with respect to the (1-100) and (11-20) crystal orientations of a group-III nitride wurtzite material are shown.

[0017] Figure 6 Examples of negative etch masks having various shapes, sizes, and orientations with respect to the (1-100) and (11-20) crystal orientations of a group-III nitride wurtzite material are shown.

[0018] Figure 7Shows the transition from an InGaN lattice characterized by a lattice parameter "a" similar to that of GaN (solid circles) to a larger relaxed InGaN lattice characterized by the lattice parameter "a" (dashed circles).

[0019] Figure 8 Shows an example of an LED incorporating a group III nitride semiconductor structure provided by the present disclosure.

[0020] Figures 9A to 9D Shows an example of an LED incorporating a group III nitride semiconductor structure provided by the present disclosure.

[0021] Figure 10 Shows an example of a laser diode (LD) incorporating a group III nitride semiconductor structure provided by the present disclosure.

[0022] Figure 11 Shows examples of lighting devices and systems in which an LED provided by the present disclosure can be incorporated.

[0023] Figure 12 Shows examples of display devices and systems in which an LED provided by the present disclosure can be incorporated.

[0024] Figure 13 Shows a cross-sectional view of an example of a group III nitride semiconductor structure provided by the present disclosure.

[0025] Figures 14A to 14B Shows the ranges of the InN mole fraction and the a lattice parameter of the (0001) relaxed InGaN region according to the peak emission wavelength, respectively.

[0026] Figures 15A to 15F Shows an example of a process flow for manufacturing an InGaN layer provided by the present disclosure.

[0027] Figures 16A to 16F Shows an example of a process flow for manufacturing an InGaN layer provided by the present disclosure.

[0028] Figure 17A and 17B Shows a cross-sectional view of an example of a group III nitride semiconductor structure provided by the present disclosure.

[0029] Figures 18A to 18C Shows an example of gradually growing InGaN on the (10-11) facet of a group III nitride semiconductor to fill a "v-pit" structure.

[0030] Figure 19 Shows the gradual growth of InGaN on the (10-11) GaN seed facet to provide a relaxed InGaN region.

[0031] Figure 20An example is shown of gradually growing InGaN on a (10-11) GaN seed facet to provide a relaxed InGaN region. Detailed Description

[0032] "Substantially uniform lattice parameter" means a semiconductor layer characterized in that the local lattice parameter of the semiconductor layer varies less than 1% relative to the average lattice parameter, such as less than 0.5% relative to the average lattice parameter, or less than 0.1% relative to the average lattice parameter.

[0033] "Defect density" means the density of extended defects (such as dislocations) in a semiconductor layer in a plan view. The defect density can be determined using, for example, etching (and counting the etch pit density, EPD), cathodoluminescence to observe and count dark spots, and atomic force microscopy (AFM) to observe and count pits.

[0034] X-ray diffraction (XRD) and reciprocal space mapping (RSM) analysis can be used to determine the lattice parameter. High-angle or near grazing incidence XRD techniques can be used to determine the lattice parameter of the upper layer in a structure where the lattice parameter can vary as a function of depth.

[0035] "III-V material" means a compound semiconductor material containing at least one group III element and at least one group V element from the periodic table.

[0036] "Growth plane" means a plane parallel to the deposition plane of the material on a plane, such as the plane of a conventional substrate growth surface.

[0037] "Substantially perpendicular to the growth plane" means a surface that forms an angle of approximately 90 degrees with respect to the growth plane, such as from 88 degrees to 92 degrees with respect to the growth plane.

[0038] Wurtzite GaN is characterized by having room temperature a and c lattice parameters of and a wurtzite crystal structure. The crystal plane perpendicular to the c lattice parameter direction ("c direction") is the c plane, which has a Ga plane (0001) and an N plane (000-1). The plane containing the c direction and perpendicular to the a lattice parameter direction ("a direction") is the (11-20) plane or "a plane". The plane containing the c direction and rotated 30 degrees relative to the a direction is the (1-100) plane or "m plane".

[0039] Wurtzite In x Ga 1-x N has the same crystal structure as wurtzite GaN, but includes a non-zero mole fraction x of InNr to form a ternary compound, where the specified fraction of group III atoms is In and the remainder is Ga. InN has and at room temperature, and In, according to the mole fraction x Ga 1-x N has room-temperature a and c lattice parameters that are between the room-temperature a and c lattice parameters of GaN and InN.

[0040] Although this specification focuses on growing (0001) InGaN on a GaN seed surface, the method can be applied to other wurtzite materials, such as InGaN on AlN, AlGaN on AlN, and AlGaN on GaN. Additionally, the present invention is applicable to non-basal wurtzite structures, such as so-called non-polar and semi-polar GaN and related materials. Finally, the present invention can also be applied to other compound semiconductor systems, including zinc blende materials, such as InGaAs on GaAs and InGaSb on GaSb, and II-VI compound semiconductor systems.

[0041] "Relaxed InGaN" refers to an InGaN material that exhibits in-plane lattice parameters equal to or nearly equal to the in-plane lattice parameters of a fully relaxed InGaN material. For example, wurtzite relaxed InGaN has a room-temperature a-plane lattice parameter greater than (0% InN) and up to (100% InN). This is in contrast to strained InGaN materials, such as InGaN grown pseudomorphically to GaN and thus exhibiting in-plane lattice parameters equal to or nearly equal to the in-plane lattice parameters of GaN (i.e., approximately 3.189), regardless of the InN mole fraction. Such a strained InGaN material is referred to as InGaN / GaN.

[0042] "In-plane lattice parameter" refers to the lattice spacing within the growth plane. For (0001) materials, the in-plane lattice parameter is the a lattice parameter.

[0043] "Lateral growth" refers to growth in a direction other than perpendicular to the growth plane, including parallel to the growth plane.

[0044] Now, certain embodiments of materials, semiconductor structures, optoelectronic devices, and methods are described in detail. The disclosed embodiments are not intended to limit the claims. Instead, the claims are intended to cover all alternatives, modifications, and equivalents.

[0045] The present invention teaches the formation of a large-area, planar, coherent, at least partially but substantially uniformly relaxed compound semiconductor material layer for use in optical and / or electronic devices. Large-area means an area greater than 1 mm 2 such as an area greater than 1 cm in extent 2A planar semiconductor layer is a semiconductor layer that exhibits at least one substantially flat surface and has substantially no significant thickness variations over a large area. For example, a planar semiconductor layer can have an RMS roughness of less than 1 nm as measured using an atomic force microscope. The planar semiconductor layer can have a thickness, for example, within + / - 10% of the average thickness. Coherent means that the material is substantially crystalline rather than amorphous. Relaxed means that the in-plane lattice parameter of the material approximates that of a free-standing, coherent, 100% relaxed form of the material. Substantially relaxed means a material in which the in-plane lattice parameter of the material is within 30% of the in-plane lattice parameter of a free-standing, coherent, 100% relaxed form of the material. Uniformly means substantially invariant in-plane lattice parameter over a large area on which optical and / or electronic device structures can be built. Additionally, the present invention is applicable to a wide range of semiconductor crystal systems, including the wurtzite crystal structure, and to higher-order alloys including ternary and quaternary alloys. Finally, the present invention is applicable to structures grown by a variety of growth methods, particularly metalorganic chemical vapor deposition (MOCVD).

[0046] In particular, the present invention teaches the formation of a large-area, planar, coherent, at least partially but substantially uniformly relaxed indium gallium nitride (InGaN) material layer for use as a substrate layer for optical and / or electronic devices. Various compositions (i.e., InN mole fractions) can be achieved. Coherent means that the InGaN material is substantially crystalline rather than amorphous. Relaxed means that the lattice parameter of the InGaN material approximates that of a free-standing, coherent, 100% relaxed InGaN material of the same composition. Uniformly relaxed means a layer in which the in-plane lattice parameter is substantially invariant over a vast majority of the large area in the plane containing the growth plane. In the present invention, such a relaxed InGaN material is referred to as relaxed InGaN, e.g., Native

[0047] The present invention also teaches the formation of optical and / or electrical devices and systems based on the relaxed InGaN, which can include other InGaN layers, e.g., Native, that are pseudomorphically grown as relaxed InGaN (i.e., InGaN / InGaN).

[0048] Other features and aspects of the present invention will become apparent from the following description and the drawings. In particular, the teachings of the present invention can be applied to other compound semiconductor device materials such as aluminum gallium nitride, aluminum gallium indium nitride, III-As, III-P, III-Sb, etc.

[0049] The present invention discloses the use of a semiconductor seed material deposited on a substrate to record the epitaxial growth of a compound semiconductor material. The seed material has a plurality of seed regions, the plurality of seed regions having edges that are planar seed surface portions, and each normal to these planar seed surface portions having a crystallographically equivalent direction that is not parallel to the normal of a large area of the substrate. A limited (preferably one) number of exposed flat seed surface crystallographically equivalent orientations ensures uniform relaxation and composition control of the InGaN material grown thereon, avoiding competing growth modes and problems associated with uncontrolled composition control, such as non-uniform InN incorporation, rough surfaces, etc. when variable seed surface orientations for InGaN growth are presented simultaneously. The size of the seed surface portions is limited to some extent such that additional compound semiconductor material can be seeded and readily relaxed to its relaxed lattice parameters during growth. The resulting "relaxed" compound semiconductor material then grows outwards and coalesces to form a large area (i.e., greater than 1×1 mm 2 , preferably greater than 1×1 cm 2 area) film. The large area, relaxed compound semiconductor material film provides a template for growing improved optical and / or electronic device structures.

[0050] In particular, the present invention discloses the use of GaN seed regions having seed surface portions to record the epitaxial growth of InGaN. The size and geometry associated with the GaN seed surface are limited to some extent such that InGaN material can be seeded and readily relaxed to its relaxed lattice parameters during growth. The crystallographic direction of the normal characterizing the planar seed surface portions can be a non-polar direction, such as (11-20) or (1-100) or a plane rotated between them, or a semi-polar direction, such as (1-101). The (relaxed) InGaN layer then grows outwards and coalesces into a planar large area film. The large area, relaxed InGaN film provides a template for growing improved InGaN-based optical and / or electronic device structures.

[0051] Figures 1A to 1E An example of a method for growing a relaxed InGaN region is shown.

[0052] As Figure 1AAs shown, a predominantly (0001), i.e., c-plane GaN (or AlN) layer 102 can be grown on a substrate 101 using any suitable semiconductor growth method. Examples of suitable substrates include sapphire, silicon carbide, silicon, aluminum nitride, and gallium nitride. Other useful substrate materials include engineered substrates such as silicon-on-insulator (SOI). The GaN layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. The GaN layer 102 can be covered with a mask layer 103 of a material that slowly promotes the nucleation of group III nitride materials. Suitable mask materials include, for example, dielectrics such as silicon nitride, silicon oxide, and aluminum oxide. The mask layer 103 and the underlying GaN layer 102 can be patterned and etched using photolithography (e.g., using nano-lithography and wet and / or dry etching techniques) to provide the desired pattern as shown in Figure 1B The etched regions 104 where the mask and GaN material have been removed expose the GaN seed surface 102a. The seed surface can be substantially perpendicular to the GaN (0001) c-plane. As shown in Figure 1C The GaN seed surface 102a can be used to grow InGaN 105 at least laterally, thereby forming an InGaN / GaN heterojunction that is non-coplanar with the substrate 101. Each exposed GaN seed surface can have an equal crystallographic orientation. For example, the GaN seed surface can be predominantly (1-100), i.e., the m-plane, or predominantly (11-20), i.e., the a-plane, or any plane rotated between the m-plane and the a-plane. Additionally, the seed surface 102a can be intentionally misoriented relative to the main GaN crystal plane, for example, to promote favorable and uniform growth characteristics. Figure 1E A plane 108a passing through the relaxed InGaN region and coplanar with the surface 107, and a plane 108b bisecting the InGaN region between the seed region 102 and the seed region 102 are shown. The center of the seed region is denoted by 108c, and the center of the InGaN region between the seed regions 102 is denoted by 108d.

[0053] The orientation of the GaN seed surface can be determined by the patterning and the growth orientation of the GaN layer. The orientation of the seed surface also depends on the angle of the etched GaN layer surface. For example, for a (0001) GaN layer and near-vertical etching, the orientation of the GaN seed surface can vary from approximately (1-100) to (11-20), and any orientation rotated between them. This orientation can be selected to optimize the InGaN growth conditions and the InGaN material quality.

[0054] For InGaN growth on certain GaN seed surfaces, particularly those that are substantially perpendicular to the main surface of the substrate, in order to promote coalescence, it may be necessary to enhance the lateral-longitudinal growth by optimizing the growth conditions and / or selecting the GaN seed surface orientation that promotes a rapid growth rate.

[0055] The small size on the GaN seed surface promotes InGaN of the InGaN material deposited thereon and provides a planar crystallization orientation to facilitate coherent InGaN growth. During growth, InGaN grows coherently and relaxes to its relaxed lattice parameter, and finally coalesces with adjacent InGaN growth fronts. Refer to Figure 1C , InGaN 105 is grown from the GaN seed surface, and InGaN 106 is grown in Figure 1D to fill the etch cavity and cover the mask layer 103. Continuous InGaN growth causes the InGaN grown on the GaN seed surfaces in adjacent cavities to coalesce. Then, relaxed InGaN is grown above the mask layer to form a continuous, planar, relaxed InGaN region or InGaN template at the upper InGaN growth surface 107.

[0056] In the InGaN growth method of the present invention, relaxation mainly occurs laterally, i.e., by distortion, rather than by tilting that occurs when attempting InGaN relaxation directly on the GaN(0001) surface. The latter method introduces a vertical InGaN strain gradient, which becomes problematic during subsequent growth and coalescence of InGaN. Instead, the present invention provides reduced tilting, which allows the final coalesced film to be substantially free of strain and / or compositional inhomogeneities, thus providing a high-quality planar relaxed InGaN large-area surface for semiconductor growth. In addition, since relaxation occurs uniformly on the GaN seed surface, the vertical strain gradient that may occur when a strained layer first grows pseudomorphically (and then is etched and relaxed) is greatly avoided.

[0057] In the InGaN growth method provided by the present disclosure, InGaN growth mainly occurs on the surface of the GaN seed material, and growth of InGaN on other exposed surfaces should be minimized or completely avoided. For this reason, it may be beneficial to etch through the GaN seed material and into the underlying substrate to move the substrate growth surface away from the InGaN nucleation region. In addition, the growth conditions of the InGaN layer can be selected to promote growth at one or more GaN seed surfaces, which is contrary to InGaN nucleation and growth on the substrate, and InGaN nucleation and growth will exhibit a competitive growth mode. This method is shown in Figures 2A to 2E where a portion of the GaN layer and the substrate are etched. By etching the substrate, the distance between competitive growth (at the substrate surface) and desired growth at one or more surfaces of the GaN seed material is increased, with the aim of making the InGaN grown on the substrate non-competitive. In addition, etching the substrate can be used to prevent nucleation and growth of InGaN, which further reduces the possibility of interfering with the competitive growth mode.

[0058] Figure 2Ashows a substrate 201, an overlying GaN layer 202, and an overlying mask layer 203. In Figure 2B , a portion of the mask layer 203, GaN layer 202, and substrate 201 have been etched to provide a cavity 204 having an exposed GaN seed surface 202a. As Figure 2C shown, InGaN 205 grows on the GaN seed surface 202a and laterally grows into the corresponding cavity 204 and above the substrate 201. As Figure 2D shown, continuous InGaN growth 206 causes the laterally grown regions to merge and grow outward from the cavity and onto the mask layer 203. A portion 208 of the cavity 204, i.e., a void, can be created between the substrate 201 and the merged InGaN 206 within the cavity. As Figure 2E shown, continuous InGaN growth causes InGaN grown from adjacent cavities to coalesce and form a relaxed InGaN surface 207, which can be used for the growth of semiconductor layers. Figure 2E shows a plane 208a that passes through the relaxed InGaN region and is coplanar with the surface 207, and a plane 208b that bisects the InGaN region between the seed region 202 and the seed region 202. The center of the seed region is denoted by 208c, and the center of the InGaN region between the seed regions 202 is denoted by 208d.

[0059] Figure 13 is formed by Figures 2A to 2EDetailed cross-sectional view of the structure produced by the process flow shown. Substrate 1301 (e.g., (0001) sapphire) includes optional etched regions 1306 extending into substrate 1301. GaN (or AlN) seed layer material 1302 characterized by an in-plane a lattice parameter a1 covers substrate 1301 in the unetched regions and is under mask layer 1303. InGaN 1305 has nucleated at the edges of the seed layer material 1302 on the GaN seed surface 1307, thereby forming an InGaN / GaN heterojunction 1307 (i.e., the heterojunction is at the interface between the InGaN region and the GaN seed region), the normal of which shares an equivalent crystallographic direction that is not parallel to the main surface of substrate 1301. The InGaN material 1305 has grown at least partially laterally outward to relax towards a relaxed in-plane a lattice parameter a2 in the InGaN region between the GaN seed surfaces. The plane 1308b parallel to the main surface of substrate 1301 and bisecting the GaN seed surface 1307 is characterized by different in-plane a lattice parameters at different positions within the cross-section. For example, at the center point within the GaN seed region, the lattice parameter along plane 1308b is characterized by a1 comparable to the GaN a lattice parameter, and at the center point 1305 between the GaN seed surfaces 1307, the lattice parameter along plane 1308b is approximately a2, comparable to the lattice parameter of at least partially relaxed InGaN, and is determined by the epitaxial growth conditions (such as temperature and relative flow rate) of an organometallic precursor such as trimethylindium (TMI) compared to trimethylgallium (TMG) in MOCVD, in particular according to the average mole fraction of InN in the InGaN layer. In the region between these two center points, the lattice parameter along plane 1308b is characterized by an in-plane a lattice parameter greater than a1 and less than a2 because a2 > a1. In a plan view (not shown), the variation of the in-plane a lattice parameter within plane 1308a is characterized by the two-dimensional mask pattern applied to the GaN seed layer (see Figure 5 and 6 ).

[0060] The InGaN material coalesces on the mask layer 1303 to form a relaxed InGaN region 1304 with a flat InGaN surface 1305c. The plane 1308a parallel to the main surface of the original growth substrate and located within the relaxed InGaN region 1304 is mainly characterized by an in-plane a lattice parameter a2. In particular, at the center point 1305 between the GaN seed surfaces, the InGaN lattice parameter along plane 1308a is characterized by a2, while at the center point above the GaN seed surface, the InGaN a lattice parameter along plane 1308a is slightly less than a2. In a plan view (not shown), the variation of the in-plane a lattice parameter within plane 1308a is characterized by the two-dimensional mask pattern applied to the GaN seed layer (see Figure 5 and6 )。For example, XRD and RSM can be used to detect changes in the in-plane a lattice parameter of InGaN, and grazing incidence angle techniques can be used to resolve in the sub-micron scale and on the upper surface. The midpoint of the plane 1308b in the seed region is denoted as 1308c, while the midpoint of the plane 1308b between the seed regions is denoted as 1308d.

[0061] The GaN seed region 1302 has an in-plane dimension of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed region 1302 can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1302, e.g., the width of the GaN seed region 1302, can be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask layer 1303 can be, for example, from 0.01 μm to 1 μm, from 0.02 μm to 0.8 μm, from 0.05 μm to 0.5 μm, or from 0.1 μm to 0.4 μm.

[0062] Figures 3A to 3E An example of a process flow for fabricating relaxed InGaN using an SOI substrate is shown. In this embodiment, it may be desirable to include a strain control interlayer, such as GaN, AlGaN, or AlInGaN, within the semiconductor structure (not shown) to manage wafer bending, as is well known for growing GaN on Si.

[0063] Figure 3A The substrate 301, oxide layer 301a and silicon layer 301b, seed layer 302, and mask layer 303 are shown. Figure 3B The cavity 304 after etching down to the silicon layer 301b is shown, which forms a seed region from the seed layer 302. Figure 3C Lateral growth of InGaN on the edge surface of the seed region from the seed layer 302 within the cavity 304 is shown. This InGaN growth has a high enough InN mole fraction to induce strain relaxation. Figure 3D In, the InGaN growth 306 from the seed layer 302 has grown outwards and merged to fill the cavity and extend over the mask 303. Figure 3E As shown, continuous InGaN growth provides a planar relaxed InGaN layer 307. Figure 3E A plane 308a passing through the relaxed InGaN region and coplanar with the surface 307, and a plane 308b bisecting the InGaN region between the seed region 302 and the seed region 302 are shown. The center of the seed region is denoted by 308c, and the center of the InGaN region between the seed regions 302 is denoted by 308d.

[0064] Figures 4A to 4EAnother example of a process flow for fabricating a relaxed InGaN layer using an SOI substrate is shown. This example is similar to Figures 3A to 3E the example in which the top silicon layer and the buried oxide layer 401a of the SOI substrate 401b are removed by etching (in region 404) to minimize the competing growth of InGaN on the silicon substrate and to facilitate the growth of InGaN on the seed surface.

[0065] Figure 4A The SOI substrate 401, the oxide layer 401a, the silicon layer 401b, the seed layer 402, and the overlying mask layer 403 are shown. Figure 4B A cavity 404 created by etching down into the substrate 401 is shown, which forms a seed region from the seed layer 402. In Figure 4C this, the lateral InGaN growth 405 extends from the edge surface of the seed layer 402 into the cavity 404. This InGaN growth has a high enough InN mole fraction to induce strain relaxation. As Figure 4D shown, the continuous InGaN growth 406 causes the InGaN grown from the opposing seed surfaces to merge and grow vertically to fill the upper part of the cavity and extend over the mask layer 403. The preferential growth from the seed surfaces creates a space 408, i.e., a void, between the substrate 401 and the InGaN layer 406 compared to the growth on the substrate. As Figure 4E shown, the continuous InGaN growth provides a planar relaxed InGaN layer 407. Figure 4E A plane 408a passing through the relaxed InGaN region and coplanar with the surface 407 is shown, as well as a plane 408b bisecting the InGaN region between the seed regions 402 and 402. The center of the seed region is denoted by 408c, and the center of the InGaN region between the seed regions 402 is denoted by 408d.

[0066] Figure 5 Examples of mask patterns for etching the seed material are shown, including stripes, rectangles, triangles, and hexagons. For wurtzite materials such as group III nitride materials, including InGaN, the preferred pattern features are those having edges with the same crystallographic orientation, such as hexagons or triangles. Other shapes and other relative dimensions can be used. The narrowest dimension of the mask pattern can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The edges of the mask pattern can be aligned with certain crystal planes. For example, for a wurtzite material having a (0001) main growth plane, the mask edges can be aligned with the (1-100) or (11-20) planes, or any orientation between these planes, to facilitate the growth of a high-quality, relaxed InGaN layer.

[0067] Figure 6 A set of alternative mask patterns is shown, which are Figure 5A negative image of the mask pattern shown, but otherwise similar.

[0068] Figure 7 A conceptual planar cross-sectional view of a patterned GaN seed material having a lattice parameter a is shown, on the side surface of which lateral heteroepitaxy is performed to grow an InGaN layer that allows relaxation to a relaxed lattice parameter a' by distortion. For sufficiently small dimensions, the deformation is fully elastic and no defects are formed. For larger dimensions, some plastic deformation may occur, but may be tolerable if the final defect density in the subsequently deposited overlying semiconductor layer is low enough. For example, it is desired that the extended defect density in the subsequently deposited semiconductor layer is less than 5E9 cm 2 , for example less than 5E8 cm 2 or less than 5E7 cm 2 . The lateral InGaN growth and coalescence method provided by the present disclosure contributes to the annihilation of line dislocations in group III nitride materials.

[0069] Further control over the thickness and compositional uniformity of relaxed InGaN growth can be provided by growing a multilayer structure instead of using a bulk InGaN layer. For example, 25% of the bulk InGaN layer can be replaced, for example, by alternating layers of 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In 0.5 Ga 0.5 N. The layer thickness of each layer can be, for example, from 0.5 nm to 100 nm, for example from 1 nm to 30 nm. The multilayer structure is not limited to the base layer, but can be used throughout the epitaxial stack or in the layer between the relaxed InGaN base layer and the device layer, the epitaxial stack including semiconductor device layers covering the relaxed InGaN layer, such as n-type, p-type, and active layers.

[0070] Compared with InGaN / GaN, the increased lattice parameter of the relaxed InGaN layer allows the subsequent deposition of semiconductor layers to be grown at much higher temperatures than InGaN / GaN. For example, compared with about 4% for InGaN / GaN, having The a-lattice parameter of InGaN has been shown to incorporate approximately 7% of InN. Since the mole fraction of InN incorporated into GaN is inversely proportional to the growth temperature in MOCVD, this indicates that an increase in the InGaN a-lattice parameter of approximately 0.015 to 0.020 can increase the useful growth temperature by approximately 50 °C. Further increases in the InGaN a-lattice parameter will allow even higher temperatures to be used for the same InN mole fraction. This effect can be used not only to achieve higher quality semiconductor layers grown on relaxed InGaN, which is achieved by reducing point defect formation at higher temperatures, but also to reduce or eliminate pits that appear at the line dislocation sites on the surface of the InGaN film. Ideally, the growth temperature of the InGaN layer is maintained high enough to eliminate or at least limit the diameter of the pits to be much less than 1 μm, such as less than 200 nm, or less than 50 nm. A thin, high-temperature GaN or AlGaN layer grown on the pitted InGaN film can be used to "fill" the small pits.

[0071] The method provided by the present disclosure may include recursion, which can help obtain large lattice parameter variations. For example, a relaxed InGaN layer can be used as a seed layer to provide a seed surface for growing a higher-InN mole fraction layer. The resulting new relaxed InGaN layer can then be used as a seed layer in another round of the process, and so on. The method can help obtain a relaxed InGaN layer with a very high InN mole fraction, which may be suitable as a base layer for growing an active semiconductor layer for emitting long wavelengths, such as in the wavelength range of 700 nm to 1.6 μm, for example, beyond red, to deep red, and even infrared emission.

[0072] The relaxed InGaN layer provided by the present disclosure can be used as a template and / or support structure for growing optical and / or electrical devices. Very large area wafers are possible, including wafers with a diameter of 150 mm, 200 mm or larger, which is beneficial for the high-volume, low-cost manufacturing of these devices.

[0073] As an example, Figure 8 An LED structure is shown, which is formed by growing an n-type layer 806 (doped with Si or Ge, for example) on the relaxed InGaN surface of an InGaN layer 804, then growing an active region 807 containing InGaN, including an optional p-type electron blocking layer 808 of, for example, GaN, AlGaN or InGaN (or a multi-layer containing these alloys), and then growing a p-type layer 809 such as a p-type GaN or InGaN layer. A highly doped (e.g., Mg-doped) p-type contact layer 810 containing, for example, GaN or InGaN covers the p-type layer 809 and provides an ohmic contact to the device on the p side. As Figure 8As shown, the semiconductor structure below the InGaN layer 804 includes a substrate 801, a GaN seed region 802, and a mask region 803. To the extent that there is a refractive index contrast between these different features, their presence can help improve light extraction from the device. The resulting semiconductor wafer can undergo a series of process steps such as lithography, etching, and semiconductor deposition to form isolated LED regions with suitable electrical contact materials to the n-type and p-type layers. Such contact materials can include those with suitable optical properties (e.g., high light reflectivity and / or transparency). Electrode metallization layers 812a (e.g., NiAg, NiAu, TiAlCrNiAu, etc.) and 812b (e.g., TiAl, TiAlCrNiAu, etc.) can be deposited and patterned to provide electrical connections, e.g., using wirebond. Various transparent conductive oxide (TCO) materials such as indium tin oxide (ITO) (not shown) can be used to facilitate the current spreading layer 811, especially for resistive p-type layers. After fabricating the semiconductor structure, the wafer can be diced to provide individual devices that can be mounted into a suitable package in various ways including epoxy die attach or soldering. For example, wirebond can be used to make electrical contact between the p-type and n-type layers to form a functional device that can ultimately be supplied with power. The device can further include a light-emitting downconversion material, and / or a packaging material such as silicone to provide desired light output characteristics, including white light for lighting applications. The device can be used in lighting systems and / or display applications.

[0074] As Figures 9A to 9D shown, various flip-chip (FC) LED structures are possible, including (a) standard, (b) thin-film flip-chip (TFFC) where the initial growth substrate has been removed but the mask and seed layer portions remain, (c) TFFC with the mask and seed layer portions removed, and (d) TFFC with the mask and seed layer portions removed and the exposed InGaN layer textured (for light extraction purposes) by techniques such as lithography and / or chemically based etching.

[0075] Figures 9A to 9D The semiconductor structure shown includes a substrate 901, a seed region 902, a mask region 903, a relaxed InGaN layer 904 and an initial InGaN growth region 905, an n-type layer 906, an InGaN-containing active region 907, an optional p-type electron blocking layer structure 908, a p-type layer 909, a p-type contact layer 910, a p-side electrode metallization layer 911, and an n-side electrode metallization layer 912. In Figure 9B this, the substrate has been removed, in Figure 9C this, the growth region and the mask region have been removed, and in Figure 9D this, a portion of the relaxed InGaN region 904 has been removed and / or roughened 904a, e.g., to enhance certain optical properties of the device.

[0076] Figure 10 shows a laser diode structure grown on a relaxed InGaN layer. As Figure 10 shown, a relaxed InGaN layer 1004 including an initial InGaN region 1005 covers a mask region 1003, a seed region 1002, and a substrate 1001. A laser diode can be formed by growing an n-type optical confinement ("cladding") layer 1007 on the relaxed InGaN material 1004 and the n-type contact layer 1006, and then growing an InGaN-based active region including a waveguide region comprising waveguide layers 1008 and 1010 on either side of the InGaN-containing active layer 1009, and subsequently growing a p-type optical confinement ("cladding") layer 1011. Layers 1012 and 1013 cover the p-cladding layer 1011. Wafer fabrication for the laser diode is similar to that for LEDs, except that the device is formed as a stripe to form a laser cavity. After cutting and forming etched or cleaved mirrors, high-reflectivity and anti-reflective dielectric coatings can be deposited on the rear and front facets (not shown), respectively. Depending on material selection and application details, the laser diode can be mounted into a suitable package, with the epitaxial side down or the substrate side down. Highly doped p-type contact layer 1014 and n-type contact layer 1006 can be made in electrical contact through electrode metallization layers 1015a and 1015b, respectively, to form a functional device to which electrical power can be supplied. The laser diode is used in lighting systems and / or display applications.

[0077] The relaxed InGaN layers provided by the present disclosure are applicable to a wide range of compound semiconductor devices, which affect the performance of a wide range of system solutions for various applications, including lighting devices and systems ( Figure 11 ) and display devices and systems ( Figure 12 ).

[0078] The target composition of the relaxed InGaN layer can be selected according to the intended device, application, and performance requirements. For conventional InGaN light-emitting diodes lattice-matched to GaN, the best-performing devices are those that emit in the violet wavelength range. At these wavelengths, the strain state of the InGaN quantum wells relative to the GaN substrate layer is about 1% to 2%. The corresponding compositional difference is high enough such that bandgap engineering can provide very high quantum efficiency devices, while the strain state is low enough to allow for relatively thick InGaN quantum well (QW) layers, which are used to reduce carrier density and mitigate non-radiative Auger recombination (also known as "decay"). Applying this acceptable range of strain states to other emission wavelengths, a preferred composition range for the relaxed InGaN substrate layer provided by the present disclosure can be calculated for a wide range of emitters from blue (about 450 nm) to infrared (about 1.3 μm) wavelengths. The preferred ranges are listed in Tables 1 and 2.

[0079] Table 1. Preferred ranges of InN mole fraction in the InGaN(0001) substrate layer for relaxation of light-emitting diodes and laser diodes according to emission color (PWL = peak wavelength in nm, Eg = bandgap in eV, a_base = a lattice parameter in the substrate plane at 300 K in , a_QW = a lattice parameter in the quantum well plane at 300 K in ).

[0080]

[0081] Table 2. Preferred ranges of InN mole fraction in the InGaN(0001) substrate layer for relaxation of light-emitting diodes and laser diodes according to emission color (PWL = peak wavelength in nm, Eg = bandgap in eV, a_base = a lattice parameter in the substrate plane at 300 K in , a_QW = a lattice parameter in the quantum well plane at 300 K in ).

[0082]

[0083] Figure 14A and 14B The figure illustrates the preferred ranges of InN mole fraction and a lattice parameter of the (0001) relaxed InGaN layer used as a template for fabricating light-emitting diodes and laser diodes according to the peak emission wavelength, which are consistent with the parameters given in Tables 1 and 2. For example, as a function of the peak emission wavelength a, the InN mole fraction x of the relaxed In x Ga 1-x N substrate layer should satisfy the condition x min ≤x≤x max , where X min and X max are defined by Equation 1 and Equation 2 respectively as:

[0084] x min =-6.046E-07 λ 2 +1.837E-03 λ - 6.917E-01, (λ≥440 nm) Equation 1

[0085] x max =-6.152E-07 λ 2 +1.847E-03 λ - 6.142E-01, (λ≥440 nm) Equation 2

[0086] Similarly, as a function of the peak emission wavelength λ, the relaxed In x Ga 1-xThe in-plane (“a”) lattice parameter a of the N layer should satisfy the condition a min ≤ a ≤ a max where a min and a max are defined by Equation 3 and Equation 4 respectively as:

[0087] a min = -2.067E-07 λ 2 + 6.366E-04 λ - 2.951, (λ ≥ 440 nm) Equation 3

[0088] a max = -2.190E-07 λ 2 + 6.575E-04 λ - 2.970, (λ ≥ 440 nm) Equation 4

[0089] The methods and semiconductor structures provided by the present disclosure can be applicable to the fabrication of vertical cavity surface emitting lasers (VCSELs). The composition selection of the relaxed InGaN layer for LD or VCSEL is similar to that for LEDs and is shown in Tables 1 and 2.

[0090] Figures 15A to 15F A method for fabricating a relaxed InGaN layer on the edge surface of a GaN seed region on a facet is shown. In this method, a (0001) GaN or AlN seed layer 1502 is provided on a substrate 1501. Figure 15A The substrate 1501, the overlying seed layer 1502, and the overlying mask layer 1503 are shown. The GaN seed layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. Referring to Figures 15A to 15F the process flow shown, the seed layer 1502 can be covered with a mask layer 1503 containing a material that slowly promotes GaN nucleation. Any suitable lithography including nano-lithography and etching techniques (wet or dry or a combination thereof) can be used to pattern and etch the mask layer 1503 into the various patterns described above. Then, the exposed GaN created by etching in the openings in the mask 1504 can be used to nucleate GaN seed material 1506, as Figure 15C and 15D shown, the seed material can grow outwards from the openings in the mask, and by appropriately selecting the growth conditions, a seed region with an edge can be allowed to form, the edge being, for example, a triangular facet with a hexagonal base. For example, the structure can be a hexagonal structure with a hexagonal base and having triangular facets that are {1-101} equivalent planes. Once the facets are as Figure 15DFully formed as shown, the triangular face surface 1507 can be used as a seed surface for at least lateral growth of InGaN, thereby forming a heterojunction that is non-coplanar with the substrate surface. As the thickness of InGaN increases, the small size of the GaN seed surface (facet) and the choice of InGaN composition promote relaxation of the overgrown InGaN while providing a flat, crystallographically equivalent orientation to ensure coherence. As Figure 15E shown, InGaN 1508 grows coherently and relaxes to its relaxed lattice parameter to form a hexagonal structure with triangular facets of relaxed InGaN. These InGaN facets can grow further outwards and eventually combine with adjacent InGaN growth fronts of other planar seed facets. As Figure 15F shown, the coalesced InGaN then grows over the mask layer and the seed region, and growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN layer or template 1509 as the upper region of the structure. This method has the advantage that it does not require etching of the GaN (or InGaN, AlGaN, or AlN) seed material to provide a portion of the seed surface for InGaN nucleation. In addition, when the growth substrate is a group III nitride material, such as a GaN or AlN substrate, this method is very suitable. Therefore, this method is beneficial for the manufacture of LD devices, where a low dislocation density (e.g., less than 5E7 cm for a GaN substrate) is preferred for long-life operation (>10,000 hours). -2 )

[0091] Figures 16A to 16F Another method for fabricating a relaxed InGaN layer on a faceted GaN surface is shown. This method is similar to Figures 15A to 15F the method shown, except that the GaN seed material nucleates on the substrate. In this method, a substrate 1601 suitable for GaN nucleation can be provided, such as sapphire, SiC, sapphire, AlN, or GaN. Referring to Figure 16A , the substrate 1601 can be covered with a mask layer 1602 of a material that slowly promotes GaN nucleation. As Figure 16B shown, the mask layer 1602 is patterned and etched into various patterns 1604 using photolithography such as nano-lithography and etching techniques (wet or dry or a combination thereof). As Figure 16C shown, the exposed substrate 1603 created by etching in the openings of the mask can then be used to nucleate the GaN seed material 1605, which grows outwards from the openings in the mask, and by appropriately selecting the growth conditions, allows the formation of a GaN seed region with edges that are triangular faces and have a hexagonal base. For example, the seed region can be hexagonal and have triangular faces of {1-101} crystallographically equivalent planes. As Figure 16DAs shown, after the seed region is fully formed, the triangular face surface 1607 serves as a seed surface for at least lateral growth of InGaN, thereby forming six heterojunctions in crystallographically equivalent planes that are non-coplanar with the substrate. The small size of the GaN seed surface and the choice of the target composition of the grown InGaN material facilitate the relaxation of the InGaN grown on the seed surface. In addition, each seed surface provides a flat, crystallographically equivalent orientation to ensure the coherence of the entire outgrowing InGaN material. The InGaN grows coherently and relaxes to its relaxed lattice parameter to form facets 1608 of relaxed InGaN as shown in Figure 16E These facets grow further outwards and eventually coalesce with adjacent InGaN growth fronts grown from other seed regions. As shown in Figure 16F The coalesced InGaN then grows over the mask layer, and the growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN region 1609 or template across the substrate. This method has the advantage of not requiring etching of GaN (or AlN) material to provide a seed surface for InGaN nucleation. This method also has the advantage of being able to provide the entire process in a single epitaxial growth process. In addition, this method is very suitable when the growth substrate is a group III nitride material, such as a GaN or AlN substrate.

[0092] Figure 17A Provided by Figures 15A to 15FDetailed cross-sectional view of the structure obtained by the process flow in. As shown in (0001), a sapphire substrate 1701 is used as the main growth substrate for a GaN (or InGaN, AlGaN, or AlN) seed layer 1702, which is characterized by an in-plane a lattice parameter a1. The GaN seed layer 1702 has grown outward between the mask regions 1703 to form a GaN seed region 1702a, which has exposed edges of a crystallographically equivalent flat GaN seed surface. InGaN material has nucleated on the triangular GaN seed surfaces of the GaN seed region, thereby forming a heterojunction 1707 that is not parallel to the main surface of the original growth substrate 1701. The heterojunction 1707 can be formed on a stable crystallographically equivalent facet of the GaN seed region, such as on a {1-101} crystallographically equivalent facet. In order to relax towards a relaxed in-plane a lattice parameter a2 of InGaN in the region 1705 between the GaN seed surfaces, the InGaN material grows at least partially laterally outward. A plane 1708b that is parallel to the main surface of the original growth substrate and bisects the GaN seed material is characterized by different in-plane a lattice parameters at different positions along this plane. In particular, at the center point within the GaN seed region 1702a, it is characterized by the lattice parameter a1, and at the center point 1705 between the GaN seed regions 1702a, the lattice parameter is approximately a2. In the GaN region between these two center points, the in-plane a lattice parameter is greater than a1 and less than a2 because a2 > a1. In a plan view (not shown), the variation of the in-plane a lattice parameter of GaN within the plane 1708b is characterized by a two-dimensional mask pattern that has been applied to the GaN seed layer material (see Figure 5 and 6 ).

[0093] As Figure 17A and 17B shown, the plane 1708b intersects the edge of the seed region 1702a to position the heterojunction 1709b at the interface between the InGaN region 1704 and the seed region. The heterojunction is coplanar with the first crystal plane of the seed region. Any plane such as the plane 1708b that is parallel to the main growth surface and intersects the InGaN region (such as 1708c) and the seed region 1702a intersects the edge of the seed region 1702a to position the heterojunction 1709c at the interface between the InGaN region and the seed region, and this interface is coplanar with the second crystal plane of the seed region. As Figure 17A and 17B shown, the first and second crystal planes are the same. The first and second crystal planes can be crystallographically equivalent crystal planes.

[0094] The InGaN material coalesces on the mask layer 1703 to form a relaxed InGaN layer 1704 having a flat surface 1705c. A plane 1708a within the InGaN layer 1704 that is parallel to the major surface of the original growth substrate and is located near the surface 1705c is characterized by an in-plane a lattice parameter a2 of the InGaN plane. At a center point 1705 between the GaN seed regions, the InGaN lattice parameter is a2, and at the center points within the GaN seed regions, the in-plane a lattice parameter is slightly less than a2. In a plan view (not shown), the variation of the in-plane a lattice parameter within the plane 1708b is characterized by a two-dimensional mask pattern applied to the seed layer material (see Figure 5 and 6 ). The variation of the in-plane a lattice parameter can be detected by measurement techniques such as XRD and RSM and can be resolved on a sub-micron scale. The midpoint along the plane 1708b within the seed region 1702a is denoted as 1708c, while the midpoint between the seed regions 1702a is denoted as 1708d.

[0095] The GaN seed regions 1702a can have in-plane dimensions, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask material 1703 can be, for example, from 0.01 μm to 1 μm. Figure 17B A detailed cross-sectional view of a structure obtained by the process flow in Figures 16A to 16F is provided. This structure is similar to the structure of Figure 17A , and similar elements are identified in the same numerical manner. However, in the structure of Figure 17B , there is no planar starting GaN (or AlN) seed layer 1702. Instead, the GaN (or AlN) seed material nucleates directly on the substrate 1701 in the openings between the mask regions 1703. The substrate can be sapphire, GaN, AlN, silicon, or the like.

[0096] A group-III nitride semiconductor structure can comprise (a) seed regions comprising In x Ga 1-x N (0 ≤ x < 1) and having a wurtzite group-III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite group-III nitride structure and intersecting the seed regions; wherein the intersection of the first plane with a first edge of the seed regions locates an In x Ga 1-x N / In y Ga 1-y N heterojunction, where 0 < y ≤ 1 and y > x; the Inx Ga 1-x N / In y Ga 1-y The GaN heterojunction is coplanar with the first crystal plane of the seed region; (c) Any second plane parallel to the (0001) plane of the wurtzite group III nitride crystal structure and intersecting the second edge of the seed region positions a group III nitride heterojunction, wherein the group III nitride heterojunction is coplanar with the second crystal plane of the seed region; and (d) Covering the (0001) InGaN region of the seed region, wherein the (0001) InGaN region is characterized by an in-plane a lattice parameter greater than such that each of the first crystal plane and the second crystal plane is crystallographically equivalent.

[0097] The first parallel plane can intersect two facets of the seed region. The facets of the seed region are parallel to the crystal planes of the seed region, such as the crystal planes of the wurtzite crystal structure. The facets of the seed region can be crystallographically equivalent facets. The intersection points of the first parallel plane with the facets of the seed region position the heterojunctions, such as In x Ga 1-x N / In y Ga 1-y N, where 0 ≤ x < 1, 0 < y ≤ 1, and y > x.

[0098] Any second plane parallel to the (0001) plane of the wurtzite group III nitride crystal structure and intersecting the seed region positions a group III nitride heterojunction. The second plane can intersect the same facets as the first plane. The second plane can intersect the facets of the seed region that are coplanar with the crystal planes of the seed region. Each of the crystallographic planes can be a crystallographically equivalent plane. Each of the seed regions is characterized by facets parallel to the crystal planes of the seed region, such as the crystal planes of the wurtzite crystal structure. Each of the crystal planes can be a crystallographically equivalent plane. Each of the crystal planes can be crystallographically equivalent to the {10-11} plane. Each of the crystal planes can be crystallographically equivalent to the {1-100} plane. Each of the crystal planes can be crystallographically equivalent to the {11-20} plane. Each of the crystal planes can be the (1-100) plane or the (11-20) plane.

[0099] The InGaN region is located between the seed regions. The InGaN region, or at least a portion of the InGaN region between the seed regions, can be a partially relaxed InGaN region. The InGaN region can include more than one InGaN layer, wherein each of the InGaN layers has a different elemental composition. The (0001) InGaN region can cover the seed regions. The (0001) InGaN region can be a fully relaxed InGaN region and can have a greater than (such as from to ) in-plane a lattice parameter.

[0100] The seed region may have two or more facets, such as 2, 3, 4, 5, or 6 facets. The seed region may have 3 or 6 facets. The seed region may have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. The seed region may have a triangular base or a hexagonal base.

[0101] Each seed region may comprise, for example, GaN and may have, for example, about of a lattice parameter. Each seed region may comprise GaN, and In x Ga 1-x N / In y Ga 1-y N heterojunctions and each of the group III nitride heterojunctions is a GaN-InGaN heterojunction.

[0102] Figures 18 to 20 illustrate various aspects of the present invention. Figure 18A , 18B and 18C show a plan view of a so-called "v-pit" structure that can be formed in the growth of group III nitrides on a basal plane. In particular, for group III nitride materials grown at low temperatures, for example, GaN grown at a temperature of less than 800 °C using MOCVD, the adsorbed atom kinetics cause the semiconductor material not to tend to fill the nearby dislocation cores, resulting in the formation of pits from the stable (10-11) plane having a dislocation core at the center. When growth continues under low temperature conditions, the pits become larger ( Figure 18B ) and collide ( Figure 18C ). As the pits become larger, the total surface area of the exposed (10-11) facets becomes comparable to or even larger than the exposed (0001) surface. The presence of such a large surface area of the (10-11) facets (where each facet is crystallographically equivalent) provides an opportunity to form high-quality, relaxed InGaN (such as GaN) on the (10-11) seed surface, as contemplated by the present invention.

[0103] For example, as Figure 19 shown, GaN can be nucleated on a suitable substrate at low temperature, such as GaN, sapphire, Si, SiC, AlN, etc. Once a reasonably high-quality GaN epitaxial film is obtained, for example, by growing a GaN epitaxial film at an elevated temperature (e.g., greater than 900 °C), the growth conditions can be changed again such that v-pits are formed, for example, by growing GaN at a temperature below 800 °C. Then the growth can be stopped, the GaN structure can be removed from the MOCVD reactor, and a suitable growth mask layer, such as SiO2 or SiN, can be selectively deposited on the (0001) surface rather than on the (10-11) surface xThe dielectric layer. This can be achieved in various ways, such as by using large-angle sputtering or deposition, or by selectively depositing photoresist into the v-grooves, followed by, for example, deposition and lift-off. The GaN structure can then be returned to a reactor, such as an MOCVD or MBE reactor. Then, InGaN can be selectively grown on the exposed GaN seed region material on the (10-11) facet, optionally preceded by depositing a thin GaN layer. The InN mole fraction can be targeted so as to cause large strain and thus relaxation as the thickness of the InGaN layer increases. The growth of InGaN can be allowed to continue and coalesce outwardly on the masked regions, thereby providing a planar, high-quality, relaxed InGaN(0001) region that can be used as a template for device fabrication as described in the present disclosure. The InGaN layer can be grown at a temperature higher than the typical temperature for InGaN / GaN growth, for example, at a temperature greater than 900 °C, which is possible because relaxed InGaN material incorporates In more readily than pseudomorphic InGaN. The increased growth temperature allows filling of the v-groove defects and provides a coalesced planar film. The control of the morphology and compositional uniformity of the relaxed InGaN growth can be facilitated by growing a multilayer structure rather than by using a bulk InGaN layer. For example, 25% of the bulk InGaN layer can be replaced by alternating layers of 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In 0.5 Ga 0.5 N. The layer thickness of each layer can be, for example, from 0.5 nm to 100 nm, such as from 1 nm to 30 nm. Many cycles of such a multilayer structure can be used, for example, 2 to 10 layers, 2 to 100 layers or more than 100 layers.

[0104] In another example, the masking step can be eliminated and the entire process can be completed in situ in the growth chamber. For example, as Figure 20As shown, GaN can nucleate on a suitable substrate, such as GaN, sapphire, Si, AlN, etc. After achieving a reasonably high-quality GaN epitaxial film, for example, by growing at an elevated temperature (e.g., >900 °C), the growth conditions can be changed again such that, for example, v-pits are formed by growing GaN at a temperature below 800 °C. The v-pits can grow outward such that the exposed surface area of the {10-11} equivalent facets is greater than the exposed surface area of the (0001) GaN. Preferably, the exposed surface area of the (10-11) facets is more than twice the exposed surface area of the (0001) GaN, and more preferably more than ten times the exposed surface area of the (0001) GaN. Then, InGaN can be selectively grown on the (10-11) facets as the seed regions. The InN composition can be targeted in order to induce large strain and thus relaxation as the thickness of the InGaN layer increases. The growth of InGaN can be allowed to continue growing outward and coalesce, thereby providing a planar, high-quality, relaxed InGaN (0001) region that can be used as a template for device fabrication, as described in the present disclosure.

[0105] Since the (0001) growth surface area is smaller than the (10-11) growth surface area, the latter growth mode dominates, allowing InGaN to relax and become the dominant growth surface as the film thickness increases. Growing the InGaN layer at a temperature higher than the typical temperature for InGaN / GaN growth is useful, which is possible because the relaxed InGaN material can be incorporated into GaN more easily than the InGaN pseudomorphic. The increased growth temperature allows the v-pit defects to be filled to provide a coalesced planar film. The control of the morphology and compositional uniformity of the relaxed InGaN growth can be facilitated by growing a multi-layer structure rather than by using a bulk InGaN layer. For example, 25% of the bulk InGaN layer can be replaced by alternating layers of 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In 0.5 Ga 0.5 N. The layer thickness of each layer can be, for example, from 0.5 nm to 100 nm, such as from 1 nm to 30 nm. Many cycles of such a multi-layer structure can be used, such as 2 to 10 layers, 2 to 100 layers or more than 100 layers.

[0106] For example, a c-plane (0001) sapphire substrate can be loaded into a MOCVD reactor capable of supplying at least trimethylgallium, trimethylindium, and ammonia. A low-temperature GaN nucleation layer can be provided, followed by a higher-temperature GaN growth, which can include forming three-dimensional islands before coalescing into a two-dimensional (0001) GaN film. This three-dimensional to two-dimensional transition helps to laterally change the direction of the line dislocations and helps to reduce the total line dislocation density at the growth surface, which can be reduced to less than 1E9 cm -2。Finally, a dislocation density of 1E8 cm -2 can be achieved in the planar GaN layer. Next, the growth temperature can be reduced (e.g., less than 800 °C) to form v-pit structures at the dislocation cores, which are characterized by inclined (10-11) planes. These planes can form an angle of approximately 63 degrees with respect to the (0001) growth surface. The thickness of the low-temperature layer controls the v-pit height and increases with growth, such that the total surface area of the exposed {10-11} facets is greater than the surface area of (0001), as shown in Table 3 for this specific example.

[0107] Table 3. Examples of growth structures.

[0108]

[0109] For example, in the case of a dislocation density of 1E8 cm -2 , the target v-pit height can be 0.14 μm or greater.

[0110] After the target surface area ratio between the (10-11) and (0001) materials can be achieved, TMI is flowed into the chamber to grow one or more InGaN layers on the (10-11) seed region and induce strain relaxation. The InGaN layers can be periodically alternated with GaN layers. For example, each InGaN layer can be 0.5 nm to 100 nm thick, e.g., 1 nm to 30 nm thick, and can be sandwiched between GaN layers of similar thickness. To induce strain relaxation, the average composition of the strain relaxation layer should be relatively high. For example, the average InN content can be greater than 5%. After or before starting the strain relaxation, the growth temperature can be increased to help flatten the growth and obtain a flat, uniform, relaxed (0001) InGaN layer for device fabrication.

[0111] It is important to note that while the foregoing discussion is directed to GaN seed regions, InGaN (or AlGaN) seed regions can also be utilized, provided that the material is pseudomorphic to any underlying GaN layer (e.g., GaN nucleation and / or buffer layer). The seed region is the region near the InGaN-GaN (or InGaN-InGaN) heterojunction that ultimately induces relaxation. The seed material below these regions is referred to as the seed material rather than the seed region.

[0112] The relaxed InGaN layers and semiconductor structures provided by the present disclosure can be used to fabricate electronic and optoelectronic devices, including InGaN-based optoelectronic devices such as LEDs and LDs (and VCSELs). The LEDs and LDs provided by the present disclosure that include relaxed InGaN layers can be used in lighting systems and display systems. In particular, for an LED, the device can be formed on a relaxed InGaN base layer on a substrate. The substrate can be thinned by techniques such as grinding, lapping, or etching, and can be cut by ways known in the art (such as sawing, scribing and breaking, or laser scribing and breaking) to provide individual LED chips or dies. The LED chip or die size can be, for example, 250 μm 2 to 10 mm 2 . Then the individual LED chips can be attached to suitable packaging components that provide leads for electrical contact and heat dissipation of the device. Any suitable method can be used to achieve die attachment, such as epoxy or silicone attachment, or solder-based attachment. The chip-to-packaging electrical connection can be accomplished by using bonding wires such as Au or Ag wires to connect the anode and cathode leads in the package to the corresponding contact metallization layers, i.e., electrodes, on the LED chip. In the case of a flip-chip device, electrical contact can be made through an intermediate substrate located between the LED chip and the package. The chip electrodes can be attached to the substrate carrier by means such as solder attachment or gold bump attachment. The substrate carrier can be cut and then installed in the package by any suitable method.

[0113] The desired emission color from the packaged LED device is obtained by fabricating and providing relaxed InGaN-based LEDs having a desired peak emission wavelength. Optionally, multiple such LED chips having different peak emission wavelengths can be included in a single package or combined together in a multi-chip package. For example, a single package can include LED chips that emit red light, green light, and blue light, which can be arranged in a circuit and electrically coupled to a driver circuit inside or outside the package for operating the LEDs. Circuit details and the driver can be selected to allow the different color LEDs to operate individually or together to provide a wide range of overall emission characteristics, including white light emission for lighting applications, or as a backlight for liquid crystal display (LCD) devices such as television displays, computer monitors, mobile phone displays, wearable display devices, etc.

[0114] One or more LED chips can be combined with a luminescent down-converting material to provide a desired emission spectrum. Such luminescent down-converting materials can include phosphors, semiconductor nanoparticles (such as quantum dots), or perovskite materials. Multiple luminescent down-converting materials can be combined together in a single package. The LED chip emission wavelength can be selected to excite the luminescent down-converting material such that the emission from the package is a combination of the direct emission of the LED chip and the emission of the luminescent down-converting material, or the emission can be primarily only the emission of the luminescent down-converting material, where the LED chip light is completely absorbed by the luminescent down-converting material or blocked or filtered from leaving the package. Encapsulated LEDs using luminescent down-converting materials can be used to generate white light, which can be used in lighting applications. Such devices can be electrically coupled to a driver circuit, powered by an external power source such as a power supply or battery power, thermally coupled to a heat sink, and optically coupled to various optical devices or lenses to provide a lighting device such as an LED lamp or LED luminaire.

[0115] LED chips having a smaller size can be fabricated using the present invention. In particular, devices having a size of 1 μm 2 to 50 μm 2 can be fabricated, so-called "micro-LEDs". For micro-LEDs, traditional cutting techniques are not very suitable, and thus other ways of dividing the devices are often used. For example, cutting can be achieved by forming LEDs of the desired size on a substrate, and then bonding the top surface of the LEDs to a carrier (such as a blue tape or a substrate carrier), and then removing the substrate. The individual devices can then be picked and placed into packaging elements or onto a backplane for a micro-LED-based display. As is known in the art, advanced die processing techniques can be used to process micro-LED devices. Specifically, red-emitting, green-emitting, and blue-emitting LEDs based on the present invention can be formed as micro-LEDs, arranged to provide a micro-LED display, and incorporated into systems such as televisions, computer monitors, tablets, mobile phones, wearable devices, etc.

[0116] The LDs provided by the present disclosure incorporating relaxed InGaN layers can also be incorporated into various systems. LD packages are similar to the LED packages described herein, except that ways are provided for thermally managing the higher power density in the LD device and for optically accessing the laser facets. LDs with multiple emission colors can be provided in separate packages or combined into a single package. The LD can be coupled to a luminescent down-converting material to provide a desired emission spectrum. LDs are useful in applications that require very high light density, such as in automotive front lighting systems or projection displays, which can include light modulation devices such as grating optics, micromirror devices, or LCD modulators.

[0117] Figure 11 and 12 Examples of lighting and display systems are shown.

[0118] Aspects of the present invention

[0119] The present invention is further defined by the following aspects.

[0120] Aspect 1. A group-III nitride semiconductor structure comprising an InGaN region, wherein the InGaN region comprises a relaxed (0001) InGaN region; and the relaxed (0001) InGaN region has an in-plane a lattice parameter characterized by periodicity in at least one direction.

[0121] Aspect 2. The semiconductor structure according to Aspect 1, wherein the relaxed InGaN region is characterized by a c-plane growth orientation.

[0122] Aspect 3. The semiconductor structure according to any one of Aspects 1 to 2, wherein the relaxed InGaN region is characterized by an average in-plane a lattice parameter greater than .

[0123] Aspect 4. The semiconductor structure according to any one of Aspects 1 to 3, wherein the relaxed InGaN region has a thickness less than 3 μm.

[0124] Aspect 5. The semiconductor structure according to any one of Aspects 1 to 4, wherein the relaxed InGaN region has a thickness of 20 nm to 1 μm.

[0125] Aspect 6. The semiconductor structure according to any one of Aspects 1 to 5, wherein the relaxed InGaN region has a defect density less than 5E9 cm 2 .

[0126] Aspect 7. The semiconductor structure according to any one of Aspects 1 to 6, wherein the relaxed InGaN region comprises an InGaN-GaN superlattice.

[0127] Aspect 8. The semiconductor structure according to any one of Aspects 1 to 7, further comprising: a plurality of mask regions under a first portion of the relaxed InGaN region; and a plurality of non-mask regions under a second portion of the relaxed InGaN region.

[0128] Aspect 9. The semiconductor structure according to Aspect 8, wherein each of the plurality of mask regions comprises a dielectric material.

[0129] Aspect 10. The semiconductor structure according to Aspect 9, wherein the dielectric material comprises silicon nitride, silicon oxide, or aluminum oxide.

[0130] Aspect 11. The semiconductor structure according to any one of Aspects 8 to 10, wherein each of the plurality of mask regions has a thickness of 20 nm to 2 μm.

[0131] Aspect 12. The semiconductor structure according to any one of Aspects 8 to 10, wherein each of the plurality of mask regions has a thickness less than 2 μm.

[0132] Aspect 13. The semiconductor structure according to any one of Aspects 8 to 12, wherein the maximum in-plane dimension of each of the plurality of non-mask regions is less than 1 μm.

[0133] Aspect 14. The semiconductor structure according to any one of Aspects 8 to 13, further comprising a seed region under each of the plurality of mask regions.

[0134] Aspect 15. The semiconductor structure according to Aspect 14, wherein the seed region comprises GaN, AlN, or AlGaN.

[0135] Aspect 16. The semiconductor structure according to any one of Aspects 14 to 15, wherein the seed region has a thickness of 20 nm to 2 μm.

[0136] Aspect 17. The semiconductor structure according to any one of Aspects 14 to 16, wherein the seed region has a thickness less than 2 μm.

[0137] Aspect 18. The semiconductor structure according to any one of Aspects 14 to 17, wherein the seed region comprises a horizontal interface and a seed interface; the horizontal interface is substantially coplanar with the (0001) InGaN crystal plane; and the seed interface comprises a planar seed portion that is not parallel to the horizontal interface.

[0138] Aspect 19. The semiconductor structure according to Aspect 18, wherein the planar seed portion comprises an a-plane, an m-plane, or a plane between the a-plane and the m-plane.

[0139] Aspect 20. The semiconductor structure according to Aspect 19, wherein the horizontal interface is characterized by a c-plane orientation; and the planar seed portion is not coplanar with the horizontal interface.

[0140] Aspect 21. The semiconductor structure according to any one of Aspects 19 to 20, wherein the planar seed portion comprises a heterojunction.

[0141] Aspect 22. The semiconductor structure according to Aspect 21, wherein the heterojunction is a GaN-InGaN heterojunction.

[0142] Aspect 23. The semiconductor structure according to aspect 22, wherein the seed region comprises GaN; the planar seed portion comprises a GaN / InGaN heterojunction; and the GaN / InGaN heterojunction is substantially parallel to the GaN (1-100) crystal plane, the GaN (11-20) crystal plane, or a crystal plane between the GaN (1-100) crystal plane and the GaN (11-20) crystal plane.

[0143] Aspect 24. The semiconductor structure according to any one of aspects 8 to 23, wherein the plurality of non-mask regions comprise InGaN.

[0144] Aspect 25. The semiconductor structure according to any one of aspects 8 to 24, wherein the plurality of non-mask regions are characterized by a pattern.

[0145] Aspect 26. The semiconductor structure according to any one of aspects 8 to 25, wherein the plurality of non-mask regions are characterized by non-mask region periodicity in at least one dimension.

[0146] Aspect 27. The semiconductor structure according to aspect 26, wherein the periodicity of the in-plane a lattice parameter of the relaxed InGaN region corresponds to the non-mask region periodicity.

[0147] Aspect 28. The semiconductor structure according to any one of aspects 8 to 27, wherein the plurality of non-mask regions are characterized by an array of shapes.

[0148] Aspect 29. The semiconductor structure according to aspect 28, wherein the shape comprises an edge oriented with respect to the crystal plane orientation of InGaN.

[0149] Aspect 30. The semiconductor structure according to aspect 29, wherein the edge is misaligned + / - 1° with respect to the InGaN a plane or the InGaN m plane.

[0150] Aspect 31. The semiconductor structure according to any one of aspects 29 to 30, wherein the edge is oriented parallel to the (1-100) InGaN crystal plane.

[0151] Aspect 32. The semiconductor structure according to any one of aspects 29 to 31, wherein the edge is oriented parallel to the (11-20) InGaN crystal plane.

[0152] Aspect 33. The semiconductor structure according to any one of aspects 29 to 31, wherein the edge orientation is in a direction not parallel to the (1-100) InGaN crystal plane and not parallel to the (11-20) InGaN crystal plane.

[0153] Aspect 34. The semiconductor structure according to any one of aspects 8 to 33, further comprising a substrate under each of the plurality of non-masking regions and under each of the plurality of masking regions.

[0154] Aspect 35. The semiconductor structure according to aspect 34, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon on insulator (SOI), or aluminum nitride.

[0155] Aspect 36. The semiconductor structure according to any one of aspects 8 to 35, further comprising: a substrate under each of the plurality of non-masking regions; and a cavity within the non-masking region and covering a portion of the substrate.

[0156] Aspect 37. The semiconductor structure according to any one of aspects 1 to 36, wherein the III-V semiconductor structure has an area defined by a width and a length; and the area is greater than 0.1 mm 2 。

[0157] Aspect 38. The semiconductor structure according to aspect 37, wherein the periodicity is characterized by a period that is at least 10 times smaller than the width and / or at least 10 times smaller than the length.

[0158] Aspect 39. The semiconductor structure according to any one of aspects 37 to 38, wherein the number of non-masking regions within the area is greater than 10.

[0159] Aspect 40. The semiconductor structure according to any one of aspects 1 to 39, wherein within a period associated with the periodicity, the in-plane a lattice parameter varies between a minimum and a maximum around an average in-plane a lattice parameter of less than 1%.

[0160] Aspect 41. The semiconductor structure according to any one of aspects 1 to 40, further comprising a plurality of seed regions under a first portion of the relaxed InGaN region, wherein each of the plurality of seed regions comprises a plurality of planar seed portions; and each of the plurality of planar seed portions is not a coplanar (0001) InGaN crystal plane.

[0161] Aspect 42. The semiconductor structure according to aspect 41, wherein the planar seed portions form at least a part of a pyramidal shape having a hexagonal base.

[0162] Aspect 43. The semiconductor structure according to any one of aspects 41 to 42, wherein each of the plurality of planar seed portions is characterized by a (1-101) crystal plane.

[0163] Aspect 44. The semiconductor structure according to any one of aspects 41 to 43, further comprising a plurality of mask regions under a second portion of the relaxed InGaN region, wherein each of the plurality of seed portions extends over the plurality of mask regions.

[0164] Aspect 45. The semiconductor structure according to aspect 44, further comprising a seed layer under each of the plurality of mask regions and under each of the plurality of seed regions.

[0165] Aspect 46. The semiconductor structure according to aspect 45, wherein the seed layer and each of the plurality of seed regions are adjacent.

[0166] Aspect 47. The semiconductor structure according to aspect 46, further comprising a substrate under the seed layer.

[0167] Aspect 48. The semiconductor structure according to any one of aspects 44 to 47, further comprising a substrate under each of the plurality of seed regions and under each of the plurality of mask regions.

[0168] Aspect 49. The semiconductor structure according to any one of aspects 1 to 48, wherein in a plane parallel to the InGaN c-plane and passing through the relaxed InGaN region, the in-plane a-plane lattice parameter is greater than

[0169] Aspect 50. The semiconductor structure according to any one of aspects 1 to 49, further comprising a plurality of non-mask regions under a portion of the relaxed InGaN region, wherein the periodicity of the lattice parameter of the relaxed InGaN region corresponds to the periodicity of the plurality of non-mask regions.

[0170] Aspect 51. The semiconductor structure according to any one of aspects 1 to 50, further comprising a plurality of seed regions under a portion of the relaxed InGaN region, wherein each of the plurality of seed regions is characterized by an in-plane a lattice parameter a1; the relaxed InGaN region is characterized by an in-plane a lattice parameter a2; and a2 is greater than a1.

[0171] Aspect 52. The semiconductor structure according to any one of aspects 1 to 51, further comprising a plurality of seed regions under a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is not parallel to the growth plane of the seed regions and the relaxed InGaN region.

[0172] Aspect 53. The semiconductor structure according to any one of Aspects 1 to 52 further includes a plurality of seed regions under a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is perpendicular to the c-plane of the relaxed InGaN region.

[0173] Aspect 54. The semiconductor structure according to any one of Aspects 1 to 53 further includes a plurality of seed regions under a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is parallel to the InGaN a-plane, parallel to the InGaN m-plane, or at an angle between the InGaN a-plane and the InGaN m-plane.

[0174] Aspect 55. The semiconductor structure according to any one of Aspects 1 to 54 further includes a plurality of seed regions under a portion of the relaxed InGaN region, wherein the plurality of seed regions are characterized by periodicity in at least one direction; and the periodicity of the in-plane a lattice parameter of the relaxed InGaN region corresponds to the periodicity of the plurality of seed regions.

[0175] Aspect 56. In the semiconductor structure according to Aspect 55, the periodicity of the in-plane a lattice parameter of the relaxed InGaN region is the same as the periodicity of the plurality of seed regions.

[0176] Aspect 57. The semiconductor structure according to any one of Aspects 1 to 56 further includes an n-doped semiconductor layer, an active semiconductor layer, and a p-doped semiconductor layer covering the relaxed InGaN region.

[0177] Aspect 58. The semiconductor structure according to any one of Aspects 1 to 57 further includes a plurality of semiconductor epitaxial layers covering the relaxed InGaN region.

[0178] Aspect 59. A group-III nitride semiconductor structure includes: an InGaN region, wherein the InGaN region includes a relaxed (0001) InGaN region; a plurality of mask regions under a first portion of the relaxed InGaN region; a plurality of non-mask regions under a second portion of the relaxed InGaN region; and a seed region under each of the mask regions.

[0179] Aspect 60. In the semiconductor structure according to Aspect 59, the seed region includes GaN; and the non-mask regions between the seed regions and under the second portion of the InGaN region include InGaN.

[0180] Aspect 61. The semiconductor structure according to any one of Aspects 59 to 60, wherein in a plane parallel to the c-plane of the relaxed InGaN region and bisecting the seed region, the in-plane a lattice parameter within the seed region is smaller than the in-plane a lattice parameter between the seed region and beneath the second portion of the InGaN region.

[0181] Aspect 62. A semiconductor device comprising a III-V semiconductor structure according to any one of Aspects 1 to 61.

[0182] Aspect 63. The semiconductor device according to Aspect 62, wherein the semiconductor device comprises an optoelectronic device.

[0183] Aspect 64. The semiconductor device according to Aspect 62, wherein the semiconductor device comprises a light-emitting diode or a laser diode.

[0184] Aspect 65. The semiconductor device according to Aspect 64, further comprising a peak emission wavelength.

[0185] Aspect 66. The semiconductor device according to Aspect 65, wherein the peak emission wavelength is between 440 nm and 460 nm, and the in-plane a lattice parameter is between and .

[0186] Aspect 67. The semiconductor device according to Aspect 65, wherein the peak emission wavelength is between 520 nm and 540 nm, and the in-plane a lattice parameter is between and .

[0187] Aspect 68. The semiconductor device according to Aspect 65, wherein the peak emission wavelength is between 580 nm and 600 nm, and the in-plane a lattice parameter is between and .

[0188] Aspect 69. The semiconductor device according to Aspect 65, wherein the peak emission wavelength is between 620 and 640 nm, and the in-plane a lattice parameter is between 3.282 and 3.296 Å.

[0189] Aspect 70. The semiconductor device according to Aspect 65, wherein the peak emission wavelength is between 690 and 710 nm, and the in-plane a lattice parameter is between and .

[0190] Aspect 71. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 840 nm and 870 nm, and the in-plane a lattice parameter is between and .

[0191] Aspect 72. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 940 nm and 980 nm, and the in-plane a lattice parameter is between and ..

[0192] Aspect 73. The semiconductor device according to aspect 65, wherein the peak emission wavelength is between 1300 nm and 1350 nm, and the in-plane a lattice parameter is between and ..

[0193] Aspect 74. An illumination system comprising the semiconductor device according to any one of aspects 62 to 73.

[0194] Aspect 75. A display system comprising the semiconductor device according to any one of aspects 62 to 73.

[0195] Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein. Accordingly, these embodiments are considered illustrative rather than restrictive, and the claims are not limited to the details given herein but may be modified within their scope and equivalents.

Claims

1. A group-III nitride semiconductor structure comprising: (a) A plurality of seed regions comprising a wurtzite group III nitride crystal structure, the wurtzite group III nitride crystal structure comprising In x Ga 1-x N, where 0 ≤ x < 1; (b) A relaxed region covering the seed region and comprising a wurtzite group-III nitride crystal structure, the wurtzite group-III nitride crystal structure comprising In y Ga 1-y N, where 0 < y ≤ 1 and y > x, (c) a first plane parallel to the (0001) plane of the wurtzite group-III nitride crystal structure and intersecting the seed region; wherein, the intersection point of the first plane and the first facet of the seed region locates a first position of a first hetero-junction extending between the relaxed region and the seed region; and The In x Ga 1-x N / In y Ga 1-y N heterojunction is coplanar with the first crystal plane of the seed region; (d) any second plane parallel to the (0001) plane of the wurtzite group-III nitride crystal structure and intersecting a second facet of the seed region locates a second position of a second hetero-junction extending between the relaxed region and the seed region, wherein the second hetero-junction is coplanar with a second crystal plane; and (e) A coalesced relaxed (0001) InGaN region covering the seed region, wherein the coalesced relaxed (0001) InGaN region is characterized by an in-plane a lattice parameter greater than and wherein each of the first crystal plane and the second crystal plane is crystallographically equivalent.

2. The group-III nitride semiconductor structure according to claim 1, wherein the first facet and the second facet are different facets.

3. The group-III nitride semiconductor structure according to claim 1, wherein the first facet and the second facet are the same facet.

4. The group-III nitride semiconductor structure according to claim 1, wherein the first crystal plane and the second crystal plane are different crystal planes.

5. The group-III nitride semiconductor structure according to claim 1, wherein the first crystal plane and the second crystal plane are the same crystal plane.

6. The group-III nitride semiconductor structure according to claim 1, wherein each of the seed regions is characterized by 3 or 6 planar seed facets.

7. The group-III nitride semiconductor structure according to any one of claims 1 and 6, wherein each of the seed regions is characterized by a triangular base or a hexagonal base.

8. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein each of the crystal planes is a crystallographically equivalent {10-11} plane.

9. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein each of the crystal planes is a crystallographically equivalent {1-100} plane.

10. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein each of the crystal planes is a crystallographically equivalent {11-20} plane.

11. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein each of the crystal planes is a (1-100) plane and a (11-20) plane.

12. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein the region at the midpoint between the seed regions is an InGaN region.

13. The group-III nitride semiconductor structure according to claim 12, wherein the InGaN region is at least partially relaxed InGaN seed region.

14. The group-III nitride semiconductor structure according to claim 12, wherein the InGaN region comprises more than one InGaN layer, wherein each InGaN layer has a different elemental content.

15. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein each of the seed regions comprises GaN and has an in-plane a lattice parameter.

16. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein the coalesced relaxed (0001) InGaN region has to in-plane a lattice parameter.

17. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein each seed region contains GaN, and The In x Ga 1-x N / In y Ga 1-y N heterojunction is a GaN-InGaN heterojunction.

18. The group-III nitride semiconductor structure according to any one of claims 1 to 6, wherein the group-III nitride semiconductor structure comprises an array including a plurality of seed regions.

19. The group-III nitride semiconductor structure according to any one of claims 1 to 6, further comprising a substrate and a mask region, wherein the seed regions cover a first portion of the substrate, and the mask region covers a second portion of the substrate.

20. The group-III nitride semiconductor structure according to claim 19, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

21. A semiconductor device comprising the group-III nitride semiconductor structure according to any one of claims 1 to 20.

22. The semiconductor device according to claim 21, wherein the semiconductor device comprises: an n-type group-III nitride layer covering the (0001) InGaN region; a p-type group-III nitride layer covering the (0001) InGaN region; an InGaN active region between the n-type group-III nitride layer and the p-type group-III nitride layer; a first electrical contact metallization layer in electrical contact with the p-type group-III nitride layer; and a second electrical contact metallization layer in electrical contact with the n-type group-III nitride layer.

23. An illumination system or a display system comprising the semiconductor device according to any one of claims 21 to 22.

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