System and method for identifying potential reliability defects in semiconductor devices

Abstract

A system and method for identifying potential reliability defects (LRDs) in semiconductor devices is configured to: perform one or more stress tests on at least some of a plurality of wafers received from one or more in-line sample analysis tools using one or more stress test tools to determine a passed set and a failed set of the plurality of wafers; perform reliability backstrike analysis on at least some wafers in the failed set of the plurality of wafers; analyze the reliability backstrike analysis to determine one or more geographical locations of one or more die failure chains caused by one or more potential reliability defects (LRDs); and perform geographical backstrike analysis on the one or more geographical locations of the one or more die failure chains caused by the LRDs.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 967,964, filed on Jan. 30, 2020, under 35 U.S.C. § 119(e), the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] This disclosure generally relates to semiconductor devices, and more particularly, to systems and methods for identifying potential reliability defects in semiconductor devices. BACKGROUND ART

[0004] The fabrication of semiconductor devices generally may require hundreds or thousands of processing steps to form a working device. During the course of these processing steps, various inspections and / or metrology measurements may be performed to identify defects and / or monitor various parameters regarding the device. Electrical tests may also be performed to verify or evaluate the functionality of the device. However, while some detected defects and metrology errors may be very significant to clearly indicate device failure, smaller variations may cause early reliability failures of the device after the device is exposed to its operating environment. Risk-averse users of semiconductor devices (e.g., automotive, military, aerospace, and medical applications) are beginning to seek failure rates in the parts per billion (PPB) range beyond the current parts per million (PPM) level. As the demand for semiconductor devices in automotive, military, aerospace, and medical applications continues to increase, identifying and controlling reliability defects is critical to meeting the requirements of these industries. Accordingly, it may be desirable to provide systems and methods for reliability defect detection. SUMMARY OF THE INVENTION

[0005] Disclose a system according to one or more embodiments of the present disclosure. In one illustrative embodiment, the system includes a controller communicatively coupled to one or more in-line sample analysis tools and one or more stress test tools. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform one or more stress tests on at least some of a plurality of wafers using the one or more stress test tools to determine a pass set and a fail set of the plurality of wafers. In another illustrative embodiment, the plurality of wafers are received from the one or more in-line sample analysis tools. In another illustrative embodiment, each wafer of the plurality of wafers includes a plurality of layers. In another illustrative embodiment, each layer of the plurality of layers includes a plurality of dies. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a reliability backstrike analysis on at least some of the wafers in the fail set of the plurality of wafers. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to analyze the reliability backstrike analysis to determine one or more geographical locations of one or more die fault chains caused by one or more potential reliability defects (LRDs). In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a geographical backstrike analysis on the one or more geographical locations of the one or more die fault chains caused by the LRDs.

[0006] Disclose a method according to one or more embodiments of the present disclosure. In one illustrative embodiment, the method may include (but is not limited to) performing one or more stress tests on at least some of a plurality of wafers using one or more stress test tools to determine a pass set of the plurality of wafers and a fail set of the plurality of wafers. In another illustrative embodiment, the plurality of wafers are received from one or more in-line sample analysis tools. In another illustrative embodiment, each wafer of the plurality of wafers includes a plurality of layers. In another illustrative embodiment, each layer of the plurality of layers includes a plurality of dies. In another illustrative embodiment, the method may include (but is not limited to) performing a reliability backstrike analysis on at least some of the wafers in the fail set of the plurality of wafers. In another illustrative embodiment, the method may include (but is not limited to) analyzing the reliability backstrike analysis to determine one or more geographical locations of one or more die fault chains caused by one or more potential reliability defects (LRDs). In another illustrative embodiment, the method may include (but is not limited to) performing a geographical backstrike analysis on the one or more geographical locations of the one or more die fault chains caused by the LRDs.

[0007] Disclosed is a system according to one or more embodiments of the present disclosure. In one illustrative embodiment, the system includes one or more online sample analysis tools. In another illustrative embodiment, the system includes one or more stress testing tools. In another illustrative embodiment, the system includes a controller communicatively coupled to the one or more online sample analysis tools and the one or more stress testing tools. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform one or more stress tests on at least some of a plurality of wafers using the one or more stress testing tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers. In another illustrative embodiment, the plurality of wafers are received from the one or more online sample analysis tools. In another illustrative embodiment, each wafer of the plurality of wafers includes a plurality of layers. In another illustrative embodiment, each layer of the plurality of layers includes a plurality of dies. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a reliability backstrike analysis on at least some of the wafers in the failing set of the plurality of wafers. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to analyze the reliability backstrike analysis to determine one or more geographical locations of one or more die fault chains caused by one or more potential reliability defects (LRDs). In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a geographical backstrike analysis on the one or more geographical locations of the one or more die fault chains caused by the LRDs.

[0008] It should be understood that both the foregoing summary and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the summary, serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Those skilled in the art will better understand the numerous advantages of the present disclosure by referring to the accompanying drawings, in which:

[0010] Figure 1A is a block diagram of a system for identifying potential reliability defects (LRDs) according to one or more embodiments of the present disclosure.

[0011] Figure 1B is a block diagram of a system for identifying LRDs according to one or more embodiments of the present disclosure.

[0012] Figure 2A It is a conceptual illustration of the online defect inspection results for multiple layers of a wafer according to one or more embodiments of the present disclosure.

[0013] Figure 2B It is a conceptual illustration of the end-of-line (EOL) classification yield map for a wafer according to one or more embodiments of the present disclosure.

[0014] Figure 2C It is a conceptual illustration of a backstrike analysis for summarizing defects based on the online defect inspection results and the end-of-line (EOL) classification yield map in multiple layers of a wafer according to one or more embodiments of the present disclosure.

[0015] Figure 3 It is a graph showing the total number of defect hits relative to a superposition threshold according to one or more embodiments of the present disclosure.

[0016] Figure 4 It is a flowchart showing the steps performed in a method for identifying LRD according to one or more embodiments of the present disclosure.

[0017] Figure 5A It is a conceptual illustration of a system 500 for identifying LRD according to one or more embodiments of the present disclosure.

[0018] Figure 5B It is an illustration of observed LRD on a wafer according to one or more embodiments of the present disclosure.

[0019] Figure 5C It is a bar chart showing the frequency of observed LRD types on a wafer relative to the types of LRD according to one or more embodiments of the present disclosure.

[0020] Figure 6 It is a flowchart showing the steps performed in a method for using a system and method for identifying LRD according to one or more embodiments of the present disclosure. Detailed Description

[0021] Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. The present disclosure has been specifically shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein are to be considered illustrative rather than restrictive. Those of ordinary skill in the art will readily appreciate that various changes and modifications in form and detail can be made without departing from the spirit and scope of the present disclosure.

[0022] Embodiments of the present disclosure relate to systems and methods for identifying potential reliability defects (LRDs) in semiconductor devices. In particular, embodiments of the present disclosure relate to identifying the source of LRDs during a baseline manufacturing process in a device including, but not limited to, semiconductor devices. Some embodiments of the present disclosure relate to detecting LRDs that may not cause a failure during manufacturing / testing or may not cause an immediate device failure during operation, but may cause an early failure of the device during operation when the device is used in a working environment.

[0023] Defects generated during the manufacturing process can have a wide impact on the performance of field devices. For example, "fatal" defects can cause an immediate device failure, while many minor defects can have little or no impact on the performance of the device throughout its lifetime. However, there can be defect types, referred to herein as potential reliability defects (LRDs) (or reliability defects or potential defects for the purposes of the present disclosure), that may not cause a failure during manufacturing / testing or may not cause an immediate device failure during operation, but may cause an early failure of the device during operation when the device is used in a working environment. LRDs can be generated by defect mechanisms within a manufacturing line operating under normal conditions without offsets. LRDs are not yield-limited and thus cannot or will not be identified by traditional electrical testing and baseline pareto methods.

[0024] It should be noted herein that, for the purposes of the present disclosure, "LRD" can represent a single potential reliability defect or multiple potential reliability defects. Additionally, it should be noted herein that, for the purposes of the present disclosure, the terms "manufacturing process" and "manufacturing process" and corresponding variants thereof (e.g., "manufacturing line" and the like) can be considered equivalent.

[0025] Various strategies can be utilized to monitor or control the reliability of a device based on the manufacturing LRD baseline pareto of a semiconductor device. The various strategies allow the manufacturing process to achieve baseline reliability defect control at the parts per million (PPM) level depending on the chip complexity and size. The new requirements of the semiconductor manufacturing industry (e.g., automotive, military, aerospace, and medical industries) are at the parts per billion (PPB) control level, thus requiring improved systems and methods to identify the source of reliability failures.

[0026] One type of strategy may include performing end-of-line (EOL) reliability testing in combination with pre-burn or other stress testing. Semiconductor device manufacturers currently use EOL electrical reliability testing in combination with pre-burn and other stress testing to generate electrical reliability or (“rel”) Pareto. This methodology is mainly limited by the type of information that can be collected from electrical testing. Thus, the identified failure mechanisms can typically only refer to the electrical characteristics of the failures (e.g., “type 1 failure” or “unit failure”). While this may provide clues to the source, it often does not give the semiconductor manufacturing process enough actionable information about the root cause to effectively guide engineering design improvement studies. In fact, EOL reliability testing performed in combination with pre-burn or other stress testing is mainly used to identify the sources of the inherent defect rate (e.g., relative to extrinsic mechanisms such as defect rate), and to quantify the ratio of reliability (e.g., relative to determining or enabling root cause identification of failures).

[0027] For example, electrical testing of die is performed to evaluate the operation of one or more aspects of the die as data for reliability analysis. Additionally, pre-burn or other stress testing can be performed at any point in the manufacturing process and can include (but is not limited to) electrical wafer sort before pre-burn and final test (e.g., electrical test) or electrical test after pre-burn. Semiconductor devices that fail the electrical test step can be isolated from other passing semiconductor devices. For example, die or wafers can be removed from the supply chain (e.g., discarded) or marked for further testing.

[0028] However, electrical testing alone may not provide enough information to meet strict reliability standards while maintaining cost and throughput goals. For example, since the die is in a near-final state, electrical testing after pre-burn can provide an accurate analysis of the operation of the die, but cannot be mass-produced due to cost, time requirements, or the possibility of introducing long-term reliability issues. As another example, electrical testing during any step of production provides pass / fail information suitable for identifying devices that have exhibited all or part of a failure, but may not be suitable for identifying devices that may fail at a later time (e.g., devices with latent defects). As another example, it is generally impractical or sometimes impossible to use electrical testing to fully characterize each die, resulting in gaps in electrical testing. For example, there may be theoretically possible defects in a particular circuit layout that may not be detectable using electrical testing even with a “perfect” test strategy. It should be noted herein that fully characterizing all aspects of each die may not be cost-effective or practical, such that the selected test strategy may deviate from an otherwise “perfect” or otherwise optimized test strategy. For example, imperfect test coverage can result from (but is not limited to) untestable regions of a particular circuit, analog circuits that are difficult to test (e.g., high-voltage analog circuits), or circuits that require multiple parts of complex simultaneous or sequential power-on. For the purposes of this disclosure, the term “test coverage” is used to broadly describe a metric for evaluating the performance of a test strategy.

[0029] Another type of strategy may include standard online defect baseline Pareto methodology and the corollary that defects causing reliability issues are the same or similar to yield-limiting defects or (“yield”) Pareto. Semiconductor device manufacturers generate an online defect baseline Pareto of yield-limiting defects. By assuming that the source of defect-driven (external) reliability failures is proportional to yield-limiting failures, this information can be used in reliability studies. The drawback of this method is that the potential reliability defect Pareto is almost certainly different from the yield-limiting Pareto in both relative population and priority. By using a reliability Pareto (or rel Pareto) to bias the yield Pareto, this uncertainty can be partially reduced. However, it should be noted that some LRDs are not related to yield-limiting defects. Additionally, it should be noted that many LRDs form only within a relatively small size range of yield-limiting defects, and the size of LRDs is typically device- or technology-specific.

[0030] Another type of strategy may include physical failure analysis (PFA) of field reliability feedback. PFA of field reliability feedback typically requires automotive semiconductor device manufacturers. For example, field reliability returns can come from first-tier component suppliers, assembly at automotive OEMs, or warranty field feedback from end consumers. Field reliability feedback may not provide enough information to generate an actionable Pareto of online reliability sources. For example, statistical significance may be lacking because the number of PPM of failures can be so small that it is difficult to fully understand the baseline reliability Pareto from a few field feedbacks. As another example, field feedback may provide information reflecting reliability issues in the semiconductor manufacturing process when manufacturing failed devices, which may result in a significant delay between manufacturing and observation (e.g., may span several years). Generally speaking, PFA can be expensive, time-consuming, and / or often uncertain or incorrect.

[0031] It should be noted herein that the limitations of the various strategies proposed may include that the root cause of the failure is compromised by the activation process of LRDs or collateral damage from the PFA delay process.

[0032] It should be understood that the labels “potential defect,” “reliability defect,” “potential reliability defect,” or LRD and the like are used herein for illustrative purposes only and should not be construed as restrictive. Additionally, the examples of defect-based reliability determination and control described herein in relation to specific types of defects (e.g., potential defects, reliability defects, LRDs, or the like) are also provided for illustrative purposes only and should not be construed as restrictive. In fact, various methodologies for defect-based reliability prediction can generally be used to identify any type of defect or multiple types of defects, regardless of the label used to describe the defect.

[0033] Now refer to Figures 1A through 6, systems and methods for identifying LRDs in semiconductor devices according to one or more embodiments of the present disclosure are described.

[0034] Figure 1A and 1B is generally a block diagram of a system 100 for identifying LRDs according to one or more embodiments of the present disclosure.

[0035] In one embodiment, the system 100 includes at least one inspection tool 102 (e.g., an in-line sample analysis tool) for detecting defects in one or more layers of the sample 104. The system 100 may generally include any number or type of inspection tools 102. For example, the inspection tool 102 may include an optical inspection tool configured to detect defects based on interrogation of the sample 104 with light from any source (e.g., but not limited to, a laser source, a lamp source, an X-ray source, or a broadband plasma source). As another example, the inspection tool 102 may include a particle beam inspection tool configured to detect defects based on interrogation of the sample with one or more particle beams (e.g., but not limited to, an electron beam, an ion beam, or a neutral particle beam). For example, the inspection tool 102 may include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For the purposes of the present disclosure, it should be noted herein that the at least one inspection tool 102 may be a single inspection tool 102 or may represent a group of inspection tools 102.

[0036] In another embodiment, the sample 104 is a wafer among a plurality of wafers, and each wafer among the plurality of wafers includes a plurality of layers. In another embodiment, each of the plurality of layers includes a plurality of dies. In another embodiment, each of the plurality of dies includes a plurality of regions. For the purposes of the present disclosure, a defect may be regarded as any deviation of a manufactured layer or a pattern in the layer from design characteristics (including but not limited to, physical, mechanical, chemical, or optical properties). In addition, the defect may have any size relative to the die or features on the die. In this way, the defect may be smaller than the die (e.g., on the scale of one or more patterned features) or may be larger than the die (e.g., as part of a wafer-level scratch or pattern). For example, the defect may include a deviation in the thickness or composition of the sample layer before or after patterning. As another example, the defect may include a deviation in the size, shape, orientation, or location of a patterned feature. As another example, the defect may include a flaw associated with a lithography and / or etching step, such as (but not limited to) a bridge (or lack thereof) between adjacent structures, a pit, or a hole. As another example, the defect may include a damaged portion of the sample 104, such as (but not limited to) a scratch or a chip. For example, the severity of the defect (e.g., the length of a scratch, the depth of a pit, the measured magnitude or polarity of the defect, or the like) may be important and should be taken into account. As another example, the defect may include an external particle introduced into the sample 104. Thus, it should be understood that the examples of defects in the present disclosure are provided for illustrative purposes only and should not be construed as restrictive.

[0037] In another embodiment, the system 100 includes at least one metrology tool 106 (e.g., an in-line sample analysis tool) for measuring one or more properties of the sample 104 or one or more layers of the sample 104. For example, the metrology tool 106 may characterize properties such as (but not limited to) layer thickness, layer composition, critical dimension (CD), overlay, or lithography process parameters (e.g., the intensity or dose of illumination during a lithography step). In this regard, the metrology tool 106 may provide information about the manufacture of the sample 104, one or more layers of the sample 104, or one or more dies of the sample 104, which may be related to the probability of manufacturing defects that may lead to reliability issues in the resulting manufactured device. For the purposes of the present disclosure, it should be noted herein that the at least one metrology tool 106 may be a single metrology tool 106 or may represent a group of metrology tools 106.

[0038] In another embodiment, system 100 includes at least one stress test tool 108 for testing the functionality of one or more portions of a fabricated device. System 100 may include any number or type of stress test tools 108 for testing, inspecting, or otherwise characterizing the properties of one or more portions of a fabricated device at any point in the manufacturing cycle. For example, stress test tool 108 may include, but is not limited to, a pre-burn-in electromechanical test tool or a post-burn-in electrical test tool configured to heat a sample 104 (e.g., an oven or other heat source), configured to cool a sample 104 (e.g., a freezer or other cold source), configured to operate a sample 104 at an incorrect voltage (e.g., a power supply), or the like.

[0039] In one embodiment, system 100 includes a controller 110. Controller 110 may include one or more processors 112 configured to execute program instructions maintained on a memory 114 (e.g., a memory medium, a memory device, or the like). Additionally, controller 110 may be communicatively coupled to any of the components of system 100, including but not limited to, inspection tool 102, metrology tool 106, or stress test tool 108.

[0040] In this regard, one or more processors 112 of controller 110 may execute any of the various process steps described throughout this disclosure. For example, one or more processors 112 of controller 110 may be configured to perform one or more of the following: characterize one or more wafers of a plurality of wafers by performing high-sensitivity defect inspection on one or more critical layers; perform electrical wafer sorting (EWS) on the plurality of wafers based on the characterization by performing high-sensitivity defect inspection on the one or more critical layers of the one or more wafers; perform a backstrike analysis on at least some wafers of a set of wafers that fail the EWS; perform one or more stress tests on at least some wafers of a set of wafers that pass the EWS; test at least some of the set of wafers that pass the EWS and are subjected to the one or more stress tests; perform a reliability backstrike analysis on at least some wafers of a set of wafers that pass the EWS and fail the one or more stress tests; analyze a combination of the backstrike analysis and the reliability backstrike analysis to determine the geographical location of a failure caused by LRD; perform a geographical backstrike analysis on the geographical location of the failure caused by LRD; generate one or more defect images including LRD; and / or generate one or more statistical representations of LRD.

[0041] One or more processors 112 of the controller 110 may include any processor or processing element known in the art. For the purposes of this disclosure, the term "processor" or "processing element" may be broadly defined to cover any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGA), or one or more digital signal processors (DSP)). In this sense, one or more processors 112 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in a memory). In one embodiment, one or more processors 112 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a networked computer, or any other computer system configured to execute programs configured to operate the operating system 100 or in conjunction with the system 100, as described throughout this disclosure.

[0042] The memory 114 may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors 112. For example, the memory 114 may include a non-transitory memory medium. As another example, the memory 114 may include (but is not limited to) read only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., disks), magnetic tapes, solid state drives, and the like. It should be further noted that the memory 114 may be housed together with the one or more processors 112 in a common controller housing. In one embodiment, the memory 114 may be remotely located relative to the physical location of the one or more processors 112 and the controller 110. For example, the one or more processors 112 of the controller 110 may access a remote memory (e.g., a server) accessible via a network (e.g., the Internet, an intranet, and the like).

[0043] In one embodiment, the user interface 116 is communicatively coupled to the controller 110. In one embodiment, the user interface 116 may include (but is not limited to) one or more desktop computers, laptop computers, tablet computers, and the like. In another embodiment, the user interface 116 includes a display for displaying data of the system 100 to the user. The display of the user interface 116 may include any display known in the art. For example, the display may include (but is not limited to) a liquid crystal display (LCD), an organic light emitting diode (OLED) based display, or a CRT display. Those skilled in the art will recognize that any display device capable of being integrated with the user interface 116 is suitable for the embodiments in this disclosure. In another embodiment, the user may input selections and / or instructions in response to data displayed to the user via the user input device of the user interface 116.

[0044] In one embodiment, the system 100 includes at least one semiconductor manufacturing tool (semiconductor manufacturing tool / semiconductor fabrication tool) 118. For example, the semiconductor manufacturing tool 118 may include any tool known in the art, including (but not limited to) an etcher, a scanner, a stepper, a cleaner, or the like. The manufacturing process may include manufacturing a plurality of dies distributed across a surface of a sample (e.g., a semiconductor wafer or the like), wherein each die includes a plurality of patterned material layers forming device components. Each patterned layer may be formed by the semiconductor manufacturing tool 118 through a series of steps including material deposition, photolithography, etching, and / or one or more exposure steps (e.g., performed by a scanner, a stepper, or the like) to produce a pattern of interest. For purposes of this disclosure, it should be noted herein that the at least one semiconductor manufacturing tool 118 may be a single semiconductor manufacturing tool 118 or may represent a group of semiconductor manufacturing tools 118.

[0045] In another embodiment, LRDs are identified using any combination of inline sample analysis tools (e.g., inspection tool 102 or metrology tool 106) after one or more processing steps (e.g., lithography, etching, or the like) for the layers of interest in the die. In this regard, defect detection at different stages of the manufacturing process may be referred to as inline defect detection.

[0046] It should be noted herein that for the purpose of this disclosure, Figure 1A The embodiments described in Figure 1B The embodiments described in the examples may be considered as parts of the same system 100 or different systems 100. In addition, it should be noted herein that Figure 1A The components within the system 100 described in Figure 1B The components within the system 100 illustrated in FIG. 1 may communicate directly or may communicate through the controller 110 .

[0047] Figures 2A through 2C is a conceptual illustration of a summary of defects in multiple layers of sample 104 according to one or more embodiments of the present disclosure.

[0048] Selection of Yield Pareto for Defect Limiting Yield-Based Hitback Analysis Methodology and Process Includes Correlating EOL Yield Failures with the Inline Sources Causing the Failures. EOL yield failures lead to PFAs, typically in the form of cross-sectional TEM confirmation of physical defects. This physical location is then overlaid with the inline defect location to correlate with inline learning. This analysis typically provides clear cause-effect relationships for yield failures, but is slow (e.g., on the order of dozens per week) and may be blind to defect modes that are difficult to locate or image in a TEM.

[0049] The selection of the yield Pareto for defect limitation is based on a yield back - strike analysis methodology and process that involves directly overlaying EOL electrical fault locations onto in - line defect data. For example, the selection of logic design methods and analysis tools allows for localizing electrical faults to "chain" locations where faults are likely to occur. Additionally, the selection of techniques allows guiding in - line inspection to potential chain - location faults purely based on the design layout.

[0050] As Figure 2A illustrated, various defects 200 can be detected in one or more layers 202 of the sample 104 (including but not limited to, inspection tool 102 or metrology tool 106), such as, for example, Figure 2A illustrated, three (3) layers 202 as illustrated.

[0051] As Figure 2B illustrated, in addition to the various defects 200 detected in one or more layers 202 of the sample 104, the EOL classified yield map 204 can also provide a reference to one or more locations 206 on the sample 104 that contain one or more die fault chains 208.

[0052] As Figure 2C illustrated, one or more layers 202 containing one or more defects 200 and the EOL classified yield map 204 containing one or more locations 206 with one or more die fault chains 208 can be graphically represented as a back - strike analysis diagram 210 in which all detected defects are merged into a single top - view representation of the sample 104. In the back - strike analysis diagram 210, the possible die fault chains 208 are overlaid with the in - line inspection results, and one or more miss locations 212 and / or one or more hit locations 214 are determined. For example, a miss location 212 is a location where one or more defects 200 do not overlap and / or are not determined to cause one or more die fault chains 208 by statistical probability. As another example, a hit location 214 is a location where one or more defects 200 overlap and / or are determined to have a selected statistical probability of causing one or more die fault chains 208.

[0053] It should be noted herein that one or more miss locations 212 and / or one or more hit locations 214 can be represented by regions from one or more die fault chains 208. For example, the regions can represent a threshold (e.g., in micrometers (μm)) of the percentage chance that a defect within the fault range has of causing a die fault chain. It should be noted herein that one or more miss locations 212 and / or one or more hit locations 214 can include characteristics that can indicate hotspots or spatial patterns where additional defects are likely to occur or that can particularly affect reliability, such as (but not limited to) film or layer thickness, film composition, wafer flatness, wafer topography, resistivity, localized stress measurements, or critical dimension measurements.

[0054] Figure 3 Figure 300 illustrates a graph of the number (count) of comparison hits versus the size of the overlay threshold (in μm) according to one or more embodiments of the present disclosure. In one embodiment, the region 302 representing a small overlay threshold will be near the left side of the graph 300 and may miss defects that cause failures, resulting in an overlay failure. For example, the region 302 may depend on the defect location accuracy (DLA) of the in-line sample analysis tool. In another embodiment, the region 304 representing a large overlay threshold will be near the right side of the graph 300 and may capture defects that do not cause failures, resulting in false positives. In another embodiment, the region 306 representing an optimal overlay threshold will be near the middle of the graph 300. For example, the region 306 may be large enough to account for the in-line sample analysis tool DLA, but small enough such that the statistical probability of a false positive determination for LRD is low or reduced. For example, although not limited, a region having at least one dimension of 5 μm may be selected.

[0055] It should be noted herein that stacking die may allow for graphical comparison of die from different locations on the sample 104 or die across different samples 104. When performed correctly, the backstrike capture rate metric (percentage) may quantify the number of failures associated with in-line defects. For example, for an in-line monitoring process, it may not be uncommon for the backstrike capture rate to increase to above 70%.

[0056] Figure 4 and 5A 5C generally illustrates an LRD methodology or process described according to one or more embodiments of the present disclosure. In one embodiment, the LRD methodology or process includes an LRD baseline Pareto using overlay-based backstrike analysis in combination with high temperature operating life (HTOL) pre-burn.

[0057] Figure 4 A flowchart of a method or process 400 illustrating an LRD methodology or process according to one or more embodiments of the present disclosure. It should be noted herein that the steps of the method or process 400 may be implemented in whole or in part by the Figures 5A through 5C system 500 illustrated in. However, it should be further recognized that since additional or alternative system-level embodiments may implement all or part of the steps of the method or process 400, the method or process 400 is not limited to the Figures 5A through 5C system 500 illustrated in.

[0058] It should be noted herein that any step of the method or process 400 may include any selected die within any selected number of samples 104. For example, the population may include (but is not limited to) selected die from a single sample 104, multiple samples 104 within a lot (e.g., a production lot), or selected samples 104 across multiple lots.

[0059] In step 402, one or more wafers among a plurality of wafers are characterized by performing high-sensitivity defect inspection on one or more critical layers. In one embodiment, block 502 represents at least some of the systems 100 as Figure 1A and 1B illustrated. In this regard, the steps of method or process 400 may be implemented in whole or in part by the systems 100 as Figure 1A and 1B illustrated. In block 502, after many (e.g., dozens, hundreds, thousands) of steps performed by many manufacturing processes, a plurality of wafers are manufactured. For example, manufacturing may be performed by at least one semiconductor manufacturing tool 118.

[0060] After manufacturing, one or more wafers among the plurality of wafers receive high-sensitivity inspection (e.g., broadband plasma inspection or the like) of all critical layers (e.g., between 20 layers and 50 layers) through a complete or nearly complete SEM review.

[0061] For example, depending on the design rules of one or more wafers, one or more wafers may include between 20 and 50 critical layers. A patterned wafer inspection system is selected and incorporated with techniques that utilize design data to define small (e.g., on the order of microns) inspection regions that focus only on critical patterns. These design-based techniques are used to inspect patterns related to potential chain failures to produce inspection results consisting of defects closely related to the yield of the back-end process. This more direct technique allows for faster analysis turnaround, enables higher sampling (hundreds of defects / wafers), and can provide successful causal relationships for defect patterns that are difficult to physically detect at EOL.

[0062] As another example, the SEM review may be 100%. Inspection tool 102 attribute information may be used in combination with on-tool deterministic sorting or machine learning analysis systems to determine critical defect types to identify potential LRDs. This may occur directly on inspection tool 102, metrology tool 106, or in an offline analysis system.

[0063] In another embodiment, additional layers after one or more critical layers are selected to observe morphological changes of critical defects as the wafers continue to be processed (e.g., continue through one or more manufacturing processes). For example, subsequent cleaning may remove defects, deposited films may embed defects, etch-back steps may decorate defects, or the like.

[0064] In step 404, electrical wafer sorting (EWS) is performed on the plurality of wafers based on the characterization by performing high-sensitivity defect inspection on one or more critical layers of one or more wafers. In block 504, the plurality of wafers are subjected to wafer-level testing, where the dies are still physically on each wafer and are packaged. The plurality of wafers are classified into an EWS passed set and an EWS failed set of the plurality of wafers.

[0065] In step 406, a back-drive analysis is performed on at least some of the wafers in the set of wafers that fail the EWS. In block 506, a back-drive analysis is performed on some or all of the wafers in the set of wafers that fail the EWS. The wafer-level testing of the failed set used for multiple wafers is associated with one or more critical layers using superposition. It should be noted herein that the back-drive analysis process is described and depicted in Figures 2A through 2C Sections 2 and 3.

[0066] In step 408, one or more stress tests are performed on at least some of the wafers in the set of wafers that pass the EWS. In block 508, the one or more stress tests are performed on some or all of the wafers in the set of wafers that pass the EWS. For example, some or all of the wafers in the set of wafers that pass the EWS include all die or calibrated die samples having reliability-related defects. For example, a deterministic sort on a tool or a machine learning analysis system can be used to determine which wafers in the set of wafers that pass the EWS. The EWS pass set of multiple wafers is classified into a stress test pass set and a stress test fail set of multiple wafers.

[0067] It should be noted herein that removing the EWS fail set of multiple wafers in step 404 / block 504 before applying one or more stress tests in step 408 / block 508 results in subtracting information unrelated to LRD before applying one or more stress tests. Additionally, it should be noted herein that one or more stress tests may need to be controlled to prevent good wafers from being incorrectly damaged, resulting in false negatives, and need to be controlled to prevent bad wafers from passing, resulting in false positives.

[0068] One or more stress tests include high-acceleration factor pre-burns, such as intensive HTOL pre-burn tests. For example, an HTOL pre-burn test can stress the device at one or more of high temperature, high voltage, and / or dynamic operation for a predefined time period. In another embodiment, one or more stress tests can include burn-in tests. For example, stressing the wafer to activate LRD can include one or more of: heating the wafer in an oven and testing at a high temperature; cooling the wafer and testing at a low temperature (e.g., -20 degrees Celsius (°C)); testing at an inappropriate voltage (e.g., 5 volts (V) instead of 3V), or the like.

[0069] In step 410, a final test is given to at least some of the wafers in a set of wafers that pass EWS and are given one or more stress tests. In block 510, the final test may allow removal of the stress test pass set of a plurality of wafers after one or more stress tests. It should be noted herein that removal of the stress test pass set of a plurality of wafers after one or more stress tests and removal of the EWS fail set of a plurality of wafers in step 404 / block 504 before applying one or more stress tests in step 408 / block 508 allows determination of wafers with LRD.

[0070] In step 412, a reliability backstrike analysis is performed on a set of wafers that pass EWS and fail one or more stress tests. In block 512, a backstrike analysis is performed on some or all of the set of wafers that fail EWS. Superposition is used to correlate wafer-level tests for the fail set of a plurality of wafers with one or more critical layers. It should be noted herein that Figures 2A through 2C The backstrike analysis process is illustrated and described in and 3. The reliability backstrike analysis provides a reference for LRDs that cause reliability failures before LRD activation.

[0071] In step 414, the backstrike analysis and the reliability backstrike analysis are combined and analyzed to determine the geographical location of the failures caused by LRD. In block 514, the analysis includes bitmap analysis and / or blockchain fault analysis. For example, the bitmap analysis and / or the blockchain fault analysis may determine the (x,y) location of a particular LRD or the localization of the failure of the particular LRD. It should be noted herein that the reliability backstrike analysis can be analyzed separately to determine the geographical location of the failures caused by LRD.

[0072] In step 416, a geographical backstrike analysis is performed on the geographical location of the failures caused by LRD. In block 516, the geographical backstrike analysis from the electrical die fault chain to the in-line defect location uses a geometric-based superposition algorithm to combine the point-based in-line defect location with the region-based EOL chain report. For example, the electrical die fault chain location can utilize layer information and (x,y) mapping. The geographical backstrike analysis superimposes the information from the bitmap analysis and / or the blockchain fault analysis in block 514 with the information from the yield management system described in block 518. For example, the yield management system in block 518 may receive result files in block 502 from system 100 and / or components of system 100 (e.g., at least one semiconductor manufacturing tool 118 or the like). It should be noted herein that the wafers used for geographical backstrike analysis should be inspected at all critical process steps of the method or process 400 to avoid loopholes in the potential causal relationships of EOL failures. For example, all defects found should be applied to the analysis, not just the defects classified by subsequent review steps.

[0073] It should be noted herein that asFigures 5A through 5C As described in Figures 5A through 5C , an additional system for recording and storing raw defect information for use during overlay may be included within a system for identifying potential reliability defects.

[0074] In step 418, one or more defect images containing LRDs are generated. Referring now to Figure 5B , a library or set 520 of defect images 520a is generated after the geographic strike analysis of block 516. For example, each defect image 520a contains a representation of an LRD 520b that causes a reliability failure, and the representation provides actionable information about the root cause of the failure before the LRD is activated. It should be noted herein that it is important to depict the LRD 520b within the defect image 520a before the LRD 520b is activated because activation of the LRD has the potential to make it impossible to determine the cause of the failure (e.g., due to partial or complete destruction of the LRD during activation, or the like). For example, it may be determined that a copper cladding layer within a process margin causes the LRD, thereby allowing the engineering team to review and address (e.g., thus providing value to the manufacturing process, system, or team) before the copper cladding layer is damaged when it is activated.

[0075] In step 420, one or more statistical representations of the LRDs are generated. Referring now to Figure 5C , after the geographic strike analysis of block 516, a chart 522 comparing the number of each LRD type to the number of LRD types is generated. In one example, the chart 522 can be used as an illustration or teaching tool for continuous improvement in reducing the number of LRD types and the number of each LRD type, which can drive continuous improvement of the baseline LRD Pareto reduction and thus provide value to an enterprise that adopts a system and method for identifying LRDs in semiconductor devices.

[0076] It should be noted herein that the set 520 of defect images 520a and / or the chart 522 can be displayed on the user interface 116 as described in Figure 1A and 1B and described throughout this disclosure. Additionally, it should be noted herein that the set 520 of defect images 520a and / or the chart 522 can be displayed on a display device separate from the user interface 116.

[0077] It should be noted herein that the system and method for identifying potential reliability defects can address extrinsic (defect) reliability failures, but may not be desired to address intrinsic failures (e.g., time-dependent dielectric breakdown, hot carrier injection, or the like).

[0078] Based on the descriptions provided throughout this disclosure, non-limiting combinations of embodiments of systems and methods for identifying potential reliability defects in semiconductor devices include an in-line defect inspection tool (e.g., broadband plasma or the like) that combines the use of design data to define small (e.g., on the order of microns) inspection regions focused on critical patterns, a yield management analysis system and process, EWS test data, final test data, and stress testing (e.g., HTOL burn-in or the like). This combination of embodiments of systems and methods for identifying LRDs in semiconductor devices provides an accurate picture (e.g., a textual and / or visual picture) of the LRD baseline for a semiconductor manufacturing process, the accurate picture being detailed enough to drive a continuous reduction in reliability defects. For example, systems and methods for identifying potential reliability defects in semiconductor devices can provide in-line SEM images of LRDs prior to activation and without collateral damage caused by PFA delays. As another example, systems and methods for identifying potential reliability defects in semiconductor devices can provide an LRD Pareto based on actual defect mechanisms rather than on resulting electrical properties. As another example, systems and methods for identifying potential reliability defects in semiconductor devices can reduce reliability failures from PPM to PPB levels.

[0079] Figure 6 Illustrate a method or process 600 that utilizes systems and methods for identifying LRDs in accordance with one or more embodiments of the present disclosure. It should be noted herein that the steps of method or process 600 may implement Figure 4 all or part of the method or process 400 illustrated in Figures 5A through 5C and / or all or part of the system 500 illustrated in Figure 4 However, it should be further recognized that because additional or alternative system-level embodiments may implement all or part of the steps of method or process 600, method or process 600 is not limited to Figures 5A through 5C the method or process 400 illustrated in

[0080] In step 602, the systems and methods for identifying LRDs are utilized at selected intervals to determine changes in LRDs within a semiconductor device. In one embodiment, some or all of the steps of method or process 400 may be used in conjunction with system 500. For example, a semiconductor device manufacturer may utilize the systems and methods for identifying LRDs in a semiconductor device at regular or irregular spatial intervals to provide an accurate view of the LRD Pareto that changes over time. It should be noted herein that the intervals may be defined at least in part by the output of one or more semiconductor manufacturing processes, the time between runs of one or more semiconductor manufacturing processes, or the like.

[0081] In step 604, the selected LRD Pareto projects are audited based on the results of the system and method for identifying LRDs. For example, a semiconductor device manufacturer may assign an engineering design team to explore the top 3 Pareto projects (e.g., selected based on frequency of occurrence, unweighted or weighted), and the engineering design team may utilize the system and method for identifying potential reliability defects in semiconductor devices to better understand the process window, process defect rate, tool defect rate, and other impacts on LRD formation.

[0082] In step 606, one or more adjustments are determined for the selected semiconductor manufacturing tool based on the audit of the selected LRD Pareto projects. For example, the engineering design team may determine adjustments including (but not limited to) process defect recipe changes, process defect escalation changes, new process defect changes, new raw material changes, or the like. For example, the changes may be based on the design specifications of the wafer or die on the wafer (e.g., film thickness; size, shape, orientation, or location of the fabricated feature; or the like). The engineering design team may generate a control signal that may be provided (e.g., transmitted via a wired or wireless connection, transmitted via a memory device, or the like) to the selected semiconductor manufacturing tool via a feedforward loop or a feedback loop, received by the selected semiconductor manufacturing tool, and implemented by the selected semiconductor manufacturing tool. However, it should be noted herein that the engineering design team may make the adjustments manually.

[0083] In step 608, additional LRD Pareto projects are audited based on the results of the system and method for identifying LRDs. For example, as the LRD sources associated with the top 3 Pareto projects decrease after adjustment of the semiconductor manufacturing tool, the engineering design team may begin to study the new top 3 Pareto projects (e.g., in one example, projects 4 to 6 of the results of the system and method for identifying LRDs). In this way, the semiconductor device manufacturer experiences an overall improvement in the LRD level over time. The semiconductor device manufacturer may understand new and recurring LRD mechanisms, especially those associated with specific technologies rather than other technologies.

[0084] It should be noted herein that the semiconductor device manufacturer may verify the effectiveness of the changes through design experiments on dedicated wafers after some or all of the steps in method or process 600.

[0085] In this regard, the semiconductor device manufacturer may utilize the results from the system and method for identifying potential reliability defects in semiconductor devices as part of the manufacturing inspection process and / or manufacturing certification to document the commitment to continuous improvement by systematically mapping the sources of potential reliability defect issues with appropriate defect reduction activities, and to monitor the drift of the semiconductor manufacturing process to determine whether the semiconductor manufacturing process is and / or can be a source of potential reliability defects.

[0086] It should be noted herein that the methods or processes 400 and 600 are not limited to the steps and / or sub-steps provided. The methods or processes 400 and 600 may include more or fewer steps and / or sub-steps. The methods or processes 400 and 600 may perform steps and / or sub-steps simultaneously. The methods or processes 400 and 600 may perform steps and / or sub-steps sequentially (including in the provided order or in an order other than the provided order). Accordingly, the foregoing description should not be construed as limiting the scope of the disclosure but merely as illustrative.

[0087] Additional non-limiting examples of how and / or when to utilize systems and methods for identifying potential reliability defects in semiconductor devices are included in U.S. Patent Application No. 17 / 101,856, filed on November 23, 2020, and U.S. Patent No. 10,761,128, issued on September 1, 2020, the entire disclosures of which are incorporated herein by reference. For example, systems and methods for identifying potential reliability defects in semiconductor devices may provide an understanding of how and / or when to apply parts average testing (PAT), in-line parts average testing (I-PAT), and geographical parts average testing (G-PAT) to screen and monitor wafers, as described in the references incorporated above.

[0088] In this regard, advantages of the present disclosure include performing a backstrike on final test data after a burn-in HTOL pre-burn test or other stress test designed to activate LRDs to exhibit as failures. Advantages of the present disclosure also include analysis software that performs superposition of test and scan chain data and removes yield-limiting failures from the data set. Advantages of the present disclosure also include the ability to view defect progression by capturing in-line SEM images at multiple levels.

[0089] The subject matter described herein sometimes illustrates different components contained within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and in fact, many other architectures may be implemented to achieve the same functionality. In a conceptual sense, any arrangement of components that achieves the same functionality is effectively "associated" such that the desired functionality is achieved. Accordingly, any two components combined herein to achieve a particular functionality may be considered "associated" with each other such that the desired functionality is achieved regardless of the architecture or intermediate components. Similarly, any two components so associated may also be considered "connected" or "coupled" to each other to achieve the desired functionality, and any two components capable of being so associated may also be considered "couplable" to each other to achieve the desired functionality. Particular examples of couplable include (but are not limited to) components that physically interact and / or physically interact, and / or components that wirelessly interact and / or wirelessly interact, and / or components that logically interact and / or logically interact.

[0090] It is believed that the present disclosure and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes may be made in the form, construction, and arrangement of the components without departing from the disclosed subject matter or sacrificing all of its material advantages. The described form is merely illustrative, and the appended claims are intended to cover and embrace such changes. Further, it is to be understood that the invention is defined by the appended claims.

Claims

1. A system, comprising: A controller communicatively coupled to one or more in-line sample analysis tools and one or more stress test tools, the controller including one or more processors configured to execute program instructions to cause the one or more processors to: Characterize at least some of a plurality of wafers; Based on the characterization, perform electrical wafer sorting (EWS) on the plurality of wafers to determine an EWS pass set of the plurality of wafers and an EWS fail set of the plurality of wafers; Perform one or more stress tests on at least some of the EWS pass set of the plurality of wafers with the one or more stress test tools to determine a pass set of the plurality of wafers and a fail set of the plurality of wafers, the plurality of wafers being received from the one or more in-line sample analysis tools, each wafer of the plurality of wafers including a plurality of layers, each layer of the plurality of layers including a plurality of dies; Perform reliability backstrike analysis on at least some wafers in the fail set of the plurality of wafers; Analyze the reliability backstrike analysis to determine one or more geographical locations of one or more die fault chains caused by one or more latent reliability defects (LRDs); And Perform geographical backstrike analysis on the one or more geographical locations of the one or more die fault chains caused by the LRDs; Perform yield backstrike analysis on at least some wafers in the EWS fail set of the plurality of wafers; And Analyze a combination of the yield backstrike analysis and the reliability backstrike analysis to determine the one or more geographical locations of the one or more die fault chains caused by the LRDs.

2. The system of claim 1, wherein at least one of the reliability backstrike analysis, the geographical backstrike analysis, or the yield backstrike analysis generates a backstrike analysis map by overlaying an end-of-line (EOL) classification yield map on a combined image set representing the plurality of layers of the wafers in the plurality of wafers, wherein the backstrike analysis map includes an overlay threshold, and wherein the overlay threshold is selected to account for in-line sample analysis tools and reduce the statistical probability of LRD false positive determinations.

3. The system of claim 2, wherein the EOL classification yield map includes the one or more die fault chains, wherein the backstrike analysis map includes one or more defects, and wherein a wafer in the plurality of wafers fails the EWS when at least some of the one or more defects are determined to have a selected statistical probability of causing at least some of the one or more die fault chains.

4. The system of claim 1, wherein the combination of the yield backstrike analysis and the reliability backstrike analysis is analyzed using at least one of bitmap analysis or blockchain fault analysis.

5. The system of claim 1, the controller including the one or more processors configured to execute the program instructions to cause the one or more processors to perform at least one of the following: Generate one or more defect images including the LRD; or Generate one or more statistical representations of the LRDs.

6. The system according to claim 5, further comprising: One or more user interfaces communicatively coupled to the controller, the one or more user interfaces being configured to display at least one of the one or more defect images including the LRDs or the one or more statistical representations including the LRDs.

7. The system according to claim 5, wherein the controller includes the one or more processors, the one or more processors being configured to execute the program instructions, thereby causing the one or more processors to: Determine one or more adjustments for one or more semiconductor manufacturing tools, the one or more adjustments being determined based on a review of at least one of the one or more defect images including the LRDs or the one or more statistical representations including the LRDs.

8. The system according to claim 7, wherein the controller includes the one or more processors, the one or more processors being configured to execute the program instructions, thereby causing the one or more processors to: Generate one or more control signals based on the determined one or more adjustments.

9. The system according to claim 8, wherein the controller includes the one or more processors, the one or more processors being configured to execute the program instructions, thereby causing the one or more processors to: Provide the one or more control signals to the one or more semiconductor manufacturing tools via at least one of a feedforward or feedback loop.

10. The system according to claim 1, wherein the one or more in-line sample analysis tools include: At least one of an inspection tool or a metrology tool.

11. The system according to claim 1, wherein the one or more stress test tools include at least one of a pre-burn-in electrical test tool or a post-burn-in electrical test tool.

12. The system according to claim 11, wherein the one or more stress test tools are configured to perform at least one of the following: heating at least some of the plurality of wafers, cooling at least some of the plurality of wafers, or operating at least some of the plurality of wafers at an incorrect voltage.

13. A method, comprising: Characterize at least some of the plurality of wafers received from one or more in-line sample analysis tools; Based on the characterization, perform electrical wafer sorting (EWS) on the plurality of wafers to determine an EWS pass set of the plurality of wafers and an EWS fail set of the plurality of wafers; Perform one or more stress tests on at least some of the EWS pass set of the plurality of wafers with one or more stress test tools to determine a pass set of the plurality of wafers and a fail set of the plurality of wafers, the plurality of wafers being received from one or more in-line sample analysis tools, each wafer of the plurality of wafers including a plurality of layers, and each layer of the plurality of layers including a plurality of die; Perform a reliability backstrike analysis on at least some wafers in the fail set of the plurality of wafers; Analyze the reliability strike analysis to determine one or more geographical locations of one or more die fault chains caused by one or more latent reliability defects (LRDs); and Perform a geographical strike analysis on the one or more geographical locations of the one or more die fault chains caused by the LRDs; Perform a yield strike analysis on at least some of the wafers in the set of wafers that failed the EWS of the plurality of wafers; and Analyze the combination of the yield strike analysis and the reliability strike analysis to determine the one or more geographical locations of the one or more die fault chains caused by the LRDs.

14. The method according to claim 13, wherein at least one of the reliability strike analysis, the geographical strike analysis, or the yield strike analysis generates a strike analysis map by overlaying an end-of-line (EOL) classified yield map on a combined image set representing multiple layers of wafers in the plurality of wafers, wherein the strike analysis map includes an overlay threshold, and wherein the overlay threshold is selected to account for in-line sample analysis tools and reduce the statistical probability of LRD false positive determination.

15. The method according to claim 14, wherein the EOL classified yield map includes the one or more die fault chains, wherein the strike analysis map includes one or more defects, and wherein a wafer in the plurality of wafers fails the EWS when at least some of the one or more defects are determined to have a selected statistical probability of causing at least some of the one or more die fault chains.

16. The method according to claim 13, wherein the combination of the yield strike analysis and the reliability strike analysis is analyzed using at least one of bitmap analysis or blockchain fault analysis.

17. The method according to claim 13, further comprising at least one of the following: Generating one or more defect images including the LRD; or Generating one or more statistical representations including the LRD.

18. The method according to claim 17, wherein at least one of the one or more defect images including the LRD or the one or more statistical representations including the LRD is displayed on one or more user interfaces.

19. The method according to claim 17, further comprising: Determining one or more adjustments for one or more semiconductor manufacturing tools, the one or more adjustments being determined based on a review of at least one of the one or more defect images including the LRD or the one or more statistical representations including the LRD.

20. The method according to claim 19, further comprising: Generating one or more control signals based on the determined one or more adjustments.

21. The method according to claim 20, further comprising: Providing the one or more control signals to the one or more semiconductor manufacturing tools via at least one of a feedforward or feedback loop.

22. The method according to claim 13, wherein the one or more in-line sample analysis tools include: At least one of an inspection tool or a metrology tool.

23. The method according to claim 13, wherein the one or more stress test tools include at least one of a pre-burn-in electrical test tool or a post-burn-in electrical test tool.

24. The method according to claim 23, wherein the one or more stress test tools are configured to perform at least one of: heating at least some of the plurality of wafers, cooling at least some of the plurality of wafers, or operating at least some of the plurality of wafers at an incorrect voltage.

25. A system, comprising: one or more in-line sample analysis tools; one or more stress test tools; and a controller communicatively coupled to the one or more in-line sample analysis tools and the one or more stress test tools, the controller including one or more processors configured to execute program instructions that cause the one or more processors to: characterize at least some of a plurality of wafers; perform electrical wafer sorting (EWS) on the plurality of wafers based on the characterization to determine an EWS pass set of the plurality of wafers and an EWS fail set of the plurality of wafers perform one or more stress tests on at least some of the EWS pass set of the plurality of wafers with the one or more stress test tools to determine a pass set of the plurality of wafers and a fail set of the plurality of wafers, the plurality of wafers being received from the one or more in-line sample analysis tools, each wafer of the plurality of wafers including a plurality of layers, each layer of the plurality of layers including a plurality of dies; perform a reliability backstrike analysis on at least some wafers in the fail set of the plurality of wafers; analyze the reliability backstrike analysis to determine one or more geographical locations of one or more die fault chains caused by one or more potential reliability defects (LRDs); and perform a geographical backstrike analysis on the one or more geographical locations of the one or more die fault chains caused by the LRDs; perform a yield backstrike analysis on at least some wafers in the EWS fail set of the plurality of wafers; and analyze a combination of the yield backstrike analysis and the reliability backstrike analysis to determine the one or more geographical locations of the one or more die fault chains caused by the LRDs.

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