Anti-interface tilt joint assembly and method of forming same

Abstract

A first bonding unit is provided that includes a first substrate, a first passivation dielectric layer, and a first bonding pad. A second bonding unit is provided that includes a second substrate, a second passivation dielectric layer, and a second bonding pad that includes a bonding post structure. A portion of solder material is formed on a physically exposed surface of the first bonding pad. The second bonding unit is attached to the first bonding unit by bonding at least one of the bonding post structures to a corresponding portion of solder material.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor devices, and more particularly to a bonding assembly configured to limit interface tilt to achieve enhanced electrical connections between bonding units and a method thereof. Background Technology

[0002] Three-dimensional memory devices can be bonded to logic dies that include peripheral circuitry. Tilting at the interface between the bonded dies can cause a break between some of the mating bonding pads of the respective bonded dies, resulting in an open circuit. Summary of the Invention

[0003] According to one aspect of this disclosure, a bonding assembly includes: a first bonding unit comprising: a first substrate; a first metal interconnect structure embedded in a first dielectric material layer; a first passivation dielectric layer having a first proximal surface and a first distal surface, the first proximal surface contacting one of the first dielectric material layers, the first distal surface being spaced from the first proximal surface by the thickness of the first passivation dielectric layer; a first bonding pad located within and laterally surrounded by a corresponding opening in the first passivation dielectric layer, wherein the distal surface of the first bonding pad is recessed relative to the first distal surface of the first passivation dielectric layer; and a solder material portion located within the first passivation dielectric layer. The second bonding unit comprises: a second substrate; a second metal interconnect structure embedded in a second dielectric layer; a second passivated dielectric layer having a second proximal surface and a second distal surface, the second proximal surface contacting one of the second dielectric layers, the second distal surface being spaced from the second proximal surface by the thickness of the second passivated dielectric layer; and a second bonding pad located within and laterally surrounded by a corresponding opening in the second passivated dielectric layer, wherein each of the second bonding pads includes a bonding pillar structure protruding beyond a horizontal plane including the second distal surface. The first subgroup of the bonding pillar structure directly contacts the first subgroup of the first bonding pads, and the second subgroup of the bonding pillar structure does not directly contact any of the first bonding pads, such that the corresponding solder material portions in the second subgroup of the solder material portions are located between each bonding pillar structure in the second subgroup of the bonding pillar structure and each corresponding first bonding pad in the second subgroup of the first bonding pads, and such that the corresponding solder material portions in the second subgroup of the solder material portions provide electrical contact between each bonding pillar structure in the second subgroup of the bonding pillar structure and each corresponding first bonding pad in the second subgroup of the first bonding pads.

[0004] According to another aspect of this disclosure, a method of forming a bonding assembly includes: providing a first bonding unit, wherein the first bonding unit includes: a first substrate; a first metal interconnect structure embedded in a first dielectric material layer; a first passivation dielectric layer having a first proximal surface and a first distal surface, the first proximal surface contacting one of the first dielectric material layers, the first distal surface and the first proximal surface being spaced apart by the thickness of the first passivation dielectric layer; and a first bonding pad located within and laterally surrounded by a corresponding opening in the first passivation dielectric layer, wherein the distal surface of the first bonding pad is recessed relative to the first distal surface of the first passivation dielectric layer; forming a solder material portion on a physically exposed surface of the first bonding pad; and providing a second bonding unit, wherein the second bonding unit includes: a first... Two substrates; a second metal interconnect structure embedded in a second dielectric material layer; a second passivated dielectric layer having a second proximal surface and a second distal surface, the second proximal surface contacting one of the second dielectric material layers, the second distal surface being spaced from the second proximal surface by the thickness of the second passivated dielectric layer; and second bonding pads located within and laterally surrounded by corresponding openings in the second passivated dielectric layer, wherein each of the second bonding pads includes a bonding pillar structure protruding beyond a horizontal plane including the second distal surface; and solder material portion reflow when the first bonding unit and the second bonding unit are pressed together, such that at least a first subgroup of the bonding pillar structure expels a first subgroup of solder material portion and directly contacts a first subgroup of the first bonding pad. Attached Figure Description

[0005] Figures 1A to 1D This is a sequential vertical cross-sectional view of a first configuration of a first joining unit during manufacturing, according to an embodiment of the present disclosure.

[0006] Figures 2A to 2C This is a sequential vertical cross-sectional view of a second configuration of a first joining unit during manufacturing, according to an embodiment of the present disclosure.

[0007] Figures 3A to 3C This is a sequential vertical cross-sectional view of the third configuration of the first joining unit during manufacturing, according to an embodiment of the present disclosure.

[0008] Figures 4A to 4D This is a sequential vertical cross-sectional view of the fourth configuration of the first joining unit during manufacturing, according to an embodiment of the present disclosure.

[0009] Figures 5A to 5F This is a sequential vertical cross-sectional view of the second joining unit during manufacturing according to an embodiment of the present disclosure.

[0010] Figure 6A This is a first configuration of the joining component according to an embodiment of the present disclosure.

[0011] Figure 6B This is a second configuration of the joining component according to an embodiment of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure relate to a disconnected bonding assembly configured to limit the connection between a pair of mating bonding pads that are inclined relative to each other at the bonding interface of a bonding die, and methods of forming the same thereof, aspects of which are described in detail below.

[0013] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0014] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0015] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0016] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are joined together, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands simultaneously as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0017] Figures 1A to 1D This is a sequential vertical cross-sectional view of a first configuration of a first joining unit during manufacturing, according to an embodiment of this disclosure. Reference Figure 1A The first bonding unit may include a first substrate 108, an optional first semiconductor device 120 formed on the top surface of the first substrate 108, a first metal interconnect structure 140 embedded within a first dielectric material layer 130, and a first passivation dielectric layer 150. In one embodiment, the first bonding unit may include a first semiconductor die, which may be, for example, a memory die or a logic die. In another embodiment, the first bonding unit may include an interposer, which may be a ceramic interposer or a laminated interposer. When the first bonding unit includes an interposer, the first semiconductor device 120 may be omitted.

[0018] Generally, the first bonding unit may be disposed within a first wafer including a first semiconductor die array, or may be provided as a separate unit such as an interposer. When the first bonding unit is disposed within the first wafer, the first wafer may include a semiconductor die array, and the first semiconductor die may be one of the semiconductor dies within the semiconductor die array. When the first bonding unit is disposed within the first wafer, the first wafer may include a first semiconductor wafer, such as a commercially available single-crystal silicon wafer.

[0019] When the first bonding unit includes a first semiconductor die, the first semiconductor device 120 may include any type of semiconductor device known in the art. In an illustrative example, the first semiconductor die may include a memory die comprising a three-dimensional array of memory elements, such as a vertical NAND memory array. Alternatively, the first semiconductor device may include a logic die. When the second bonding unit, to be used subsequently, includes a memory die, the first bonding unit may include a logic die comprising peripheral circuitry configured to control the operation of memory elements within the memory die.

[0020] The first metal interconnect structure 140 may include metal via structures and metal line structures configured to provide electrical interconnects between and / or to respective nodes (e.g., source, drain, and / or gate) of the first semiconductor device 120. The first metal interconnect structure 140 may include conductive alloys and / or compounds of tungsten, copper, cobalt, tantalum, titanium, molybdenum, ruthenium, and / or the like. The total number of layers of metal lines within the first metal interconnect structure 140 may range from 1 to 20, such as 2 to 10. The total number of layers of metal via structures within the first metal interconnect structure 140 may range from 1 to 20, such as 2 to 10. In one embodiment, the first metal interconnect structure 140 may include an optional first distal metal interconnect structure 148, which is the first metal interconnect structure 140 furthest from the first substrate 108. In one embodiment, the first distal metal interconnect structure 148 may include metal pads or metal lines. Alternatively, the first distal metal interconnect structure 148 may be omitted.

[0021] When the first bonding unit comprises a semiconductor die, the first dielectric layer 130 may comprise at least one interlayer dielectric (ILD) material, which may include, for example, undoped silicate glass, doped silicate glass, organosilicon glass, silicon carbide nitride, silicon oxynitride, and / or silicon nitride. When the first bonding unit comprises an interposer, the first dielectric layer 130 may comprise at least one laminateable polymer material, or may comprise at least one ceramic material. The total thickness of the first dielectric layer 130 may range from 500 nm to 10 micrometers, but smaller and larger thicknesses are also possible.

[0022] The first passivation dielectric layer 150 includes a dielectric material that prevents the diffusion of hydrogen, moisture, and / or metallic contaminants. For example, the first passivation dielectric layer 150 may include at least one of a silicon nitride layer, a silicon nitride carbide layer, or a polymer material layer (such as a polyimide layer) and / or consist substantially of the latter. The total thickness of the first passivation dielectric layer 150 may range from 500 nm to 5 micrometers, but smaller and larger thicknesses are also possible. The first passivation dielectric layer 150 may be deposited as a blanket-cover passivation dielectric layer over the top surface (i.e., the distal surface) of the first dielectric material layer 130. As used herein, a blanket-cover layer refers to an unpatterned material layer.

[0023] refer to Figure 1B An array of openings 152 can be formed through the blanket-covered passivated dielectric layer, such that the top surface of the corresponding first distal metal interconnect structure 148 is physically exposed below the openings through the blanket-covered passivated dielectric layer. The continuous remaining portion of the blanket-covered passivated dielectric layer after the formation of the array of openings 152 constitutes the first passivated dielectric layer 150.

[0024] In one embodiment, the openings 152 in the first passivation dielectric layer 150 may be arranged as a periodic two-dimensional array of openings. In one embodiment, the periodic two-dimensional array of openings 152 may comprise a rectangular two-dimensional array of openings having a first spacing along a first horizontal direction and a second spacing along a second horizontal direction perpendicular to the first horizontal direction. In one embodiment, each of the first and second spacings may be in the range of 2 micrometers to 30 micrometers, such as 5 micrometers to 10 micrometers, but smaller and larger spacings may also be used. The edges of adjacent openings 152 may be spaced apart by a distance in the range of 1 micrometer to 5 micrometers, and the width (e.g., diameter) of each opening 152 may be in the range of 2 micrometers to 10 micrometers, such as 3 micrometers to 5 micrometers.

[0025] refer to Figure 1C An electroplating or electroless plating process can be performed to selectively deposit metal portions directly within openings in the first passivation dielectric layer 150 onto the physically exposed surface of the first distal metal interconnect structure 148. The metal portions constitute the first bonding pad 160. The metal portions may include at least one metallic material that can be deposited by electroplating or electroless plating. In one embodiment, the first bonding pad 160 may include metallic materials such as copper, silver, gold, nickel, brass, palladium, and / or cobalt-tungsten-phosphorus alloys. In one embodiment, the thickness of the first bonding pad 160 may be less than the thickness of the first passivation dielectric layer 150. For example, the thickness of the first bonding pad 160 may be in the range of 300 nm to 4 micrometers, but smaller and larger thicknesses may also be used.

[0026] refer to Figure 1DAn array of solder material portions 190 may be formed on the physically exposed surface of the first bonding pad 160. The solder material portions 190 may be tin-based and may include an atomic percentage of tin greater than 50%. The solder material portions 190 may consist of 99 to 100 atomic percentages of tin plus unavoidable impurities, or may comprise tin alloys containing 75% to 99 atomic percentages of tin plus the remainder of one or more other metals (such as indium, copper, silver, nickel, bismuth, and / or lead or their oxides). In one embodiment, the array of solder material portions 190 may be formed by directly immersing deposited solder material onto the surface of the first bonding pad 160 using an immersion bath. For example, an exemplary process for immersion-deposited solder material is described in Kovac et al., “Immersion tin: Its chemistry, metallurgy, and application in electronic packaging technology,” IBM Journal of Research and Development 28.6 (1984), pp. 726–734. The thickness of the solder material portion 190 can be selected such that the top surface of the solder material portion 190 (i.e., the distal surface away from the first substrate 108) lies below a horizontal plane including the top surface (i.e., the distal surface) of the first passivation dielectric layer 150. For example, the thickness of the solder material portion 190 can be from 100 nm to 1 micrometer.

[0027] Generally, the first bonding unit 100 includes: a first substrate 108; a first metal interconnect structure 140 embedded in a first dielectric material layer 130; a first passivation dielectric layer 150 having a first proximal surface and a first distal surface, the first proximal surface contacting one of the first dielectric material layers 130, the first distal surface and the first proximal surface being separated by the thickness of the first passivation dielectric layer 150; and a first bonding pad 160 located within a corresponding opening in the first passivation dielectric layer 150 and laterally surrounded by the corresponding opening.

[0028] The distal surface of the first bonding pad 160 may be recessed relative to the first distal surface of the first passivation dielectric layer 150. An array of solder material portions 190 may be located on the physically exposed surface of the first bonding pad 160. Each of the first bonding pads 160 may have a sidewall contacting the first passivation dielectric layer 150. In one embodiment, the entire volume of the array of solder material portions 190 may lie between a horizontal plane including the interface between the array of solder material portions 190 and the first bonding pad 160 and a horizontal plane including the first distal surface of the first passivation dielectric layer 150.

[0029] Figures 2A to 2C This is a sequential vertical cross-sectional view of a second configuration of the first joining unit during manufacturing, according to an embodiment of this disclosure. Reference Figure 2A The second configuration of the first joining unit can be with Figure 1C The first configuration of the first joining unit shown is the same.

[0030] refer to Figure 2B Solder material layer 190L can be formed by selective or non-selective deposition processes. Solder material layer 190L may include the aforementioned tin-based solder material. Solder material layer 190L can be deposited by electroplating or physical vapor deposition. In one embodiment, solder material layer 190L can be deposited by a non-selective deposition process (such as physical vapor deposition). Solder material layer 190L may have a top surface that extends continuously over the first passivation dielectric layer 150.

[0031] refer to Figure 2C Solder material can be planarized by removing a portion of the solder material layer 190L from above a horizontal plane including the first distal surface of the first passivation dielectric layer 150. For example, the solder material can be removed from above the horizontal plane including the first distal surface of the first passivation dielectric layer 150 by a chemical mechanical planarization (i.e., chemical mechanical polishing, CMP) process or a recess etching process. In one embodiment, the solder material layer 190L can be isotropically recessed, for example, by a dry etching process or a wet etching process. In one embodiment, the solder material can be vertically recessed within an opening 152 in the first passivation dielectric layer 150. An array of solder material portions 190 can be formed. In one embodiment, the top surface of the solder material portions 190 can be located below the horizontal plane including the first distal surface of the first passivation dielectric layer 150.

[0032] Figures 3A to 3C This is a sequential vertical cross-sectional view of the third configuration of the first joining unit during manufacturing, according to an embodiment of this disclosure. Reference Figure 3A This can be achieved by extending the deposition process that forms the first bonding pad 160. Figure 1CThe first configuration of the first bonding unit shown derives a third configuration of the first bonding unit. For example, the deposition of metal material on the first bonding pad 160 may be extended such that the metal material fills the entire volume of the opening 152 through the first passivation dielectric layer 150. In one embodiment, the metal material may be deposited by directly electroplating the metal material onto the physically exposed surface of the first distal metal interconnect structure 148, which is the surface of a subgroup of the first metal interconnect structure 140. The metal material may be electroplated to fill each opening in the opening 152 of the first passivation dielectric layer 150.

[0033] A portion of the dielectric material can be removed from above a horizontal plane including the first distal surface of the first passivation dielectric layer 150 via a planarization process such as a chemical mechanical planarization process. The top surface of the first bonding pad 160 may be coplanar with the top surface of the first passivation dielectric layer 150.

[0034] refer to Figure 3B A recess etching process can be performed to vertically recess the first bonding pad 160 within an opening 152 in the first passivation dielectric layer 150. The top surface (i.e., the distal surface) of the first bonding pad 160 can be vertically recessed below a horizontal plane including the top surface of the first passivation dielectric layer 150. Thus, an array of first bonding pads 160 is formed.

[0035] refer to Figure 3C Executable Figure 1D Processing steps or Figure 2B and Figure 2C The processing steps are to form an array of solder material portions 190.

[0036] Figures 4A to 4D This is a sequential vertical cross-sectional view of the fourth configuration of the first joining unit during manufacturing, according to an embodiment of this disclosure. Reference Figure 4A The second configuration of the first joining unit can be with Figure 3B The third configuration of the first joining unit shown is the same.

[0037] refer to Figure 4B Executable Figure 2B The processing steps involve depositing solder material. A solder material layer 190L is formed, which extends continuously over the top surface of the first passivation dielectric layer 150.

[0038] refer to Figure 4C Solder material can be planarized by removing a portion of the solder material layer 190L from above a horizontal plane including the first distal surface of the first passivation dielectric layer 150. For example, solder material can be removed from above a horizontal plane including the first distal surface of the first passivation dielectric layer 150 by a chemical mechanical planarization process.

[0039] refer to Figure 4D An etching process can be performed to vertically recess solder material into openings 152 in the first passivation dielectric layer 150. The solder material can be recessed isotropically, for example, by a dry etching process or a wet etching process. An array of solder material portions 190 can be formed. In one embodiment, the top surface of the solder material portions 190 may be located below a horizontal plane including the first distal surface of the first passivation dielectric layer 150.

[0040] Figures 5A to 5F This is a sequential vertical cross-sectional view of the second joining unit during manufacturing according to an embodiment of the present disclosure.

[0041] refer to Figure 5A The second bonding unit may include a second substrate 208, an optional second semiconductor device 220 formed on the top surface of the second substrate 208, a second metal interconnect structure 240 embedded within a second dielectric material layer 230, and a second passivation dielectric layer 250. In one embodiment, the second bonding unit may include a second semiconductor die, which may be, for example, a memory die or a logic die. In another embodiment, the second bonding unit may include an interposer, which may be a ceramic interposer or a laminated interposer. When the second bonding unit includes an interposer, the second semiconductor device 220 may be omitted.

[0042] Generally, the second bonding unit may be disposed within a second wafer including an array of semiconductor dies, or may be provided as a separate unit such as an interposer. When the second bonding unit is disposed within the second wafer, the second wafer may include an array of semiconductor dies, and the second semiconductor die may be one of the semiconductor dies within the array. When the second bonding unit is disposed within the second wafer, the second wafer may include a second semiconductor wafer, such as a commercially available single-crystal silicon wafer.

[0043] When the second bonding unit includes a second semiconductor die, the second semiconductor device 220 may include any type of semiconductor device known in the art. In an illustrative example, the second semiconductor die may include a memory die comprising a three-dimensional array of memory elements, such as a vertical NAND memory array. Alternatively, the second semiconductor device may include a logic die. When the first bonding unit includes a memory die, the second bonding unit may include a logic die including peripheral circuitry configured to control the operation of memory elements within the memory die, and vice versa. In one embodiment, one of the first and second bonding units may include a memory die comprising a three-dimensional array of memory elements, such as a three-dimensional NAND memory array, and the other of the first and second bonding units may include a logic die including peripheral (i.e., driver) circuitry configured to control the operation of the three-dimensional array of memory elements.

[0044] The second metal interconnect structure 240 may include metal via structures and metal line structures configured to provide electrical interconnections between and / or to respective nodes of the second semiconductor device 220. The second metal interconnect structure 240 may include conductive alloys and / or compounds of tungsten, copper, cobalt, tantalum, titanium, molybdenum, ruthenium, and / or the conductive materials thereof. The total number of layers of metal lines within the second metal interconnect structure 240 may be in the range of 2 to 20. The total number of layers of metal via structures within the second metal interconnect structure 240 may be in the range of 2 to 20. In one embodiment, the second metal interconnect structure 240 may optionally include a second distal metal interconnect structure 248, which is the part of the second metal interconnect structure 240 furthest from the second substrate 208. In one embodiment, the second distal metal interconnect structure 248 may include metal pads or metal lines. Alternatively, the second distal metal interconnect structure 248 may be omitted.

[0045] When the second bonding unit comprises a semiconductor die, the second dielectric layer 230 may comprise at least one interlayer dielectric (ILD) material, which may include, for example, undoped silicate glass, doped silicate glass, organosilicon glass, silicon carbide nitride, silicon oxynitride, and / or silicon nitride. When the second bonding unit comprises an interposer, the second dielectric layer 230 may comprise at least one laminateable polymer material, or may comprise at least one ceramic material. The total thickness of the second dielectric layer 230 may range from 500 nm to 20 micrometers, but smaller and larger thicknesses are also possible.

[0046] The second passivation dielectric layer 250 includes a dielectric material that prevents the diffusion of hydrogen, moisture, and / or metallic contaminants. For example, the second passivation dielectric layer 250 may include at least one of a silicon nitride layer, a silicon nitride carbide layer, or a polymer material layer (such as a polyimide layer) and / or consist substantially of the latter. The total thickness of the second passivation dielectric layer 250 may range from 500 nm to 5 micrometers, but smaller and larger thicknesses are also possible. The second passivation dielectric layer 250 may be deposited as a blanket-covered passivation dielectric layer over the top surface (i.e., the distal surface) of the second dielectric material layer 230.

[0047] refer to Figure 5B An array of openings 252 can be formed through the blanket-covered passivated dielectric layer, such that the top surface of the corresponding second distal metal interconnect structure 248 is physically exposed below the openings through the blanket-covered passivated dielectric layer. The continuous remaining portion of the blanket-covered passivated dielectric layer after the formation of the array of openings 252 constitutes the second passivated dielectric layer 250.

[0048] In one embodiment, the openings 252 in the second passivation dielectric layer 250 may be arranged as a periodic two-dimensional array of openings. In one embodiment, the periodic two-dimensional array of openings may comprise a rectangular two-dimensional array of openings having a second spacing along a second horizontal direction and a second spacing along a second horizontal direction perpendicular to the second horizontal direction. In one embodiment, each of the second spacing and the second spacing may be in the range of 2 micrometers to 30 micrometers, such as 5 micrometers to 10 micrometers, but smaller and larger spacings may also be used. The edges of adjacent openings 252 may be spaced apart by a distance in the range of 1 micrometer to 5 micrometers, and the width (e.g., diameter) of each opening 152 may be in the range of 2 micrometers to 10 micrometers, such as 3 micrometers to 5 micrometers. In one embodiment, the pattern of the openings 252 in the second passivation dielectric layer 250 may be a mirror image of the pattern of the openings 152 in the first passivation dielectric layer 150.

[0049] refer to Figure 5CThe metal portion can be selectively deposited within openings in the second passivation dielectric layer 250. An electroplating or electroless plating process can be performed to directly and selectively deposit the metal portion within openings in the second passivation dielectric layer 250 onto the physically exposed surface of the second distal metal interconnect structure 248. The metal portion constitutes a pad base portion 262, which is the base portion of the second bonding pad to be subsequently completed. The metal portion may include at least one metallic material that can be deposited by electroplating or electroless plating. In one embodiment, the pad base portion 262 may include a metallic material such as copper, silver, gold, nickel, brass, palladium, and / or a cobalt-tungsten-phosphorus alloy. In one embodiment, the thickness of the pad base portion 262 may be less than the thickness of the second passivation dielectric layer 250. For example, the thickness of the pad base portion 262 may be in the range of 300 nm to 4 micrometers, but smaller and larger thicknesses are also possible.

[0050] See Figure 5D A photoresist layer 277 may be applied over a second passivation dielectric layer 250 and may be photolithographically patterned to form an array of openings therein. In one embodiment, each opening in the patterned photoresist layer 277 may be formed over and within a region of a corresponding pad base portion 262. In one embodiment, the periphery of each opening in the patterned photoresist layer 277 may be laterally offset inward from the periphery of the lower opening 252 in the second passivation dielectric layer 250. In one embodiment, each opening in the patterned photoresist layer 277 may have a circular, rectangular, or rounded rectangular shape. The maximum lateral dimension of each opening in the patterned photoresist layer 277 may be in the range of 10% to 90%, such as 40% to 70%, of the maximum lateral dimension of the lower pad base portion 262. In one embodiment, each opening in the patterned photoresist layer 277 may have a circular horizontal cross-sectional shape with a diameter ranging from 1 micrometer to 20 micrometers, such as from 2 micrometers to 8 micrometers, but smaller and larger sizes may also be used.

[0051] refer to Figure 5EMetallic materials, such as copper or copper-based alloys, can be directly formed on the physically exposed surface of the pad base portion 262 within openings in the patterned photoresist layer 277. In one embodiment, an electroplating or electroless plating process can be performed to selectively deposit portions of metal (e.g., copper or copper-based alloys, nickel or nickel-based alloys, cobalt or cobalt-based alloys, etc.) directly within openings in the patterned photoresist layer 277 onto the corresponding pad base portions in the pad base portion 262. Alternatively, non-selective metal deposition, such as metal-organic chemical vapor deposition or sputtering, can be used to directly deposit portions of metallic material within openings in the patterned photoresist layer 277 onto the physically exposed surface of the pad base portion 262, depositing the metallic material on top of the patterned photoresist layer 277, followed by stripping the patterned photoresist layer 277. The metallic portions within the openings constitute a bonding pillar structure 268. Generally, bonding pillar structures 268 can be formed in the openings of the patterned photoresist layer 277 on the corresponding pad base portions of the pad base portions 262. Each bonding pillar structure in the bonding pillar structures 268 may have sidewalls laterally spaced from the second passivation dielectric layer 250. In one embodiment, the openings in the patterned photoresist layer 277 may have vertical sidewalls, and each bonding pillar structure in the bonding pillar structures 268 may have a correspondingly uniform horizontal cross-sectional shape that remains unchanged along the vertical direction. In this case, the sidewalls of the bonding pillar structures 268 may be vertical.

[0052] Each successive combination of pad base portion 262 and bonding pillar structure 268 constitutes a second bonding pad 260. In other words, each second bonding pad 260 may comprise a vertical stack of pad base portion 262 and bonding pillar structure 268. In one embodiment, each second bonding pad in the second bonding pad 260 includes a pad base portion 262 that abuts against a corresponding bonding pillar structure in the bonding pillar structure 268 and contacts the sidewall of the second passivation dielectric layer 250.

[0053] The bonding pillar structure 268 has a smaller lateral dimension than the pad base portion 262. The bonding pillar structure 268 may include at least one metallic material that can be deposited by electroplating or electroless plating. In one embodiment, the bonding pillar structure 268 may include a metallic material such as copper or a copper-based alloy containing more than 50 atomic percent copper, silver, gold, nickel, brass, palladium, and / or a cobalt-tungsten-phosphorus alloy. In one embodiment, the height of the bonding pillar structure 268 may be selected to be small, such that the top surface of the bonding pillar structure 268 is formed above a horizontal plane including the second distal surface of the second passivation dielectric layer 250. If selective deposition of the bonding pillar structure 268 is used, the top surface of the bonding pillar structure 268 is formed below a horizontal plane including the patterned photoresist layer 277. In one embodiment, the top surface of the bonding pillar structure 268 may protrude above the horizontal plane including the second distal surface of the second passivation dielectric layer 250 by a vertical distance ranging from 0.5 micrometers to 3 micrometers, such as 1 micrometer to 2 micrometers, but smaller and larger vertical distances are also possible.

[0054] refer to Figure 5F The patterned photoresist layer 277 can be removed, for example, by ashing or by dissolving in a solvent. If a stripping process is used, the metal material deposited on the top surface of the patterned photoresist layer 277 is stripped (i.e., removed) to leave the bonding pillar structure 268. A second bonding unit 200 may be provided. Generally, the second bonding unit 200 includes: a second substrate 208; a second metal interconnect structure 240 embedded in a second dielectric material layer 230; a second passivated dielectric layer 250 having a second proximal surface and a second distal surface, the second proximal surface contacting one of the second dielectric material layers 230, the second distal surface being spaced from the second proximal surface by the thickness of the second passivated dielectric layer 250; and a second bonding pad 260 including a corresponding bonding pillar structure 268 protruding away from a horizontal plane including the second distal surface of the second passivated dielectric layer 250.

[0055] refer to Figure 6A The bonding assembly of the first bonding unit 100 and the second bonding unit 200 can be formed by positioning the second bonding unit 200 and the first bonding unit such that the bonding post structure 268 faces the corresponding solder material portion in the solder material portion 190. The array of bonding post structures 268 is aligned with and disposed on the array of solder material portions 190.

[0056] A bonding annealing process can be performed to soften or reflow the solder material portion 190. The high temperature of the annealing process can be selected based on the material composition of the solder material portion 190. The annealing temperature that causes the tin solder material portion 190 to melt into a liquid state is typically around 232°C. If the bonding pillar structure 268 includes copper, the melting point of copper is 1085°C. Therefore, the bonding annealing temperature can be higher than 232°C, such as 240°C to 350°C, including 250°C to 300°C. The hardness and elastic modulus of copper do not change significantly at the bonding annealing temperature, while the solder material portion 190 reflows at the bonding annealing temperature. Therefore, the liquid solder material portion 190 can be easily extruded during bonding to conform to the shape of the first bonding pad 160 and the second bonding pad 260 (i.e., the bonding pillar structure).

[0057] The solder material portion 190 array can be reflowed during bonding annealing, such that when bonding unit 100 is pressed against bonding unit 200, bonding pillar structure 268 extrudes the liquid solder material portion 190 into the side of the opening 152 in the first passivated dielectric layer 150. Therefore, the bonding pillar structure 268 of the second bonding pad 260 can contact the first bonding pad 160. After bonding annealing, the solder material portion 190 is cured and provides enhanced bonding between the respective first bonding pads in the paired first bonding pads 160 and the respective bonding pillar structures in the bonding pillar structures 268 through the bonding interface surrounding the pad 160 and the structure 268. Generally, the second bonding unit 200 can be bonded to the first bonding unit 100 by bonding the bonding pillar structure 268 to the respective first bonding pad 160 and the solder material portion 190. Figure 6A This illustrates an ideal situation where, after forming the bonding assembly of the first bonding unit 100 and the second bonding unit 200, the first distal surface of the first passivated dielectric layer 150 is parallel to the second distal surface of the second passivated dielectric layer 250.

[0058] Figure 6B This is a second configuration of the joining component according to an embodiment of the present disclosure. Figure 6B This illustrates a configuration in which the second joining unit 200 is tilted relative to the first joining unit 100 during and / or after joining the second joining unit 200 to the first joining unit 100. For example, the second joining unit 200 may be tilted to the right, as shown. Figure 6BAs shown. In this configuration, when the bonding unit 100 is pressed against the bonding unit 200, the array of solder material portions 190 (including portions 190A and 190B) can reflow during bonding annealing. The first bonding pillar structure 268A on the right side of the second bonding unit 200 is closer to the first bonding unit 100 than the second bonding pillar structure 268B on the left side of the second bonding unit 200. In this configuration, the first bonding pillar structure 268A extrudes the underlying liquid first solder material portion 190A. Therefore, the first bonding pillar structure 268A contacts the underlying first bonding pad 160A. In contrast, the second bonding pillar structure 268B does not extrude the liquid second solder material portion 190B and does not contact the underlying first bonding pad 160B. However, after bonding annealing, the second solder material portion 190B solidifies and contacts both the underlying first bonding pad 160B and the overlying second bonding pillar structure 268B. Therefore, the second solder material portion 190B provides electrical contact between the lower first bonding pad 160B and the overlying second bonding pillar structure 268B, and avoids an open circuit between the lower first bonding pad 160B and the overlying second bonding pillar structure 268B.

[0059] The inclination between the second joining unit 200 and the first joining unit 100 can be less than the arctangent (1×10). -3 In an illustrative example, if the maximum lateral dimension of the second bonding unit 200 is approximately 1 cm, the difference in vertical separation distance on one side of the bonding assembly relative to the opposite side may be less than 10 micrometers. In one embodiment, the Euclidean two-dimensional plane comprising the second distal surface of the second passivation dielectric layer 250 may be relative to the Euclidean two-dimensional plane comprising the first distal surface of the first passivation dielectric layer 150 in arctangent (1 × 10⁻⁶). -9 ) to arctangent (1×10 -3 Angle tilt within the range of ).

[0060] According to one aspect of this disclosure, the tilt angle between the second bonding unit 200 and the first bonding unit 100 can be self-limiting due to the metal-to-metal contact that can be provided between the bonding post structure 268A of the first bonding pad 160A and the second bonding pad 260. Specifically, the first bonding pad 160 and the second bonding pad 260 include metal material that does not reflow during the bonding annealing process that causes the solder material portion 190 to reflow.

[0061] In an illustrative example of the limitation on the tilt angle caused by the geometry of the first bonding pad 160 and the second bonding pad, the first bonding unit 100 and the second bonding unit 200 may be semiconductor dies with a square horizontal cross-sectional shape, each side having a length of 5 mm, and the variation in the vertical separation distance between the two semiconductor dies may be approximately 2 micrometers per 1 cm. In this case, the variation in the vertical separation distance may be approximately 1 micrometer. In this example, the thickness of each solder material portion 190 (such as a tin-containing solder board) may be equal to or less than 1 micrometer. If the total variation in the vertical separation distance is 1 micrometer, the bonding pillar structure 268A may contact the surface of the first bonding pad 160A at the position of minimum vertical separation distance.

[0062] In one embodiment, each bonding pad (160, 260) array may have a pitch of approximately 5 micrometers, and the lateral spacing between adjacent pads (160, 260) within the bonding pads may be in the range of 1 to 2 micrometers. The lateral dimension (160, 260) of each bonding pad may be in the range of 3 to 4 micrometers. After the reflow process, the distal surface of the solder material portion 190 may be closer to the first substrate 108 than the first distal surface of the first passivation dielectric layer 150 is to the first substrate 108. Solder bridging can be avoided by employing a passivation dielectric layer (150, 250) with a thickness greater than the thickness of the solder material portion 190. Therefore, an array of solder material portions 190 with fine pitch can be employed while simultaneously avoiding the problem of solder bridging.

[0063] With a limited tilt between the first bonding unit 100 and the second bonding unit 200, the first subgroup of the bonding pillar structure 268A directly contacts the first subgroup of the first bonding pad 160A, and the second subgroup of the bonding pillar structure 268B does not directly contact any of the first bonding pads 160B, but rather contacts the solder material portion 190B. This provides electrical contact between them, such as... Figure 6B As shown.

[0064] The bonding process can be a die-to-die bonding process, a wafer-to-wafer bonding process, or a wafer-to-die bonding process. In one embodiment, a first bonding unit 100 may be disposed within a first wafer including a first semiconductor die array, and the first bonding unit 100 may be one of the first semiconductor dies. A second bonding unit 200 may be disposed within a second wafer including a second semiconductor die array, and the second bonding unit 200 may be one of the second semiconductor dies. In this case, each pair of mating first and second semiconductor dies can be bonded simultaneously via wafer-to-wafer bonding.

[0065] In another embodiment, the first wafer may be diced to cut the first semiconductor die before it is placed on a second wafer including an array of second semiconductor dies. Alternatively, the second wafer may be diced to cut the second semiconductor die before it is placed on a first wafer including an array of first semiconductor dies. In this case, a wafer-to-die bonding process may be performed.

[0066] In yet another embodiment, the first wafer can be diced and the second wafer can be diced before joining a pair of mating first and second semiconductor dies. In this case, a die-to-die bonding process can be used.

[0067] In yet another embodiment, one of the first bonding unit 100 and the second bonding unit 200 includes a semiconductor die in which a semiconductor device (120 or 220) is included; and the other of the first bonding unit 100 and the second bonding unit 200 includes an interposer. In this case, the semiconductor die can be bonded to the interposer using the methods of this disclosure.

[0068] Referring to all the accompanying drawings and various embodiments of the present disclosure, the bonding assembly 300 includes a first bonding unit 100, the first bonding unit comprising: a first substrate 108; a first metal interconnect structure 140 embedded in a first dielectric material layer 130; a first passivation dielectric layer 250 having a first proximal surface and a first distal surface, the first proximal surface contacting one of the first dielectric material layers 130, the first distal surface being spaced from the first proximal surface by the thickness of a first passivation dielectric layer 150; a first bonding pad 160 located within and laterally surrounded by a corresponding opening 152 in the first passivation dielectric layer 150, wherein the distal surface of the first bonding pad 160 is recessed relative to the first distal surface of the first passivation dielectric layer 150; and a solder material portion 190 located within and laterally surrounded by a corresponding opening 152 in the first passivation dielectric layer 150. The bonding assembly 300 further includes a second bonding unit 200, which includes: a second substrate 208; a second metal interconnect structure 240 embedded in a second dielectric layer 230; a second passivation dielectric layer 250 having a second proximal surface and a second distal surface, the second proximal surface contacting one of the second dielectric layers 230, the second distal surface being spaced from the second proximal surface by the thickness of the second passivation dielectric layer 250; and a second bonding pad 260 located within and laterally surrounded by a corresponding opening 252 in the second passivation dielectric layer 250. Each of the second bonding pads 260 includes a bonding pillar structure 268 protruding beyond a horizontal plane including the second distal surface. A first subgroup (e.g., 268A) of the bonding pillar structures 268 directly contacts a first subgroup (e.g., 160A) of the first bonding pads 160. The second subgroup (e.g., 268B) of the bonding pillar structure 268 does not directly contact any of the first bonding pads 16. A corresponding solder material portion in the second subgroup (e.g., 190B) of the solder material portion 190 is located between each bonding pillar structure in the second subgroup 268B of the bonding pillar structure 268 and each corresponding first bonding pad in the second subgroup 160B of the first bonding pad 160. The corresponding solder material portion in the second subgroup 190B of the solder material portion 190 provides electrical contact between each bonding pillar structure in the second subgroup 268B of the bonding pillar structure 268 and each corresponding first bonding pad in the second subgroup 160B of the first bonding pad 160.

[0069] In one embodiment, the first bonding unit 100 is tilted relative to the second bonding unit 200. In one embodiment, the solder material portion 190 comprises tin or a tin-based alloy containing more than 50 atomic percent tin, the first bonding pad 160 comprises copper or a copper-based alloy containing more than 50 atomic percent copper, and the bonding pillar structure 268 comprises copper or a copper-based alloy containing more than 50 atomic percent copper.

[0070] In one embodiment, a corresponding solder material portion in the first subgroup 190A of solder material portion 190 is located between the sidewall of the corresponding bonding pillar structure in the first subgroup 268A of bonding pillar structure 268 and the sidewall of the corresponding opening 152 in the first passivation dielectric layer 150. The corresponding solder material portion in the first subgroup 190A of solder material portion 190 contacts the distal surface of the corresponding first bonding pad in the first subgroup 160A of first bonding pad 160 and surrounds the bonding interface between the distal surface of the corresponding first bonding pad in the first subgroup 160A of first bonding pad 160 and the surface of the corresponding bonding pillar structure in the first subgroup 268A of bonding pillar structure 268.

[0071] In one embodiment, each of the first bonding pads 160 has a sidewall contacting the first passivation dielectric layer 150, and each bonding pillar structure 268 has a sidewall laterally spaced from the second passivation dielectric layer 250. Each of the second bonding pads 260 includes a pad base portion 262 that abuts against a corresponding bonding pillar structure in the bonding pillar structure 268 and contacts the sidewall of the second passivation dielectric layer 250. In one embodiment, a second distal surface of the second passivation dielectric layer 250 is vertically spaced from a first distal surface of the first passivation dielectric layer 150.

[0072] In one embodiment, the first bonding unit 100 includes a first semiconductor die comprising a first semiconductor device 120 located on a first substrate 108 and embedded in a first dielectric layer 130; and the second bonding unit 200 includes a second semiconductor die comprising a second semiconductor device 220 located on a second substrate 208 and embedded in a second dielectric layer 230. In one embodiment, the first semiconductor device includes a three-dimensional memory device, and the second semiconductor device includes peripheral devices for the three-dimensional memory device.

[0073] In another embodiment, one of the first bonding unit 100 and the second bonding unit 200 includes a semiconductor die in which a semiconductor device is included; and the other of the first bonding unit 100 and the second bonding unit 200 includes an interposer.

[0074] Various embodiments of this disclosure can be used to provide a joint assembly with a lower failure rate and higher joint reliability when tilted between the respective joint units.

[0075] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joining assembly, comprising: A first bonding unit, comprising: a first substrate; a first metal interconnect structure embedded in a first dielectric material layer; a first passivation dielectric layer having a first proximal surface and a first distal surface, the first proximal surface contacting one of the first dielectric material layers, the first distal surface and the first proximal surface being spaced apart by the thickness of the first passivation dielectric layer; a first bonding pad located within and laterally surrounded by a corresponding opening in the first passivation dielectric layer, wherein the distal surface of the first bonding pad is recessed relative to the first distal surface of the first passivation dielectric layer; and a solder material portion located within and laterally surrounded by a corresponding opening in the first passivation dielectric layer; and The second bonding unit includes: a second substrate; a second metal interconnect structure embedded in a second dielectric material layer; a second passivation dielectric layer having a second proximal surface and a second distal surface, the second proximal surface contacting one of the second dielectric material layers, the second distal surface being spaced from the second proximal surface by the thickness of the second passivation dielectric layer; and second bonding pads located within and laterally surrounded by corresponding openings in the second passivation dielectric layer, wherein each of the second bonding pads includes a bonding pillar structure protruding beyond a horizontal plane including the second distal surface, wherein: The first subgroup of the bonding pillar structure directly contacts the first subgroup of the first bonding pad; and The second subgroup of the bonding pillar structure does not directly contact any of the first bonding pads of the first bonding pad, such that a corresponding solder material portion in the second subgroup of the solder material portion is located between each bonding pillar structure in the second subgroup of the bonding pillar structure and each corresponding first bonding pad in the second subgroup of the first bonding pad, and such that the corresponding solder material portion in the second subgroup of the solder material portion provides electrical contact between each bonding pillar structure in the second subgroup of the bonding pillar structure and each corresponding first bonding pad in the second subgroup of the first bonding pad.

2. The joining assembly according to claim 1, wherein the first joining unit is inclined relative to the second joining unit.

3. The joining assembly according to claim 1, wherein: The solder material contains tin or a tin-based alloy; The first bonding pad comprises copper or a copper-based alloy; and The joint post structure comprises copper or a copper-based alloy.

4. The bonding assembly of claim 1, wherein a corresponding solder material portion in the first subgroup of the solder material portions is located between a sidewall of the corresponding bonding pillar structure in the first subgroup of the bonding pillar structure and a sidewall of the corresponding opening in the first passivation dielectric layer.

5. The bonding assembly of claim 4, wherein the respective solder material portion of the first subgroup of the solder material portion contacts the distal surface of the respective first bonding pad of the first subgroup of the first bonding pad, and surrounds the bonding interface between the distal surface of the respective first bonding pad of the first subgroup of the first bonding pad and the surface of the respective bonding pillar structure of the first subgroup of the bonding pillar structure.

6. The bonding assembly of claim 1, wherein each of the first bonding pads has a sidewall that contacts the first passivated dielectric layer.

7. The bonding assembly of claim 1, wherein each bonding pillar structure has a sidewall laterally spaced from the second passivation dielectric layer.

8. The bonding assembly of claim 7, wherein each of the second bonding pads includes a pad base portion that abuts a corresponding bonding pillar structure in the bonding pillar structure and contacts a sidewall of the second passivation dielectric layer.

9. The bonding assembly of claim 1, wherein the second distal surface of the second passivated dielectric layer is vertically spaced from the first distal surface of the first passivated dielectric layer.

10. The joining assembly according to claim 1, wherein: The first bonding unit includes a first semiconductor die, the first semiconductor die including a first semiconductor device located on the first substrate and embedded in the first dielectric material layer; and The second bonding unit includes a second semiconductor die, the second semiconductor die including a second semiconductor device located on the second substrate and embedded in the second dielectric material layer.

11. The joining assembly according to claim 10, wherein: The first semiconductor device includes a three-dimensional memory device; and The second semiconductor device includes peripheral devices for the three-dimensional memory device.

12. The joining assembly according to claim 1, wherein: One of the first bonding unit and the second bonding unit includes a semiconductor die, wherein the semiconductor die includes a semiconductor device; and The other of the first bonding unit and the second bonding unit includes an intermediary layer.

13. A method of forming a mating assembly, the method comprising: A first bonding unit is provided, wherein the first bonding unit comprises: a first substrate; a first metal interconnect structure embedded in a first dielectric material layer; a first passivation dielectric layer having a first proximal surface and a first distal surface, the first proximal surface contacting one of the first dielectric material layers, the first distal surface and the first proximal surface being spaced apart by the thickness of the first passivation dielectric layer; and a first bonding pad located within and laterally surrounded by a corresponding opening in the first passivation dielectric layer, wherein the distal surface of the first bonding pad is recessed relative to the first distal surface of the first passivation dielectric layer. Solder material portions are formed on the physically exposed surface of the first bonding pad; A second bonding unit is provided, wherein the second bonding unit includes: a second substrate; a second metal interconnect structure embedded in a second dielectric material layer; a second passivation dielectric layer having a second proximal surface and a second distal surface, the second proximal surface contacting one of the second dielectric material layers, the second distal surface and the second proximal surface being spaced apart by the thickness of the second passivation dielectric layer; and second bonding pads located within and laterally surrounded by corresponding openings in the second passivation dielectric layer, wherein each of the second bonding pads includes a bonding pillar structure protruding beyond a horizontal plane including the second distal surface; and When the first bonding unit and the second bonding unit are pressed together, the solder material portion is reflowed, causing at least a first subgroup of the bonding pillar structure to be extruded from the first subgroup of the solder material portion and directly contact the first subgroup of the first bonding pad; and in: The first joining unit is inclined relative to the second joining unit; and The second subgroup of the bonding pillar structure does not directly contact any of the first bonding pads of the first bonding pads and does not completely extrude the second subgroup of the solder material portion, such that the corresponding solder material portion in the second subgroup of the solder material portion is located between each bonding pillar structure in the second subgroup of the bonding pillar structure and each corresponding first bonding pad in the second subgroup of the first bonding pads, and such that the corresponding solder material portion in the second subgroup of the solder material portion provides electrical contact between each bonding pillar structure in the second subgroup of the bonding pillar structure and each corresponding first bonding pad in the second subgroup of the first bonding pads.

14. The method of claim 13, wherein: The corresponding solder material portion in the first subgroup of the solder material portion is located between the sidewall of the corresponding bonding pillar structure in the first subgroup of the bonding pillar structure and the sidewall of the corresponding opening in the first passivation dielectric layer; and The corresponding solder material portion in the first subgroup of the solder material portion contacts the distal surface of the corresponding first bonding pad in the first subgroup of the first bonding pad and surrounds the bonding interface between the distal surface of the corresponding first bonding pad in the first subgroup of the first bonding pad and the surface of the corresponding bonding pillar structure in the first subgroup of the bonding pillar structure.

15. The method according to claim 13, wherein: The solder material contains tin or a tin-based alloy; The first bonding pad comprises copper or a copper-based alloy; The connecting post structure comprises copper or a copper-based alloy; and The reflow of the solder material portion occurs at a temperature higher than the melting temperature of the solder material portion but lower than the melting temperature of the first bonding pad and the bonding post structure.

16. The method of claim 15, wherein providing the first joining unit comprises: A blanket-like passivated dielectric layer is formed on the top surface of the first dielectric material layer; An opening is formed through the blanket-covered passivated dielectric layer, wherein the blanket-covered passivated dielectric layer becomes the first passivated dielectric layer; as well as The first bonding pad is formed by selectively depositing a portion of copper or a copper-based alloy within the opening in the first passivation dielectric layer.

17. The method of claim 16, wherein forming the solder material portion comprises directly immersing the solder material in a dip bath to deposit it on the surface of the first bonding pad.

18. The method of claim 16, wherein forming the solder material portion comprises: Solder material is plated onto the first bonding pad; The solder material is planarized by removing a portion of the solder material from above a horizontal plane including the first distal surface; as well as The remaining portion of the solder material is vertically recessed into the opening in the first passivation dielectric layer.

19. The method of claim 16, wherein the step of forming the first bonding pad by selectively depositing a copper or copper-based alloy portion within the opening in the first passivation dielectric layer comprises: The copper or the copper-based alloy is directly electroplated onto the surface of the subgroup of the first metal interconnect structure within the opening in the first passivation dielectric layer; Remove a portion of the copper or the copper-based alloy from above a horizontal plane including the first distal surface; as well as The remaining portion of the copper or the copper-based alloy is vertically recessed within the opening in the first passivated dielectric layer.

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