Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device involved in the present disclosure includes: a main part, which has a semiconductor substrate, a first cladding layer of a first type provided on the semiconductor substrate and being one of the n-type and the p-type, an active layer provided on the first cladding layer, and a second cladding layer of a second type provided on the active layer and being the other of the n-type and the p-type, and is formed with a flat portion and a mesa portion including the active layer; and a first buried layer of the second type covering the upper surface of the flat portion and the side surface of the mesa portion, the first buried layer having a protrusion on the upper surface of a portion of the upper surface of the flat portion provided in an area within the height of the mesa portion from the boundary between the mesa portion and the flat portion.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Patent document 1 discloses a method for manufacturing an optical semiconductor device. In this manufacturing method, a mesa structure is formed by selectively etching an n-type cladding layer, an active layer, and a p-type cladding layer sequentially formed on a substrate. Next, a p-type semiconductor layer having a thickness of 5 nm to 45 nm is formed on the planar portion from the side of the mesa structure to the planar portion of the substrate other than the mesa structure. Next, a high-resistance semiconductor layer is formed on the p-type semiconductor layer to bury the mesa structure. In the planar portion, the product of the thickness of the p-type semiconductor layer and the concentration of the p-type dopant is 2.5×10 19 nm / cm 3 By providing such a p-type semiconductor layer, leakage current can be suppressed. In addition, by sufficiently reducing the thickness of the p-type semiconductor layer, the element capacitance that is inevitably generated when forming the p-type semiconductor layer can be reduced.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2011-249767

[0004] The first buried layer, which is the p-type semiconductor layer covering the mesa portion and the planar portion disclosed in Patent Document 1, may have a portion thinner than other portions due to the influence of the transition surface generated during epitaxial growth. Therefore, the first buried layer may be discontinuous. Summary of the invention

[0005] The present disclosure provides a semiconductor device capable of suppressing discontinuity of a first buried layer and a method for manufacturing the semiconductor device.

[0006] The semiconductor device according to the present disclosure comprises: a main part having a semiconductor substrate, a first cladding layer of a first type which is one of an n-type and a p-type and is provided on the semiconductor substrate, an active layer provided on the first cladding layer, and a second cladding layer of a second type which is the other of the n-type and the p-type and is provided on the active layer, and having a flat portion and a mesa portion which is adjacent to the flat portion and protrudes upward relative to the flat portion and includes the active layer; a first buried layer of the second type and having a first portion covering the upper surface of the flat portion and a second portion covering the side surface of the mesa portion; a second buried layer of the first type provided on the first buried layer; a first electrode provided above the mesa portion; and a second electrode provided below the mesa portion, the first buried layer having a protrusion on the upper surface of a portion of the upper surface of the flat portion provided in a region within a height of the mesa portion from a boundary between the mesa portion and the flat portion.

[0007] The method for manufacturing a semiconductor device according to the present disclosure comprises: forming a first cladding layer of a first type, which is one of an n-type and a p-type, on a semiconductor substrate, forming an active layer on the first cladding layer, and forming a second cladding layer of a second type, which is the other of the n-type and the p-type, on the active layer, thereby forming a main portion having the semiconductor substrate, the first cladding layer, the active layer, and the second cladding layer; forming a flat portion, and a mesa portion, which is adjacent to the flat portion and protrudes upward relative to the flat portion and includes the active layer, on the main portion; and forming a first step of forming a first cladding layer on the first cladding layer. A process of forming a first semiconductor layer of the second type and convex shape in an area on the upper surface of the flat portion within the height of the mesa portion from the boundary between the mesa portion and the flat portion; a second process of covering the side surfaces of the mesa portion, the upper surface of the flat portion and the first semiconductor layer with the second semiconductor layer of the second type to form a first buried layer having the first semiconductor layer and the second semiconductor layer; a process of forming the first type second buried layer on the first buried layer; a process of forming a first electrode above the mesa portion; and a process of forming a second electrode below the mesa portion.

[0008] In the semiconductor device according to the present disclosure, the protrusion can suppress the first buried layer from being discontinued.

[0009] In the method for manufacturing a semiconductor device according to the present disclosure, it is possible to suppress discontinuity of the first buried layer due to the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 2 It is a figure which shows the state which formed the flat part and the terrace part.

[0012] Figure 3 It is a diagram showing a state where the mesa portion is covered with an insulating film.

[0013] Figure 4 This is a diagram showing a state where the first semiconductor layer is grown.

[0014] Figure 5 It is a figure which shows the state which covered the mesa part with the photoresist.

[0015] Figure 6 It is a diagram showing a state where the first semiconductor layer is being etched.

[0016] Figure 7 It is a diagram showing a state where the second semiconductor layer is formed.

[0017] Figure 8 This is a diagram for explaining a state in which a flat portion is formed by plasma dry etching.

[0018] Fig. 9 It is a diagram showing an initial state of the epitaxial growth step of the first buried layer according to the comparative example.

[0019] Fig.10 This is a diagram for explaining the state of introduction of a dopant in a comparative example.

[0020] Fig.11 This is a diagram for explaining a state in which a (111) B plane and a (001) plane are formed in a comparative example.

[0021] Fig.12 This is a diagram for explaining a state in which a transition surface is formed in a comparative example.

[0022] Fig.13 is a cross-sectional view of a semiconductor device according to a comparative example.

[0023] Fig.14 This is a cross-sectional view of a semiconductor device according to a first variation of the first embodiment.

[0024] Fig.15 This is a cross-sectional view of a semiconductor device according to a second variation of the first embodiment.

[0025] Fig.16 This is a cross-sectional view of a semiconductor device according to a third variation of the first embodiment. DETAILED DESCRIPTION

[0026] A semiconductor device and a method for manufacturing a semiconductor device according to each embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and repeated description may be omitted.

[0027] Implementation Method 1

[0028] Figure 1 is a cross-sectional view of the semiconductor device 100 according to the first embodiment. Figure 1 In the figure, a part of the semiconductor device 100 is omitted. In addition, in the following, n-type and p-type are sometimes marked as n- and p-, respectively. In addition, the semiconductor action surface and the surface of the substrate are sometimes marked as above the substrate. In addition, the connection between structures having electrical functions includes electrical connection or mechanical connection.

[0029] The semiconductor device 100 is, for example, an optical semiconductor device such as a semiconductor laser. The semiconductor device 100 is, for example, a semiconductor laser having a buried structure. The semiconductor device 100 may also have a buried heterostructure.

[0030] The semiconductor device 100 includes a main part 10. The main part 10 includes a semiconductor substrate 12, a first type first cladding layer 14 disposed on the semiconductor substrate 12, an active layer 16 disposed on the first cladding layer 14, and a second type second cladding layer 18 disposed on the active layer 16. The first cladding layer 14 and the second cladding layer 18 are also referred to as SCH (Separate Confinement Heterostructure) layers. In the present embodiment, the first type is n-type and the second type is p-type. However, this is not limiting, as long as the first type is one of the n-type and the p-type, and the second type is the other of the n-type and the p-type.

[0031] The main portion 10 includes a flat portion 10a and a mesa portion 10b adjacent to the flat portion 10a and protruding upward relative to the flat portion 10a. The mesa portion 10b is formed in a stripe shape. The flat portion 10a is formed on both sides of the mesa portion 10b. The mesa portion 10b includes a portion of the first cladding layer 14, the active layer 16, and the second cladding layer 18.

[0032] The semiconductor device 100 according to the present embodiment is, for example, a p-InP / n-InP buried type. The semiconductor substrate 12 is formed of, for example, n-InP. The first cladding layer 14 is formed of, for example, n-InP. The second cladding layer 18 is formed of, for example, p-InP.

[0033] Both sides of the mesa portion 10b are buried by the buried layer 20. The buried layer 20 includes a first buried layer 22, a second buried layer 24, and a third buried layer 26. The first buried layer 22 is p-type. The first buried layer 22 includes: a first portion 22a covering the upper surface 10f of the flat portion 10a; and a second portion 22b covering the side surface 10e of the mesa portion 10b. The first buried layer 22 is provided along the side surface 10e of the mesa portion 10b and the upper surface 10f of the flat portion 10a.

[0034] The side surface 10e of the mesa portion 10b has: a vertical surface 10c perpendicular to the upper surface 10f of the flat portion 10a; and an inclined surface 10d connected to the upper surface 10f of the flat portion 10a. The second portion 22b covers the vertical surface 10c and the inclined surface 10d. The second portion 22b is provided to the same height as the upper surface of the second cladding layer 18. The upper end portion of the second portion 22b tapers toward the tip.

[0035] The second buried layer 24 is provided on the first buried layer 22. The second buried layer 24 is of n-type. The second buried layer 24 is provided, for example, to a height above the upper surface of the active layer 16 and below the upper surface of the second cladding layer 18. The second buried layer 24 is provided so as not to be in contact with the mesa portion 10b. The third buried layer 26 is provided on the second buried layer 24. The third buried layer 26 is of p-type. The third buried layer 26 is provided to a position higher than the upper surface of the second cladding layer 18.

[0036] The first buried layer 22 is formed of, for example, p-InP. The first buried layer 22 contains, for example, Zn as a dopant. The second buried layer 24 is formed of, for example, n-InP. The third buried layer 26 is formed of, for example, p-InP.

[0037] A contact layer 30 is provided on the mesa portion 10b and the buried layer 20. The contact layer 30 is formed of, for example, p-InP. An insulating film 32 is provided on the contact layer 30. A first electrode 34 is provided on the insulating film 32 and above the mesa portion 10b. The first electrode 34 is a p-type electrode. An opening is formed in the insulating film 32 and above the mesa portion 10b. The first electrode 34 is connected to the contact layer 30 at the opening. In addition, a second electrode 40 is provided on the back side of the semiconductor substrate 12 and below the mesa portion 10b. The second electrode 40 is an n-type electrode.

[0038] A protrusion 23 is provided on the upper surface of the first buried layer 22. The protrusion 23 is provided adjacent to the boundary between the terrace portion 10b and the flat portion 10a. The portion of the first buried layer 22 provided with the protrusion 23 is thicker than the portion of the first portion 22a other than the protrusion 23. In addition, the portion of the first buried layer 22 provided with the protrusion 23 is thicker than the second portion 22b. In other words, T3>T1, T3>T2. In addition, the portion of the first buried layer 22 provided with the protrusion 23 may be thicker than the portion of the first buried layer 22 covering the inclined surface 10d.

[0039] The protrusion 23 is convex. Figure 1 In the embodiment, the tip of the protrusion 23 is sharp. However, the present invention is not limited thereto, and the tip of the protrusion 23 may also be round. In addition, the cross-sectional shape of the protrusion 23 may be a quadrilateral or a polygon.

[0040] Next, a method for manufacturing the semiconductor device 100 according to the present embodiment is described. First, the first cladding layer 14 is formed on the semiconductor substrate 12. The semiconductor substrate 12 is, for example, in the form of a flat plate. The first cladding layer 14 is epitaxially grown by, for example, MOCVD (Metal Organic Chemical Vapor Deposition).

[0041] Next, an active layer 16 is formed on the first cladding layer 14. The active layer 16 is epitaxially grown by MOCVD. The active layer 16 has a strained multi-quantum well (MQW: Multi-QuantumWell) structure. As a result, the semiconductor device 100 can be implemented with high output and low distortion to achieve high performance. Next, a second cladding layer 18 is formed on the active layer 16. Based on the above, the main part 10 is formed.

[0042] Next, the flat portion 10 a and the mesa portion 10 b are formed on the main portion 10 . Figure 2 10a and the terrace portion 10b are formed. In this process, first, an insulating film 50 is formed on the upper surface of the second cladding layer 18. The insulating film 50 is, for example, a SiO2 film. The insulating film 50 is formed by, for example, plasma CVD (Chemical Vapor Deposition). The insulating film 50 is used as a protective mask during embedded growth in subsequent processes.

[0043] Next, the portion of the insulating film 50 other than the portion where the mesa portion 10b is formed is removed by photolithography. Next, the first cladding layer 14, the active layer 16, and the second cladding layer 18 are etched using the insulating film 50. Thus, the flat portion 10a and the mesa portion 10b are formed. The etching is, for example, plasma dry etching.

[0044] In addition, the root portion of the mesa portion 10b is removed by plasma dry etching. Thus, the inclined surface 10d is formed on the mesa portion 10b. In addition, the root portion of the mesa portion 10b is also removed by migration when the temperature is raised in the initial stage of the process of epitaxially growing the first buried layer 22. In this process, the inclined surface 10d is also formed.

[0045] Next, the entire surface of the substrate is covered with an insulating film 52. The insulating film 52 is, for example, a SiN film. The insulating film 52 is formed, for example, by plasma CVD. Next, the portion of the insulating film 52 covering the mesa portion 10b is selectively covered with a photoresist. Next, the portion of the insulating film 52 covering the flat portion 10a is removed using the photoresist. The insulating film 52 is processed, for example, by plasma dry etching using SF6 / He gas. Next, the photoresist is removed. As a result, the mesa portion 10b is covered with the insulating film 52. Figure 3 This is a diagram showing a state where the mesa portion 10 b is covered with the insulating film 52 .

[0046] Next, the first step of forming the first semiconductor layer 22c as the base of the protrusion 23 is described. First, the first semiconductor layer 22c is formed to cover the flat portion 10a. The first semiconductor layer 22c is formed of, for example, p-InP. The first semiconductor layer 22c is grown by MOCVD using the insulating film 52 as a mask. Figure 4 This is a diagram showing a state where the first semiconductor layer 22c is grown.

[0047] Next, the upper surface and side surface 10e of the mesa portion 10b are covered with photoresist 54 from above the insulating film 52. At this time, the upper surface of the first semiconductor layer 22c is covered with photoresist 54 to a predetermined distance from the boundary between the flat portion 10a and the mesa portion 10b. Figure 5 The figure shows a state where the mesa portion 10 b is covered with a photoresist 54 .

[0048] Next, the first semiconductor layer 22 c is etched using the photoresist 54 as a mask. Figure 6 1 is a diagram showing a state where the first semiconductor layer 22c is etched. For example, plasma dry etching is used for etching. Thus, the first semiconductor layer 22c is formed in a convex shape. In this way, the portion of the first semiconductor layer 22c covered by the photoresist 54 is p-type and forms the convex first semiconductor layer 22c.

[0049] Among them, Figure 6 In the state shown, the photoresist 54 and the insulating film 52 are removed. The insulating film 52, which is a SiN film, is removed by plasma dry etching using, for example, SF6 / He gas having high selectivity with the insulating film 50, which is a SiO film. Thus, the insulating film 50 remains on the mesa portion 10b.

[0050] Next, a second step is performed to form the first buried layer 22. First, the side surface 10e of the mesa portion 10b, the upper surface 10f of the flat portion 10a, and the first semiconductor layer 22c are covered with the p-type second semiconductor layer 22d. Figure 7 2 is a diagram showing a state where the second semiconductor layer 22d is formed. The second semiconductor layer 22d is epitaxially grown on both sides of the mesa portion 10b by, for example, MOCVD using the insulating film 50 as a mask. The second semiconductor layer 22d is formed of the same material as the first semiconductor layer 22c. Thus, the first buried layer 22 having the first semiconductor layer 22c and the second semiconductor layer 22d is formed.

[0051] In the second step, the protrusion 23 is formed on the upper surface of the portion of the second semiconductor layer 22d covering the first semiconductor layer 22c. In other words, the portion of the first buried layer 22 corresponding to the protrusion 23 is formed thicker than other portions by the height of the first semiconductor layer 22c.

[0052] Next, a second buried layer 24 is formed on the first buried layer 22. And a third buried layer 26 is formed on the second buried layer 24. The second buried layer 24 and the third buried layer 26 are epitaxially grown on both sides of the mesa portion 10b by, for example, MOCVD. Based on the above, a buried layer 20 is formed on both sides of the mesa portion 10b. The buried layer 20 is also called a barrier layer. The first buried layer 22 has a function of narrowing the path width of the ineffective current. Therefore, the ineffective current can be reduced by the first buried layer 22.

[0053] Next, a contact layer 30 is formed on the main part 10 and the buried layer 20. The contact layer 30 plays a role in allowing electricity to flow efficiently from the electrode to the laser. Next, an insulating film 32 is formed on the contact layer 30. Next, an opening is formed in the insulating film 32. The insulating film 32 plays a role in reducing parasitic capacitance and protecting the semiconductor layer.

[0054] Next, the first electrode 34 is formed on the mesa portion 10b so as to contact the contact layer 30 at the opening of the insulating film 32. Furthermore, the second electrode 40 is formed below the mesa portion 10b. The first electrode 34 and the second electrode 40 are formed by, for example, a lift-off method.

[0055] The semiconductor device 100 according to the present embodiment is, for example, a light source for optical communication. The semiconductor device 100 is, for example, an InP-based long-wavelength semiconductor laser having a wavelength of 1.3 to 1.55 μm. With such a semiconductor device 100 , the loss in the silica optical fiber can be suppressed.

[0056] In recent years, the amount of data communication has increased rapidly due to the popularity of mobile terminals such as smartphones and tablets and the cloudification of information. In optical communications, in addition to high speed and large capacity, stable operation in a high temperature environment is sometimes required. In order to achieve high speed and large capacity, DFB (Distributed FeedBack Laser) lasers with a fine periodic structure that unifies the wavelength are sometimes used. In addition, it is sometimes required to reduce the electrostatic capacitance of the device.

[0057] The first cladding layer 14 and the buried layer 20 of this embodiment form a pnpn structure. In such a structure, by controlling the dopant concentration of the first portion 22a and the second portion 22b of the first buried layer 22, it is possible to reduce the capacitance and suppress the leakage current.

[0058] The ratio of the leakage current flowing in the portion of the first buried layer 22, especially the portion covering the side surface of the active layer 16, to the injection current of the entire semiconductor device 100 is proportional to the cross-sectional area of ​​the first buried layer 22. Therefore, by thinning the portion of the first buried layer 22 covering the side surface of the active layer 16, the leakage current can be reduced. However, when the first buried layer 22 is made too thin, the leakage current may increase instead. Therefore, the control of the thickness of the portion of the first buried layer 22, especially the portion covering the side surface of the active layer 16, is important for the high performance and stable operation of the semiconductor device 100.

[0059] In addition, the second buried layer 24 has a high resistance and is inserted to reduce the capacitance. If the portion of the first buried layer 22 covering the flat portion 10a is made thicker, the thickness of the second buried layer 24 may not be ensured. Therefore, the speed increase of the semiconductor device 100 may be hindered. Therefore, it is also important to control the thickness of the portion of the first buried layer 22 covering the flat portion 10a.

[0060] Next, as a comparative example of the present embodiment, a mechanism of generating a transition surface when forming the first buried layer will be described. Figure 8 This is a diagram for explaining a state where the flat portion 10a is formed by plasma dry etching. The vertical surface 10c of the terrace portion 10b is a (110) plane in plane orientation. The upper surface 10f of the flat portion 10a is a (001) plane in plane orientation.

[0061] Fig. 9 It is a diagram showing an initial state of the epitaxial growth step of the first buried layer according to the comparative example. Fig. 9 This shows the state where the growth of the first buried layer has just started. At this time, an epitaxial growth component 72 of the (001) plane is generated. In addition, an epitaxial growth component 71 of the (111)B plane is generated by migration. The (111)B plane corresponds to the inclined plane 10d of this embodiment. However, the inclined plane 10d may not be a complete (111)B plane.

[0062] Fig.10 This is a diagram illustrating the state of introducing a dopant in a comparative example. The dopant is Zn. Fig. 9 , 10 The epitaxial growth and introduction of dopants shown result in the appearance of (111) B plane and (001) plane. Fig.11 This is a diagram for explaining a state in which a (111) B plane and a (001) plane are formed in a comparative example.

[0063] The (111)B plane and the (001) plane are planes on which the first buried layer grows easily. The portion where these planes with fast growth rates intersect becomes a transition plane 873 . Fig.12This is a diagram for explaining a state in which a transition surface 873 is formed in a comparative example. In the transition surface 873, since the material enters the (111)B plane and the (001) plane, the first buried layer is not easily grown.

[0064] Fig.13 8 is a cross-sectional view of a semiconductor device 800 according to a comparative example. The structure of the buried layer 820 of the semiconductor device 800 according to the comparative example is different from that of the semiconductor device 100. The buried layer 820 includes a first buried layer 822. A transition surface 873 is formed in the first buried layer 822. In a portion corresponding to the transition surface 873, the first buried layer 822 is thinner than in other portions.

[0065] In the semiconductor device 800, the first buried layer 822 may be interrupted due to the influence of the transition surface 873. Therefore, the first cladding layer 14 may be connected to the second buried layer 24. In addition, the semiconductor substrate 12 may be connected to the second buried layer 24. In this way, an n-n connection may be generated in the semiconductor device 800. Therefore, the operation of the semiconductor device 800 may be unstable.

[0066] In order to suppress the nn connection, it is considered to make the first buried layer 822 thicker. However, as mentioned above, if the first buried layer 822 is made thicker, the leakage current may increase. In addition, it may not be possible to ensure the thickness of the second buried layer 24. In addition, in order to suppress the nn connection, it is considered to increase the p-type dopant concentration. In this case, there is a high concentration of p-type dopant on the side of the active layer 16. At this time, the p-type dopant concentration of the active layer 16 increases, which may hinder high performance and stable operation.

[0067] In contrast, in the present embodiment, a protrusion 23 is provided in the first buried layer 22 adjacent to the boundary between the (111)B plane and the (001) plane. By forming the first buried layer 22 thicker than other parts at the portion corresponding to the transition surface, it is possible to suppress the first buried layer 22 from being interrupted. Therefore, a pnpn structure can be reliably formed, and the function of the first buried layer 22 can be ensured.

[0068] In addition, the portion other than the protrusion 23 of the first buried layer 22 can be made thinner. In particular, it is possible to suppress the second portion 22b of the first buried layer 22 covering the side surface 10e from being thickened in order to ensure the thickness of the first buried layer 22 at the transition surface 873. Therefore, leakage current can be suppressed. In addition, by thinning the first portion 22a of the first buried layer 22, the thickness of the second buried layer 24 can be ensured. Therefore, the capacitance of the semiconductor device 100 can be reduced. Therefore, it is possible to simultaneously achieve high performance and stable operation of the semiconductor device 100.

[0069] Here, the final thickness of the first buried layer 22 of the present embodiment is thicker at the portion where the protrusion 23 is provided than at other portions. However, this is not limiting, as long as the first buried layer 22 is not interrupted when the first buried layer 22 is formed. In other words, as a result of growing the second semiconductor layer 22d in a manner covering the first semiconductor layer 22c, the protrusion 23 may not be formed on the upper surface of the portion of the second semiconductor layer 22d covering the first semiconductor layer 22c due to the influence of the transition surface.

[0070] In other words, as long as the first buried layer 22 is not interrupted, Fig.13 Alternatively, the upper surface of the first embedded layer 22 may be flat.

[0071] exist Figure 8 In the state shown, the side surface of the table portion 10b is formed only by the vertical surface 10c. However, it is not limited to this. When the table portion 10b is just formed, the side surface of the table portion 10b may also have an inclined surface. In this case, the table portion 10b is just formed and the vertical surface 10c is formed. Fig. 9 , 10 The state during the epitaxial growth shown is the same. Therefore, in this case, a transition surface 873 is also generated.

[0072] In addition, nn connection is sometimes actually generated at a position away from the table portion 10b. Therefore, the protrusion 23 can be set at a position away from the boundary between the table portion 10b and the flat portion 10a. The protrusion 23 only needs to be set on the upper surface of the portion of the first embedded layer 22 that is set in a specified area of ​​the flat portion 10a. For example, the predetermined area is an area within the height of the table portion 10b from the boundary between the table portion 10b and the flat portion 10a in the upper surface 10f of the flat portion 10a. By providing the protrusion 23 in this area, nn connection can be effectively suppressed. In addition, the protrusion 23 can also be set at a position on the upper surface 10f of the flat portion 10a where nn connection is easily generated. Among them, the height of the table portion 10b is the height from the upper surface 10f of the flat portion 10a to the upper surface of the table portion 10b.

[0073] In the first step, the first semiconductor layer 22c may be formed in a region of the upper surface 10f of the flat portion 10a within the height of the mesa portion 10b from the boundary between the mesa portion 10b and the flat portion 10a. The distance between the protrusion 23 and the mesa portion 10b can be Figure 3 In the process shown, the portion of the flat portion 10a covered by the insulating film 52 is adjusted. In other words, the convex first semiconductor layer 22c is formed at the end of the insulating film 52. Therefore, the end of the insulating film 52 serves as a reference for the formation position of the protrusion 23.

[0074] In the present embodiment, InP is used for the main portion 10, the buried layer 20, and the contact layer 30. The main portion 10, the buried layer 20, and the contact layer 30 may be formed of a material other than InP.

[0075] In addition, in this embodiment, the semiconductor device 100 is described as a laser. The laser includes an EML (Electroabsorption Modulator Integrated Laser Diode). The semiconductor device 100 can also be applied to an EA (Electroabsorption) portion of the EML. The semiconductor device 100 can also be applied to a so-called optical semiconductor device.

[0076] Fig.14 2 is a cross-sectional view of a semiconductor device 200 according to a first variant of Embodiment 1. The structure of the first buried layer 222 of the semiconductor device 200 is different from that of the semiconductor device 100. The first buried layer 222 includes: a convex first semiconductor layer 222c provided directly below the protrusion 223; and a second semiconductor layer 222d covering the first semiconductor layer 222c. The first semiconductor layer 222c and the second semiconductor layer 222d are formed of different materials.

[0077] The first semiconductor layer 222c may be a layer having a higher carrier concentration than the second semiconductor layer 222d, for example. Thus, the first semiconductor layer 222c can be made thinner. Therefore, the first buried layer 222 can be made thinner.

[0078] Fig.15 2 is a cross-sectional view of a semiconductor device 300 according to a second variation of Embodiment 1. The structure of the first buried layer 322 of the semiconductor device 300 is different from that of the semiconductor device 100. In the first buried layer 322, the first semiconductor layer 322c has a plurality of layers. In other words, the first semiconductor layer 322c has a multilayer structure.

[0079] Thus, the characteristics of the first semiconductor layer 322c can be optimized and the carrier concentration can be further increased. Thus, the first semiconductor layer 322c can be made thinner. The first semiconductor layer 322c includes, for example, any one or more of Al, In, As, Ga, P, and Sb. In addition, the first semiconductor layer 322c includes, for example, Zn, Fe, and Be as a p-type dopant.

[0080] Fig.16 FIG. 4 is a cross-sectional view of a semiconductor device 400 according to a third variation of the first embodiment. In the semiconductor device 400, the side surface 10e of the mesa portion 10b may be formed only by the vertical surface 10c. In the case where the (111) B surface does not appear due to migration, it is also conceivable that Fig.16In this case, the transition surface 873 is more likely to appear than in the case where the (111) B surface appears. In this case, it is more important to suppress the discontinuity of the first buried layer 22 by the protrusion 23.

[0081] The present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present disclosure. In addition, the technical features described in the present embodiment can be used in combination as appropriate.

[0082] Description of Reference Numerals

[0083] 10...main part; 10a...flat part; 10b...table part; 10c...vertical surface; 10d...inclined surface; 10e...side surface; 10f...upper surface; 12...semiconductor substrate; 14...first cladding layer; 16...active layer; 18...second cladding layer; 20...buried layer; 22...first buried layer; 22a...first part; 22b...second part; 22c...first semiconductor layer; 22d...second semiconductor layer; 23...protrusion; 24...second buried layer; 26...third buried layer; 30...contact layer; 32... .Insulating film; 34...the first electrode; 40...the second electrode; 50...the insulating film; 52...the insulating film; 54...the photoresist; 71, 72...the epitaxial growth component; 100, 200...the semiconductor device; 222...the first buried layer; 222c...the first semiconductor layer; 222d...the second semiconductor layer; 223...the protrusion; 300...the semiconductor device; 322...the first buried layer; 322c...the first semiconductor layer; 400, 800...the semiconductor device; 820...the buried layer; 822...the first buried layer; 873...the transition surface.

Claims

1. A semiconductor device, characterized in that: have: a main portion having a semiconductor substrate, a first cladding layer provided on the semiconductor substrate and being a first type either of an n-type and a p-type, an active layer provided on the first cladding layer, a second cladding layer provided on the active layer and being a second type either of an n-type and a p-type, and having a flat portion and a mesa portion adjacent to the flat portion and protruding upward relative to the flat portion and including the active layer; a first embedded layer of the second type having a first portion covering the upper surface of the flat portion and a second portion covering the side surface of the mesa portion; The second buried layer of the first type is disposed on the first buried layer; a first electrode disposed above the mesa portion; and a second electrode disposed below the mesa portion, The first embedding layer has a protrusion on the upper surface of a portion of the upper surface of the flat portion provided in a region within a height of the mesa portion from a boundary between the mesa portion and the flat portion. The first buried layer includes: a convex first semiconductor layer provided directly below the protrusion; and a second semiconductor layer covering the side surface of the mesa portion, the upper surface of the flat portion, and the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein: A portion of the first embedding layer where the protrusion is provided is thicker than a portion of the first portion excluding the protrusion.

3. The semiconductor device according to claim 1 or 2, characterized in that: The protrusion is provided adjacent to the boundary between the mesa portion and the flat portion.

4. The semiconductor device according to claim 1 or 2, characterized in that: A portion of the first embedding layer where the protrusion is provided is thicker than the second portion.

5. The semiconductor device according to claim 1 or 2, characterized in that: The first semiconductor layer has a plurality of layers.

6. The semiconductor device according to claim 1 or 2, characterized in that: The side surface of the table portion has an inclined surface connected to the upper surface of the flat portion, A portion of the first embedding layer where the protrusion is provided is thicker than a portion of the first embedding layer covering the inclined surface.

7. A method for manufacturing a semiconductor device, characterized in that: have: A step of forming a first cladding layer of a first type, which is one of an n-type and a p-type, on a semiconductor substrate, forming an active layer on the first cladding layer, and forming a second cladding layer of a second type, which is the other of the n-type and the p-type, on the active layer, thereby forming a main portion having the semiconductor substrate, the first cladding layer, the active layer, and the second cladding layer; forming a flat portion and a mesa portion adjacent to the flat portion and protruding upward relative to the flat portion and including the active layer on the main portion; In a first step, a first semiconductor layer is formed as the second type and in a convex shape in a region within a height of the mesa portion from a boundary between the mesa portion and the flat portion on the upper surface of the flat portion; A second step of covering the side surfaces of the mesa portion, the upper surface of the flat portion, and the first semiconductor layer with the second type second semiconductor layer to form a first buried layer having the first semiconductor layer and the second semiconductor layer; forming a second buried layer of the first type on the first buried layer; forming a first electrode on the mesa portion; and A step of forming a second electrode below the mesa portion.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: In the second step, a protrusion is formed on the upper surface of a portion of the second semiconductor layer that covers the first semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, characterized in that: The first step comprises: forming the first semiconductor layer so as to cover the flat portion; A step of covering the upper surface and the side surface of the mesa portion and a portion of the upper surface of the first semiconductor layer from the boundary between the flat portion and the mesa portion to a predetermined distance with a photoresist; as well as The first semiconductor layer is etched using the photoresist as a mask to form the first semiconductor layer into a protrusion shape.

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