Method for manufacturing channel structure of semiconductor device

Abstract

The present invention provides a method for fabricating a channel structure for a semiconductor device, comprising: a first channel region and a second channel region, both formed between the source and drain regions of the GAA device; the first channel region formed on a first region of a substrate; the second channel region formed on a second region of the substrate; the first channel region comprising: a first channel layer and a plurality of second channel layers formed sequentially away from the substrate, with no contact between the second channel layers and between the plurality of second channel layers and the first channel layer; and the second channel region comprising: the first channel layer formed on the substrate. This method solves the problem of how to fabricate the channel structure of a semiconductor device using a simple process, achieving process simplification and reducing device defects.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for manufacturing a channel structure of a semiconductor device. Background Art

[0002] Currently, existing GAA devices include a hybrid channel layer of P-type and N-type channel layers. However, in the integration scheme of this hybrid channel layer, epitaxial layers of different materials need to be produced during epitaxy, which is a relatively complex process and prone to device defects. Therefore, developing a new semiconductor device channel structure with a simple process has become a technical focus that technicians in this field urgently need to solve. Summary of the Invention

[0003] The present invention provides a method for manufacturing a channel structure of a semiconductor device, so as to solve the problems of complex manufacturing process of a hybrid channel layer and easy occurrence of defects in the device.

[0004] According to a first aspect of the present invention, there is provided a channel structure of a semiconductor device, comprising: a first channel region and a second channel region, wherein the first channel region and the second channel region are both formed between a source region and a drain region of a GAA device;

[0005] The first channel region is formed on a first area of a substrate; the second channel region is formed on a second area of the substrate;

[0006] The first channel region includes: a first channel layer and a plurality of second channel layers sequentially formed in a direction away from the substrate, wherein the second channel layers are not in contact with each other and the plurality of second channel layers are not in contact with the first channel layer;

[0007] The second channel region includes: the first channel layer formed on the substrate.

[0008] Optionally, the material of the first channel layer is SiGe.

[0009] Optionally, the material of the second channel layer is Si.

[0010] Optionally, the first region is an N-type region, and the second region is a P-type region.

[0011] According to a second aspect of the present invention, there is provided a semiconductor device comprising the channel structure of the semiconductor device according to any one of the first aspects of the present invention.

[0012] According to a third aspect of the present invention, there is provided an electronic device comprising the semiconductor device according to the second aspect of the present invention.

[0013] According to a fourth aspect of the present invention, there is provided a method for manufacturing a channel structure of a semiconductor device, comprising:

[0014] providing a substrate;

[0015] Epitaxially growing a first channel layer and a stacked layer in sequence on the first and second regions of the substrate in a direction away from the substrate; the stacked layer includes a second channel layer and a sacrificial layer stacked at intervals;

[0016] doping the sacrificial layer to form a doped region;

[0017] Etching the first channel layer and the stacked layer to form a plurality of fin structures arranged along a first direction in the first region and the second region respectively;

[0018] forming a plurality of dummy gate stacks; the dummy gate stacks are formed on each fin structure and arranged along the second direction, each of the dummy gate stacks spanning each of the fin structures; the dummy gate stacks include a dummy gate and an inner isolation layer;

[0019] Etching the fin structure to form an etched cavity;

[0020] forming inner sidewalls on both sides of the sacrificial layer along the second direction;

[0021] forming a source region and a drain region in the etched cavity;

[0022] forming an interlayer dielectric layer; the interlayer dielectric layer is formed on top of the source region and the drain region and spans the source region and the drain region, and the source region and the drain region are arranged along the second direction;

[0023] removing the false grid;

[0024] Coating a photoresist on top of the stacked layer, exposing and developing the photoresist to form a patterned photoresist, so that the patterned photoresist covers the stacked layer in the first area and exposes the stacked layer in the second area;

[0025] Etching the stacked layer in the second region, so that the remaining first channel layer in the second region constitutes a second channel region in the second region;

[0026] The sacrificial layer in the first region is selectively etched to release the channel layer and keep the first channel layer intact; the remaining second channel layer and the first channel layer constitute the first channel region in the first region.

[0027] Optionally, the technology used for doping the sacrificial layer is epitaxial in-situ doping technology.

[0028] Optionally, the method of etching the stacked layer in the second region is an anisotropic etching method.

[0029] According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a method for manufacturing the channel structure of a semiconductor device according to any one of the fourth aspects of the present invention.

[0030] The present invention provides a channel structure of a semiconductor device, which directly uses the first channel layer as the channel structure of the second channel region; it solves the technical problem of how to use a simple manufacturing process to manufacture a structure of a hybrid transistor including a P-type region and an N-type region, and achieves the technical effect of simplifying the device process and reducing the generation of device defects.

[0031] Furthermore, the present invention provides a method for manufacturing a channel structure of a semiconductor device, which epitaxially grows a first channel layer and a stacked layer in both a first region and a second region on a substrate, and in the process of manufacturing the structure of the first channel region and the structure of the second channel region, etches away the sacrificial layer in the first region to use the first channel layer and the second channel layer as the structure of the first channel region, and etches away the stacked layer in the second region to directly use the first channel layer as the structure of the second channel region; this solves the problem of how to use a simple process to manufacture the channel structure of a semiconductor device, thereby achieving the simplification of the process and the reduction of device defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 It is a schematic flow chart of a method for manufacturing a channel structure of a semiconductor device provided by one embodiment of the present invention;

[0034] Figure 2 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure of a semiconductor device provided by an embodiment of the present invention Figure 1 ;

[0035] Figure 3 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure of a semiconductor device provided by an embodiment of the present invention Figure 2 ;

[0036] Description of reference numerals:

[0037] 101-substrate;

[0038] 102-first channel layer;

[0039] 103-sacrificial layer;

[0040] 104 - second channel layer. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0042] The terms "first," "second," "third," "fourth," and so on (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0043] In the currently available integrated solutions for mixed channel layers including P-type and N-type channel layers, epitaxial layers made of different materials need to be fabricated during epitaxy, which results in a relatively complex process and is prone to defects.

[0044] In view of this, the inventors of this application proposed a semiconductor device and a manufacturing method that combine the channel structure of a GAA transistor with the channel structure of a fin field-effect transistor; they solved the problem of how to use a simple process to manufacture the channel structure of a semiconductor device, and can achieve the effect of simplifying the process and reducing device defects.

[0045] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0046] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a device structure manufactured according to a method for manufacturing a channel structure of a semiconductor device provided in one embodiment of the invention; Figure 3 The portion within the middle dotted line 1 is the first channel region; Figure 3 The portion within the middle dotted line 2 is the second channel region; other specific structures of the semiconductor device, Figure 3 Not shown in the figure.

[0047] According to an embodiment of the present invention, a channel structure of a semiconductor device is provided, comprising: a first channel region and a second channel region, wherein the first channel region and the second channel region are both formed between a source region and a drain region of a GAA device;

[0048] The first channel region is formed on a first region of the substrate 101; the second channel region is formed on a second region of the substrate 101;

[0049] The first channel region includes: a first channel layer 102 and a plurality of second channel layers 104 formed in sequence in a direction away from the substrate 101, wherein the second channel layers 104 and the plurality of second channel layers 104 are not in contact with each other and the first channel layer 102 are not in contact with each other, wherein the first channel layer 102 is formed on the substrate 101, such as Figure 3 As shown;

[0050] The second channel region includes: the first channel layer 102 formed in a first area on the substrate 101, such as Figure 3 shown.

[0051] In one specific embodiment, the material of the first channel layer 102 is SiGe; the material of the second channel layer 104 is Si. Of course, the two structural layers can also be composed of other materials, and the present invention is not limited to this. Any implementation of the materials of the corresponding structural layers falls within the scope of protection of the present invention. In one specific embodiment, the first region is an N-type region, and the second region is a P-type region.

[0052] The present invention provides a channel structure of a semiconductor device, which directly uses the first channel layer 102 as the channel structure of the second channel region; it solves the technical problem of how to use a simple manufacturing process to manufacture a structure of a hybrid transistor including a P-type region and an N-type region, and achieves the technical effect of simplifying the device process and reducing the generation of device defects.

[0053] Secondly, according to another embodiment of the present invention, a semiconductor device is provided, comprising the channel structure of the semiconductor device according to any one of the aforementioned embodiments of the present invention.

[0054] According to other embodiments of the present invention, there is further provided an electronic device comprising the semiconductor device described in the foregoing embodiments of the present invention.

[0055] Also, please refer to Figure 1-Figure 3 According to another embodiment of the present invention, a method for manufacturing a channel structure of a semiconductor device is further provided. The flow chart of the method for manufacturing a channel structure of a semiconductor device is as follows: Figure 1 As shown, the method includes:

[0056] S11: providing a substrate 101;

[0057] S12: epitaxially growing a first channel layer 102 and a stacked layer in sequence on the first and second regions of the substrate 101 in a direction away from the substrate 101; the stacked layer includes a second channel layer 104 and a sacrificial layer 103 stacked at intervals, such as Figure 2 As shown; In a specific embodiment, the sacrificial layer 103 is made of SiGe, but it can also be made of other materials. The present invention is not limited thereto, and any material implementation of the sacrificial layer 103 that can achieve the purpose of the present invention is within the scope of protection of the present invention;

[0058] S13: doping the sacrificial layer 103 to form a doped region; in a specific embodiment, the technique used to dope the sacrificial layer 103 is epitaxial in-situ doping. Of course, other doping techniques may also be used, and the present invention is not limited thereto. Any implementation of the doping technique that can achieve the purpose of the present invention is within the scope of protection of the present invention; since the epitaxial sacrificial layer 103 is doped, when the sacrificial layer 103 material and the first channel layer 102 material are both SiGe, the etching selectivity ratio between the first channel layer 102 and the sacrificial layer 103 is changed;

[0059] S14: etching the first channel layer 102 and the stacked layer to form a plurality of fin structures arranged along a first direction in the first region and the second region respectively;

[0060] S15: forming a plurality of dummy gate stacks; the dummy gate stacks are formed on each fin structure and arranged along the second direction, and each of the dummy gate stacks spans each of the fin structures; the dummy gate stacks include a dummy gate and an inner isolation layer;

[0061] S16: etching the fin structure to form an etched cavity;

[0062] S17: forming inner sidewalls on both sides of the sacrificial layer 103 along the second direction;

[0063] S18: forming a source region and a drain region in the etched cavity;

[0064] S19: forming an interlayer dielectric layer; the interlayer dielectric layer is formed on top of the source region and the drain region and spans the source region and the drain region, and the source region and the drain region are arranged along the second direction;

[0065] S20: removing the dummy gate;

[0066] S21: coating a photoresist on top of the stacked layer, exposing and developing the photoresist to form a patterned photoresist, so that the patterned photoresist covers the stacked layer in the first area and exposes the stacked layer in the second area;

[0067] S22: etching the stacked layer in the second region, and the remaining first channel layer 102 in the second region constitutes a second channel region in the second region. The structure of the second channel region is as follows: Figure 3 As shown. In a specific embodiment, the method for etching the stacked layer in the second region is anisotropic etching. Of course, other etching methods can also be used, and the present invention is not limited thereto. Any etching method that can achieve the purpose of the present invention is within the scope of protection of the present invention;

[0068] S23: Selectively etch the sacrificial layer 103 in the first region to release the channel layer and keep the first channel layer 102 intact; the remaining second channel layer 104 and the first channel layer 102 constitute the first channel region of the first region. The structure of the first channel region is as follows: Figure 3 As shown;

[0069] Among them, since the sacrificial layer 103 material is doped in step S13, the etching selectivity of the sacrificial layer 103 and the first channel layer 102 is changed, so when the sacrificial layer 103 in the first area is selectively etched to release the channel layer, the first channel layer 102 in the first area and the second area can be kept intact.

[0070] The present invention provides a method for manufacturing a channel structure of a semiconductor device, which combines the channel structure of a GAA transistor with the channel structure of a fin field-effect transistor. Specifically, a first channel layer 102 and a stacked layer are epitaxially grown in both a first region and a second region on a substrate 101, and the stacked layer in the second region is etched away during the process of manufacturing the structure of the first channel region and the structure of the second channel region, so that the first channel layer 102 is directly used as the structure of the second channel region. This solves the problem of how to use a simple process to manufacture the channel structure of a semiconductor device, thereby achieving the effect of simplifying the process and reducing device defects.

[0071] According to other embodiments of the present invention, a method for manufacturing a semiconductor device is further provided, comprising: a method for manufacturing the channel structure of the semiconductor device according to any one of the aforementioned embodiments of the present invention.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a channel structure of a semiconductor device, characterized in that: include: providing a substrate; epitaxially growing a first channel layer and a stacked layer in sequence on the first region and the second region of the substrate in a direction away from the substrate; The stacked layer includes a second channel layer and a sacrificial layer stacked at intervals; doping the sacrificial layer to form a doped region; Etching the first channel layer and the stacked layer to form a plurality of fin structures arranged along a first direction in the first region and the second region respectively; forming a plurality of dummy gate stacks; A dummy gate stack is formed on each fin structure and arranged along the second direction, and each of the dummy gate stacks spans across each of the fin structures; The dummy gate stack includes a dummy gate and an inner isolation layer; Etching the fin structure to form an etched cavity; forming inner sidewalls on both sides of the sacrificial layer along the second direction; forming a source region and a drain region in the etched cavity; forming an interlayer dielectric layer; the interlayer dielectric layer is formed on top of the source region and the drain region and spans the source region and the drain region, and the source region and the drain region are arranged along the second direction; removing the false grid; Coating a photoresist on top of the stacked layer, exposing and developing the photoresist to form a patterned photoresist, so that the patterned photoresist covers the stacked layer in the first area and exposes the stacked layer in the second area; Etching the stacked layer in the second region, so that the remaining first channel layer in the second region constitutes a second channel region in the second region; The sacrificial layer in the first region is selectively etched to release the channel layer and keep the first channel layer intact; the remaining second channel layer and the first channel layer constitute a first channel region in the first region.

2. The method for manufacturing a channel structure of a semiconductor device according to claim 1, wherein: The technology used for doping the sacrificial layer is epitaxial in-situ doping technology.

3. The method for manufacturing a channel structure of a semiconductor device according to claim 2, wherein: The method of etching the stacked layers in the second region is an anisotropic etching method.

4. A method for manufacturing a semiconductor device, characterized in that: include: A method for manufacturing a channel structure of a semiconductor device according to any one of claims 1 to 3.

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