A pre-charge circuit with timing control function for space flight

Abstract

The application discloses a pre-charging circuit with time sequence control function for spaceflight, comprising: a main power circuit, a pre-charging circuit and a pre-charging completion indication circuit; wherein the main power circuit is connected in parallel with the pre-charging circuit, the pre-charging circuit provides a switching signal for the on-off of a P-MOS tube Q2 in the main power circuit; the pre-charging completion indication circuit is connected with the pre-charging circuit, the pre-charging completion indication circuit plays a role of charging completion indication and controls the enable of the pre-charging circuit, thereby avoiding the persistent oscillation phenomenon caused by the working of the pre-charging circuit in the pre-charging process. The application can achieve the purpose of safely and reliably inhibiting the large inrush current caused by the bus power-on moment.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of switching power supply technology in aerospace, and particularly relates to a pre-charging circuit with time sequence control function for aerospace. BACKGROUND

[0002] In order to suppress the influence of the electric device on the input bus, a capacitor filter circuit is designed at the input end of the power supply. At the moment of connecting the bus, due to the capacitive characteristics of the capacitor, a large instantaneous current, that is, the inrush current, will be introduced at the moment of connecting the bus. The inrush current usually can reach several tens of times or even hundreds of times of the static working current of the power supply. The pressure drop generated by the large inrush current on the bus bar can cause the voltage at the power supply end of the device to drop sharply, thereby forcing the device to restart and the system to collapse. Meanwhile, the instantaneous characteristics and peak characteristics of the inrush current also cause troubles in the selection of the onboard power distribution system. Therefore, in order to prevent the damage of the inrush current to the onboard device, the satellite construction specification has a strict regulation on the inrush current: the starting current rising slope of the device is not greater than 10 A / s, and the duration is not greater than 5 ms (3 ms for some models), which is limited to 1.5 times of the corresponding rated current or 2 A (the larger one) within; within 10 μs, the instantaneous starting current cannot exceed 10 times of the average steady-state input current. 5

[0003] In order to suppress the starting inrush current, the traditional methods for suppressing the starting inrush current mainly include the following three methods:

[0004] (1) NTC suppresses the starting inrush current: one or several NTC (negative temperature coefficient) current limiting resistors are connected in series on the input bus. Since the resistance value of the NTC resistor decreases with the increase of temperature, at the start of the power supply, the NTC resistor is at room temperature and has a high resistance value, which can effectively limit the current;

[0005] (2) Power resistor and relay in parallel suppress the starting inrush current: a relay is connected in parallel across the current limiting power resistor of the input bus. When the power is turned on, the current is limited through the power resistor to charge the capacitor, and when the power supply is powered on and enters the normal output state, the relay is closed, and at this time the input bus current mainly flows through the relay;

[0006] (3) Soft start technology suppresses the starting inrush current: MOSFET is used to suppress the starting inrush current, and the effect is very obvious, especially for capacitive loads. The scheme slowly increases the output voltage of the power supply through soft start, that is, by reducing the rising slope of the output voltage of the power supply, the power supply output capacitor or load is slowly charged, so as to reduce the starting inrush current.

[0007] ​Among the above three traditional methods, the method of using MOSFET to suppress surge current has a fast response speed and higher efficiency. However, this method has a high requirement for the safe working area of MOSFET. If the type selection is improper, it is difficult to accurately suppress the surge current, and the MOSFET is easily burned out, affecting the system work. SUMMARY

[0008] The technical problem solved by the present application is to overcome the shortcomings of the prior art and provide a spaceflight pre-charging circuit with timing control function, which can safely and reliably suppress the large surge current caused by the bus power-on moment, and provide a charging completion indication signal, which can enable the subsequent circuit to avoid the persistent oscillation phenomenon caused by the early work of the subsequent circuit during the charging process.

[0009] The purpose of the present application is achieved by the following technical scheme: a spaceflight pre-charging circuit with timing control function, comprising: a main power circuit, a pre-charging circuit, and a pre-charging completion indication circuit; wherein the main power circuit is connected in parallel with the pre-charging circuit, and the pre-charging circuit provides a switching signal for the on-off of a P-MOS tube Q2 in the main power circuit; the pre-charging completion indication circuit is connected with the pre-charging circuit, and the pre-charging completion indication circuit plays a role of charging completion indication and controls the enablement of the pre-charging circuit to avoid the persistent oscillation phenomenon caused by the work of the pre-charging circuit during the pre-charging process.

[0010] In the above-mentioned spaceflight pre-charging circuit with timing control function, the main power circuit comprises a MOS tube switching circuit and a locking circuit, wherein the MOS tube switching circuit and the locking circuit are connected.

[0011] In the above-mentioned spaceflight pre-charging circuit with timing control function, the MOS tube switching circuit comprises a P-MOS tube Q2, a resistor R4, a resistor R10, a capacitor C1, and a capacitor C4; wherein the resistor R4 and the capacitor C1 are connected in parallel between the s pole of the P-MOS tube Q2 and the g pole of the P-MOS tube Q2, the d pole of the P-MOS tube Q2 is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with one end of the resistor R10, and the other end of the resistor R10 is connected with the g pole of the P-MOS tube Q2.

[0012] In the pre-charge circuit with timing control function for spaceflight, the locking circuit comprises a PNP transistor Q1, a resistor R3, a resistor R1 and a resistor R2, wherein the E pole of the PNP transistor Q1 is connected with the s pole of the P-MOS transistor Q2, the C pole of the PNP transistor Q1 is connected with the g pole of the P-MOS transistor Q2, one end of the resistor R1 is connected with the E pole of the PNP transistor Q1, the other end of the resistor R1 is connected with one end of the resistor R3 and one end of the resistor R2, the other end of the resistor R3 is connected with the B pole of the transistor Q1, and the other end of the resistor R2 is connected with the pre-charge circuit.

[0013] In the pre-charge circuit with timing control function for spaceflight, the pre-charge circuit comprises a MOS transistor driving circuit and a pre-charge delay-off circuit, wherein the MOS transistor driving circuit and the pre-charge delay-off circuit are connected.

[0014] In the pre-charge circuit with timing control function for spaceflight, the MOS transistor driving circuit comprises a P-MOS transistor Q4, a resistor R8, a resistor R9, a capacitor C3 and a resistor R5, wherein the resistor R5 is connected in series between the positive end Vin+ of the power bus and the s pole of the P-MOS transistor Q4, the capacitor C3 and the resistor R9 are connected in parallel between the s pole of the P-MOS transistor Q4 and the g pole of the P-MOS transistor Q4, and one end of the resistor R8 is connected with the g pole of the P-MOS transistor Q4.

[0015] In the pre-charge circuit with timing control function for spaceflight, the pre-charge delay-off circuit comprises an NPN transistor Q3, a resistor R7, a capacitor C2, a clamping diode D1 and a resistor R6, wherein the C pole of the NPN transistor Q3 is connected with the other end of the resistor R8, the E pole of the NPN transistor Q3 is grounded, the resistor R6, the capacitor C2 and the resistor R7 are connected in series between the positive end Vin+ of the power bus and the B pole of the NPN transistor Q3, the cathode of the clamping diode D1 is connected between the capacitor C2 and the resistor R7, and the anode of the clamping diode D1 is grounded.

[0016] In the pre-charge circuit with timing control function for spaceflight, the pre-charge completion indication circuit comprises a PNP transistor Q5, a resistor R11, a resistor R12, a resistor R13 and a capacitor C5, wherein the resistor R12 and the capacitor C5 are connected in parallel between the E pole of the PNP transistor Q5 and the B pole of the PNP transistor Q5, one end of the resistor R11 is connected with the B pole of the PNP transistor Q5, the other end of the resistor R11 is connected with one end of the resistor R5, and the C pole of the PNP transistor Q5 is grounded through the resistor R13.

[0017] In the pre-charge circuit with time sequence control function for space flight, when the bus is connected, the main power circuit is turned off due to the existence of capacitor C1, and the pre-charge circuit is started first, and the main power circuit is clamped by PNP transistor Q1.

[0018] In the pre-charge circuit with time sequence control function for space flight, the pre-charge circuit can avoid the damage of P-MOS transistor Q2 in the main power circuit due to the over-high inrush current in the inrush time.

[0019] Compared with the prior art, the present application has the following advantages:

[0020] (1) The present application can solve the short-time but large-amplitude inrush current generated in the moment of bus connection;

[0021] (2) The present application can avoid the damage of MOS transistor in the main power circuit due to the over-high inrush current in the inrush time, and is suitable for high-level places such as aviation and space flight;

[0022] (3) The present application has time sequence control function, which ensures that the MOS transistor in the pre-charge circuit is turned on before the main power switch tube is turned on, and the filter capacitor is charged, and then the main power MOS tube is turned on;

[0023] (4) The present application has a charging completion indication function, which is used as an enable signal to prevent the continuous oscillation problem caused by the working of the subsequent power equipment during the inrush period. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the application. Moreover, like reference numerals designate similar parts throughout the several views in the drawings. In the drawings:

[0025] Figure 1 The pre-charge circuit structure with time sequence control function for the embodiment of the present application;

[0026] Figure 2 The main power circuit principle diagram for the embodiment of the present application;

[0027] Figure 3 The pre-charge circuit principle diagram for the embodiment of the present application;

[0028] Figure 4 The pre-charge completion indication circuit principle diagram for the embodiment of the present application;

[0029] Figure 5 The simulation waveform diagram for the embodiment of the present application. Detailed Implementation

[0030] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a schematic diagram of a pre-charging circuit with timing control function according to an embodiment of the present invention. Figure 1 As shown, the aerospace pre-charging circuit with timing control function is characterized by comprising: a main power circuit, a pre-charging circuit, and a pre-charging completion indicator circuit; wherein, the main power circuit and the pre-charging circuit are connected in parallel, and the pre-charging circuit provides a switching signal for the on / off state of the P-MOS transistor Q2 in the main power circuit; the pre-charging completion indicator circuit is connected to the pre-charging circuit, and the pre-charging completion indicator circuit serves as a charging completion indicator and controls the enabling of the pre-charging circuit to avoid continuous oscillation caused by the pre-charging circuit operating during the pre-charging process.

[0032] like Figure 1 As shown, the main power circuit includes a MOSFET switching circuit and a latching circuit, wherein the MOSFET switching circuit and the latching circuit are connected.

[0033] like Figure 2 As shown, the MOS transistor switching circuit includes a P-MOS transistor Q2, resistors R4 and R10, and capacitors C1 and C4. Resistor R4 and capacitor C1 are connected in parallel between the source (s) and gate (g) of P-MOS transistor Q2. The drain (d) of P-MOS transistor Q2 is connected to one end of capacitor C4, and the other end of capacitor C4 is connected to one end of resistor R10. The other end of resistor R10 is connected to the gate (g) of P-MOS transistor Q2.

[0034] like Figure 2As shown, the locking circuit includes PNP type transistor Q1, resistor R3, resistor R1 and resistor R2, wherein the E pole (emitter) of the PNP type transistor Q1 is connected with the s pole (source) of the P-MOS tube Q2, the C pole (collector) of the PNP type transistor Q1 is connected with the g pole (gate) of the P-MOS tube Q2, one end of the resistor R1 is connected with the E pole (emitter) of the PNP type transistor Q1, the other end of the resistor R1 is connected with one end of the resistor R3 and one end of the resistor R2, the other end of the resistor R3 is connected with the B pole (base) of the transistor Q1, and the other end of the resistor R2 is connected with the pre-charge circuit.

[0035] Specifically, the main power circuit includes the power switch MOS tube Q2 capable of controlling the main power on-off, the transistor Q1 capable of locking the state of Q2, and resistors R1, R2, R3, R4 and the slow start capacitor C1. The transistor Q1 clamps the on state of the MOS tube Q2, and Q1 is controlled by the voltage across the current limiting resistor R5 and the ratio of the voltage dividing resistors R1 and R2; the pre-charge circuit is composed of a pre-charge off delay circuit composed of the MOS tube Q4, the slow start capacitor C3, the resistors R6, R7, the capacitor C2 and the diode D1, the current limiting resistor R5 and the voltage dividing resistors R8, R9. The pre-charge off delay circuit composed of the resistors R6, R7, the capacitor C2 and the diode D1 determines the working time of the pre-charge circuit. The current limiting resistor R5 determines the maximum charging current. The resistors R8, R9 provide the gate voltage for the pre-charge MOS tube Q4; the pre-charge completion indication circuit is composed of the transistor Q5, the current limiting resistor R13, the voltage dividing resistors R11, R12 and the filter capacitor C5, and the on state of the transistor Q5 is determined by the voltage across the current limiting resistor R5 and the ratio of the voltage dividing resistors R11, R12.

[0036] As shown in the figure, Figure 2 The P-MOS tube Q2 is used for main power path control. At the moment of bus connection, the main power circuit is started due to the existence of the capacitor C1, the pre-charge circuit is started first, the voltage across the current limiting resistor R5 is divided by the voltage dividing resistors R1, R2, and then the transistor Q1 is turned on, thereby clamping the MOS tube Q2 in the main power circuit, so that Q2 maintains the off state; after the pre-charge circuit is charged, the transistor Q1 is turned off, and the main power circuit MOS tube is no longer clamped by Q1 and is turned on.

[0037] The pre-charge circuit includes a MOS tube driving circuit and a pre-charge delay off circuit; wherein the MOS tube driving circuit and the pre-charge delay off circuit are connected.

[0038] As shown in the figure, Figure 3As shown, the MOS transistor drive circuit includes a P-MOS transistor Q4, resistors R8 and R9, capacitor C3, and resistor R5. Resistor R5 is connected in series between the positive terminal Vin+ of the power bus and the source (s) of the P-MOS transistor Q4. Capacitor C3 and resistor R9 are connected in parallel between the source (s) and gate (g) of the P-MOS transistor Q4. One end of resistor R8 is connected to the gate (g) of the P-MOS transistor Q4.

[0039] like Figure 3 As shown, the pre-charge delay shutdown circuit includes an NPN transistor Q3, a resistor R7, a capacitor C2, a clamping diode D1, and a resistor R6. The collector (C) of the NPN transistor Q3 is connected to the other end of the resistor R8, and the emitter (E) of the NPN transistor Q3 is grounded. Resistors R6, C2, and R7 are connected in series between the positive terminal Vin+ of the power bus and the base (B) of the NPN transistor Q3. The cathode of the clamping diode D1 is connected between capacitor C2 and resistor R7, and the anode of the clamping diode D1 is grounded.

[0040] Figure 3 This is a schematic diagram of the pre-charge circuit of the present invention. Its function is to protect the MOSFETs in the main power circuit from damage caused by excessive surge current during the surge period. Since the capacitance of capacitor C3 is much smaller than that of C1, after the bus is connected, the MOSFET Q4 in the pre-charge circuit will turn on before the MOSFETs in the main power circuit. The bus charges the capacitors in the subsequent circuit through the current-limiting resistor R5. As the voltage of the subsequent stage increases, the charging current will continuously decrease. When the voltage generated across resistor R5 is insufficient to turn on Q1 in the main power circuit, the pre-charge process ends, and the main power circuit then turns on. Because the DC blocking capacitor C2 is large enough, the pre-charge circuit has sufficient time to charge the capacitors in the subsequent circuit to a level close to the bus voltage. When the voltage across capacitor C2 is insufficient to keep transistor Q3 on, the pre-charge circuit ends its operation.

[0041] like Figure 4 As shown, the pre-charge completion indicator circuit includes a PNP transistor Q5, resistors R11, R12, and R13, and a capacitor C5. Resistor R12 and capacitor C5 are connected in parallel between the emitter (E) and base (B) of PNP transistor Q5. One end of resistor R11 is connected to the base (B) of PNP transistor Q5, and the other end of resistor R11 is connected to one end of resistor R5. The collector (C) of PNP transistor Q5 is grounded through resistor R13.

[0042] Figure 4The pre-charge indication completion circuit diagram is used for indicating the pre-charge completion. When the pre-charge circuit works, the voltage across the current-limiting resistor R5 makes the transistor Q5 conduct through the voltage division resistors R11 and R12, and the voltage across the resistor R13 is generated after the transistor Q5 conducts, which can be used for enabling the subsequent circuit. When the voltage exists across the resistor R13, the subsequent circuit is disabled, and vice versa, so that the subsequent circuit is in the disabled state during the pre-charge process, thereby avoiding the continuous oscillation phenomenon caused by the working of the subsequent circuit during the pre-charge process.

[0043] Figure 5 The schematic diagram of the key circuit simulation waveform of the application is shown in the figure. Figure 5 As shown in the figure, from top to bottom, they are the bus voltage waveform, the voltage waveform of the subsequent circuit, the surge current waveform and the pre-charge completion indication voltage waveform. When the bus is connected, the pre-charge circuit is started first, the subsequent voltage is slowly raised, the surge current is reduced with the rise of the subsequent voltage, and the pre-charge completion indication circuit continuously outputs high voltage during this period; after the subsequent voltage approaches the bus voltage, the voltage drop formed by the surge current on the current-limiting resistor is not enough to continue to clamp the main power circuit MOS tube, at this time the main power MOS tube is turned on, and the pre-charge completion indication circuit outputs low voltage.

[0044] The pre-charge circuit and the pre-charge completion indication circuit are connected in parallel across the main power circuit. Before the main power switch tube is turned on, the MOS tube in the pre-charge circuit is turned on to charge the capacitor, and after the capacitor is charged, the main power MOS tube is turned on, which solves the surge current generated at the moment of turning on the switch tube, and avoids the damage of the MOS tube in the main power circuit caused by the over-high surge current in the surge time. In addition, the pre-charge indication completion circuit can control the enablement of the subsequent circuit, avoid the continuous oscillation phenomenon caused by the working of the subsequent circuit during the surge period, and has important significance for improving the reliability and safety of power distribution.

[0045] Although the application has been disclosed with the above preferred embodiments, it is not intended to limit the application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the application by using the disclosed methods and technical contents without departing from the spirit and scope of the application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application, which does not deviate from the technical solutions of the application, belongs to the protection scope of the technical solutions of the application.

Claims

1. A pre-charge circuit for aerospace applications with timing control function, characterized in that... include: Main power circuit, pre-charge circuit, pre-charge completion indicator circuit; among which, The main power circuit is connected in parallel with the pre-charge circuit, and the pre-charge circuit provides a switching signal for the P-MOS transistor Q2 in the main power circuit to be turned on or off. The pre-charge completion indicator circuit is connected to the pre-charge circuit. The pre-charge completion indicator circuit serves as a charging completion indicator and controls the enabling of the pre-charge circuit to avoid continuous oscillation caused by the operation of the pre-charge circuit during the pre-charge process. The MOS transistor drive circuit includes a P-MOS transistor Q4, resistor R8, resistor R9, capacitor C3, and resistor R5; wherein, The resistor R5 is connected in series between the positive terminal Vin+ of the power bus and the source (s) terminal of the P-MOS transistor Q4. The capacitor C3 and the resistor R9 are connected in parallel between the source (s) terminal and the gate (g) terminal of the P-MOS transistor Q4. One end of the resistor R8 is connected to the gate (g) terminal of the P-MOS transistor Q4. The pre-charge delay shutdown circuit includes an NPN transistor Q3, a resistor R7, a capacitor C2, a clamping diode D1, and a resistor R6; wherein... The collector (C) of the NPN transistor Q3 is connected to the other end of the resistor R8, the emitter (E) of the NPN transistor Q3 is grounded, the resistor R6, the capacitor C2, and the resistor R7 are connected in series between the positive terminal Vin+ of the power bus and the base (B) of the NPN transistor Q3, the cathode of the clamping diode D1 is connected between the capacitor C2 and the resistor R7, and the anode of the clamping diode D1 is grounded. The pre-charge completion indicator circuit includes a PNP transistor Q5, resistors R11, R12, and R13, and a capacitor C5; wherein, The resistor R12 and the capacitor C5 are connected in parallel between the emitter (E) and base (B) of the PNP transistor Q5. One end of the resistor R11 is connected to the base (B) of the PNP transistor Q5, and the other end of the resistor R11 is connected to one end of the resistor R5. The collector (C) of the PNP transistor Q5 is grounded through the resistor R13. When the pre-charge circuit is working, the voltage across the current-limiting resistor R5 turns on the transistor Q5 through the voltage divider resistors R11 and R12. After Q5 turns on, a voltage is generated across the resistor R13. This voltage can be used to enable the subsequent circuit. When there is a voltage across R13, it is used to disable the subsequent circuit, and vice versa, it enables the circuit to work. This ensures that the subsequent circuit is disabled during the pre-charge process, so as to avoid the continuous oscillation caused by the operation of the subsequent circuit during the pre-charge process. When the pre-charge circuit is working, the voltage across the current-limiting resistor R5 turns on the transistor Q5 through the voltage divider resistors R11 and R12. After Q5 turns on, a voltage is generated across the resistor R13, which can be used to enable the subsequent circuit.

2. The aerospace pre-charge circuit with timing control function according to claim 1, characterized in that: The main power circuit includes a MOSFET switching circuit and a locking circuit, wherein the MOSFET switching circuit and the locking circuit are connected.

3. The aerospace pre-charge circuit with timing control function according to claim 2, characterized in that: The MOSFET switching circuit includes a P-MOSFET Q2, resistor R4, resistor R10, capacitor C1, and capacitor C4; wherein, The resistor R4 and the capacitor C1 are both connected in parallel across the source (s) and gate (g) terminals of the P-MOS transistor Q2. The drain (d) terminal of the P-MOS transistor Q2 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is connected to one end of the resistor R10. The other end of the resistor R10 is connected to the gate (g) terminal of the P-MOS transistor Q2.

4. The aerospace pre-charge circuit with timing control function according to claim 2, characterized in that: The locking circuit includes a PNP transistor Q1, resistors R3, R1, and R2, wherein... The emitter (E) of the PNP transistor Q1 is connected to the source (S) of the P-MOS transistor Q2, the collector (C) of the PNP transistor Q1 is connected to the gate (G) of the P-MOS transistor Q2, one end of the resistor R1 is connected to the emitter (E) of the PNP transistor Q1, the other end of the resistor R1 is connected to one end of the resistor R3 and one end of the resistor R2, the other end of the resistor R3 is connected to the base (B) of the transistor Q1, and the other end of the resistor R2 is connected to the pre-charge circuit.

5. The aerospace pre-charge circuit with timing control function according to claim 1, characterized in that: The pre-charge circuit includes a MOS transistor driving circuit and a pre-charge delay shutdown circuit; wherein the MOS transistor driving circuit and the pre-charge delay shutdown circuit are connected.

6. The aerospace pre-charge circuit with timing control function according to claim 4, characterized in that: When the bus is connected, the main power circuit is powered on, but the pre-charge circuit starts first due to the presence of capacitor C1, and the main power circuit is turned off by the clamping of PNP transistor Q1.

7. The aerospace pre-charge circuit with timing control function according to claim 1, characterized in that: The purpose of the pre-charge circuit is to prevent the P-MOS transistor Q2 in the main power circuit from being damaged by excessive surge current during the surge period.

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