Apparatus, device, and method for complex multiplication and accumulation and machine readable medium

Abstract

Apparatuses and methods for complex multiplication and accumulation are disclosed. An embodiment of the invention is a processor including execution circuitry to compute a result of a complex multiply-accumulate of a first complex number, a second complex number, and a third complex number in response to a decoded instruction. The computation includes a first operation to compute a first term of a real component of the result and a first term of an imaginary component of the result. The computation also includes a second operation to compute a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder to decode the instruction to generate the decoded instruction, and first, second, and source and destination registers to provide the first, second, and third complex numbers, respectively.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of computer processors. More particularly, embodiments relate to apparatus and methods for complex multiplication and accumulation. Background Technology

[0002] The instruction set, or instruction set architecture (ISA), is the part of a computer architecture relevant to programming. It includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" in this text generally refers to macro-instructions, which are instructions provided to the processor for execution. These are the opposite of micro-instructions or micro-operations, which are the result of the processor decoder decoding macro-instructions. Micro-instructions or micro-operations can be configured to instruct execution units on the processor to perform operations to implement the logic associated with macro-instructions.

[0003] An instruction set assembly (ISA) differs from a microarchitecture, which is a collection of processor design techniques used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, Pentium 4 processor, Core TM Processors, and processors from Advanced Micro Devices, Inc. in Sunnyvale, California, implement nearly the same version of the x86 instruction set (with some extensions added in newer versions), but with different internal designs. For example, the same register architecture of the ISA can be implemented differently in different microarchitectures using well-known techniques, including dedicated physical registers and one or more dynamically allocated physical registers using register renaming mechanisms such as register alias tables (RATs), reorder buffers (ROBs), and retired register files. Unless otherwise stated, the phrases register architecture, register file, and register are used herein to refer to what is visible to the software / programmer and how registers are specified by instructions. Where distinction is required, the adjectives “logical,” “architectural,” or “software visible” will be used to indicate registers / files within a register architecture, while different adjectives will be used to specify registers (e.g., physical registers, reorder buffers, retired registers, register pools) within a given microarchitecture. Attached Figure Description

[0004] The invention is illustrated in the figures by way of example and not limitation, in which the same reference numerals indicate similar elements, and in the figures:

[0005] Figure 1A-1BThis is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention;

[0006] Figure 1A This is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to an embodiment of the present invention;

[0007] Figure 1B It is a block diagram illustrating a general vector-friendly instruction format and its B-type instruction template according to an embodiment of the present invention;

[0008] Figure 2A This is a block diagram illustrating an exemplary specific vector-friendly instruction format according to an embodiment of the present invention;

[0009] Figure 2B It is a block diagram illustrating the fields of a specific vector-friendly instruction format 200 constituting the full opcode field 174 according to an embodiment of the present invention;

[0010] Figure 2C It is a block diagram illustrating the fields of a specific vector-friendly instruction format 200 constituting register index field 144 according to an embodiment of the present invention;

[0011] Figure 2D It is a block diagram illustrating the fields of a specific vector-friendly instruction format 200 constituting an amplification operation field 150 according to an embodiment of the present invention;

[0012] Figure 3 This is a block diagram of a register architecture 300 according to an embodiment of the present invention;

[0013] Figure 4A It is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming and unordered release / execution pipeline according to embodiments of the present invention;

[0014] Figure 4B It is a block diagram illustrating an exemplary embodiment of an ordered architecture core to be included in a processor according to an embodiment of the present invention, as well as exemplary register renaming and out-of-order release / execution of the architecture core;

[0015] Figure 5A -B illustrates a block diagram of a more specific exemplary core architecture, which will be one of several logical blocks in the chip (including other cores of the same type and / or different types);

[0016] Figure 5A This is a block diagram of a single processor core according to an embodiment of the present invention, together with its connection to the on-die interconnect network 502 and a partial subset thereof, together with its Level 2 (L2) cache 504;

[0017] Figure 5B This is according to an embodiment of the present invention. Figure 5A An expanded view of a portion of the processor core;

[0018] Figure 6 This is a block diagram of a processor 600 according to an embodiment of the present invention. The processor 600 may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0019] Figure 7-10 This is a block diagram of an exemplary computer architecture;

[0020] Figure 7 A block diagram of a system according to an embodiment of the present invention is shown;

[0021] Figure 8 This is a block diagram of a first more specific exemplary system according to an embodiment of the present invention;

[0022] Figure 9 This is a block diagram of a second, more specific, exemplary system according to an embodiment of the present invention;

[0023] Figure 10 This is a block diagram of a SoC according to an embodiment of the present invention;

[0024] Figure 11 It is a block diagram that contrasts the use of a software instruction converter according to an embodiment of the present invention for converting binary instructions in a source instruction set into binary instructions in a target instruction set.

[0025] Figure 12 This is a block diagram of an apparatus for multiplying and accumulating complex numbers according to an embodiment of the present invention;

[0026] Figure 13 This is a flowchart of a method for multiplying and accumulating complex numbers according to an embodiment of the present invention. Detailed Implementation

[0027] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0028] References to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the stated particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is claimed that, whether explicitly described or not, those skilled in the art will understand that such feature, structure, or characteristic can be affected by other embodiments.

[0029] As used in this description and claims, and unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” “third,” etc., to describe an element merely indicates that a particular instance of the element or different instances of the same element are being mentioned, and is not intended to imply that the element described in this way must be in a particular sequence in time, space, hierarchy, or any other way.

[0030] Instructions to be executed by a processor core according to embodiments of the present invention can be embodied in the “generic vector-friendly instruction format” detailed below. In other embodiments, such a format is not utilized; instead, another instruction format is used. However, the following descriptions of write-mask registers, various data transformations (swizzling, broadcasting, etc.), addressing, etc., are generally applicable to the descriptions of embodiments of the above-described instructions(s). Furthermore, exemplary systems, architectures, and pipelines are detailed below. Instructions can be executed in such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0031] Instruction set

[0032] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., the number of bits, the position of bits) to specify, among many other things, the operation to be performed (e.g., the opcode) and the operand(s) to which the operation will be performed, and / or (e.g., multiple) other data fields (e.g., a mask). Although there are definitions of instruction templates (or subformats), some instruction formats are further decomposed. For example, an instruction template of a given instruction format may be defined to have different subsets of the fields of the instruction format (the included fields are typically in the same order, but at least some have different bit positions because fewer fields are included) and / or to have given fields that are interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, a given instruction template from the instruction templates of that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and instruction format, the instruction format including an opcode field for specifying the opcode and an operand field (source 1 / destination and source 2) for selecting operands; and the appearance of the ADD instruction in the instruction stream will have specific content in the operand field that selects specific operands. Sets of SIMD extensions known as Advanced Vector Extensions (AVX, AVX2, and AVX-512) and using the Vector Extensions (VEX) encoding scheme have been published and / or disclosed (e.g., see...). Software Developer's Manual for IA-64 and IA-32 Architectures, September 2014; Advanced Vector Extension Programming Reference, October 2014; and Extended Programming Reference for Architecture Instruction Sets, October 2016.

[0033] Exemplary instruction format

[0034] Examples of the instructions described herein may be embodied in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Examples of the instructions may be executed in such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0035] General Vector-Friendly Instruction Format

[0036] Vector-friendly instruction formats are instruction formats suitable for vector instructions (e.g., those with certain fields specific to vector operations). While an embodiment in which both vector and scalar operations are supported through a vector-friendly instruction format has been described, alternative embodiments simply use a vector-operation vector-friendly instruction format.

[0037] Figure 1A-1BThis is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention. Figure 1A It is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to an embodiment of the present invention; and Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction templates according to an embodiment of the present invention. Specifically, a general vector-friendly instruction format 100 defines Class A and Class B instruction templates, which include a no-memory-access instruction template 105 and a memory-access instruction template 120. In the context of a vector-friendly instruction format, the term "general" means that the instruction format is not constrained to any particular instruction set.

[0038] While embodiments of the invention will be described, the vector-friendly instruction format supports the following: a 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector consists of 16 double-word-sized elements, or alternatively, 8 quad-word-sized elements); a 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); and 32-bit (4-byte), 64-bit (8-byte), and 16-bit... 32-byte vector operand lengths (or sizes) with a width (or size) of 2-byte or 8-bit (1-byte) data elements; and 16-byte vector operand lengths (or sizes) with a width (or size) of 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data elements; however, alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) with more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0039] Figure 1A The Class A instruction templates include: 1) within the no-memory-access instruction template 105, which shows the no-memory-access, full-round control type operation instruction template 110 and the no-memory-access, data transformation type operation instruction template 115; and 2) within the memory-access instruction template 120, which shows the memory-access, temporary instruction template 125 and the memory-access, non-temporary instruction template 130. Figure 1BThe B-type instruction templates include: 1) within the no-memory access instruction template 105, which shows the no-memory access, write mask control, and partial rounding control type operation 112 instruction template, and the no-memory access, write mask control, and vsize type operation 117 instruction template; and 2) within the memory access instruction template 120, which shows the memory access and write mask control instruction template 127.

[0040] General vector friendly instruction format 100 includes the following: Figure 1A-1B The following fields are listed in the order shown in the diagram.

[0041] Format field 140 – A specific value in this field (the instruction format identifier value) uniquely identifies the vector-friendly instruction format, and thus the occurrence of an instruction in the instruction stream in the vector-friendly instruction format. Accordingly, this field is optional in the sense that it is not needed for instruction sets that only have a general vector-friendly instruction format.

[0042] Basic Operation Field 142 – Its content distinguishes different basic operations.

[0043] Register index field 144—its contents specify the location of the source and destination operands, either directly or through address generation, whether they are in registers or in memory. These include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment N can be up to three source and one destination registers, alternative embodiments can support more or fewer source and destination registers (e.g., up to two sources, one of which also acts as a destination; up to three sources, one of which also acts as a destination; up to two sources and one destination).

[0044] Modifier field 146—its content distinguishes the occurrence of instructions in the general vector instruction format that specify memory access versus those that do not; that is, it differentiates between the no-memory-access 105 instruction template and the memory-access 120 instruction template. Memory access operations read from and / or write to memory hierarchies (in some cases specifying source and / or destination addresses using values ​​in registers), while non-memory-access operations do not (e.g., source and destination are registers). Although in one embodiment this field also selects between three different methods for performing memory address calculations, alternative embodiments may support more, fewer, or different methods for performing memory address calculations.

[0045] The augmented operation field 150 distinguishes which of the various operations will be performed in addition to the basic operation. This field is content-specific. In one embodiment of the invention, this field is divided into a class field 168, an alpha field 152, and a beta field 154. The augmented operation field 150 allows common group operations to be performed in a single instruction, rather than two, three, or four instructions.

[0046] The scaling field 160—its contents allow scaling the contents of the index field for use in memory address generation (e.g., for use with "2"). 缩放 Address generation of “*index + base(2scale*index + base)”).

[0047] Displacement field 162A – its contents are used as part of memory address generation (e.g., for using "2"). 缩放 Address generation of “*index + base + displacement (2scale*index + base + displacement)”.

[0048] The displacement factor field 162B (note that the juxtaposition of displacement field 162A directly on displacement factor field 162B indicates that one or the other is used) – its contents are used as part of the address generation; it specifies the displacement factor by which the size (N) of the memory access will be scaled – where N is the number of bytes in the memory access (e.g., used for using "2"). 缩放 *Address generation of "index + base + scaled displacement (2scale*index + base + scaled displacement)". Redundant low-order bits are ignored and therefore, the contents of the displacement factor field are multiplied by the total size of the memory operands (N) to generate the final displacement that will be used in the calculation of the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used in the no-memory-access 105 instruction template, and / or different embodiments may implement only one of the two or neither of them.

[0049] The data element width field 164—its content distinguishes which of the multiple data element widths will be used (in some embodiments for all instructions; in other embodiments only for some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or if the data element width is supported by using some aspect of the opcode.

[0050] The write mask field 170—its content controls, based on the location of each data element, whether the location of that data element in the destination vector operand reflects the results of the basic and augmentation operations. Type A instruction templates support merge-write masking, while Type B instruction templates support both merge-write masking and zero-write masking. When merging, the vector mask allows protection from updates to any set of elements in the destination during the execution of any operation (specified by the basic and augmentation operations); in another embodiment, the old value of each element in the destination where the corresponding mask bit is 0 is preserved. Conversely, when zeroing, the vector mask allows zeroing any set of elements in the destination during the execution of any operation (specified by the basic and augmentation operations); in one embodiment, the elements in the destination are set to 0 when the corresponding mask bit has a value of 0. This subset of functionality is the ability to control the vector length of the performed operations (i.e., the span from the first to the last modified element); however, it is not necessary for the modified elements to be consecutive. Therefore, write mask field 170 allows for some vector operations, including load, store, arithmetic, logic, etc. Although embodiments of the invention have been described in which the content of write mask field 170 selects one of a plurality of write mask registers to contain the write mask to be used (and thus the content of write mask field 170 indirectly identifies the mask to be performed), alternative embodiments may instead or additionally allow the content of mask write field 170 to directly specify the mask to be performed.

[0051] The immediate field 172—its contents allow for the specification of an immediate value. This field is optional in the following sense: it does not exist in implementations of general vector-friendly formats that do not support immediate values, and it does not exist in instructions that do not use immediate values.

[0052] Class field 168 – its content distinguishes instructions from different classes. (See reference) Figure 1A -B indicates that the content of this field selects between type A and type B instructions. Figure 1A In -B, a square with rounded corners is used to indicate the presence of a specific value in the field (e.g., in...). Figure 1A In -B, this refers to class A (168A) and class B (168B) of class field 168.

[0053] Type A Instruction Template

[0054] In the case of the non-memory access instruction template 105 (Class A), the alpha field 152 is interpreted as the RS field 152A, the content of which distinguishes which of the different amplification operation types will be performed (e.g., rounding type operation 110 and data transformation type operation 115 instruction templates specify rounding 152A.1 and data transformation 152A.2, respectively), while the beta field 154 distinguishes which of the specified operation types will be performed. In the non-memory access instruction template 105, the scaling field 160, the displacement field 162A, and the displacement-scaling field 162B are not present.

[0055] No memory access instruction template - full rounding control type operation

[0056] In the instruction template of Operation 110 of the No Memory Access Full Rounding Control Type, the beta field 154 is interpreted as the rounding control field 154A, the contents of which provide static rounding. Although in the embodiments described in this invention, the rounding control field 154A includes a suppress all floating-point exception (SAE) field 156 and a rounding operation control field 158, alternative embodiments may support, encode, or have only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 158).

[0057] SAE field 156 – Its content distinguishes whether exception event reporting should be disabled; when the content of SAE field 156 indicates that suppression is enabled, the given instruction will not report any kind of floating-point exception flags and will not trigger any floating-point exception handlers.

[0058] The rounding operation control field 158 distinguishes which of a group of rounding operations (e.g., round up, round down, round to zero, and round to nearest) should be performed. Therefore, the rounding operation control field 158 allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides that register value.

[0059] No memory access instruction template – Data transformation type operation

[0060] In the instruction template of No Memory Access Data Transformation Type Operation 115, the beta field 154 is interpreted as the data transformation field 154B, the contents of which distinguish which of the multiple data transformations will be performed (e.g., no data transformation, mixing, broadcasting).

[0061] In the case of the Class A memory access 120 instruction template, the alpha field 152 is interpreted as the eviction hint field 152B, the content of which distinguishes which eviction hint will be used (in...). Figure 1A In this context, temporary (152B.1) and non-temporary (152B.2) instruction templates are specified for memory access, temporary (125) instruction template, and memory access, non-temporary (130) instruction template, respectively. The beta field 154 is interpreted as the data manipulation field 154C, the contents of which distinguish which of several data manipulation operations (also called primitives) will be performed (e.g., no manipulation; broadcast; source upconversion; and destination downconversion). The memory access instruction template 120 includes a scaling field 160, and optionally a displacement field 162A or a displacement-scaling field 162B.

[0062] Vector memory instructions perform vector loads from and vector stores to memory, provided translation support is available. Like regular vector instructions, vector memory instructions pass data to / from memory element by element, with the actual elements passed indicated by the contents of a vector mask selected as the write mask.

[0063] Memory access instruction template - Temporary

[0064] Temporary data is data that is likely to be reused quickly enough to benefit from the cache. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0065] Memory access instruction template - non-temporal

[0066] Non-temporary data is unlikely to be reused quickly enough to benefit from being cached in the first-level cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0067] Type B Instruction Template

[0068] In the case of the B-type instruction template, the alpha field 152 is interpreted as the write mask control (Z) field 152C, the content of which distinguishes whether the write mask controlled by the write mask field 170 should be merged or zeroed.

[0069] In the case of the non-memory access instruction template 105 (Class B), a portion of the beta field 154 is interpreted as the RL field 157A, the content of which distinguishes which of the different amplification operation types will be performed (e.g., rounding 157A.1 and vector length (VSIZE) 157A.2 are specified for the no-memory access, write mask control, partial rounding control type operation 112 instruction template and the no-memory access, write mask control, VSIZE type operation 117 instruction template, respectively), while the remaining portion of the beta field 154 distinguishes which of the specified types of operations will be performed. In the no-memory access instruction template 105, the scaling field 160, the displacement field 162A, and the displacement-scaling field 162B are absent.

[0070] In the instruction template of operation 110 with no memory access, write mask control, and partial rounding control, the remainder of beta field 154 is interpreted as rounding operation field 159A and exception reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not raise any floating-point exception handler).

[0071] Rounding operation control field 159A—like rounding operation control field 158—distinguishes which of a group of rounding operations (e.g., round up, round down, round to zero, and round to nearest) should be performed. Thus, rounding operation control field 159A allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of rounding operation control field 150 overrides that register value.

[0072] In the instruction template 117 for No Memory Access, Write Mask Control, and VSIZE Type Operation, the remainder of the beta field 154 is interpreted as the vector length field 159B, the contents of which distinguish which of the multiple data vector lengths (e.g., 128, 256, or 512 bytes) will be executed.

[0073] In the case of the Class B memory access 120 instruction template, a portion of the beta field 154 is interpreted as a broadcast field 157B, the content of which distinguishes whether a broadcast-type data manipulation operation will be performed, while the remainder of the beta field 154 is interpreted as a vector length field 159B. The memory access 120 instruction template includes a scaling field 160, and optionally a displacement field 162A or a displacement-scaling field 162B.

[0074] Regarding the general vector-friendly instruction format 100, a full opcode field 174 is shown, which includes a format field 140, a basic operation field 142, and a data element width field 164. While one embodiment is shown where the full opcode field 174 includes all of these fields, in embodiments that do not support all of them, the full opcode field 174 includes fewer than all of these fields. The full opcode field 174 provides the operation code (opcode).

[0075] The augmentation operation field 150, the data element width field 164, and the write mask field 170 allow these features to be specified on a per-instruction basis in a generic vector-friendly instruction format.

[0076] The combination of a write mask field and a data element width field creates typed instructions because they allow masks to be applied based on different data element widths.

[0077] The various instruction templates found within classes A and B are advantageous in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only class B, a core primarily intended for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, some hybrid core having templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the invention). Moreover, a single processor may include multiple cores, all of which support the same class or in which different cores support different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores primarily intended for graphics and / or scientific computing may support only class A, while one or more of the general-purpose cores may be a high-performance general-purpose core supporting only class B, with out-of-order execution and register renaming intended for general-purpose computing. Another processor without separate graphics cores may include one or more general-purpose ordered or out-of-order cores supporting both class A and class B. Of course, in different embodiments of the invention, features from one class can also be implemented in another class. Programs written in high-level languages ​​will be placed in various executable forms (e.g., just-in-time compilation or static compilation), including: 1) forms having only instructions from the class(s) supported by the target processor for execution; or 2) forms having alternative routines written using different combinations of instructions from all classes and having control flow code that selects the routine to be executed based on instructions supported by the processor currently executing the code.

[0078] Exemplary Vector-Friendly Instruction Format

[0079] Figure 2A This is a block diagram illustrating an exemplary vector-friendly instruction format according to an embodiment of the present invention. Figure 2A A specific vector-friendly instruction format 200 is illustrated, which is specific in the sense that it specifies the position, size, interpretation, and order of fields, as well as the values ​​of some of those fields. This specific vector-friendly instruction format 200 can be used to extend the x86 instruction set, and therefore some of the fields are similar to or the same as those used in existing x86 instruction sets and their extensions (such as AVX). The format maintains consistency with the prefix-encoded fields, real opcode byte fields, MOD R / M fields, SIB fields, shift fields, and immediate numeric fields of existing x86 instruction sets with extensions. The illustration shows... Figure 2A The fields are mapped to the ones from Figure 1B The field.

[0080] It should be understood that although embodiments of the invention have been described with reference to a specific vector-friendly instruction format 200 in the context of the general vector-friendly instruction format 100 for illustrative purposes, the invention is not limited to the specific vector-friendly instruction format 200 except where required. For example, the general vector-friendly instruction format 100 envisions various possible sizes for various fields, while the specific vector-friendly instruction format 200 is shown as a field with a specific size. As a specific example, although the data element width field 164 is illustrated as a one-bit field in the specific vector-friendly instruction format 200, the invention is not limited in this way (that is, the general vector-friendly instruction format 100 envisions other sizes for the data element width field 164).

[0081] General vector friendly instruction format 100 includes the following: Figure 2A The following fields are listed in the order shown in the diagram.

[0082] The EVEX prefix (bytes 0-3) 202 — is encoded in four-byte form.

[0083] Format field 140 (EVEX byte 0, bits [7:0]) — The first byte (EVEX byte 0) is format field 140 and it contains 0x62 (in one embodiment of the invention, a unique value used to distinguish vector-friendly instruction formats).

[0084] The second to fourth bytes (EVEX bytes 1-3) include multiple bit fields that provide specific capabilities.

[0085] REX field 205 (EVEX byte 1, bit [7-5]) – includes the EVEX.R bit field (EVEX byte 1, bit [7]-R), the EVEX.X bit field (EVEX byte 1, bit [6]-X), and the 157BEX byte 1, bit [5]-B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as their corresponding VEX bit fields and are encoded using multiple 1s complement forms, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of the instruction encode the lower three bits of the register index as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0086] REX' field 110—This is the first part of REX' field 110 and is the EVEX.R' bit field (EVEX byte 1, bit [4]-R'), which is used to encode the higher 16 or lower 16 of the extended 32 register set. In one embodiment of the invention, this bit, along with others as indicated below, is stored in a bit-inverted format to (in the well-known x8632 bit mode) differ from the BOUND instruction, which has an actual opcode byte of 62, but does not accept the value 11 in the MOD field in the MOD R / M field (described below); alternative embodiments of the invention do not store this and the other bits indicated below in an inverted format. The value 1 is used to encode the lower 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and other RRRs from other fields.

[0087] Opcode mapping field 215 (EVEX byte 1, bit [3:0]-mmmm) — its content encodes the implied leading opcode byte (0F, 0F 38 or 0F 3).

[0088] The data element width field is 164 (EVEX byte 2, bit [7]-W) – which is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32-bit data element or 64-bit data element).

[0089] EVEX.vvvv220 (EVEX byte 2, bits [6:3] - vvvv) — The function of EVEX.vvvv can include the following: 1) EVEX.vvvv encodes the first source register operand specified in reverse (multiple two's complement) form and is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand, which is specified in multiple two's complement form for some vector shift; or 3) EVEX.vvvv does not encode any operands, and the field is reserved and should contain 1111b. Therefore, the EVEX.vvvv field 220 encodes the four lower-order bits of the first source register specifier stored in reverse (multiple two's complement) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0090] EVEX.U 168 Class Field (EVEX byte 2, bit [2]-U) — If EVEX.U = 0, it indicates Class A or EVEX.U0; if EVEX.U = 1, it indicates Class B or EVEX.U1.

[0091] The prefix encoding field 225 (EVEX byte 2, bits [1:0]-pp) provides additional bits for the basic operation field. Besides supporting legacy SSE instructions in EVEX prefix format, this has the benefit of making the SIMD prefix more compact (the EVEX prefix requires only 2 bits instead of one byte to represent the SIMD prefix). In one embodiment, to support legacy SSE instructions using SIMD prefixes (66H, F2H, F3H) in both legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and are expanded to the legacy SIMD prefix at runtime before being provided to the decoder's PLA (so the PLA can execute these legacy instructions in both legacy and EVEX formats without modification). While newer instructions can directly use the contents of the EVEX prefix encoding field as opcode extensions, some embodiments expand in a similar manner for consistency, but allow different meanings to be specified via these legacy SIMD prefixes. Alternative embodiments can redesign the PLA to support 2-bit SIMD prefix encoding and therefore do not require expansion.

[0092] Alpha field 152 (EVEX byte 3, bit [7]-EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control and EVEX.N; also referred to as α) - as previously described, this field is content-specific.

[0093] Beta field 154 (EVEX byte 3, bit [6:4]-SSS, also known as EVEX.s2-0, EVEX.r2-0, EVEX.rr1, EVEX.LL0 and EVEX.LLB; also referred to as βββ) — as previously described, this field is content-specific.

[0094] REX' field 110 — This is the remainder of the REX' field and is the EVEX.V' bit field (EVEX byte 3, bit [3]-V'), which can be used to encode the higher 16 or lower 16 of the extended 32 register set. This bit is stored in bit-inverted format. The value 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V' and EVEX.vvvv.

[0095] Write mask field 170 (EVEX byte 3, bits [2:0]-kkk) – its content specifies the index of a register in the write mask register, as previously described. In one embodiment of the invention, the specific value EVEX.kkk = 000 has a special behavior, implying that no write mask is used for a specific instruction (this can be implemented in various ways, including using a write mask hardwired to all one or hardware that bypasses the masking hardware).

[0096] The actual opcode field 230 (byte 4) is also known as the opcode byte. This field specifies the portion of the opcode.

[0097] The MOD R / M field 240 (byte 5) includes the MOD field 242, the Reg field 244, and the R / M field 246. As previously described, the content of the MOD field 242 distinguishes between memory access and non-memory access operations. The function of the Reg field 244 can be summarized in two cases: encoding the destination register operand or the source register operand, or being treated as an opcode extension and not used to encode any instruction operand. The function of the R / M field 246 can include encoding instruction operands referencing memory addresses, or encoding the destination register operand or the source register operand.

[0098] Scaling, Indexing, Basic (SIB) Byte (Byte 6) – As previously described, the contents of scaling field 150 are used for memory address generation. SIB.xxx 254 and SIB.bbb 256 – The contents of these fields have already been mentioned previously regarding register indices Xxxx and Bbbb.

[0099] Displacement field 162A (bytes 7-10) — When MOD field 242 contains 10, bytes 7-10 are displacement field 162A, and it functions the same as the traditional 32-bit displacement (disp32), operating at the byte level.

[0100] Displacement Factor Field 162B (Byte 7) – Byte 7 is the displacement factor field 162B when MOD field 242 contains 0s and 1s. This field is located in the same position as the 8-bit displacement (disp8) of the traditional x86 instruction set, which operates at byte granularity. Because disp8 is sign-extended, it can only address offsets between -128 and 127 bytes; for a 64-byte cache line, disp8 uses 8 bits, which can be set to only four truly useful values: -128, -64, 0, and 64; because a larger range is typically required, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 162B is a reinterpretation of disp8; when using the displacement factor field 162B, the actual displacement is determined by multiplying the content of the displacement factor field by the size (N) of the memory operand access. This type of displacement is called disp8*N. This reduces the average instruction length (a single byte used for displacement but with a much larger range). This compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and therefore, redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 162B replaces the traditional 8-bit displacement of the x86 instruction set. Therefore, the displacement factor field 162B is encoded in the same way as the 8-bit displacement of the x86 instruction set (and thus unchanged in the ModRM / SIB encoding rules), with the only exception that disp8 is overloaded to disp8*N. In other words, there is no change in the encoding rules or encoding length, only in the interpretation of the displacement value by the hardware (which needs to scale the displacement according to the size of the memory operand to obtain the byte-wise address offset). Immediate digital segment 172 operates as previously described.

[0101] Full opcode field

[0102] Figure 2B This is a block diagram illustrating the fields constituting a specific vector-friendly instruction format 200 for a full opcode field 174 according to an embodiment of the present invention. Specifically, the full opcode field 174 includes a format field 140, a basic operation field 142, and a data element width (W) field 164. The basic operation field 142 includes a prefix encoding field 225, an opcode mapping field 215, and a real opcode field 230.

[0103] Register index field

[0104] Figure 2C This is a block diagram illustrating the fields of a specific vector-friendly instruction format 200 constituting register index field 144 according to an embodiment of the present invention. Specifically, register index field 144 includes REX field 205, REX' field 210, MODR / M.reg field 244, MODR / Mr / m field 246, VVVV field 220, xxx field 254, and bbb field 256.

[0105] Amplification operation field

[0106] Figure 2D This is a block diagram illustrating the fields constituting a specific vector-friendly instruction format 200 of the amplification operation field 150 according to an embodiment of the present invention. When the class (U) field 168 contains 0, it represents EVEX.U0 (Class A 168A); when it contains 1, it represents EVEX.U1 (Class B 168B). When U = 0 and the MOD field 242 contains 11 (indicating no memory access operation), the alpha field 152 (EVEX byte 3, bit [7]-EH) is interpreted as the rs field 152A. When the rs field 152A contains a 1 (rounded 152A.1), the beta field 154 (EVEX byte 3, bit [6:4]-SSS) is interpreted as the rounding control field 154A. The rounding control field 154A includes a one-bit SAE field 156 and a two-bit rounding operation field 158. When rs field 152A contains a 0 (data transformation 152A.2), beta field 154 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data transformation field 154B. When U = 0 and MOD field 242 contains 00, 01, or 10 (indicating a memory access operation), alpha field 152 (EVEX byte 3, bits [7]-EH) is interpreted as an eviction hint (EH) field 152B, and beta field 154 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data manipulation field 154C.

[0107] When U = 1, the alpha field 152 (EVEX byte 3, bit [7]-EH) is interpreted as the write mask control (Z) field 152C. When U = 1 and the MOD field 242 contains 11 (indicating no memory access operation), a portion of the beta field 154 (EVEX byte 3, bit [4]-S0) is interpreted as the RL field 157A; when it contains a 1 (rounding 157A.1), the remainder of the beta field 154 (EVEX byte 3, bit [6-5]-S2-1) is interpreted as the rounding operation field 159A, and when the RL field 157A contains a 0 (VSIZE 157.A2), the remainder of the beta field 154 (EVEX byte 3, bit [6-5]-S2-1) is interpreted as the vector length field 159B (EVEX byte 3, bit [6-5]-L1-0). When U=1 and MOD field 242 contains 00, 01 or 10 (indicating a memory access operation), beta field 154 (EVEX byte 3, bit [6:4]-SSS) is interpreted as vector length field 159B (EVEX byte 3, bit [6-5]-L1-0) and broadcast field 157B (EVEX byte 3, bit [4]-B).

[0108] Exemplary Register Architecture

[0109] Figure 3 This is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310, each 512 bits wide; these registers are referenced as zmm0 to zmm31 (zmm ​​register group). Instead of the zmm register group, other embodiments may include a group of sixteen vector registers, each 256 bits wide; these registers are referenced as ymm0 to ymm15 (ymm register group). Instead of the zmm register group or ymm register group, other embodiments may include a group of sixteen vector registers, each 128 bits wide; these registers are referenced as xmm0 to xmm15 (xmm register group). Figure 3 In this process, the lower 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-15, and the lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0110] Specific vector-friendly instruction format 200 operates on these overlaid register files as illustrated in the following table.

[0111]

[0112] In other words, the vector length field 159B is selected between a maximum length and one or more other shorter lengths, each of which is half the length of the preceding length; and no instruction template with the vector length field 159B operates on the maximum vector length. Furthermore, in one embodiment, the Class B instruction template of the specific vector-friendly instruction format 200 operates on packed or scalar single-precision / double-precision floating-point data and packed or scalar integer data. Scalar operations are performed on the lowest-order data element location in the zmm / ymm / xmm registers; either the higher-order data element locations are made the same as they were before the instruction, or the higher-order data element locations are zeroed, depending on the embodiment.

[0113] Write mask register 315—In the illustrated embodiment, there are eight write mask registers (k0 through k7), each 64 bits in size. In an alternative embodiment, write mask register 315 is 16 bits in size. In one embodiment, vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for the write mask, it selects a hard-wired write mask of 0xFFFF, effectively disabling write masking for that instruction.

[0114] General Purpose Register 325 — In the illustrated embodiment, there are sixteen 64-bit general purpose registers that are used in conjunction with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0115] A scalar floating-point stack register file (x87 stack) 345 is aliased on top of an MMX-packed integer flat register file 350. In the illustrated embodiment, the x87 stack is an octal stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set extensions; while the MMX registers are used to perform operations on 64-bit packed integer data and to hold operands for some operations performed between the MMX and XMM registers.

[0116] Alternative embodiments of the present invention may use wider or narrower registers. Furthermore, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0117] Exemplary core architectures, processors, and computer architectures

[0118] The processor cores that embody this invention can be implemented in different ways, for different purposes, and in different processors. For example, such implementations may include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose unordered cores intended for general-purpose computing; and 3) dedicated cores primarily intended for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a central processing unit (CPU) comprising one or more general-purpose ordered cores intended for general-purpose computing and / or one or more general-purpose unordered cores intended for general-purpose computing; and 2) a coprocessor comprising one or more dedicated cores primarily intended for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or referred to as a dedicated core); and 4) a system-on-a-chip (SoC) which may include the described CPU (sometimes referred to as application cores or application processors), the coprocessors described above, and additional functionality on the same die.

[0119] Exemplary core architecture

[0120] Ordered and Unordered Kernel Block Diagrams

[0121] Figure 4A It is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming and unordered release / execution pipeline according to embodiments of the present invention. Figure 4B It is a block diagram illustrating an exemplary embodiment of an ordered architecture core to be included in a processor, as well as exemplary register renaming and out-of-order release / execution of the architecture core, according to embodiments of the present invention. Figure 4A The solid boxes in -B illustrate ordered pipelines and ordered cores, while the optional dashed boxes illustrate register renaming, out-of-order release / execution pipelines, and cores. Since the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0122] exist Figure 4A In the processor pipeline 400, there are fetch stage 402, length decoding stage 404, decoding stage 406, allocation stage 408, renaming stage 410, scheduling (also known as dispatch or issue) stage 412, register read / memory read stage 414, execution stage 416, write-back / memory write stage 418, exception handling stage 422, and commit stage 424.

[0123] Figure 4BA processor core 490 is shown, which includes a front-end unit 430 coupled to an execution engine unit 450, and both the front-end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. Core 490 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 490 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0124] Front-end unit 430 includes branch prediction unit 432 coupled to micro-operation cache 433 and instruction cache unit 434 coupled to instruction translation lookup buffer (TLB) 436 coupled to instruction fetch unit 438 coupled to decoding unit 440. Decoding unit 440 (or decoder) can decode instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, or otherwise reflect or derived from, the original instruction. Decoding unit 440 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 490 includes microcode ROM or other media that stores microcode for certain macro instructions (e.g., in decoding unit 440 or otherwise within front-end unit 430). Micro-operations cache 433 and decoding unit 440 are coupled to rename / allocator unit 452 in execution engine unit 450. In various embodiments, micro-operations cache, such as 433, may also be referred to as operations cache or alternatively.

[0125] Execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set of one or more scheduler units 456. The scheduler units 456 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 456 are coupled to a set of physical register file units 458. Each of the physical register file units 458 represents one or more physical register files, where different files store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 458 include vector register units, write mask register units, and scalar register units. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. Multiple physical register file units 458 are overlapped by retirement units 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., by using multiple reordering buffers and multiple retirement register files; by using multiple future files, multiple history buffers, and multiple retirement register files; by using register mappings and register pools; etc.). Retirement units 454 and multiple physical register file units 458 are coupled to multiple execution clusters 460. Multiple execution clusters 460 include a group of one or more execution units 462 and a group of one or more memory access units 464. Execution units 462 can perform various operations (e.g., shift, addition, subtraction, multiplication) and can perform various operations on various data types (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include multiple execution units dedicated to a particular function or function set, other embodiments may include only one execution unit or multiple execution units that perform all functions. Multiple scheduler units 456, multiple physical register file units 458, and multiple execution clusters 460 are shown as possibly numerous because some embodiments create separate pipelines for certain data / operation types (e.g., scalar integer pipelines, scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having its own scheduler unit, multiple physical register file units, and / or execution clusters—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of that pipeline has multiple memory access units 464). It should also be understood that in cases where separate pipelines are used, one or more of these pipelines may be out-of-order release / execution and the rest may be ordered.

[0126] The memory access unit 464 is coupled to a memory unit 470, which includes a data TLB unit 472. The data TLB unit 472 is coupled to a data cache unit 474, which is coupled to a Level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access unit 464 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is further coupled to the Level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and finally to main memory.

[0127] As an example, the exemplary register renaming, out-of-order release / execution core architecture can implement pipeline 400 as follows: 1) Instruction fetch 438 executes fetch and length decoding stages 402 and 404; 2) Decoding unit 440 executes decoding stage 406; 3) Rename / allocator unit 452 executes allocation stage 408 and rename stage 410; 4) (multiple) scheduler units 456 execute scheduling stage 412; 5) (multiple) physical register file units 458 and memory units 470 execute register read / memory read stage 414; execution cluster 460 executes execution stage 416; 6) memory unit 470 and (multiple) physical register file units 458 execute write-back / memory write stage 418; 7) Various units may be involved in exception handling stage 422; and 8) retirement unit 454 and (multiple) physical register file units 458 execute commit stage 424.

[0128] Core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, California; the ARM instruction set of ARM Holdings, Sunnyvale, California (with optional additional extensions, such as NEON)), including the instructions(s) described herein. In one embodiment, core 490 includes logic for supporting packaged data instruction set extensions (e.g., AVX, AVX2, AVX-512), thereby allowing operations used by many multimedia applications to be performed using packaged data.

[0129] It should be understood that a core can support multithreading (executing two or more sets of parallel operations or threads), and can do so in various ways, including time-sliced ​​multithreading, SMT (e.g., a single physical core providing a logical core for each of the threads that are being multithreaded simultaneously), or a combination thereof (e.g., time-slice extraction and decoding followed by SMT, such as in...). (like in hyper-threading technology).

[0130] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in ordered architectures. While the illustrated embodiment of the processor also includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0131] Specific Exemplary Core Architecture

[0132] Figure 5A -B illustrates a block diagram of a more specific exemplary core architecture, where the core will be one of several logic blocks (including other cores of the same and / or different types) in a chip. Depending on the application, the logic block communicates with a fixed functional logic, memory I / O interface, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0133] Figure 5A This is a block diagram of a single processor core according to an embodiment of the invention, along with its connection to the on-die interconnect network 502 and a local subset thereof, along with its Level 2 (L2) cache 504. In one embodiment, the instruction decoder 500 supports the x86 instruction set with Packed Data Instruction Set Extensions. The L1 cache 506 allows low-latency access to cache memory in scalar and vector units. Although in one embodiment (for design simplification), scalar unit 508 and vector unit 510 use separate register sets (correspondingly, scalar register 512 and vector register 514), and data passed between them is written to memory and then read back from the Level 1 (L1) cache 506, alternative embodiments of the invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be passed between two register files without being written and read back).

[0134] The local subset 504 of the L2 cache is part of the global L2 cache, which is divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and is evicted from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents, such as processor cores, L2 caches, and other logic blocks, to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0135] Figure 5B This is according to an embodiment of the present invention. Figure 5A An expanded view of the processor core portion. Figure 5B This includes the L1 data cache 506A portion of L1 cache 504, and further details regarding vector unit 510 and vector register 514. Specifically, vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports mixing register inputs using mixing unit 520, performing numerical conversions using conversion units 522A-B, and copying memory inputs using copy unit 524. Write mask register 526 allows the writing of vectors generated from prediction results.

[0136] Specific processor architecture

[0137] Figure 6 This is a block diagram of a processor 600 according to an embodiment of the present invention. The processor 600 may have more than one core, may have an integrated memory controller, and may have an integrated graphics element. Figure 6 The solid box in the figure illustrates a processor 600 having a single core 602A, a system agent 610, and a group of one or more bus controller units 616, while the optional addition of the dashed box illustrates an alternative processor 600 having multiple cores 602A-N, a group of one or more integrated memory controller units 614 in the system agent unit 610, and dedicated logic 608.

[0138] Therefore, different implementations of processor 600 may include: 1) a CPU with dedicated logic 608 and cores 602A-N, wherein the dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and the cores 602A-N are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose unordered cores, or a combination of both); 2) a coprocessor with cores 602A-N, wherein the cores 602A-N are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput) purposes; and 3) a coprocessor with cores 602A-N, wherein the cores 602A-N are a large number of general-purpose ordered cores. Thus, processor 600 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. The processor 600 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a number of processing technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0139] The memory hierarchy includes one or more levels of cache within the core, a set or one or more shared cache units 606, and external memory (not shown) coupled to the set of integrated memory controller units 614. The set of shared cache units 606 may include one or more intermediate caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, Last Level Cache (LLC), and / or combinations thereof. While in one embodiment, ring-based interconnect units 612 interconnect integrated graphics logic 608 (which is an example of dedicated logic and is also referred to herein as dedicated logic), the set of shared cache units 606, and system proxy units 610 / (multiple) of integrated memory controller units 614, alternative embodiments may use any number of well-known techniques to interconnect such units. In one embodiment, consistency is maintained between one or more cache units 606 and core 602-AN.

[0140] In some embodiments, one or more of the cores 602A-N are capable of multithreading. System agent 610 includes those components that coordinate and operate the cores 602A-N. System agent unit 610 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include the logic and components required for regulating the power state of the cores 602A-N and the integrated graphics logic 608. The display unit is used to drive one or more externally connected displays.

[0141] In terms of instruction set architecture, cores 602A-N can be homogeneous or heterogeneous; that is, two or more cores in 602A-N can execute the same instruction set, while other cores can execute only a subset of that instruction set or a different instruction set.

[0142] Exemplary computer architecture

[0143] Figure 7-10 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are suitable.

[0144] Now for reference Figure 7 The diagram illustrates a block diagram of a system 700 according to an embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, the controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on a separate chip); the GMCH 790 includes memory and a graphics controller, to which memory 740 and a coprocessor 745 are coupled; the IOH 750 couples an input / output (I / O) device 760 to the GMCH 790. Alternatively, one or both of the memory and the graphics controller may be integrated within a processor (as described herein), with memory 740 and coprocessor 745 directly coupled to processor 710, and the controller hub 720 and IOH 750 on a single chip.

[0145] exist Figure 7 The optional nature of the additional processor 715 is indicated by a broken line. Each processor 710, 715 may include one or more of the processing cores described herein, and may be a version of processor 600.

[0146] The memory 740 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In at least one embodiment, the controller hub 720 communicates with the processors(s) 710, 715 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface such as a QuickPath Interconnect (QPI), or a similar connection 795.

[0147] In one embodiment, the coprocessor 745 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0148] In terms of the range of metrics including architecture, microarchitecture, thermal properties, power consumption characteristics, etc., there can be various differences between physical resources 710 and 715.

[0149] In one embodiment, processor 710 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 710 identifies these coprocessor instructions as having a type that should be executed by an attached coprocessor 745. Therefore, processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 745 on a coprocessor bus or other interconnect. Coprocessors 745 (multiple) receive and execute the received coprocessor instructions.

[0150] Now for reference Figure 8 The diagram shown is a block diagram of a first more specific exemplary system 800 according to an embodiment of the present invention. Figure 8 As shown, the multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be a version of processor 600. In one embodiment of the invention, processors 870 and 880 are processors 710 and 715, respectively, and coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processor 710 and coprocessor 745, respectively.

[0151] Processors 870 and 880 are shown, each including an integrated memory controller (IMC) unit 872 and 882, respectively. Processor 870, as part of its bus controller unit, also includes point-to-point (PP) interfaces 876 and 878; similarly, a second processor 880 includes PP interfaces 886 and 888. Processors 870 and 880 can exchange information via point-to-point (PP) interface 850 using PP interface circuits 878 and 888. Figure 8 As shown, IMC 872 and 882 couple the processor to the corresponding memory, namely memory 832 and memory 834, which may be portions of the main memory that are locally attached to the corresponding processor.

[0152] Processors 870 and 880 can each exchange information with chipset 890 via separate PP interfaces 852 and 854 using point-to-point interface circuits 876, 894, 886, and 898, respectively. Chipset 890 can optionally exchange information with coprocessor 838 via high-performance interface 892. In one embodiment, coprocessor 838 is a dedicated processor, such as a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, etc.

[0153] A shared cache (not shown) may be included in either processor or external to both processors and connected to the processors via a PP interconnect, such that if the processors are in a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0154] Chipset 890 can be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a peripheral component interconnect (PCI) bus, or a bus such as PCI Fast Bus or another third-generation I / O interconnect bus, but the scope of the invention is not limited in this way.

[0155] like Figure 8As shown, various I / O devices 814 can be coupled to a first bus 816 together with a bus bridge 818, which couples the first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815, such as coprocessors, high-throughput MIC processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field-programmable gate arrays, or any other processors, are coupled to the first bus 816. In one embodiment, the second bus 820 can be a low pin count (LPC) bus. In one embodiment, various devices can be coupled to the second bus 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage unit 828, such as a disk drive or other mass storage device, which may include instructions / code and data 830. Furthermore, audio I / O 824 can be coupled to the second bus 820. Note that other architectures are possible. For example, instead of… Figure 8 The point-to-point architecture allows the system to implement multi-point branch bus or other similar architectures.

[0156] Now for reference Figure 9 The diagram shown is a block diagram of a second more specific exemplary system 900 according to an embodiment of the present invention.

[0157] Figure 8 and 9 The same elements in the same text have the same reference number, and Figure 8 Some aspects have already been from Figure 9 Omitted in order to avoid making Figure 9 Other aspects are unclear.

[0158] Figure 9 The illustration shows that processors 870 and 880 may include integrated memory and I / O control logic (“CL”) 872 and 882, respectively. Therefore, CL 872 and 882 include an integrated memory controller unit and I / O control logic. Figure 9 The diagram illustrates that not only are the memories 832 and 834 coupled to CLs 872 and 882, but the I / O device 914 is also coupled to the control logic 872 and 882. The conventional I / O device 915 is coupled to the chipset 890.

[0159] Now for reference Figure 10 The diagram shown is a block diagram of a SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements within the same text have the same reference numerals. Furthermore, the dashed box is an optional feature on more advanced SoCs. Figure 10In this configuration, multiple interconnect units 1002 are coupled to: an application processor 1010, which includes a set of one or more cores 602A-N and multiple shared cache units 606, the cores including cache units 604A-N; a system proxy unit 610; multiple bus controller units 616; multiple integrated memory controller units 614; a set of one or more coprocessors 1020, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, the multiple coprocessors 1020 include dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, embedded processors, etc.

[0160] Embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system, said programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0161] Program code, such as Figure 8 The code 830 illustrated herein can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0162] The program code can be implemented using a high-level procedural programming language or an object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented using assembly or machine language. In fact, the mechanisms described herein are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0163] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium, the representative instructions representing various logics within a processor that, when read by a machine, cause the machine to manufacture the logic to perform the techniques described herein. Such a representation, referred to as an "IP core," can be stored on a tangible machine-readable medium and supplied to various consumer or manufacturing facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0164] Such machine-readable storage media can, without limitation, include non-transitory, tangible arrangements of articles made or formed by a machine or device, including storage media such as hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable device (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM)), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions.

[0165] Therefore, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or design data, such as a hardware description language (HDL), defining the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0166] Simulation (including binary conversion, code transformation, etc.)

[0167] In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can transform (e.g., through static binary translation, dynamic binary translation including dynamically compiled binary translation), morph, emulate, or otherwise translate instructions into one or more other instructions for processing by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on and partially off the processor.

[0168] Figure 11 This is a block diagram illustrating the use of a software instruction converter according to an embodiment of the invention for converting binary instructions in a source instruction set into binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter may be implemented using software, firmware, hardware, or various combinations thereof. Figure 11A program employing a high-level language 1102 is shown to be compiled using an x86 compiler 1104 to generate x86 binary code 1106, which can be executed natively by a processor having at least one x86 instruction set core 1116. A processor having at least one x86 instruction set core 1116 refers to any processor that can perform substantially the same functions as an Intel processor having at least one x86 instruction set core by: compatibly executing or otherwise processing (1) a large portion of the instruction set of the Intel x86 instruction set core, or (2) a version of object code for an application or other software targeted to run on an Intel processor having at least one x86 instruction set core, in order to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 1104 represents a compiler operable to generate x86 binary code 1106 (e.g., object code), which can be executed on a processor having at least one x86 instruction set core 1116 with or without additional linking processing. Similarly, Figure 11 A program employing a high-level language 1102 is shown to be compiled using a replaceable instruction set compiler 1108 to generate replaceable instruction set binary code 1110, which can be executed natively by a processor 1114 without at least one x86 instruction set core (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies, Sunnyvale, California and / or the ARM instruction set of ARM Holdings, Sunnyvale, California). An instruction converter 1112 is used to translate the x86 binary code 1106 into code that can be executed natively by the processor 1114 without an x86 instruction set core. This translated code is unlikely to be identical to the replaceable instruction set binary code 1110, as instruction converters capable of doing so are difficult to manufacture; however, the translated code will implement general operations and consist of instructions from the replaceable instruction set. Therefore, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without an x86 instruction set processor or core to execute x86 binary code 1106 through emulation, simulation, or any other process.

[0169] Complex multiplication and accumulation

[0170] Embodiments of the present invention can be used Figure 12 The apparatus shown in the diagram performs complex multiplication and accumulation by using packed real and imaginary data elements. Figure 12The apparatus may be included in the respective processors and / or systems of Figures 4 to 10 as described above, which illustrate processors and systems including embodiments of the present invention, wherein processors 490, 600, 710, 715, 870, 880, and 1010 and systems 700, 800, 900, and 1000 may include Figure 12 Any or all of the blocks and / or elements shown in the diagram can be used in accordance with the... Figure 13 The techniques and / or methods described in the description shall be used to operate.

[0171] The described embodiments perform operations on 16-bit half-precision floating-point values ​​in 128-bit, 256-bit, and 512-bit packed data registers and memory locations. For example, one embodiment multiplies the packed data values ​​in xmm2 and xmm3 / m128, adds the packed data value from xmm1 to the product, and accumulates the result in xmm1, wherein xmm1, xmm2, and xmm3 / m128 store the real components of the complex number in even elements and the imaginary components of the complex number in odd elements. However, other embodiments may perform operations on other sizes and / or data types.

[0172] In an embodiment, processing hardware including a fused multiply-accumulator performs a first calculation to compute the real component of the result and a second calculation to compute the imaginary component of the result. Using the notations X = Xr + i*Xi, Y = Yr + i*Yi, and Z = Zr = i*Zi to represent a first complex number X having a real component Xr and an imaginary component Xi, a second complex number Y having a real component Yr and an imaginary component Yi, and a third complex number Z having a real component Zr and an imaginary component Zi, respectively, the first calculation can be expressed as Zr + Xr*Yr - Xi*Yi, and the second calculation can be expressed as Zi + Xr*Yi + Yr*Xi, because (Xr + i*Xi)(Yr + i*Yi) = [Xr*Yr + i*Xi...]. 2 (Xi*Yi)]+i[Xr*Yi+Yr*Xi].

[0173] The embodiment uses processing hardware to perform these two calculations in response to decoding a single instruction, which is identified herein using the mnemonic VCFMADDPH. In contrast, other approaches to performing complex multiplication-accumulation can use more than one instruction, such as a combination of instructions including one or more scrambling instructions and one or more multiply-accumulate instructions.

[0174] The following pseudocode specifies the computation performed in one embodiment, where SRC1 and SRC2 are source registers or memory locations, TEMP is a register used to store intermediate values, DEST is a source and destination register, real components are stored in even elements (e.g., the lower 16 bits of each 32-bit word) of the source and destination registers or memory locations, and virtual components are stored in odd elements (e.g., the higher 16 bits of each 32-bit word) of the source and destination registers or memory locations.

[0175] Example pseudocode for calculating even elements:

[0176] TEMP[15:0]←DEST[15:0]+SRC1[15:0]*SRC2[15:0]

[0177] DEST[15:0]←TEMP[15:0]-SRC1[31:16]*SRC2[31:16]

[0178] Example pseudocode for calculating odd elements:

[0179] TEMP[31:16]←DEST{31:16]+SRC1[31:16]*SRC2[15:0]

[0180] DEST[31:16]←TEMP[31:16]+SRC1[15:0]*SRC2[31:16]

[0181] Therefore, the real components of the result are stored in the even elements of DEST, and the imaginary components of the result are stored in the odd elements of DEST.

[0182] In addition, the execution of a single VCFMADDPH instruction can also perform two operations to calculate the real and imaginary components of other words in the packing result, such as the other three words in the 128-bit packing result, the other seven words in the 256-bit packing result, or the other fifteen words in the 512-bit packing result.

[0183] In embodiments, the processor's ISA may include a first single instruction (e.g., VCFADDPH) to perform a complex multiplication-addition as described above, and a second single instruction, identified herein by the mnemonic VCFCMADDPH, to perform a conjugate version of the complex multiplication performed by VCFMADDPH. For example, in embodiments where VCFMADDPH is to compute even elements, including subtracting the product of two odd input elements from the product of two corresponding even input elements, VCFCMADDPH is to compute even elements, including adding the product of two odd input elements to the product of two corresponding even input elements.

[0184] In various embodiments, either or both of the VCFMADDPH and VCFCMADDPH instructions can provide optional write masking, broadcasting, and / or zeroing.

[0185] Return to Figure 12 Register file 1210 can store a first vector X in a first source register, a second vector Y in a second source register, and a third vector X in a source / destination register, where each of vectors X, Y, and Z can represent a set of n complex numbers. Each pair of even and odd elements of X (e.g., X[0] and X[1], X[2] and X[3]...X[2n-2] and X[2n-1]) can store the real component of the complex number in the even element and the imaginary component of the complex number in the odd element. Similarly, each pair of even and odd elements of Y (e.g., Y[0] and Y[1], Y[2] and Y[3]...Y[2n-2] and Y[2n-1]) can store the real component of the complex number in the even element and the imaginary component of the complex number in the odd element; and each pair of even and odd elements of Z (e.g., Z[0] and Z[1], Z[2] and Z[3]...Z[2n-2] and Z[2n-1]) can store the real component of the complex number in the even element and the imaginary component of the complex number in the odd element.

[0186] The duplication mux 1220 can perform a copy of values ​​from odd elements to even elements (e.g., transforming {a,b,c,d} into {b,b,d,d}). In one embodiment, the duplication mux 1220 can be implemented in hardware with a dual-input vector, single-output vector multiplexer circuit. The swap mux 1230 can perform a copy of values ​​from odd elements to even elements (e.g., transforming {a,b,c,d} into {b,b,d,d}), a copy of values ​​from even elements to odd elements (e.g., transforming {a,b,c,d} into {a,a,c,c}), or a swap of odd and even elements (e.g., transforming {a,b,c,d} into {b,a,d,c}) based on the values ​​of one or more control signals. In an embodiment, the swap mux 1230 can be implemented in hardware with two dual-input vector, single-output vector multiplexer circuits.

[0187] The fused multiply-adder (FMA) 1240 can be any type of multiplier and adder circuit. In an embodiment, the FMA 1240 can be implemented in hardware with floating-point vector FMA circuitry. The FMA 1240 can multiply each element of any size (e.g., 16 bits) of the first input vector by each element of the same size of the second input vector, and add the product to each element of the same size of the third input vector.

[0188] In an embodiment, the VCFMADDPH instruction can be decoded into two micro-operations, which can enable processing hardware (such as...) Figure 12 The one that calculates the even and odd elements of a vector of complex numbers.

[0189] For example, the first micro-operation can use control signals to cause the hardware to use a first operand (e.g., X) from a first source register in register file 1210 as an input to dup mux 1220; use a second operand (e.g., Y) from a second source register as an input to swap mux 1230; use dup mux 1220 to pass the unchanged first operand to the first input 1241 of FMA 1240; use swap mux 1230 to copy the even elements of the second operand to the odd elements and pass the transformed second operand to the second input 1242 of FMA 1240; use a third operand (e.g., Z) from the source / destination register as the third input 1243 of FMA 1240; perform the FMA operation; and store the result of the FMA operation in a temporary register. Therefore, for example, the first input 1241 of FMA 1240 will be {X[0],X[1],X[2],X[3],…X[2n-2],X[2n-1]}; the second input 1242 of FMA 1240 will be {Y[0],Y[0],Y[2],Y[2],…Y[2n-2],Y[2n-2]}; the third input 1243 of FMA 1240 will be {Z[0],Z[1],Z[2],Z[3],…Z[2n-2],Z[2n-1]}; FMA 1240 will multiply the first input by the second input and add Z to the product; and the FMA result stored in the temporary register will be {Z[0]+X[0]*Y[0],Z[1]+X[1]*Y[0],Z[2]+X[2]*Y[2],Z[3]+X[3]*Y[2],…Z[2n-2]+X[2n-2]*Y[2n-2],Z[2n-1]+X[2n-1]*Y[2n-2]}.

[0190] Continuing with the previous example, the corresponding second micro-operation can use control signals to cause the same hardware to use a second operand (e.g., Y) from a second source register in register file 1210 as an input to dup mux 1220; use a first operand (e.g., X) from a first source register as an input to swap mux 1230; use dupmux 1220 to copy the odd elements of the second operand to even elements and pass the transformed second operand to the first input 1241 of FMA 1240; use swap mux 1230 to swap the even and odd elements of the first operand and pass the transformed first operand to the second input 1242 of FMA 1240; use the result of the first micro-operation from a temporary register as the third input 1243 of FMA 1240; perform the multiplication part of the FMA operation; use a NOT circuit (such as FMA control logic) to invert the even elements of the multiplication result; perform the addition part of the FMA operation; and store the result of the FMA operation in a source / destination register in register file 1210. Therefore, for example, the first input 1241 of FMA 1240 will be {Y[1],Y[1],Y[3],Y[3],…Y[2n-1],Y[2n-1]}; the second input 1242 of FMA 1240 will be {X[1],X[0],X[3],X[2],…X[2n-1],X[2n-2]}; the multiplication result will be {X[1]*Y[1],X[0]*Y[1],X[3]*Y[3],X[2]*Y[3],…X[2n-1]*Y[2n-1],X[2n-2]*Y[2n-1]}; and the FMA result stored in the source / destination register will be {Z[0]+X[0]*Y [0]-X[1]*Y[1],Z[1]+X[1]*Y[0]+X[0]*Y[1],Z[2]+X[2]*Y[2]-X[3]*Y[3],Z[3]+X[3]*Y[2]+X[2]*Y [3],…Z[2n-2]+X[2n-2]*Y[2n-2]-X[2n-1]*Y[2n-1],Z[2n-1]+X[2n-1]*Y[2n-2]+X[2n-2]*Y[2n-1]}.

[0191] Therefore, the real component of the result is stored in the even element of the destination register, and the imaginary component of the result is stored in the odd element of the destination register.

[0192] exist Figure 13 The figure illustrates a method according to an embodiment of the present invention. The method can be implemented within the context of the processor architecture described herein, but is not limited to any particular processor architecture.

[0193] In step 1302, a first instruction (e.g., VCFMADDPH) is fetched, which has fields specifying the opcode, first and second source operands, and source / destination operands. In an embodiment, the first and second source operand fields and the source / destination operand field will specify a 128-bit, 256-bit, or 512-bit packed data register that stores a set of complex numbers with 16-bit packed data elements, where each even data element represents a real component of the complex number and each corresponding odd data element represents a corresponding imaginary component of the complex number.

[0194] In step 1304, the first instruction is decoded. In this embodiment, the instruction is decoded into a first micro-operation and a second micro-operation.

[0195] In step 1310, the execution of the first micro-operation begins. The execution of the first micro-operation includes steps 1312, 1314, 1316, and 1318.

[0196] In step 1312, the first operand from the first source register is used as an input to the `dup mux`, and the second operand from the second source register is used as an input to the `swap mux`. In step 1314, the `dup mux` passes the unchanged first operand to the first input of the FMA; the `swap mux` copies the even elements of the second operand to the odd elements and passes the transformed second operand to the second input of the FMA; and the third operand from the source / destination register is used as the third input of the FMA. In step 1316, the FMA operation is performed by multiplying the vectors provided to the first and second inputs and adding the vector provided to the third input to the product. In step 1318, the result of the FMA operation is stored in a temporary register.

[0197] In 1320, the execution of the second micro-operation begins. The execution of the first micro-operation includes 1322, 1324, 1326, and 1328.

[0198] In step 1322, the second operand is used as an input to the `dup mux`, and the first operand is used as an input to the `swap mux`. In step 1324, the `dup mux` copies the odd elements of the second operand to the even elements and passes the transformed second operand to the first input of the FMA. The `swap mux` swaps the even and odd elements of the first operand and passes the transformed first operand to the second input of the FMA. The result of the first micro-operation from the temporary register is used as the third input of the FMA. In step 1326, the FMA operation is performed by multiplying the vectors provided to the first and second inputs, inverting the even elements of the multiplication result, and adding the vector provided to the third input to the product. In step 1328, the result of the FMA operation is stored in the destination register.

[0199] Although the real and imaginary values ​​described above are 16 bits in length, the basic principles of this invention can be implemented using data elements of any size. For example, the real and imaginary components can be 8 bits, 32 bits, or 64 bits, while still adhering to the basic principles of this invention. Figure 13 Variations and various other method embodiments are possible within the scope of this invention. As an example, a second instruction (e.g., VCFCMADDPH) may be fetched in 1302, decoded in 1304, and executed in 1326 by omitting the negation of the even elements of the multiplication result. As another example, the first and / or second source operand fields may specify a 128-bit, 256-bit, or 512-bit memory location storing a set of complex numbers with 16-bit packed data elements, where each even data element represents a real component of the complex number and each corresponding odd data element represents a corresponding imaginary component of the complex number.

[0200] The operations in the flowcharts may have been described with reference to exemplary embodiments of other figures. However, it should be understood that the operations in the flowcharts may be performed by embodiments of the invention other than those discussed with reference to other figures, and the embodiments of the invention discussed with reference to other figures may perform different operations than those discussed with reference to the flowcharts. Furthermore, while the flowcharts in the figures illustrate a specific order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary (e.g., alternative embodiments may perform operations in a different order, combine certain operations, overlap certain operations, etc.).

[0201] Therefore, the present invention can be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform operations. Alternatively, these operations can be performed by a specific hardware component containing logic for performing the operations, or by any combination of programmed computer components and custom hardware components.

[0202] Therefore, one or more portions of embodiments of the present invention can be implemented using different combinations of software, firmware, and / or hardware. Embodiments can be implemented using electronic devices that store and transmit (internal and / or via a network to other electronic devices) code (consisting of software instructions and sometimes referred to as computer program code or computer program) and / or data, which is done by using machine-readable media (also referred to as computer-readable media), such as machine-readable storage media (e.g., disks, optical disks, read-only memory (ROM), flash memory devices, phase-change memory) and machine-readable transmission media (also referred to as carriers) (e.g., electrical, optical, radio, acoustic, or other forms of propagated signals—such as carrier waves, infrared signals). Thus, an electronic device (e.g., a computer) can include hardware and software, such as a group of one or more processors coupled to one or more machine-readable storage media for storing code to be executed on the group of processors and / or for storing data. For example, an electronic device may include non-volatile memory containing code, because the non-volatile memory retains the code / data even when the electronic device is turned off (when power is removed), and when the electronic device is turned on, the portion of the code to be executed by the processor(s) of the electronic device is typically copied from the slower non-volatile memory to the volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)). A typical electronic device also includes a set or more physical network interfaces for establishing network connections with other electronic devices (for transmitting and / or receiving code and / or data using propagation signals).

[0203] An embodiment of the present invention is a processor including execution circuitry to compute a complex multiplication-accumulation result of a first complex number, a second complex number, and a third complex number in response to a decoded instruction. The computation includes a first operation for computing a first term of the real component and a first term of the imaginary component of the result. The computation also includes a second operation for computing a second term of the real component and a second term of the imaginary component of the result. The processor further includes a decoder, a first source register, a second source register, and source and destination registers. The decoder decodes instructions to generate decoded instructions. The first source register provides the first complex number, the second source register provides the second complex number, and the source and destination registers provide the third complex number.

[0204] The results can be stored in source and destination registers. The first complex number can be one of a first set of complex numbers represented by a first vector stored in the first source register; the second complex number can be one of a second set of complex numbers represented by a second vector stored in the second source register; the third complex number can be one of a third set of complex numbers represented by a third vector; and the result can be a fourth vector representing a fourth set of complex numbers. The first vector can include a first set of elements representing the real components of the first set of complex numbers and a second set of elements representing the imaginary components of the first set of complex numbers; the second vector can include a third set of elements representing the real components of the second set of complex numbers and a fourth set of elements representing the imaginary components of the second set of complex numbers; the third vector can include a fifth set of elements representing the real components of the third set of complex numbers and a sixth set of elements representing the imaginary components of the third set of complex numbers; and the fourth vector can include a seventh set of elements representing the real components of the fourth set of complex numbers and an eighth set of elements representing the imaginary components of the fourth set of complex numbers. The first, third, fifth, and seventh sets of elements can be even elements, and the second, fourth, sixth, and eighth sets of elements can be odd elements. The first real component can be represented by the first even element of the first operand, the first imaginary component can be represented by the first odd element of the first operand, the second real component can be represented by the second even element of the second operand, the second imaginary component can be represented by the second odd element of the second operand, the third real component can be represented by the third even element of the third operand, the third imaginary component can be represented by the third odd element of the third operand, the fourth real component can be represented by the fourth even element of the result, and the fourth imaginary component can be represented by the fourth odd element of the result. The execution circuit may include a first multiplexer to copy the second real component from the second even element of the second operand to the second odd element of the transformed second operand of the first operation. The execution circuit may include a second multiplexer to copy the first real component from the first even element of the first operand to the first odd element of the transformed first operand of the second operation, and to copy the first imaginary component from the first odd element of the first operand to the first even element of the transformed first operand of the second operation, and the first multiplexer may also copy the second imaginary component from the second odd element of the second operand to the second even element of the transformed second operand of the second operation. The execution circuit may include a multiplication circuit and an addition circuit, used as part of a first operation to multiply the first even element of the first operand with the second even element of the transformed second operand of the first operation to calculate a first real product; to add the third even element of the third operand to the first real product to calculate the first term of a fourth real component; to multiply the first odd element of the first operand with the second even element of the transformed second operand of the first operation to calculate a first imaginary product; and to add the third odd element of the third operand to the first imaginary product to calculate the first term of a fourth imaginary component. The processor may include a temporary register in which the first term of the fourth real component and the first term of the fourth imaginary component are stored.The multiplication circuit can be part of a second operation to multiply the first odd element of the transformed first operand of the second operation with the second odd element of the transformed second operand of the second operation to calculate the second term of the fourth real component, and to multiply the first even element of the transformed first operand of the second operation with the second odd element of the transformed second operand of the second operation to calculate the second term of the fourth imaginary component. The execution circuit can include a NOT circuit for inverting the second term of the fourth real component to generate the inverted second term of the fourth real component. The addition circuit can add the first term of the fourth real component to the inverted second term of the fourth real component to calculate the fourth real component, and add the first term of the fourth imaginary component to the second term of the fourth imaginary component to calculate the fourth imaginary component. The execution circuit can include a fused multiply-adder, which includes the multiplication circuit and the addition circuit. The decoder can also decode a second instruction to generate a second decoded instruction, and the execution circuit can execute the second decoded instruction, wherein the execution of the second decoded instruction will include bypassing the NOT circuit and adding the first term of the fourth real component to the second term of the fourth real component to calculate the fourth real component.

[0205] An embodiment of the present invention is a system including a processor and system memory. The system memory may provide a second complex number.

[0206] In an embodiment, a method may include: decoding a first instruction to generate a first micro-operation and a second micro-operation, the first instruction specifying a first operand having a first real component and a first imaginary component, a second operand having a second real component and a second imaginary component, and a third operand having a third real component and a third imaginary component; performing the first micro-operation to compute a first term of a fourth real component and a first term of a fourth imaginary component; performing the second micro-operation to compute a second term of a fourth real component and a second term of a fourth imaginary component, inverting the second term of the fourth real component to generate an inverted second term of the fourth real component, adding the first term of the fourth real component and the inverted second term of the fourth real component to compute a fourth real component, and adding the second term of the fourth imaginary component to compute a fourth imaginary component; and storing the fourth real component and the fourth imaginary component in a destination register.

[0207] Performing the first micro-operation may include multiplying the first real component by the second real component to calculate the first real product, adding the third real component to the first real product to calculate the first term of the fourth real component, multiplying the first imaginary component by the second real component to calculate the first imaginary product, and adding the third imaginary component to the third imaginary product to calculate the first term of the fourth imaginary component. Performing the second micro-operation may include multiplying the first imaginary component by the second imaginary component to calculate the second term of the fourth real component, and multiplying the first real component by the second imaginary component to calculate the second term of the fourth imaginary component.

[0208] In an embodiment, an apparatus may include components for performing any of the methods described above. In an embodiment, a machine-readable tangible medium may store instructions that, when executed by a machine, cause the machine to perform any of the methods described above.

[0209] This application provides the following technical solution:

[0210] 1. A processor, comprising:

[0211] A decoder, which is used to decode the first instruction to generate the first decoded instruction;

[0212] A first source register, in which a first complex number having a first real component and a first imaginary component will be stored;

[0213] The second source register will store the second complex number having a second real component and a second imaginary component;

[0214] Source and destination registers, which are used to store a third complex number having a third real component and a third imaginary component;

[0215] An execution circuit is configured to execute a first decoded instruction, wherein execution of the first decoded instruction includes performing a calculation comprising a first operation and a second operation, the calculation being used to calculate the result of complex multiplication of a first complex number and a second complex number and complex addition of a third complex number, the result being used to include a fourth real component and a fourth imaginary component, the first operation being used to calculate a first term of the fourth real component and a first term of the fourth imaginary component, and the second operation being used to calculate a second term of the fourth real component and a second term of the fourth imaginary component.

[0216] 2. The processor described in technical solution 1, wherein the result will be stored in source and destination registers.

[0217] 3. The processor described in technical solution 1, wherein:

[0218] The first complex number is one of the first set of complex numbers that will be represented by the first vector to be stored in the first source register;

[0219] The second complex number is one of the second set of complex numbers, which will be represented by the second vector that will be stored in the second source register;

[0220] The third complex number is one of the third set of complex numbers, represented by a third vector that will be stored in the source and destination registers; and

[0221] The result is the fourth vector used to represent the fourth group of complex numbers.

[0222] 4. The processor described in technical solution 3, wherein:

[0223] The first vector will include a first set of elements for representing the real components of the first group of complex numbers and a second set of elements for representing the imaginary components of the first group of complex numbers;

[0224] The second vector will include a third set of elements for representing the real components of the second group of complex numbers and a fourth set of elements for representing the imaginary components of the second group of complex numbers.

[0225] The third vector will include a fifth set of elements representing the real components of the third group of complex numbers and a sixth set of elements representing the imaginary components of the third group of complex numbers; and

[0226] The fourth vector will include a seventh set of elements to represent the real components of the fourth group of complex numbers and an eighth set of elements to represent the imaginary components of the fourth group of complex numbers.

[0227] 5. The processor described in technical solution 4, wherein the first, third, fifth and seventh groups of elements are even elements, and the second, fourth, sixth and eighth groups of elements are odd elements.

[0228] 6. The processor described in technical solution 1, wherein:

[0229] The first real component will be represented by the first even element of the first operand and the first imaginary component will be represented by the first odd element of the first operand;

[0230] The second real component will be represented by the second even element of the second operand and the second imaginary component will be represented by the second odd element of the second operand;

[0231] The third real component will be represented by the third even element of the third operand, and the third imaginary component will be represented by the third odd element of the third operand; and

[0232] The fourth real component will be represented by the fourth even element of the result, and the fourth imaginary component will be represented by the fourth odd element of the result.

[0233] 7. The processor of claim 6, wherein the execution circuitry includes a first multiplexer to copy a second real component from a second even element of a second operand to a second odd element of a transformed second operand of a first operation.

[0234] 8. The processor of technical solution 7, wherein the execution circuit further includes a second multiplexer for copying a first real component from a first even element of a first operand to a first odd element of a transformed first operand of a second operation, and for copying a first imaginary component from a first odd element of a first operand to a first even element of a transformed first operand of a second operation, and the first multiplexer is further configured to copy a second imaginary component from a second odd element of a second operand to a second even element of a transformed second operand of a second operation.

[0235] 9. The processor of technical solution 8, wherein the execution circuit further includes a multiplication circuit and an addition circuit for use as part of the first operation:

[0236] The first even element of the first operand is multiplied by the second even element of the transformed second operand of the first operation to calculate the first real product, and the third even element of the third operand is added to the first real product to calculate the first term of the fourth real component.

[0237] The first odd element of the first operand is multiplied by the second even element of the transformed second operand of the first operation to calculate the first imaginary product, and the third odd element of the third operand is added to the first imaginary product to calculate the first term of the fourth imaginary component.

[0238] 10. The processor of technical solution 9 further includes a temporary register in which the first item of the fourth real component and the first item of the fourth imaginary component are stored.

[0239] 11. The processor of technical solution 10, wherein the fused multiplication circuitry is further used as part of the second operation:

[0240] The first odd element of the transformed first operand of the second operation is multiplied by the second odd element of the transformed second operand of the second operation to calculate the second term of the fourth real component, and the first even element of the transformed first operand of the second operation is multiplied by the second odd element of the transformed second operand of the second operation to calculate the second term of the fourth imaginary component.

[0241] 12. The processor of claim 11, wherein the execution circuitry further includes a NOT circuitry for inverting the second term of the fourth real component to generate the inverted second term of the fourth real component.

[0242] 13. The processor of technical solution 12, wherein the addition circuit is further used for:

[0243] The first term of the fourth real component is added to the inverted second term of the fourth real component to calculate the fourth real component; and

[0244] The first term of the fourth imaginary component is added to the second term of the fourth imaginary component to calculate the fourth imaginary component.

[0245] 14. The processor of claim 13, wherein the execution circuitry further comprises a fused multiply-adder, which includes a multiplication circuit and an adder circuit.

[0246] 15. The processor described in technical solution 14, wherein:

[0247] The decoder is also used to decode the second instruction to generate a second decoded instruction; and

[0248] The execution circuit can also be used to execute a second decoded instruction, wherein the execution of the second decoded instruction will include bypassing the non-circuit and adding the first term of the fourth real component to the second term of the fourth real component to calculate the fourth real component.

[0249] 16. A method comprising:

[0250] Decode the first instruction to generate the first micro-operation and the second micro-operation, wherein the first instruction is used to specify a first operand having a first real component and a first imaginary component, a second operand having a second real component and a second imaginary component, and a third operand having a third real component and a third imaginary component;

[0251] Perform the first micro-operation to calculate the first term of the fourth real component and the first term of the fourth imaginary component;

[0252] The second micro-operation is performed to calculate the second term of the fourth real component and the second term of the fourth imaginary component; the second term of the fourth real component is inverted to generate the inverted second term of the fourth real component; the first term of the fourth real component is added to the inverted second term of the fourth real component to calculate the fourth real component; and the second term of the third imaginary component is added to the second term of the fourth imaginary component to calculate the fourth imaginary component; and

[0253] Store the fourth real component and the fourth imaginary component in the destination register.

[0254] 17. The method described in technical solution 16, wherein performing the first micro-operation includes:

[0255] Multiply the first real component by the second real component to calculate the first real product;

[0256] The first term of the fourth real component is calculated by multiplying the third real component by the first real component;

[0257] Multiply the first imaginary component by the second real component to calculate the first imaginary product; and

[0258] The first term of the fourth imaginary component is calculated by adding the product of the third imaginary component and the first imaginary component.

[0259] 18. The method of technical solution 17, wherein performing the second micro-operation includes:

[0260] Multiply the first imaginary component by the second imaginary component to calculate the second term of the fourth real component; and

[0261] Multiply the first real component by the second imaginary component to calculate the second term of the fourth imaginary component.

[0262] 19. A machine-readable medium having program code stored thereon, said program code, when executed by a machine, causing the machine to perform the following operations:

[0263] Decode the first instruction to generate the first micro-operation and the second micro-operation, wherein the first instruction is used to specify a first operand having a first real component and a first imaginary component, a second operand having a second real component and a second imaginary component, and a third operand having a third real component and a third imaginary component;

[0264] Perform the first micro-operation to calculate the first term of the fourth real component and the first term of the fourth imaginary component;

[0265] The second micro-operation is performed to calculate the second term of the fourth real component and the second term of the fourth imaginary component; the second term of the fourth real component is inverted to generate the inverted second term of the fourth real component; the first term of the fourth real component is added to the inverted second term of the fourth real component to calculate the fourth real component; and the second term of the fourth imaginary component is added to the second term of the fourth imaginary component to calculate the fourth imaginary component; and

[0266] Store the fourth real component and the fourth imaginary component in the destination register.

[0267] 20. The machine-readable medium of technical solution 19, wherein:

[0268] Performing the first micro-operation includes multiplying the first real component by the second real component to calculate the first real product, adding the third real component to the first real product to calculate the first term of the fourth real component, multiplying the first imaginary component by the second real component to calculate the first imaginary product, and adding the third imaginary component to the first imaginary product to calculate the first term of the fourth imaginary component; and

[0269] Performing the second micro-operation includes multiplying the first imaginary component by the second imaginary component to calculate the second term of the fourth real component, and multiplying the first real component by the second imaginary component to calculate the second term of the fourth imaginary component.

[0270] Although the invention has been described with reference to several embodiments, the invention is not limited to the described embodiments, and it can be practiced with various modifications without departing from the spirit and scope of the invention as set forth in the appended claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An apparatus for complex number multiplication and accumulation, comprising: A decoder is used to decode a first instruction, which has a first operand, a second operand, and a third operand; Wherein, the first operand is used to specify a first register to store a first plurality of packed complex numbers, the second operand is used to specify a second register to store a second plurality of packed complex numbers, and the third operand is used to specify a third register to store a third plurality of packed complex numbers, and each packed complex number consists of a 16-bit half-precision floating-point element in the even position corresponding to the real component and a 16-bit half-precision floating-point element in the odd position corresponding to the imaginary component; and An execution circuit, coupled to the decoding circuit, is configured to perform an operation corresponding to the first instruction, the operation including, for at least one of the first plurality of packed complexes: Multiply the elements in even positions of the corresponding second-packed complex number together to generate a first product, and multiply the elements in odd positions of the corresponding second-packed complex number together to generate a second product. The elements at the odd positions and the elements at the even positions of the corresponding second packed complex number are multiplied to generate a third product. The elements in the even positions and the elements in the odd positions of the corresponding second packed complex number are multiplied to generate a fourth product. The first result is generated by subtracting the second product from the sum of the first product and the elements in the even positions of the corresponding third packed complex number. The second result is generated by adding the third product to the elements in the odd positions of the corresponding third packed complex number and the fourth product. The first result is stored in the even position of the corresponding complex number generated in the destination register, and The second result is stored in the odd position of the packed complex number generated by the corresponding result in the destination register.

2. The apparatus of claim 1, wherein, The execution circuit is further configured to copy the element in the even position of the corresponding second packed complex number to the odd position of the transformed second packed complex number.

3. The apparatus of claim 1, wherein, The execution circuit is further configured to copy the element in the even position of the at least one first packed complex number to the odd position of the transformed first packed complex number.

4. The apparatus of claim 1, wherein, The execution circuit is further configured to copy the element in the odd position of the at least one first packed complex number to the even position of the transformed first packed complex number.

5. The apparatus of claim 1, wherein, The execution circuit is further configured to copy the element in the odd position of the corresponding second packed complex number to the even position of the transformed second packed complex number.

6. The apparatus of claim 1, wherein, The decoder is also configured to decode the second instruction, and the execution circuit is configured to perform an operation corresponding to the second instruction, including, for at least one of the first plurality of packed complex numbers, adding the second product to the first product to generate the first result, rather than subtracting the second product from the first product to generate the first result.

7. A method for complex number multiplication and accumulation, comprising: Decode the first instruction, which has a first operand, a second operand, and a third operand; Wherein, the first operand is used to specify a first register to store a first plurality of packed complex numbers, the second operand is used to specify a second register to store a second plurality of packed complex numbers, and the third operand is used to specify a third register to store a third plurality of packed complex numbers, and each packed complex number consists of a 16-bit half-precision floating-point element in the even position corresponding to the real component and a 16-bit half-precision floating-point element in the odd position corresponding to the imaginary component; and Perform the operation corresponding to the first instruction, the operation including for at least one first packaged complex among the first plurality of packaged complexes: Multiply the elements in the even positions of the corresponding second packed complex number by the elements in the even positions to generate the first product. The elements at odd positions of the corresponding second packed complex number are multiplied together to generate the second product. The elements at the odd positions and the elements at the even positions of the corresponding second packed complex number are multiplied to generate a third product. The elements in the even positions and the elements in the odd positions of the corresponding second packed complex number are multiplied to generate a fourth product. The first result is generated by subtracting the second product from the sum of the first product and the elements in the even positions of the corresponding third packed complex number. The second result is generated by adding the third product to the elements in the odd positions of the corresponding third packed complex number and the fourth product. The first result is stored in the even position of the corresponding complex number generated in the destination register, and The second result is stored in the odd position of the packed complex number generated by the corresponding result in the destination register.

8. The method of claim 7, wherein, The operation further includes copying the element in the even position of the corresponding second packed complex number to the odd position of the transformed second packed complex number.

9. The method of claim 7, wherein, The operation further includes copying the element from the even position of the at least one first packed complex number to the odd position of the transformed first packed complex number.

10. The method of claim 7, wherein, The operation further includes copying the element from the odd position of the at least one first packed complex number to the even position of the transformed first packed complex number.

11. The method of claim 7, wherein, The operation further includes copying the element in the odd position of the corresponding second packed complex number to the even position of the transformed second packed complex number.

12. The method of claim 7, further comprising decoding the second instruction and performing an operation corresponding to the second instruction, the operation comprising, for at least one of the first plurality of packed complex numbers, adding the second product to the first product to generate the first result, rather than subtracting the second product from the first product to generate the first result.

13. A non-transitory machine-readable medium storing a first instruction having a first operand, a second operand, and a third operand; in, The first operand is used to specify a first register to store a first plurality of packed complex numbers, the second operand is used to specify a second register to store a second plurality of packed complex numbers, and the third operand is used to specify a third register to store a third plurality of packed complex numbers. Each packed complex number consists of a group of 16-bit half-precision floating-point elements in even positions corresponding to the real components and 16-bit half-precision floating-point elements in odd positions corresponding to the imaginary components. The first instruction, when executed by the machine, causes the machine to execute a method, the method including, for at least one of the first plurality of packed complex numbers: Multiply the elements in the even positions of the corresponding second packed complex number by the elements in the even positions to generate the first product. The elements at odd positions of the corresponding second packed complex number are multiplied together to generate the second product. The elements at the odd positions and the elements at the even positions of the corresponding second packed complex number are multiplied to generate a third product. The fourth product is generated by multiplying the element in the even position and the element in the odd position of the corresponding second packed complex number. The first result is generated by subtracting the second product from the sum of the first product and the elements in the even positions of the corresponding third packed complex number. The second result is generated by adding the third product to the elements in the odd positions of the corresponding third packed complex number and the fourth product. The first result is stored in the even position of the packaged complex number generated by the corresponding result in the destination register, and the second result is stored in the odd position of the packaged complex number generated by the corresponding result in the destination register.

14. The non-transitory machine-readable medium of claim 13, wherein, The method further includes copying the element in the even position of the corresponding second packed complex number to the odd position of the transformed second packed complex number.

15. The non-transitory machine-readable medium of claim 13, wherein, The method further includes copying the element from the even position of the at least one first packed complex number to the odd position of the transformed first packed complex number.

16. The non-transitory machine-readable medium of claim 13, wherein, The method further includes copying the element in the odd position of the at least one first packed complex number to the even position of the transformed first packed complex number.

17. The non-transitory machine-readable medium of claim 13, wherein, The method further includes copying the element in the odd position of the corresponding second packed complex number to the even position of the transformed second packed complex number.

18. The non-transitory machine-readable medium of claim 13, further storing a second instruction, wherein the second instruction, when executed by a machine, causes the machine to perform the method, the method comprising, for at least one of the first plurality of packed complexes, adding the second product to the first product to generate the first result, rather than subtracting the second product from the first product to generate the first result.

19. An apparatus for complex number multiplication and accumulation, comprising: A means for decoding a first instruction, the first instruction having a first operand, a second operand, and a third operand; Wherein, the first operand is used to specify a first register to store a first plurality of packed complex numbers, the second operand is used to specify a second register to store a second plurality of packed complex numbers, and the third operand is used to specify a third register to store a third plurality of packed complex numbers, and each packed complex number consists of a 16-bit half-precision floating-point element in the even position corresponding to the real component and a 16-bit half-precision floating-point element in the odd position corresponding to the imaginary component; and A means for performing an operation corresponding to the first instruction, the operation including for at least one first packaged complex among the first plurality of packaged complexes: Multiply the elements in the even positions of the corresponding second packed complex number by the elements in the even positions to generate the first product. The elements at odd positions of the corresponding second packed complex number are multiplied together to generate the second product. The elements at the odd positions and the elements at the even positions of the corresponding second packed complex number are multiplied to generate a third product. The fourth product is generated by multiplying the element in the even position and the element in the odd position of the corresponding second packed complex number. The first result is generated by subtracting the second product from the sum of the first product and the elements in the even positions of the corresponding third packed complex number. The second result is generated by adding the third product to the elements in the odd positions of the corresponding third packed complex number and the fourth product. The first result is stored in the even position of the corresponding complex number generated in the destination register, and The second result is stored in the odd position of the packed complex number generated by the corresponding result in the destination register.

20. The device as claimed in claim 19, wherein, The operation further includes copying the element in the even position of the corresponding second packed complex number to the odd position of the transformed second packed complex number.

21. The device as claimed in claim 19, wherein, The operation further includes copying the element from the even position of the at least one first packed complex number to the odd position of the transformed first packed complex number.

22. The device as claimed in claim 19, wherein, The operation further includes copying the element from the odd position of the at least one first packed complex number to the even position of the transformed first packed complex number.

23. The device as claimed in claim 19, wherein, The operation further includes copying the element in the odd position of the corresponding second packed complex number to the even position of the transformed second packed complex number.

24. The apparatus of claim 19, further comprising means for decoding the second instruction and performing an operation corresponding to the second instruction, the operation comprising, for at least one of the first plurality of packed complex numbers, adding the second product to the first product to generate the first result, rather than subtracting the second product from the first product to generate the first result.

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