Nonvolatile semiconductor memory device and method of operation thereof

Abstract

Embodiments provide a nonvolatile semiconductor memory device that, based on multivalued data, sets a non-selected block including a bad block as usable, thereby improving the yield of a memory cell array. The nonvolatile semiconductor memory device of the embodiments has a memory cell array having a plurality of selected blocks and a plurality of non-selected blocks, and a row decoder having a block decoder that switches the selected blocks or the non-selected blocks. The block decoder, based on the multivalued data, switches to the non-selected blocks in the case where it is determined that the block is a bad block, and switches to the selected blocks in the case where it is determined that the block is not a bad block. Further, the block decoder has a bad block flag circuit having a plurality of latch circuits that store the multivalued data.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-022542 (filed on February 16, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The embodiments of the present invention relate to a non-volatile semiconductor memory device and a method of operating the same. Background Technology

[0004] NAND flash memory is a known non-volatile semiconductor memory device. It is known that NAND flash memory, when bad blocks are present, prevents the driving of the word line corresponding to the logic block. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a non-volatile semiconductor memory device that, based on multi-valued data, enables the use of non-selected blocks containing bad blocks, thereby improving the yield of memory cell arrays.

[0006] The non-volatile semiconductor memory device of this embodiment includes: a memory cell array having multiple selectable blocks and multiple non-selectable blocks, and a row decoder having a block decoder for switching between selectable and non-selectable blocks. The block decoder includes a bad block flag circuit, which has multiple latch circuits storing multi-valued data. Based on the multi-valued data, the block decoder switches to a non-selectable block if it determines that the block is bad, and switches to a selectable block if it determines that the block is not bad. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating an example of the block configuration of a storage system using a non-volatile semiconductor memory device according to an implementation method.

[0008] Figure 2 This is a diagram illustrating an example of the block configuration of a non-volatile semiconductor memory device according to an embodiment.

[0009] Figure 3 This is a diagram illustrating an example of the circuit configuration of a memory cell array according to an implementation method.

[0010] Figure 4 This is a diagram showing a cross-sectional structure example of a memory cell array according to an implementation method.

[0011] Figure 5 This is a diagram illustrating an example of the block structure of a line decoder in an implementation method.

[0012] Figure 6This is a diagram illustrating an example of the circuit configuration of a block decoder in an implementation method.

[0013] Figure 7 This is a diagram illustrating an example of the circuit configuration of the bad block flag circuit in the first embodiment.

[0014] Figure 8A This is a flowchart illustrating examples of unit testing operations for the MLC (quadratic) and SLC (binary) systems in the first embodiment. (Part 1)

[0015] Figure 8B This is a flowchart illustrating examples of unit testing operations for the MLC (quadratic) and SLC (binary) systems in the first embodiment. (Part 2)

[0016] Figure 9 This is a schematic diagram showing the relationship between the cell distribution of a quaternary memory cell and the threshold.

[0017] Figure 10 This is a diagram illustrating an example table of bad block address mappings in the first implementation.

[0018] Figure 11 This is a diagram illustrating the relationship between bad block flag information and determination in the first embodiment.

[0019] Figure 12 This is a flowchart illustrating an example of the power-on reset process in the first embodiment.

[0020] Figure 13 This is a flowchart illustrating an example of the operation of the SLC (binary) buffer in the first embodiment.

[0021] Figure 14 This is a diagram illustrating an example of the circuit configuration of the bad block flag circuit in the second embodiment.

[0022] Figure 15A This is a flowchart illustrating an example of unit testing operations for TLC (octal), TLC (octal) tPROG, and SLC (binary) in the second embodiment. (Part 1)

[0023] Figure 15B This is a flowchart illustrating the operation examples of unit testing for TLC (octal), TLC (octal) tPROG, and SLC (binary) in the second embodiment. (Part 2)

[0024] Figure 16 This is a schematic diagram showing the relationship between the cell distribution of an octal storage unit and the threshold.

[0025] Figure 17 This is a diagram illustrating an example table of bad block address mappings in the second implementation.

[0026] Figure 18 This is a diagram illustrating the relationship between bad block flag information and determination in the second embodiment.

[0027] Figure 19 This is a flowchart illustrating an example of the power-on reset process in the second embodiment.

[0028] Figure 20A This is a flowchart illustrating an example of the operation of the SLC (binary) buffer in the second embodiment.

[0029] Figure 20B This is a flowchart representing a write operation example in TLC (eight-value).

[0030] Figure 21A This is a flowchart illustrating the operation examples of the failure bit count determination test in the third embodiment, using 10 bits, 50 bits, and 100 bits. (Part 1)

[0031] Figure 21B This is a flowchart illustrating the operation examples of the failure bit count determination test for 10 bits, 50 bits, and 100 bits in the third embodiment. (Part 2)

[0032] Figure 22 This is a diagram illustrating the relationship between bad block flag information and determination in the third embodiment.

[0033] Explanation of reference numerals in the attached figures

[0034] 1… Storage system,

[0035] 10… Controller,

[0036] 20…Non-volatile semiconductor memory devices (NAND flash memory),

[0037] 21… storage cell array,

[0038] 22…Input / output circuit,

[0039] 23… Logic control circuit,

[0040] 24… register,

[0041] 25…sequencer,

[0042] 26…Voltage generation circuit,

[0043] 27… drive group,

[0044] 28…line decoder,

[0045] 29…sensor amplification module,

[0046] 51A, 51B... transmission switches,

[0047] 52A, 52B... block decoders

[0048] 53A, 53B, 53A2… bad block flag circuit,

[0049] Tr1, 2, 5…p-channel MOS transistors

[0050] Tr3, Tr4, Tr6~Tr10, Tr11~Tr27, Tr31~Tr51…n-channel MOS transistors. Detailed Implementation

[0051] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the drawings described below, the same or similar parts are labeled with the same or similar reference numerals. The drawings are schematic diagrams.

[0052] Furthermore, the embodiments shown below illustrate apparatus and methods for embodying technical ideas, without specifying the material, shape, structure, or arrangement of the constituent components. Various modifications can be added to these embodiments within the scope of the claims.

[0053] In the following description, pass / fail information for various unit tests such as SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell), as well as tPROG NG block information, are sometimes simplified and recorded as SLC, MLC, TLC, QLC, and tPROG.

[0054] [Implementation Method]

[0055] (Storage system)

[0056] The storage system 1, which employs the non-volatile semiconductor memory device 20 of the embodiment, is configured with blocks such as... Figure 1 As shown.

[0057] Storage system 1 communicates with, for example, an external host device. Storage system 1 holds data from the host device (not shown) and also reads data from the host device.

[0058] like Figure 1As shown, the storage system 1 includes a controller 10 and a non-volatile semiconductor memory device (NAND flash memory) 20. The controller 10 receives instructions from a host device and controls the non-volatile semiconductor memory device 20 based on the received instructions. Specifically, the controller 10 writes data instructed to be written by the host device to the non-volatile semiconductor memory device 20, reads data instructed to be read by the host device from the non-volatile semiconductor memory device 20, and sends it to the host device. The controller 10 is connected to the non-volatile semiconductor memory device 20 via a NAND bus. The non-volatile semiconductor memory device 20 has multiple memory cells and stores data non-volatilely.

[0059] The NAND bus transmits and receives each of the signals / CE, CLE, ALE, / WE, / RE, / WP, / PB, and I / O <7:0> conforming to the NAND interface via separate wiring. The / CE signal is used to enable the non-volatile semiconductor memory device 20. The CLE signal informs the non-volatile semiconductor memory device 20 that, while the CLE signal is at a "H" (high) level, the incoming I / O <7:0> signals are commands. The ALE signal informs the non-volatile semiconductor memory device 20 that, while the ALE signal is at a "H" (high) level, the incoming I / O <7:0> signals are addresses. The / WE signal indicates that, while the / WE signal is at a "L" (low) level, the incoming I / O signals are retrieved from the non-volatile semiconductor memory device 20. The signal / RE indicates the following information: output signal I / O <7:0> to the non-volatile semiconductor memory device 20. The signal / WP is used to indicate whether data writing and erasing are disabled to the non-volatile semiconductor memory device 20. The signal / RB indicates whether the non-volatile semiconductor memory device 20 is in a ready state (accepting instructions from external sources) or a busy state (not accepting instructions from external sources). Signal I / O <7:0> is, for example, an 8-bit signal. Signal I / O <7:0> is the entity of data transmitted and received between the non-volatile semiconductor memory device 20 and the controller 10, including instructions (CMD), addresses (ADD), and data (DAT). Data DAT includes write and read data.

[0060] like Figure 1As shown, the controller 10 includes a processor (central processing unit CPU) 11, built-in memory (random access memory RAM) 12, ECC (Error Check and Correction) circuit 13, NAND interface circuit 14, buffer memory 15, and host interface circuit 16.

[0061] The processor 11 controls the overall operation of the controller 10. For example, in response to a read command received from the host device, the processor 11 issues a read command based on the NAND interface to the non-volatile semiconductor memory device 20. This operation is the same in the case of writing and erasing. In addition, the processor 11 has the function of performing various operations on the read data from the non-volatile semiconductor memory device 20.

[0062] Built-in memory 12, such as DRAM (Dynamic RAM), is used as the operating area of ​​processor 11. Built-in memory 12 holds firmware and various management tables used to manage non-volatile semiconductor memory device 20.

[0063] ECC circuit 13 performs error detection and error correction. Specifically, during data writing, ECC codes are generated for each group of data received from the host device, based on a certain number of data segments. Furthermore, during data reading, ECC decoding is performed based on the ECC codes to detect the presence or absence of errors. And when an error is detected, its bit position is determined and the error is corrected.

[0064] NAND interface circuit 14 is connected to non-volatile semiconductor memory device 20 via NAND bus and manages communication with non-volatile semiconductor memory device 20. According to instructions from processor 11, NAND interface circuit 14 sends instruction CDM, address ADD, and write data to non-volatile semiconductor memory device 20. In addition, NAND interface circuit 14 receives read data from non-volatile semiconductor memory device 20.

[0065] The buffer memory 15 temporarily holds data received by the controller 10 from the non-volatile semiconductor memory device 20 and the host device. The buffer memory 15 is also used, for example, as a storage area to temporarily hold the calculation results corresponding to the read data and read data from the non-volatile semiconductor memory device 20.

[0066] The host interface circuit 16 is connected to the host device and manages communication with the host device. For example, the host interface circuit 16 transmits instructions and data received from the host device to the processor 11 and the buffer memory 15, respectively.

[0067] (The structure of a non-volatile semiconductor memory device)

[0068] The non-volatile semiconductor memory device 20 of the embodiment is composed of blocks, for example... Figure 2 As shown. Figure 2 As shown, the non-volatile semiconductor memory device 20 of the embodiment includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a driver group 27, a line decoder 28, and a sensing amplification module 29.

[0069] The memory cell array 21 comprises multiple blocks BLK (BLK0, BLK1, ...). Each block BLK contains multiple non-volatile memory cell transistors associated with word lines and bit lines. A block BLK serves as an erasure unit, erasing all data within the same block BLK simultaneously. Each block BLK contains multiple string cells SU (SU0, SU1, SU2, ...). Each string cell SU is a collection of NAND strings NS. Each NAND string NS contains multiple memory cell transistors. Hereinafter, memory cell transistors will be referred to simply as "cells". Furthermore, the number of blocks in the memory cell array 21, the number of string cells in a block BLK, and the number of NAND strings in a string cell SU can be set to any number.

[0070] Input / output circuit 22 transmits and receives signals I / O<7:0> with controller 10. Input / output circuit 22 transmits the instruction CMD and address ADD within signals I / O<7:0> to register 24. Input / output circuit 22 transmits and receives write data and read data with sensing amplification module 29.

[0071] The logic control circuit 23 receives signals / CE, CLE, ALE, / WE, / RE, and / WP from the controller 10. Furthermore, the logic control circuit 23 transmits signal / RB to the controller 10 and notifies the outside of the status of the non-volatile semiconductor memory device 20.

[0072] Register 24 holds the instruction CMD and the address ADD. Register 24 transmits the address ADD to the line decoder 28 and the sensing amplifier module 29, and transmits the instruction CMD to the sequencer 25.

[0073] The sequencer 25 receives instructions CMD and controls the entire non-volatile semiconductor memory device 20 according to the sequence based on the received instructions CMD.

[0074] The voltage generation circuit 26 generates the voltage required for data writing, reading, and erasing based on instructions from the sequencer 25. The voltage generation circuit 26 supplies the generated voltage to the driver assembly 27.

[0075] Driver group 27 has multiple drivers and supplies various voltages from voltage generation circuit 26 to row decoder 28 and sensing amplification module 29 based on addresses from register 24. Driver group 27 supplies various voltages to row decoder 28, for example, based on row addresses in the address.

[0076] The row decoder 28 receives the row address from the address ADD in the register 24, and selects the block BLK, etc., based on the block address within the row address. The voltage from the driver group 27 is transmitted to the selected block BLK via the row decoder 28.

[0077] When reading data, the sensing amplification module 29 senses the read data read from the memory cell transistor to the bit line and transmits the sensed read data to the input / output circuit 22. When writing data, the sensing amplification module 29 transmits the write data written via the bit line to the memory cell transistor. Furthermore, the sensing amplification module 29 receives the column address from the address ADD in the register 24 and outputs column data based on the column address.

[0078] (Example of circuit configuration for a memory cell array)

[0079] The circuit configuration of the memory cell array 21 of the non-volatile semiconductor memory device 20 in the embodiment is, for example, Figure 3 As shown. Figure 3 As shown, each NAND string NS includes, for example, i (where i is a natural number) memory cell transistors MT (MT0 to MTi), select transistor ST1, and select transistor ST2. The number i of memory cell transistors MT can be, for example, 8, 16, 32, 64, 96, 128, etc., and is not limited in quantity. The memory cell transistors MT have a stacked gate structure including a control gate and a charge accumulation layer. Alternatively, the memory cell transistors MT may have a stacked gate structure including a control gate and a floating gate. Each memory cell transistor MT is connected in series between select transistors ST1 and ST2. Furthermore, in the following description, "connection" also includes cases where other conductive elements are interposed between them.

[0080] Within a certain block BLK, the gates of the selection transistor ST1 for serial cells SU0 to SU3 are respectively connected to the selection gate lines SGD0 to SGD3. The control gates of the memory cell transistors MT0 to MTi within the same block BLK are respectively connected to word lines WL0 to WLi. That is, word lines WL at the same address are commonly connected to all serial cells SU within the same block BLK. On the other hand, the selection gate line SGD is connected to one of the serial cells SU within the same block BLK.

[0081] Furthermore, the other end of the selection transistor ST1 of the NAND string NS located in the same row of the matrix NAND strings NS in the memory cell array 21 is connected to one of the m bit lines BL (BL0 to BL(m-1) (m is a natural number)). In addition, the bit lines BL are connected to the NAND strings NS in the same column across multiple blocks BLK.

[0082] In addition, the other end of the select transistor ST2 is connected to the source line CELSRC. The source line CELSRC is connected to multiple NAND strings NS across multiple blocks BLK.

[0083] Data erasure is performed simultaneously on all memory cell transistors MT located within the same block BLK. Conversely, data reading and writing are performed simultaneously on multiple memory cell transistors MT that are commonly connected to a word line WL within a string of cells SU of a block BLK. Within a string of cells SU, a group of memory cell transistors MT sharing the word line WL is called a cell unit CU. A cell unit CU is a group of memory cell transistors MT capable of performing simultaneous write or read operations.

[0084] Furthermore, a single memory cell transistor MT can, for example, hold multiple bits of data. Within the same cell group CU, the set of 1 bits held by each memory cell transistor MT in the same bit position is called a "page". A "page" is defined as the storage space formed by a group of memory cell transistors MT within the same cell group CU.

[0085] (Example of a cross-sectional structure of a memory cell array)

[0086] A cross-sectional view of the memory cell array 21 of the non-volatile semiconductor memory device 20 of the embodiment is shown in Figure 4. Figure 4 This refers to the portion associated with two string units SU0 and SU1 within a block BLK. Specifically, Figure 4 The diagram shows the NAND string NS and surrounding portions of each of the two string units SU0 and SU1. Furthermore, Figure 4 The NAND string NS shown is constructed with multiple NAND strings arranged in the X and Y directions. For example, the set of multiple NAND strings NS arranged in the X and Y directions is equivalent to a string unit SU.

[0087] The memory cell array 21 is disposed on the semiconductor substrate 30. The surface parallel to the surface of the semiconductor substrate 30 is designated as the XY plane, and the direction perpendicular to the XY plane is designated as the Z direction. Furthermore, the X direction and the Y direction are orthogonal to each other.

[0088] A p-type well region 30p is disposed on the upper part of the semiconductor substrate 30. For example... Figure 4As shown, multiple NAND strings NS are configured on the p-type well region 30p. Specifically, on the p-type well region 30p, for example, a wiring layer 31 serving as the select gate line (SGS), a wiring layer 32 (WL0 to WLi) serving as the i+1 layer serving as word lines WL0 to WLi, and a wiring layer 33 serving as the select gate line (SGD) are sequentially stacked. Multiple layers of wiring layers 31 and 33 can also be stacked. An insulating layer (not shown) is disposed between the stacked wiring layers 31 to 33.

[0089] Wiring layer 31 is, for example, commonly connected to the gate of the select transistor ST2 of each NAND string NS within a block BLK. Wiring layer 32 is commonly connected in each layer to the control gate of the memory cell transistor MT of each of the multiple NAND strings NS within a block BLK.

[0090] The memory via MH is configured to pass through wiring layers 33, 32, and 31 and reach the p-well region 30p. On the side of the memory via MH, from the outside, a barrier insulating film 34, a charge accumulation layer (insulating film) 35, and a tunnel oxide film 36 are sequentially arranged. A semiconductor pillar (conductive film) 37 is embedded within the memory via MH. The semiconductor pillar 37 is, for example, undoped polysilicon, serving as the current path for the NAND string NS. A wiring layer 38, serving as the bit line BL, is arranged on the upper end of the semiconductor pillar 37.

[0091] As described above, above the p-type well region 30p, there are sequentially stacked selection transistor ST2, multiple memory cell transistors MT, and selection transistor ST1, with one memory hole MH corresponding to one NAND string NS.

[0092] n is configured above the p-type well region 30p. + Type impurity diffusion region 39 and p + Type n impurity diffusion region 40. In n + A contact plug 41 is disposed on the upper surface of the impurity diffusion region 39. A wiring layer 42, functioning as a source line CELSRC, is disposed on the upper surface of the contact plug 41. + A contact plug 43 is disposed on the upper surface of the impurity diffusion layer 40. A wiring layer 44, which functions as a CPWELL trap line, is disposed on the upper surface of the contact plug 43.

[0093] (Example of block structure in a line decoder)

[0094] The blocks of the line decoder 28 of the non-volatile semiconductor memory device 20 in the embodiment constitute, for example, Figure 5 As shown. Figure 5As shown, the line decoder 28 has multiple transmission switches 51 (51A, 51B, ...) and multiple block decoders 52 (52A, 52B, ...).

[0095] A transmission switch group 51 and a block decoder 52 are, for example, assigned to a block BLK. Figure 5 In one example, transmission switch group 51A and block decoder 52A are assigned to block BLK0, and transmission switch group 51B and block decoder 52B are assigned to block BLK1. In the following description, the block that will be the object of writing, reading, and erasing is called the "selected block BLK", and the blocks other than the selected block BLK are called the "non-selected block BLK".

[0096] Furthermore, in the following description, when distinguishing between the nodes corresponding to transmission switch group 51A and block decoder 52A, and the nodes corresponding to transmission switch group 51B and block decoder 52B, the reference numerals will be appended with _A, _B, etc., to distinguish them. For example, the selection block node BLKSEL connected between transmission switch group 51A and block decoder 52A is called selection block node BLKSEL_A, and the selection block node BLKSEL connected between transmission switch group 51B and block decoder 52B is called selection block node BLKSEL_B. Conversely, when not distinguishing between the nodes corresponding to transmission switch group 51A and block decoder 52A, and the nodes corresponding to transmission switch group 51B and block decoder 52B, the reference numerals will not be appended with _A, _B, etc.

[0097] For example, the transmission switch group 51 has (i+6) transmission transistors TTr (TTr0 to TTr5).

[0098] Transmission transistors TTr0 to TTri transmit the voltage supplied from driver group 27 to wirings CG0 to CGi to word lines WL0 to WLi of the selected block BLK. Transmission transistors TTr0 to TTri each have a first terminal connected to the word lines WL0 to WLi of the corresponding block BLK, a second terminal connected to wirings CG0 to CGi, and a gate commonly connected to the node BLKSEL.

[0099] The transfer transistors TTr(i+1) to (i+4) transmit the voltage supplied from the driver group 27 to the wirings SGDL (SGDL0 to SGDL3) to the select gate lines SGD0 to SGD3 of the select block BLK, respectively. The transfer transistors TTr(i+1) to (i+4) each have a first terminal connected to the select gate lines SGD0 to SGD3 of the corresponding block BLK, a second terminal connected to the wirings SGDL0 to SGDL3, and a gate that is commonly connected to the node BLKSEL.

[0100] The transfer transistor TTr(i+5) transfers the voltage supplied from driver group 27 to wiring SGSL to the gate line SGS of select block BLK. The transfer transistor TTr(i+5) has a first terminal connected to the select block gate line SGS of the corresponding block, a second terminal connected to wiring SGSL, and a gate connected to node BLKSEL.

[0101] During data writing, reading, and erasing, the block decoder 52 decodes the block address signal received from register 24. If the decoding result determines that the block BLK corresponding to the block decoder 52 is a selected block, the block decoder 52 outputs an "H" level signal to the node BLKSEL.

[0102] Furthermore, when the block decoder 52 determines that the corresponding block BLK is not the selected block, it outputs an "L" level signal to the node BLKSEL. When the signal output to the node BLKSEL is at the "H" level, it turns on the transmission transistors TTr0 to TTr(i+5), and when it is at the "L" level, it turns off the transmission transistors TTr0 to TTr(i+5).

[0103] The block decoder 52 includes a bad block flag circuit 53, which has multiple latch circuits storing multi-valued data. Specifically, the block decoder 52A includes a bad block flag circuit 53A, and the block decoder 52B includes a bad block flag circuit 53B. Here, multi-valued data refers to the bad block flag information in each of the multiple test storage partitions. Furthermore, the bad block flag information in each of the multiple test storage partitions refers to information indicating whether anomalies such as unit tests have occurred in each block. In the following description, as an example of multi-valued data, information indicating whether anomalies such as unit tests have occurred in each block BLK is also referred to as "bad block flag data". In addition, bad block flag data may also be, for example, unit test pass / fail information, input buffer write time success / failure determination information, and failure bit count determination tests.

[0104] For example, if an anomaly (a bad block) occurs in the selected block BLK, the block decoder 52 can set the signal output by the node BLKSEL to "L" based on the information held in the latch circuit within the bad block flag circuit 53.

[0105] Therefore, for example, in the transmission switch group 51 corresponding to the selected block BLK, when the selected block BLK is normal (not a bad block), the transmission transistors TTr0 to TTr(i+5) are set to the on state. Thus, word lines WL0 to WLi are connected to wirings CG0 to CGi, respectively. Select gate lines SGD0 to SGD3 are connected to wirings SGDL0 to SGDL3, respectively. Select gate SGS is connected to wiring SGSL.

[0106] On the other hand, in the transmission switch group 51 corresponding to the selected block BLK, when the selected block BLK is a bad block, the transmission transistors TTr0 to TTr(i+5) are set to the off state. As a result, the word line WL is electrically cut off by the slave wiring CG, and the selected gate lines SGD and SGS are electrically cut off by the slave wirings SGDL and SGSL, respectively.

[0107] Furthermore, in the transmission switch group 51 corresponding to the non-selection block BLK, when the non-selection block BLK is a bad block, the transmission transistors TTr0 to TTr(i+5) are set to the off state. As a result, the word line WL is electrically cut off by the slave wiring CG, and the select gate lines SGD and SGS are electrically cut off by the slave wirings SGDL and SGSL, respectively.

[0108] For example, according to an instruction issued from the controller 10, if the non-selected block BLK is not a bad block (it can be used under the condition of bad block flag data), the block decoder 52 can set the signal output by node BLKSEL in the non-selected block BLK to "H" based on the information held in the latch circuit in the bad block flag circuit 53.

[0109] Therefore, for example, in the transmission switch group 51 corresponding to the non-selection block BLK, if the non-selection block BLK is not a bad block (it can be used under the condition of bad block flag data), the transmission transistors TTr0 to TTr(i+5) are set to the on state. Thus, word lines WL0 to WLi are connected to wirings CG0 to CGi, respectively. Select gate lines SGD0 to SGD3 are connected to wirings SGDL0 to SGDL3, respectively. Select gate SGS is connected to wiring SGSL.

[0110] Driver group 27 supplies voltage to wiring CG, SGDL, and SGSL according to the address ADD received from register 24. Wiring CG, SGDL, and SGSL transmit each of the transmission switches 51A, 51B, ... from the voltage supplied by driver group 27.

[0111] (Example of a block decoder circuit configuration)

[0112] The circuitry of the block decoder 52 of the non-volatile semiconductor memory device 20 in the embodiment is, for example, configured as a... Figure 6 As shown. In Figure 6 In the example shown, the configuration of block decoder 52A corresponding to block BLK0 is illustrated. Figure 6 As shown, the block decoder 52A includes n-channel MOS transistors Tr3, Tr4, Tr6 to Tr10, p-channel MOS transistors Tr1, Tr2, Tr5, inverters INV1 to 3, and a bad block flag circuit 53A.

[0113] The p-channel MOS transistor Tr1 has a first terminal connected to voltage VDD, a second terminal connected to node N2_A, and a gate connected to node RDEC. Voltage VDD is, for example, the power supply voltage, which enables each transistor Tr within the block decoder 52A to be in the conducting state. Node RDEC is the node whose input block address decoding is enabled by the enable signal. For example, when the block decoder 52A is disabled, node RDEC is set to the "L" level, and when it is enabled, it is set to the "H" level.

[0114] The p-channel MOS transistor Tr2 has a first terminal connected to voltage VDD, a second terminal connected to node N2_A, and a gate connected to node SEL. Node SEL is the node into which the signal input to node N2_A is inverted by inverter INV1.

[0115] Inverter INV1 has an input terminal connected to node N2_A and an output terminal connected to node SEL. That is, inverter INV1 inverts the voltage level in node N2_A and outputs it to node SEL. In other words, nodes N2_A and node SEL have logic level signals that are inverted from each other.

[0116] Inverter INV2 has an input terminal connected to node SEL and an output terminal connected to node RDECADn. That is, inverter INV2 inverts the voltage level in node SEL and outputs it to node RDECADn. In other words, nodes SEL and RDECADn have mutually inverted logic levels. Node RDECADn is the node that receives the signal after the voltage level of node SEL has been inverted by inverter INV2.

[0117] Inverter INV3 has an input terminal connected to node RDECADn and an output terminal connected to the first terminal of n-channel MOS transistor Tr3. That is, inverter INV3 inverts the voltage level in node RDECADn and outputs it to the first terminal of n-channel MOS transistor Tr3. In other words, node RDECADn and the first terminal of n-channel MOS transistor Tr3 have mutually inverted logic level signals.

[0118] n-channel MOS transistors Tr3 and Tr4 are connected in series between the output of inverter INV3 and node BLKSEL_A. Specifically, the first terminal of n-channel MOS transistor Tr3 is connected to the output of inverter INV3, and the second terminal of n-channel MOS transistor Tr4 is connected to node BLKSEL_A. The gates of n-channel MOS transistors Tr3 and Tr4 are respectively supplied with the signal BSTON.

[0119] The p-channel MOS transistor Tr5 has a first terminal connected to the second terminal of the n-channel MOS transistor Tr6, a second terminal connected to node BLKSEL_A, and a gate connected to node RDECADn. Node BLKSEL_A can be at a "H" level, for example, when block BLK0 is the selected block BLK. Furthermore, node BLKSEL_A can be at a "L" level when block BLK0 is the non-selected block BLK.

[0120] The n-channel MOS transistor Tr6 has a first terminal connected to node VRDEC, a second terminal connected to the first terminal of the p-channel MOS transistor Tr5, and a gate connected to node BLKSEL_A. Node VRDEC is used to supply high voltage.

[0121] n-channel MOS transistors Tr7 to Tr8 are connected in series between node N2_A and the first terminal of n-channel MOS transistor Tr9. Specifically, the first terminal of n-channel MOS transistor Tr7 is connected to node N2_A, and the second terminal of n-channel MOS transistor Tr8 is connected to the first terminal of n-channel MOS transistor Tr9. Signals AROWA to AROWE are supplied to the gates of n-channel MOS transistors Tr7 to Tr8, respectively. Signals AROWA to AROWE are generated based on the block address signal. When block BLK0 is the selected block, n-channel MOS transistors Tr7 to Tr8 are respectively turned on.

[0122] The n-channel MOS transistor Tr9 has a first terminal connected to the second terminal of the n-channel MOS transistor Tr8, a second terminal connected to node N1_A, and a gate connected to the signal RDEC. Node N1_A is the node that supplies voltage level to the bad block flag circuit 53A described later.

[0123] The n-channel MOS transistor Tr10 has a first terminal connected to node N1_A, a second terminal connected to voltage VSS, and a gate connected to signal ROMBAEN.

[0124] The p-channel MOS transistors Tr1 and n-channel MOS transistors Tr7-Tr10 constitute the input address decoding section. When signals AROWA-AROWE, RDEC, and ROMBAEN are all at "H" level, node N2_A is grounded and becomes "L" level. In the following explanation, the configuration of p-channel MOS transistors Tr1 and n-channel MOS transistors Tr7-Tr10 will be referred to as the input address decoding section.

[0125] Conversely, as long as node N2_A is not grounded, node N2_A maintains an "H" level. Thus, the input address decoding unit outputs the voltage level of node N2_A to inverter INV1.

[0126] In the following description of the non-volatile semiconductor memory device 20 of the first to third embodiments, the same representation applies to the common parts of the row decoder 28, such as the block decoder 52A, and detailed descriptions are omitted; the different parts are described instead.

[0127] (First Implementation)

[0128] The bad block flag circuit 53 of the non-volatile semiconductor memory device 20 in the first embodiment is configured as follows: Figure 7 As shown. In Figure 7In the example shown, the configuration of the bad block flag circuit 53A corresponding to block BLK0 is illustrated. The bad block flag circuit 53 of the non-volatile semiconductor memory device 20 of the first embodiment has 2 bits of bad block flag data, which is an example of multi-valued data.

[0129] (Example of circuit configuration for the bad block flag circuit in the first embodiment)

[0130] like Figure 7 As shown, the bad block flag circuit 53A consists of n-channel MOS transistors Tr11 to Tr25 and inverters INV4 to INV7.

[0131] n-channel MOS transistors Tr11 and Tr12 are connected in series between node N1_A and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr11 is connected to node N1_A, and the second terminal of n-channel MOS transistor Tr12 is connected to voltage VSS. The gate of n-channel MOS transistor Tr11 is supplied to node GD_A1. Furthermore, the gate of n-channel MOS transistor Tr12 is supplied with signal AROW_A1. That is, when node GD_A1 and signal AROW_A1 are at a "H" level, node N1_A becomes a "L" level. In the following description, the n-channel MOS transistors Tr11 and Tr12 that transmit an "L" level to node N1_A when node GD_A1 and signal AROW_A1 are at a "H" level will be referred to as the "first transistor group".

[0132] Inverters INV4 and INV5 are cross-connected to form the first latch circuit. Specifically, inverter INV4 has an input connected to node GD_A1 and an output connected to node BD_A1. In addition, inverter INV5 has an input connected to node BD_A1 and an output connected to node GD_A1. That is, nodes GD_A1 and BD_A1 have logic levels that are inverted from each other. Specifically, it contains a 1-bit bad block flag. For example, if nodes GD_A1 and BD_A1 are at "H" level and "L" level respectively, it indicates that block BLK0 is not a bad block; if they are at "L" level and "H" level respectively, it indicates that block BLK0 is a bad block. In the following description, an example of the first latch circuit formed by the cross-connection of inverters INV4 and INV5 will also be referred to as "Latch Circuit A".

[0133] n-channel MOS transistors Tr13 and Tr14 are connected in series between node GD_A1 and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr13 is connected to node GD_A1, and the second terminal of n-channel MOS transistor Tr14 is connected to voltage VSS. The gate of n-channel MOS transistor Tr13 is supplied to node RFSET_A1. Furthermore, n-channel MOS transistor Tr14 is supplied to node SET.

[0134] Node RFSET_A1 transmits a signal indicating that block BLK0 is set as a bad block to latch circuit A. Specifically, when node RFSET_A1 is at an "H" level, an "L" level is transmitted to GD_A1, thereby indicating that block BLK0 is set as a bad block to latch circuit A of bad block flag circuit 53A. In the following description, the n-channel MOS transistors Tr13 and TR14 that transmit the information indicating that latch circuit A is set as a bad block are referred to as the "first data setting unit".

[0135] n-channel MOS transistors Tr15 and Tr16 are connected in series between node BD_A1 and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr15 is connected to node BD_A1, and the second terminal of n-channel MOS transistor Tr16 is connected to voltage VSS. The gate of n-channel MOS transistor Tr15 is supplied to node RFRST_A1. Furthermore, n-channel MOS transistor Tr16 is supplied to node SEL.

[0136] Node RFRST_A1 transmits a signal indicating that block BLK0 is a bad block, which is then reset from latch circuit A. Specifically, when node RFRST_A1 is at an "H" level, an "L" level is transmitted to BD_A1, and the information indicating that block BLK0 is not a bad block is reset from latch circuit A of bad block flag circuit 53A. In the following description, the n-channel MOS transistors Tr15 and Tr16 that reset the latch circuit A to indicate that it is a bad block are referred to as the "first data reset section".

[0137] n-channel MOS transistors Tr17 to Tr19 are connected in series between node PBUSBS and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr17 is connected to node PBUSBS, and the second terminal of n-channel MOS transistor Tr19 is connected to voltage VSS.

[0138] The n-channel MOS transistor Tr17 is supplied to node SEL in the gate. Furthermore, the n-channel MOS transistor Tr18 is supplied to node BLKSENSE_A1. Also, the n-channel MOS transistor Tr19 is supplied to node BD_A1. Node BLKSENSE_A1 is used to determine whether information from latch circuit A is being used.

[0139] Node PBUSBS is, for example, a node (the sensing node of bad block flag circuit 53) that transmits the following signal, which is used to sense information held in all bad block flag circuits 53, including bad block flag circuit 53A. Node PBUSBS, for example, becomes a floating state at "H" level when the block BLK corresponding to the bad block flag circuit 53 of the sensing object is a bad block, and becomes a "L" level when it is not a bad block. In the following description, the n-channel MOS transistors Tr17 to Tr19 used to sense information in latch circuit A are referred to as the "second transistor group".

[0140] n-channel MOS transistors Tr20 and Tr21 are connected in series between node N1_A and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr20 is connected to node N1_A, and the second terminal of n-channel MOS transistor Tr21 is connected to voltage VSS. The gate of n-channel MOS transistor Tr20 is supplied to node GD_A2. Furthermore, the gate of n-channel MOS transistor Tr21 is supplied with signal AROW_A2. That is, when node GD_A2 and signal AROW_A2 are at a "H" level, node N1_A becomes a "L" level. In the following explanation, the n-channel MOS transistors Tr20 and Tr21 that supply an "L" level to node N1_A when node GD_A2 and signal AROW_A2 are at a "H" level will be referred to as the "third transistor group".

[0141] Inverters INV6 and INV7 are cross-connected to form a second latch circuit. Specifically, inverter INV6 has an input connected to node GD_A2 and an output connected to node BD_A2. In addition, inverter INV7 has an input connected to node BD_A2 and an output connected to node GD_A2. That is, nodes GD_A2 and BD_A2 have logic levels that are inverted from each other. Specifically, it contains a 1-bit bad block flag. For example, if nodes GD_A2 and BD_A2 are at "H" level and "L" level respectively, it indicates that block BLK0 is not a bad block; if they are at "L" level and "H" level respectively, it indicates that block BLK0 is a bad block. In the following description, an example of a second latch circuit formed by cross-connecting inverters INV6 and INV7 will also be referred to as "Latch Circuit B".

[0142] The n-channel MOS transistor Tr22 has a first terminal connected to node GD_A2, a second terminal connected to the first terminal of the n-channel MOS transistor Tr14, and a gate connected to signal RFSET_A2.

[0143] Node RFSET_A2 transmits a signal indicating that block BLK0 is set as a bad block to latch circuit B. Specifically, when node RFSET_A2 is at an "H" level, an "L" level is transmitted to GD_A2, indicating that block BLK0 is set as a bad block to latch circuit B of bad block flag circuit 53A. In the following description, the n-channel MOS transistor Tr22 that transmits the signal indicating that latch circuit B is set as a bad block is referred to as the "second data setting unit".

[0144] The n-channel MOS transistor Tr23 has a first terminal connected to node BD_A2, a second terminal connected to the first terminal of the n-channel MOS transistor Tr16, and a gate connected to signal RFRST_A2.

[0145] Node RFRST_A2 transmits a signal indicating that block BLK0 is a bad block from latch circuit B. Specifically, when node RFSET_A2 is at an "H" level, an "L" level is transmitted to GD_A2 to indicate that block BLK0 is not a bad block from latch circuit B of bad block flag circuit 53A. In the following description, the n-channel MOS transistor Tr23 that transmits the information indicating that latch circuit B is a bad block is referred to as the "second data reset unit".

[0146] n-channel MOS transistors Tr24 and Tr25 are connected in series between the second terminal of n-channel MOS transistor Tr17 and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr24 is connected to the second terminal of n-channel MOS transistor Tr17, and the second terminal of n-channel MOS transistor Tr25 is connected to voltage VSS.

[0147] The n-channel MOS transistor Tr24 is supplied to node BLKSENSE_A2 in its gate. Additionally, the n-channel MOS transistor Tr25 is supplied to node BD_A2. Node BLKSENSE_A2 is used to determine whether information from latch circuit B is being considered. In the following description, the n-channel MOS transistors Tr24 and Tr25 used to sense information from latch circuit B will be referred to as the "fourth transistor group".

[0148] As explained above, according to the first embodiment, the bad block flag circuit 53 includes latch circuit A and latch circuit B, which are examples of a first latch circuit and a second latch circuit, respectively. It can hold 2 bits of bad block flag data, which is an example of multi-valued data. That is, the bad block flag circuit 53 selects the bad block flag data by registering information from two test partitions that serve as the bad block flag data, thereby switching the state of the non-selected block BLK (registered as a bad block) to the selected block BLK for use. The operation of the bad block flag circuit 53 switching from the non-selected block BLK (registered as a bad block) to the selected block BLK will be explained later.

[0149] (Examples of unit test actions)

[0150] Next, an example of the operation of the unit test of the bad block flag circuit 53 in the first embodiment will be described. Specifically, the bad block flag circuit 53 sets bad block flag data for two unit test results in the 2-bit bad block flag data. The first is 1 bit held in latch circuit A, for example, as a four-value unit test result of MLC. The second is 1 bit held in latch circuit B, for example, as a two-value unit test result of SLC. In the following description, the four-value unit test as MLC is referred to as the MLC unit test. Furthermore, the two-value unit test as SLC is referred to as the SLC unit test.

[0151] An example of the unit test operation of the non-volatile semiconductor memory device 20 according to the first embodiment. Figure 8A as well as Figure 8B As shown. In the cell testing of the non-volatile semiconductor memory device 20, various tests are performed by a tester to detect bad blocks from the memory cell array 21. The address of the detected bad block is written into the memory cell array 21.

[0152] As described above, the bad block flags for different unit tests are registered in each bit through multiple latching circuits within the bad block flag circuit 53. That is, since the block decoder 52 of the first embodiment has 2 bits of bad block flag data, it is written to the memory cell array 21 with four values. Alternatively, the 1-bit bad block flag data for each unit test can also be written to the memory cell array 21 with two values. However, it is not limited to these examples in practice.

[0153] In step S11, the row decoder 28 selects the block BLK of the object based on the row address received from the address ADD in the register 24. Specifically, the row decoder 28, for example, sets the signal output to the node BLKSEL_A to "H" through the block decoder 52A, thereby setting the block BLK0 of the object as the selected block BLK.

[0154] In step S12, the line decoder 28 performs MLC unit tests on the block BLK of the object. Specifically, the line decoder 28 performs MLC unit tests on the block BLK0, which is set as the selected block BLK, for example, through the block decoder 52A.

[0155] In step S13, for the block BLK of the object, the line decoder 28 proceeds to step S14 if the block is bad. If the block is not bad, the process proceeds to step S15.

[0156] In step S14, the line decoder 28 sets the target block BLK in latch circuit A, which is an example of a first latch circuit. Specifically, the line decoder 28 sets node RFSET_A1 to "H" level, for example, through bad block flag circuit 53A in block decoder 52A, which is the target BLK0. By setting node RFSET_A1 to "H" level, bad block flag circuit 53A transmits "L" level to GD_A1, indicating that it sets block BLK0 as a bad block in latch circuit A.

[0157] In step S15, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S16. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S11.

[0158] In step S16, the row decoder 28 selects the block BLK of the object based on the row address received from the address ADD in the register 24. Specifically, the row decoder 28, for example, sets the signal output to the node BLKSEL_A to "H" through the block decoder 52A, and sets the block BLK0 of the object as the selected block BLK.

[0159] In step S17, the line decoder 28 performs SLC unit tests for the block BLK of the object. Specifically, the line decoder 28 performs SLC unit tests, for example, through the block decoder 52A, for the block BLK0 that is set as the selected block BLK.

[0160] In step S18, for the block BLK of the object, the line decoder 28 proceeds to step 19 if the block is bad. If the block is not bad, the process proceeds to step S20.

[0161] In step S19, the line decoder 28 sets the target block BLK in latch circuit B, which is an example of a second latch circuit. Specifically, the line decoder 28 sets node RFSET_A2 to "H" level, for example, through bad block flag circuit 53A in block decoder 52A, which is the target BLK0. By setting node RFSET_A2 to "H" level, bad block flag circuit 53A transmits "L" level to GD_A2, indicating to latch circuit B that block BLK0 is a bad block.

[0162] In step S20, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S21. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S16.

[0163] In step S21, the line decoder 28 searches latch circuit A and latch circuit B. Specifically, starting from block BLK0, the line decoder 28 sequentially checks whether data has been added to latch circuit A and latch circuit B with bad block flags.

[0164] In step S22, when bad block flags are set in latch circuit A and latch circuit B, the line decoder 28 transmits the block address of register 24 to the sensing amplifier module 29.

[0165] In step S23, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S24. If the line decoder 28 receives the row address from address ADD in register 24 but does not select all blocks BLK based on the block address within the row address, return to step S21.

[0166] In step S24, after transmitting the bad block flags from all latch circuits A and B and the block address data from register 24 to the sensing amplification module 29, the line decoder 28 writes to the memory cell array 21.

[0167] As explained above, according to the first embodiment, the row decoder 28 can write data of multiple bad block flags obtained from different unit tests to the memory cell array 21 during the unit test of the non-volatile semiconductor memory device 20. Specifically, during the unit test, the row decoder 28 writes the bad block flag data into the memory cell array 21 as four-valued data, wherein the bad block flag data includes the following unit test results: 1 bit held by one latch circuit A is, for example, the unit test result of MLC, and 1 bit held by the other latch circuit B is, for example, the unit test result of SLC.

[0168] Figure 9 This is a schematic diagram showing the relationship between cell distribution and threshold voltage when four-valued data is written to the storage cell array 21. That is, by writing to block BLK with different threshold voltages, four-valued data can be written to the storage cell array 21. Specifically, Figure 9 For example, for a cell distribution, data "11" represents threshold level Level-0, data "10" represents threshold level Level-1, data "01" represents threshold level Level-2, and data "00" represents threshold level Level-3.

[0169] Figure 10 The address mapping of bad block flag data is shown. This address mapping is, for example, an example of bad block flag data written to the memory cell array 21 through the unit test operations (S11-S24) described above.

[0170] like Figure 10As shown, region A of the bad block flag data is held as 1 bit in latch circuit A, for example, the unit test result of MLC. Similarly, region B of the bad block flag data is held as 1 bit in latch circuit B, for example, the unit test result of SLC. That is, in the block address (block BLK0, block BLK1, ...), corresponding to the unit test of MLC or SLC, in the case of a bad block, a "1" is set to the corresponding block address.

[0171] exist Figure 10 In this code, "0" indicates a good block address, while "1" indicates a bad block address. For example, block BLK0 indicates that both the MLC and SLC unit tests are good. Similarly, block BLK1 indicates that the MLC unit test is bad, but the SLC unit test is good. Block BLK2 indicates that the MLC unit test is good, but the SLC unit test is bad. Block BLK3 indicates that both the MLC and SLC unit tests are bad.

[0172] Figure 11 This is a diagram illustrating an example of the relationship between bad block flags and determination. According to the first embodiment, as... Figure 11 As shown, the non-volatile semiconductor memory device 20, based on the results of a unit test where one bit of A, serving as a bad block marker, is set to MLC, and the results of a unit test where another bit of B, serving as a bad block marker, is set to SLC, can use the non-selected block BLK as the selected block BLK. That is, in Figure 11 For example, if the unit test results for MLC are poor but the unit test results for SLC are good, then it cannot be used in MLC but can be used in SLC ("it works in B"). In the following description, both MLC and SLC unit tests being good are referred to as "completely good". Furthermore, both MLC and SLC unit tests being poor are referred to as "completely bad". However, the actual implementation is not limited to these examples.

[0173] (Example of power-on reset operation)

[0174] Next, an example of the power-on reset operation of the bad block flag circuit 53 in the first embodiment will be described.

[0175] like Figure 12 The diagram illustrates an example of the power-on reset operation of the non-volatile semiconductor memory device 20 according to the first embodiment. For ease of explanation, the method of setting the flag during the power-on reset process will be described, for example.

[0176] After detecting the power supply, the non-volatile semiconductor memory device 20 performs a power-on reset process as an initialization action through the sequencer 25.

[0177] In this power-on reset process, the bad block address stored in the memory cell array 21 is read out and set to one or both of the corresponding latch circuit A and latch circuit B.

[0178] In step S31, the sequencer 25 reads the bad block data from the storage cell array 21 through the sensing amplification module 29. Specifically, it reads the bad block address, column permutation information, and adjustment information from the storage cell array 21 and transmits them to the sensing amplification module 29. Furthermore, the data read from the bad block address stored in the storage cell array 21 can be data other than the bad block address, column permutation information, and adjustment information; it is not limited to these parameters.

[0179] In step S32, the sequencer 25 senses the bad block address data read by the sensing amplification module 29 and transmits the sensed bad block data to the register 24.

[0180] In step S33, the row decoder 28 sets bad block flag data to latch circuits A and B based on the row address received from address ADD in register 24. Specifically, the row decoder 28 sets bad block flag data to latch circuits A and B sequentially, starting from block BLK0. Furthermore, the row decoder 28 sets selected BLK blocks where both latch circuits A and B have data of "0" (i.e., the unit test results for MLC and SLC are completely good), and sets other blocks as non-selected BLK blocks.

[0181] In step S34, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S35. If the line decoder 28 receives the row address from address ADD in register 24 but does not select all blocks BLK based on the block address within the row address, return to step S33.

[0182] In step S35, after all blocks BLK are selected, the sequencer 25 makes the non-volatile semiconductor memory device 20 a chip-ready state that can be accessed, and can receive instructions from the controller 10.

[0183] As explained above, according to the first embodiment, the row decoder 28 completes the data processing of setting multiple bad block flags to latch circuit A and latch circuit B during the power-on reset of the non-volatile semiconductor memory device 20. By completing the data processing of setting multiple bad block flags to latch circuit A and latch circuit B, the row decoder 28 sets bad block addresses judged as bad in different unit tests as non-selectable blocks (BLKs). That is, when a block is judged as bad based on multi-valued data, the row decoder 28 switches to non-selectable blocks; when it is judged not to be a bad block, it switches to selected blocks. In other words, all block BLKs are set as non-selectable blocks (BLKs) when bad block flags are present.

[0184] (Example of SLC buffer actions)

[0185] Next, an example of the operation of the SLC cache, specifically an example of the first instruction of the bad block flag circuit 53 in the first embodiment, will be described. For example... Figure 11 As shown, if in different unit tests, the unit test of one MLC is bad but the unit test of the other SLC is good, then the block BLK can be used exclusively for the SLC. That is, after power-on reset, according to the instruction from the controller 10, for example, in the first instruction (i.e., when using the SLC cache), based on one bit of the bad block flag A being the result of the MLC unit test, and the other bit of the bad block flag B being the result of the SLC unit test, the non-selection block BLK can be switched to a selection block for use. Furthermore, the method for switching the non-selection block BLK to a selection block can be not only based on the instruction from the controller 10, but also, for example, by reading a specific instruction register from register 24 via the sequencer 25. However, it is not limited to these examples in practice.

[0186] like Figure 13 The diagram illustrates an example of the operation of the SLC cache in the non-volatile semiconductor memory device 20 according to the first embodiment. Here, the operation of the SLC cache will be described, for example, when the SLC cache is used according to instructions from the controller 10 after power-on and power-on reset processing.

[0187] In step S41, after the power is connected, the sequencer 25 performs a power-on reset process.

[0188] In step S42, the row decoder 28 searches latch circuit A and latch circuit B. Specifically, the row decoder 28 uses the block decoder 52 to sequentially detect, starting from block BLK0, whether data with a bad block flag set in latch circuit A and latch circuit B is present.

[0189] In step S43, the line decoder 28 extracts bad blocks from the bad block address where latch circuit A is "1" and latch circuit B is "0". If the block meets this condition, the process proceeds to step S44. The line decoder 28 extracts bad blocks from the bad block address where latch circuit A is "1" and latch circuit B is "0". If the block does not meet this condition, the process proceeds to step S45.

[0190] In step S44, the line decoder 28 sets the target bad block from a non-selectable block to a selected block. Specifically, when the line decoder 28 determines, based on the condition that latch circuit A is "1" and latch circuit B is "0", that the block BLK set as the target is a selected block, it outputs an "H" level signal to the node BLKSEL. That is, the line decoder 28 switches from a non-selectable block to a selected block.

[0191] In step S45, the row decoder 28, through the block decoder 52, decodes the block address signal received from the register 24 during data writing, reading, and erasing, and performs data writing, reading, and erasing on the selected block. That is, the row decoder 28 performs writing on the storage cell array 21.

[0192] As explained above, according to the first embodiment, the line decoder 28 switches from a non-selection block to a selection block based on multi-valued data according to the instructions in the register. Specifically, for example, in one example of the first instruction of the non-volatile semiconductor memory device 20, that is, when using SLC cache, the addresses of bad blocks judged as bad in different unit tests are switched from non-selection block BLK to selection block BLK based on the data of latch circuit A and latch circuit B, which serve as multiple bad block flags. That is, the non-selection block BLK becomes a selection block based on the data of multiple bad block flags.

[0193] (Effects of the first implementation method)

[0194] According to the first embodiment, the line decoder 28, which switches between the selected block BLK and the non-selected block BLK, includes latch circuit A and latch circuit B, which are examples of a first latch circuit and a second latch circuit, respectively, and has 2-bit bad block flag data, which is an example of multi-valued data. That is, the bad block flag circuit 53 selects the bad block flag data by registering information of two test partitions that serve as bad block flag data, thereby enabling the non-selected block BLK, which has been registered as a bad block, to be used as the selected block BLK.

[0195] According to the first embodiment, the line decoder 28 is capable of classifying bad blocks, for example, by using a portion of the bad blocks as selected blocks according to a first instruction from the controller 10. This improves the yield rate of the non-volatile semiconductor memory device 20 as a single NAND flash memory unit. Furthermore, by using a portion of the bad blocks as selected blocks, the non-volatile semiconductor memory device 20 can increase the number of block BLKs usable by the controller 10.

[0196] (Second Implementation)

[0197] like Figure 14 The diagram shows an example of the circuit configuration of the bad block flag circuit 53 in the non-volatile semiconductor memory device 20 according to the second embodiment. Figure 14 In the example shown, the configuration of the bad block flag circuit 53A2 corresponding to block BLK0 is illustrated as a bad block flag circuit 53. The bad block flag circuit 53 of the non-volatile semiconductor memory device 20 of the second embodiment has 3 bits of bad block flag data as an example of multi-valued data.

[0198] (Example of circuit configuration for the bad block flag circuit in the second embodiment)

[0199] like Figure 14 As shown, the bad block flag circuit 53A2 includes n-channel MOS transistors Tr31 to Tr51 and inverters INV8 to INV13.

[0200] The bad block flag circuit 53A2, for example, compared with the bad block flag circuit 53A of the first embodiment, also includes a latch circuit C as an example of a third latch circuit, a third data setting unit that sets the latch circuit C to indicate that it is a bad block, a third data reset unit that resets the latch circuit C to indicate that it is a bad block, a fifth transistor group that transmits an "L" level to node N1_A, and a sixth transistor group for sensing information of the latch circuit C.

[0201] like Figure 14 As shown, the bad block flag circuit 53A2 has the same structure as the bad block flag circuit 53A in the first embodiment, which is composed of n-channel MOS transistors Tr31 to Tr45 and inverters INV8 to INV11, consisting of n-channel MOS transistors Tr11 to Tr25 and inverters INV4 to INV7.

[0202] n-channel MOS transistors Tr46 and Tr47 are connected in series between node N1_A and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr46 is connected to node N1_A, and the second terminal of n-channel MOS transistor Tr47 is connected to voltage VSS. The gate of n-channel MOS transistor Tr46 is supplied with voltage at node GD_A3. Furthermore, n-channel MOS transistor Tr47 is supplied with voltage AROW_A3. That is, when node GD_A3 and voltage AROW_A3 are at an "H" level, node N1_A becomes an "L" level. In the following explanation, n-channel MOS transistors Tr46 and Tr47, which supply an "L" level to node N1_A when node GD_A3 and voltage AROW_A3 are at an "H" level, will be referred to as the "fifth transistor group".

[0203] Inverters INV12 and INV13 are cross-connected to form a third latch circuit. Specifically, inverter INV12 has an input connected to node GD_A3 and an output connected to node BD_A3. In addition, inverter INV13 has an input connected to node BD_A3 and an output connected to node GD_A3. That is, nodes GD_A3 and BD_A3 have logic levels that are inverted from each other. Specifically, it contains a 1-bit bad block flag. For example, if nodes GD_A3 and BD_A3 are at "H" level and "L" level respectively, it indicates that block BLK0 is not a bad block; if they are at "L" level and "H" level respectively, it indicates that block BLK0 is a bad block. In the following description, an example of a third latch circuit in which inverters INV12 and INV13 are cross-connected will also be referred to as "latch circuit C".

[0204] The n-channel MOS transistor Tr48 has a first terminal connected to node GD_A3, a second terminal connected to the first terminal of the n-channel MOS transistor Tr34, and a gate connected to signal RFSET_A3.

[0205] Node RFSET_A3 transmits a signal indicating that block BLK0 is set as a bad block to latch circuit C. Specifically, when node RFSET_A3 is at an "H" level, an "L" level is transmitted to GD_A3, indicating that block BLK0 is set as a bad block to latch circuit C of bad block flag circuit 53A. In the following description, the n-channel MOS transistor Tr48 that transmits the signal indicating that latch circuit C is set as a bad block is referred to as the "third data setting unit".

[0206] The n-channel MOS transistor Tr49 has a first terminal connected to node BD_A3, a second terminal connected to the first terminal of the n-channel MOS transistor Tr36, and a gate connected to signal RFRST_A3.

[0207] Node RFRST_A3 transmits a signal indicating that block BLK0 is a bad block from latch circuit C. Specifically, when node RFSET_A3 is at an "H" level, an "L" level is transmitted to GD_A3 to indicate that block BLK0 is not a bad block from latch circuit C of bad block flag circuit 53A. In the following description, the n-channel MOS transistor Tr49 that transmits the information indicating that latch circuit C is a bad block is referred to as the "third data reset section".

[0208] n-channel MOS transistors Tr50 and Tr51 are connected in series between the second terminal of n-channel MOS transistor Tr38 and voltage VSS. Specifically, the first terminal of n-channel MOS transistor Tr50 is connected to the second terminal of n-channel MOS transistor Tr37, and the second terminal of n-channel MOS transistor Tr51 is connected to voltage VSS.

[0209] The gate of n-channel MOS transistor Tr50 is supplied to node BLKSENSE_A3. Furthermore, the gate of n-channel MOS transistor Tr51 is supplied to node BD_A3. Node BLKSENSE_A3 is used to determine whether information from latch circuit C is being used. In the following description, the n-channel MOS transistors Tr50 and Tr51 used to sense information from latch circuit C will be referred to as the "sixth transistor group".

[0210] As explained above, according to the second embodiment, the bad block flag circuit 53 includes latch circuit A, latch circuit B, and latch circuit C, which are examples of a first latch circuit, a second latch circuit, and a third latch circuit. It can hold 3 bits of bad block flag data, which is an example of multi-valued data. That is, the bad block flag circuit 53 selects the bad block flag data by registering information from three test partitions that serve as the bad block flag data, and can switch the non-selected block BLK registered as a bad block to the selected block BLK for use. The operation of the bad block flag circuit 53 switching from the non-selected block BLK registered as a bad block to the selected block BLK will be explained later.

[0211] (Examples of unit test actions)

[0212] Next, an example of the operation of the unit test of the bad block flag circuit 53 in the second embodiment will be described. Specifically, the bad block flag circuit 53 sets the bad block flag data of three unit test results in the 3-bit bad block flag data. The first is a 1-bit unit test result held in latch circuit A, for example, as an octet of TLC. The second is a 1-bit unit test result held in latch circuit B, for example, as an octet of TLC TLC TLCtPROG. The third is a 1-bit unit test result held in latch circuit C, for example, as a binary unit test result of SLC. In the following description, the unit test as an octet of TLC is referred to as the TLC unit test. Here, TLCtPROG refers to the time up to the point where data is written to the input buffer of the memory cell array 21.

[0213] like Figure 15A as well as Figure 15B The image shows an example of the operation of a unit test for the non-volatile semiconductor memory device 20 according to the second embodiment.

[0214] As described above, the bad block flags for different unit tests are registered in each bit through multiple latching circuits within the bad block flag circuit 53. That is, since the block decoder 52 of the second embodiment has 3 bits of bad block flag data, it is written to the memory cell array 21 with an eight-value format. Alternatively, the 1-bit bad block flag data for each unit test can also be written to the memory cell array 21 with a two-value format. However, the implementation is not limited to these examples.

[0215] In step S51, the line decoder 28 selects the block BLK of the object based on the line address received from the address ADD in the register 24.

[0216] In step S52, the line decoder 28 performs TLC unit tests for the block BLK of the object.

[0217] In step S53, for the block BLK of the object, the line decoder 28 proceeds to step S44 if the block is bad. If the block is not bad, the process proceeds to step S45.

[0218] In step S54, the line decoder 28 sets the latch circuit A, which is an example of the first latch circuit, for the block BLK of the object.

[0219] In step S55, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S56. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S51.

[0220] In step S56, the line decoder 28 selects the block BLK of the object based on the line address received from the address ADD in the register 24.

[0221] In step S57, the line decoder 28 performs unit tests of TLCtPROG for the block BLK of the object.

[0222] In step S58, for the block BLK of the object, the line decoder 28 proceeds to step S59 if the block is bad. If the block is not bad, the process proceeds to step S60.

[0223] In step S59, the line decoder 28 sets the latch circuit B, which is an example of the second latch circuit, for the block BLK of the object.

[0224] In step S60, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S61. If the line decoder 28 receives the row address from address ADD in register 24 but does not select all blocks BLK based on the block address within the row address, return to step S56.

[0225] In step S61, the line decoder 28 selects the block BLK of the object based on the line address received from the address ADD in the register 24.

[0226] In step S62, the line decoder 28 performs unit tests of the SLC for the block BLK of the object.

[0227] In step S63, for the block BLK of the object, the line decoder 28 proceeds to step 54 if the block is bad. If the block is not bad, the process proceeds to step S65.

[0228] In step S64, the line decoder 28 sets the latch circuit C, which is an example of a third latch circuit, for the target block BLK. Specifically, the line decoder 28 sets node RFSET_A3 to "H" level, for example, through the bad block flag circuit 53A in the block decoder 52A for the target BLK0. By setting node RFSET_A3 to "H" level, the bad block flag circuit 53A transmits "L" level to GD_A3, thus setting the latch circuit C with the information that block BLK0 is a bad block.

[0229] In step S65, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S66. If the line decoder 28 receives the row address from address ADD in register 24 but does not select all blocks BLK based on the block address within the row address, return to step S61.

[0230] In step S66, the line decoder 28 searches latch circuits A, B, and C. Specifically, starting from block BLK0, the line decoder 28 sequentially checks whether data with a bad block flag set in latch circuits A, B, and C is present.

[0231] In step S67, when the line decoder 28 has set the bad block flag in latch circuit A, latch circuit B, and latch circuit C, it transmits the block address of register 24 to the sensing amplification module 29.

[0232] In step S68, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S69. If the line decoder 28 receives the row address from address ADD in register 24 but does not select all blocks BLK based on the block address within the row address, return to step S66.

[0233] In step S69, after transmitting the bad block flag data of all latch circuits A, B, and C, and the block address data of register 24 to the sensing amplification module 29, the line decoder 28 writes to the memory cell array 21.

[0234] As explained above, according to the second embodiment, the row decoder 28 can write data of multiple bad block flags obtained from different unit tests to the memory cell array 21 during the unit test of the non-volatile semiconductor memory device 20. Specifically, during the unit test, the row decoder 28 writes the bad block flag data into the memory cell array 21 as eight-value data, which includes the following unit test results: a unit test result where 1 bit held by latch circuit A is, for example, TLC (eight-value), a unit test result where 1 bit held by latch circuit B is, for example, TLC (eight-value) tPRG, and a unit test result where 1 bit held by latch circuit C is, for example, SLC.

[0235] Figure 16 This is a schematic diagram showing the relationship between cell distribution and threshold voltage when 8-valued data is written to the memory cell array 21. That is, by writing to block BLK at different threshold voltages, 8-valued data can be written to the memory cell array 21. Specifically, Figure 16 For example, for the cell distribution, it is shown that data "111" is the threshold level Level-0, data "110" is the threshold level Level-1, data "101" is the threshold level Level-2, data "100" is the threshold level Level-3, data "011" is the threshold level Level-4, data "010" is the threshold level Level-5, data "001" is the threshold level Level-6, and data "000" is the threshold level Level-7.

[0236] Figure 17 The address mapping of bad block flag data is shown. This address mapping is, for example, an example of bad block flag data written to the memory cell array 21 through the unit test operation (S51-S69) described above.

[0237] like Figure 17 As shown, region A of the bad block flag data is held as 1 bit in latch circuit A, for example, the unit test result of TLC. Region B of the bad block flag data is held as 1 bit in latch circuit B, for example, the unit test result of TLCtPROG. Region C of the bad block flag data is held as 1 bit in latch circuit C, for example, the unit test result of SLC. That is, in the block address (block BLK0, block BLK1, ...), corresponding to the unit test of TLC, the unit test of TLCtPROG, and the unit test of SLC, in the case of a bad block, "1" is set accordingly to the block address.

[0238] exist Figure 17In this code, "0" indicates that the block address is good. Conversely, "1" indicates that the block address is bad. That is, for example, in block BLK0, the unit tests for TLC, TLCtPROG, and SLC are all good.

[0239] Figure 18 This is a diagram illustrating an example of the relationship between bad block flags and determination. According to the second embodiment, as... Figure 18 As shown, the non-volatile semiconductor memory device 20 can use a non-selected block BLK as a selected block BLK based on the results of a unit test in which 1 bit of A, which serves as a bad block marker, is TLC, the results of a unit test in which 1 bit of B, which serves as a bad block marker, is TLCtPROG, and the results of a unit test in which 1 bit of C, which serves as a bad block marker, is SLC.

[0240] exist Figure 18 For example, if the unit test results for TLC are poor but the unit test results for SLC are good, then although it cannot be used in TLC, it can be used in SLC ("It works in C"). Furthermore, for example, if the unit test results for both TLC and SLC are poor but the unit test results for TLCtPROG are good, then although it cannot be used in TLC, it can be used under the condition that TLCtPROG is slower ("It works in B"). However, in practice, it is not limited to these examples.

[0241] (Example of power-on reset operation)

[0242] Next, an example of the power-on reset operation of the bad block flag circuit 53 in the second embodiment will be described.

[0243] like Figure 19 The diagram illustrates an example of the power-on reset operation of the non-volatile semiconductor memory device 20 according to the second embodiment. For ease of explanation, the method of setting the flag during the power-on reset process will be described, for example.

[0244] After detecting the power supply, the non-volatile semiconductor memory device 20 performs a power-on reset process as an initialization action through the sequencer 25.

[0245] In this power-on reset process, the bad block address stored in the memory cell array 21 is read out and set to one or all of the corresponding latch circuits A, B, and C.

[0246] In step S71, the sequencer 25 reads the data of bad blocks from the storage cell array 21 through the sensing amplification module 29.

[0247] In step S72, the sequencer 25 senses the data of the bad block address read by the sensing amplification module 29 and transmits the sensed and read bad block data to the register 24.

[0248] In step S73, the row decoder 28 sets bad block flag data to latch circuits A, B, and C based on the row address received from address ADD in register 24. Specifically, the row decoder 28 sets bad block flag data to latch circuits A, B, and C sequentially, starting from block BLK0. Furthermore, the row decoder 28 sets the bad block flag data to select BLK for blocks where all data in latch circuits A, B, and C is "0" (i.e., the TLC unit test, TLCtPROG unit test, and SLC unit test results are all good), and sets all other blocks to non-select BLK.

[0249] In step S74, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S75. If the line decoder 28 receives the row address from address ADD in register 24 but does not select all blocks BLK based on the block address within the row address, return to step S73.

[0250] In step S75, when all blocks BLK are selected, the sequencer 25 makes the non-volatile semiconductor memory device 20 a chip-ready state that can be accessed and can receive instructions from the controller 10.

[0251] As explained above, according to the second embodiment, the row decoder 28 completes the data processing of setting multiple bad block flags to latch circuits A, B, and C during the power-on reset of the non-volatile semiconductor memory device 20. By completing the data processing of setting multiple bad block flags to latch circuits A, B, and C, the row decoder 28 sets bad block addresses determined to be bad in different unit tests as non-selectable blocks (BLKs). That is, the row decoder 28 switches to a non-selectable block when it determines a block is bad based on multi-valued data, and switches to a selected block when it determines a block is not bad. In other words, all block BLKs with bad block flags become non-selectable block BLKs.

[0252] (Example of SLC caching actions)

[0253] Next, an example of the operation of the first instruction of the bad block flag circuit 53 in the second embodiment, namely an example of the SLC cache operation, will be described. Figure 18As shown, if in different unit tests, the 1-bit TLC of A, which serves as the bad block flag, fails the unit test, while the 1-bit SLC of C, which serves as the bad block flag, succeeds in the unit test, then block BLK can be used exclusively for SLC. That is, after power-on reset, through instructions from controller 10, such as the first instruction (when using the SLC cache), based on the results of unit tests where the 1-bit of A, which serves as the bad block flag, is TLC, the 1-bit of B, which serves as the bad block flag, is TLCtPROG, and the 1-bit of C, which serves as the bad block flag, is SLC, the non-selection block BLK can be switched to a selection block for use. Furthermore, the method of switching the non-selection block BLK to a selection block is not only executed through instructions from controller 10, but can also be executed by the sequencer 25 reading a specific instruction register from register 24. However, it is not limited to these examples in practice.

[0254] like Figure 20A The diagram illustrates an example of the operation of the SLC cache in the non-volatile semiconductor memory device 20 according to the second embodiment. Here, the operation of the SLC cache will be described, for example, when the SLC cache is used via an instruction from the controller 10 after power is applied and a power-on reset process is performed.

[0255] In step S81, after the power is connected, the sequencer 25 performs a power-on reset process.

[0256] In step S82, the row decoder 28 searches latch circuits A, B, and C. Specifically, the row decoder 28 uses the block decoder 52 to sequentially detect, starting from block BLK0, whether data with a bad block flag set in latch circuits A, B, and C is present.

[0257] In step S83, the line decoder 28 extracts bad blocks from the bad block address where latch circuit A is "1" and latch circuit C is "0". If the block meets this condition, the process proceeds to step S84. The line decoder 28 extracts bad blocks from the bad block address where latch circuit A is "1" and latch circuit C is "0". If the block does not meet this condition, the process proceeds to step S85.

[0258] In step S84, the line decoder 28 sets the target bad block from a non-selectable block to a selected block. Specifically, the line decoder 28, through the block decoder, based on the condition that latch circuit A is "1" and latch circuit C is "0", outputs an "H" level signal to the node BLKSEL when it determines that the target bad block BLK is a selected block. That is, the line decoder 28 switches from a non-selectable block to a selected block.

[0259] In step S85, the row decoder 28, through the block decoder 52, decodes the block address signal received from the register 24 during data writing, reading, and erasing, and performs data writing, reading, and erasing on the selected block. That is, the row decoder 28 performs writing on the storage cell array 21.

[0260] As explained above, according to the second embodiment, the line decoder 28 switches from a non-selection block to a selection block based on multi-valued data according to the instructions in the register. Specifically, for example, in one example of the first instruction of the non-volatile semiconductor memory device 20, i.e., when using SLC cache, the addresses of bad blocks judged as bad in different unit tests are switched from non-selection block BLK to selection block BLK based on the data of latch circuits A, B, and C, which serve as multiple bad block flags. That is, the non-selection block BLK becomes a selection block based on the data of multiple bad block flags.

[0261] (Example of a write operation in TLC)

[0262] Next, an example of the second instruction of the bad block flag circuit 53 in the second embodiment, namely an example of the TLC write operation, will be described. Figure 18 As shown, if in different unit tests, the unit test where 1 bit of A, the bad block flag, is TLC, and the unit test where 1 bit of C, the bad block flag, is SLC, are both good, and the unit test where 1 bit of B, the bad block flag, is TLCtPROG, is bad, then although tPROG is slower, block BLK can be used as TLC. That is, after power-on reset, according to the instruction from controller 10, such as the second instruction (writing under TLC), based on the results of the unit tests where 1 bit of A, the bad block flag, is TLC, the unit test where 1 bit of B, the bad block flag, is TLCtPROG, and the unit test where 1 bit of C, the bad block flag, is SLC, the non-selectable block BLK can be switched to a selected block for use. Furthermore, the method of switching the non-selectable block BLK to a selected block is not only executed by the instruction from controller 10, but also, for example, by the sequencer 25 reading a specific instruction register from register 24. However, it is not limited to these examples.

[0263] like Figure 20B The image shows an example of a TLC-based write operation of the non-volatile semiconductor memory device 20 according to the second embodiment. Here, the TLC-based write operation will be described, for example, when a TLC-based write is performed according to a second instruction from the controller 10 after power is applied and a power-on reset process is performed.

[0264] In step S91, after the power is connected, the sequencer 25 performs a power-on reset process.

[0265] In step S92, the row decoder 28 searches latch circuits A, B, and C. Specifically, the row decoder 28 uses the block decoder 52 to sequentially check, starting from block BLK0, whether data with a bad block flag set in latch circuits A, B, and C is present.

[0266] In step S93, the line decoder 28 extracts bad blocks from the bad block address where latch circuit A and latch circuit C are both "0" and latch circuit B is "1". If the block meets this condition, the process proceeds to step S94. The line decoder 28 extracts bad blocks from the bad block address where latch circuit A and latch circuit C are both "0" and latch circuit B is "1". If the block does not meet this condition, the process proceeds to step S95.

[0267] In step S94, the line decoder 28 sets the target bad block from a non-selectable block to a selected block. Specifically, the line decoder 28, through the block decoder, based on the condition that latch circuits A and C are "0" and latch circuit B is "1", outputs an "H" level signal to the node BLKSEL when the block BLK, which is determined to be the target bad block, is selected. That is, the line decoder 28 switches from a non-selectable block to a selected block.

[0268] In step S95, the row decoder 28, through the block decoder 52, decodes the block address signal received from the register 24 during data writing, reading, and erasing, and performs data writing, reading, and erasing on the selected block. That is, the row decoder 28 performs writing on the storage cell array 21.

[0269] As explained above, according to the second embodiment, the line decoder 28 switches from a non-selection block to a selection block based on multi-valued data according to the instructions in the register. Specifically, for example, in a second instruction of the non-volatile semiconductor memory device 20, i.e., during a write operation using TLC, the addresses of bad blocks judged as bad in different unit tests are switched from non-selection block BLK to selection block BLK based on the data of latch circuits A, B, and C, which serve as multiple bad block flags. That is, the non-selection block BLK becomes a selection block based on the data of multiple bad block flags.

[0270] (Effects of the second implementation method)

[0271] According to the second embodiment, the line decoder 28, in its block decoder that switches between the selected block BLK and the non-selected block BLK, includes latch circuits A, B, and C, which are examples of a first latch circuit, a second latch circuit, and a third latch circuit, respectively. These latch circuits are capable of storing 3 bits of bad block flag data. That is, the bad block flag circuit 53 selects the bad block flag data by registering information from three test partitions that serve as the bad block flag data, enabling the switching of the non-selected block BLK registered as a bad block to the selected block BLK for use.

[0272] According to the second embodiment, the row decoder 28 can classify bad blocks, for example, by using a portion of the bad blocks as selected blocks according to a first instruction from the controller 10. This improves the yield rate of the non-volatile semiconductor memory device 20 as a single NAND flash memory unit. Furthermore, by using a portion of the bad blocks as selected blocks, the non-volatile semiconductor memory device 20 can increase the number of block BLKs usable by the controller 10.

[0273] According to the second embodiment, the line decoder 28 can classify bad blocks, for example, by using a portion of the bad blocks as selected blocks according to a second instruction from the controller 10. This improves the yield rate of the non-volatile semiconductor memory device 20 as a single NAND flash memory unit. Furthermore, by using a portion of the bad blocks as selected blocks, the non-volatile semiconductor memory device 20 can increase the number of block BLKs usable by the controller 10.

[0274] (Third Implementation)

[0275] The bad block flag circuit 53 of the non-volatile semiconductor memory device 20 in the third embodiment has the same circuit configuration as the bad block flag circuit 53 of the non-volatile semiconductor memory device 20 in the second embodiment. That is, the bad block flag circuit 53 of the non-volatile semiconductor memory device 20 in the third embodiment has 3 bits of bad block flag data, which is an example of multi-valued data.

[0276] The bad block flag circuit 53 selects the bad block flag data by registering information from three test partitions that serve as bad block flags, and can switch the non-selectable block BLK registered as a bad block to the selected block BLK for use. The operation of the bad block flag circuit 53 switching from the non-selectable block BLK registered as a bad block to the selected block BLK will be explained later.

[0277] (Examples of unit test actions)

[0278] Next, an example of the operation of the unit test of the bad block flag circuit 53 in the third embodiment will be described. Specifically, the bad block flag circuit 53 sets bad block flag data for three unit test results in the 3-bit bad block flag data. The first is 1 bit held in latch circuit A, for example, as a failure bit count of 10 bits for the determination result. The second is 1 bit held in latch circuit B, for example, as a failure bit count of 50 bits for the determination result. The third is 1 bit held in latch circuit C, for example, as a failure bit count of 100 bits for the determination result.

[0279] like Figure 21A as well as Figure 21B The image shows an example of the operation of a unit test of the non-volatile semiconductor memory device 20 according to the third embodiment.

[0280] As described above, the bad block flags for different unit tests are registered in each bit through multiple latching circuits within the bad block flag circuit 53. That is, since the block decoder 52 of the third embodiment has 3 bits of bad block flag data, it is written to the memory cell array 21 with an eight-value format. Alternatively, the 1-bit bad block flag data for each unit test can also be written to the memory cell array 21 with a two-value format. However, it is not limited to these examples in practice.

[0281] In step S101, the line decoder 28 selects the block BLK of the object based on the line address received from the address ADD in the register 24.

[0282] In step S102, the line decoder 28 performs a failure bit count 10-bit determination test on the block BLK of the object.

[0283] In step S103, for the block BLK of the object, the line decoder 28 proceeds to step S104 if the block is bad. If the block is not bad, the process proceeds to step S105.

[0284] In step S104, the line decoder 28 sets the latch circuit A, which is an example of the first latch circuit, for the block BLK of the object.

[0285] In step S105, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S106. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S101.

[0286] In step S106, the line decoder 28 selects the block BLK of the object based on the line address received from the address ADD in the register 24.

[0287] In step S107, the line decoder 28 performs a failure bit count 50-bit determination test on the block BLK of the object.

[0288] In step S108, for the block BLK of the object, the line decoder 28 proceeds to step S109 if the block is bad. If the block is not bad, the process proceeds to step S110.

[0289] In step S109, the line decoder 28 sets the latch circuit B, which is an example of the second latch circuit, for the block BLK of the object.

[0290] In step S110, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S111. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S106.

[0291] In step S111, the line decoder 28 selects the block BLK of the object based on the line address received from the address ADD in the register 24.

[0292] In step S112, the line decoder 28 performs a failure bit count 100-bit determination test on the block BLK of the object.

[0293] In step S113, for the block BLK of the object, the line decoder 28 proceeds to step S114 if the block is bad. If the block is not bad, the process proceeds to step S115.

[0294] In step S114, the line decoder 28 sets the latch circuit C, which is an example of a third latch circuit, for the block BLK of the object.

[0295] In step S115, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S106. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S111.

[0296] In step S116, the line decoder 28 searches for latch circuit A, latch circuit B, and latch circuit C.

[0297] In step S117, when the line decoder 28 has set the bad block flag in latch circuit A, latch circuit B, and latch circuit C, it transmits the block address of register 24 to the sensing amplification module 29.

[0298] In step S118, if the line decoder 28 selects all blocks BLK based on the row address received from address ADD in register 24, proceed to step S119. If the line decoder 28 receives the row address from address ADD in register 24 and does not select all blocks BLK based on the block address within the row address, return to step S116.

[0299] In step S119, after the line decoder 28 transmits the bad block flag data and the block address data of register 24 from all latch circuits A, B, and C to the sensing amplification module 29, it writes the data into the memory cell array 21.

[0300] As explained above, according to the third embodiment, the row decoder 28 can write data of multiple bad block flags obtained from different unit tests to the memory cell array 21 during the unit test of the non-volatile semiconductor memory device 20. Specifically, during the unit test, the row decoder 28 writes the bad block flag data into the memory cell array 21 as eight-valued data, wherein the bad block flag data includes the following judgment test results: 1 bit held by latch circuit A, for example, a failure bit count of 10 bits; 1 bit held by latch circuit B, for example, a failure bit count of 50 bits; and 1 bit held by latch circuit C, for example, a failure bit count of 100 bits.

[0301] Figure 22 This is a diagram illustrating an example of the relationship between bad block flag data and determination. According to the third embodiment, the non-volatile semiconductor memory device 20, based on a test result showing that 1 bit of bad block flag A has a failure bit count of 10 bits, a test result showing that 1 bit of bad block flag B has a failure bit count of 50 bits, and a test result showing that 1 bit of bad block flag C has a failure bit count of 100 bits, can use a non-selected block BLK as a selected block BLK. That is, as... Figure 22 As shown, the non-volatile semiconductor memory device 20, for example, can be used as a block BLK (which can be used in B) with a low failure bit count when the failure bit count 100-bit determination test result is good and the failure bit count 10-bit determination test result is bad. Furthermore, as... Figure 22As shown, the non-volatile semiconductor memory device 20 can be used as a block BLK (which can be used in A) with a low failure bit count, for example, when the failure bit count of 100 bits determines a good result and the failure bit count of 50 bits determines a bad result. However, it is not limited to these examples in practice.

[0302] (Effects of the third implementation method)

[0303] According to the third embodiment, such as Figure 22 As shown, in the case where the failure bit count 100-bit determination test result is good, and the failure bit count 10-bit determination test result or the failure bit count 50-bit determination test result is bad, the non-volatile semiconductor memory device 20 prioritizes the use of the block BLK with the low failure bit count as the block BLK with the high reliability requirement, thereby improving reliability.

[0304] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A non-volatile semiconductor memory device, comprising: A storage cell array having multiple selectable blocks and multiple non-selectable blocks; and The line decoder has a block decoder that switches between the selected block and the non-selected block. The block decoder includes a bad block flag circuit, which has multiple latch circuits for storing multi-value data. The block decoder, when determining that the current storage block is a bad block based on the multi-value data, switches the current storage block to the non-selected block; when determining that the current storage block is not a bad block based on the multi-value data, it switches the current storage block to the selected block.

2. The non-volatile semiconductor memory device as described in claim 1, It also includes registers that store instruction and block address information, the instructions being used to perform write, read, and erase operations. The line decoder switches from the non-selection block to the selection block based on the instructions in the register and the multi-value data.

3. The non-volatile semiconductor memory device as described in claim 1, The multi-value data is information indicating bad blocks for each of the multiple test storage partitions.

4. The non-volatile semiconductor memory device as described in claim 2, The multi-value data is information indicating bad blocks for each of the multiple test storage partitions.

5. The non-volatile semiconductor memory device as described in claim 3, The bad block flag information is at least one of the following: unit test pass / fail information, input buffer write time availability determination information, and failure bit count determination test.

6. The non-volatile semiconductor memory device as described in claim 4, The bad block flag information is at least one of the following: unit test pass / fail information, input buffer write time availability determination information, and failure bit count determination test.

7. The non-volatile semiconductor memory device as described in claim 2, The instruction has: The first instruction is used to execute a binary single-level cell buffer as 1-bit information; and The second instruction is used to execute the writing of an eight-value three-layer unit as 3-bit information.

8. The non-volatile semiconductor memory device as described in claim 3, The plurality of latch circuits includes a first latch circuit and a second latch circuit. The first latch circuit contains information about the bad block flag of the first test partition among the plurality of test storage partitions. The second latch circuit contains information about setting the bad block flag of the second test partition among the plurality of test storage partitions.

9. The non-volatile semiconductor memory device as claimed in claim 8, The line decoder switches from the non-selected block to the selected block based on the multi-value data, which includes information on bad block flags of the first test partition and bad block flags of the second test partition.

10. The non-volatile semiconductor memory device as claimed in claim 8, The bad block flag information of the first test partition indicates whether an anomaly has occurred in the first test partition. The bad block flag information of the second test partition indicates whether an anomaly has occurred in the second test partition.

11. The non-volatile semiconductor memory device as claimed in claim 8, The first test partition is a multi-level cell unit test partition. The second test partition is a unit test partition for a single-layer cell.

12. The non-volatile semiconductor memory device as claimed in claim 3, The plurality of latch circuits includes a first latch circuit, a second latch circuit, and a third latch circuit. The first latch circuit contains information about the bad block flag of the first test partition among the plurality of test storage partitions. The second latch circuit contains information about the bad block flag of the second test partition among the plurality of test memory partitions. The third latch circuit contains information about the bad block flag of the third test partition among the plurality of test storage partitions.

13. The non-volatile semiconductor memory device as claimed in claim 12, The line decoder switches from the non-selected block to the selected block based on the multi-value data, which includes information on bad block flags of the first test partition, the second test partition, and the third test partition.

14. The non-volatile semiconductor memory device as claimed in claim 12, The bad block flag information of the first test partition indicates whether an anomaly has occurred in the first test partition. The bad block flag information of the second test partition indicates whether an anomaly has occurred in the second test partition. The bad block flag information of the third test partition indicates whether an anomaly has occurred in the third test partition.

15. The non-volatile semiconductor memory device as claimed in claim 12, The first test partition is a three-layer unit test partition. The second test partition is a test partition for the write time of the three-level cell. The third test partition is a unit test partition for a single-layer cell.

16. A method for operating a non-volatile semiconductor memory device. The row decoder receives a row address from a register and sets multi-value data to multiple latch circuits based on the row address. The row decoder has a block decoder that switches between selected and non-selected blocks of the non-volatile semiconductor memory device. The block decoder includes a bad block flag circuit, and the bad block flag circuit has the multiple latch circuits storing the multi-value data. The block decoder, when determining that the current storage block is a bad block based on the multi-value data, switches the current storage block to a non-selected block; when determining that the current storage block is not a bad block based on the multi-value data, it switches the current storage block to a selected block.

17. The method of operating the non-volatile semiconductor memory device as described in claim 16, The multi-value data is information indicating bad blocks for each of the multiple test storage partitions.

18. The method of operating the non-volatile semiconductor memory device as described in claim 17, The bad block flag information is at least one of the following: unit test pass / fail information, input buffer write time availability determination information, and failure bit count determination test.

19. A method for operating a non-volatile semiconductor memory device. The row decoder, based on instructions held in a register, sequentially checks, starting from the first block, whether data with a bad block flag set in multiple latch circuits has been configured. The row decoder also includes a block decoder that switches between selected and non-selected blocks in the non-volatile semiconductor memory device. The block decoder further includes a bad block flag circuit, which in turn includes the multiple latch circuits storing multi-valued data. If data with the bad block flag set is detected, the bad block flag data held in the plurality of latch circuits is extracted from the bad block address. When the block decoder determines that the current storage block is a selected block based on the bad block flag data, it switches the current storage block from a non-selected block to a selected block and performs a write operation on the storage cell array.

20. The method of operating the non-volatile semiconductor memory device as described in claim 19, The instruction has: The first instruction is used to execute a binary single-level cell buffer as 1-bit information; and The second instruction is used to execute the writing of an eight-value three-layer unit as 3-bit information.

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