Fabrication method of shielded gate trench field-effect transistor

Abstract

This invention provides a method for fabricating a shielded gate trench field-effect transistor (G-S Leakage) comprising: forming a barrier stack on a substrate, including a first barrier layer, a second barrier layer, and a third barrier layer stacked sequentially; forming a patterned window in the barrier stack; etching a first trench while retaining the first barrier layer, the second barrier layer, and a portion of the third barrier layer; forming a field plate at the bottom and sidewalls of the first trench; depositing a polysilicon layer to fill the first trench; removing the polysilicon layer above the top surface of the third barrier layer and a portion of the polysilicon layer in the first trench to form a second trench; and performing ion implantation to achieve ion doping of the polysilicon layer within the trench, thereby increasing the IPO thickness and optimizing G-S Leakage performance. This invention effectively simplifies the process, increases the ion implantation process window, reduces process difficulty, and saves process costs. Furthermore, this optimized process does not interfere with the front-end design simulation results and has virtually no impact on electrical parameters.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a method for fabricating a shielded gate trench field-effect transistor. Background Technology

[0002] In the field of low-to-medium voltage devices with a withstand voltage of 60V and above, shielded gate trench (SGT) devices are widely used due to their low specific on-resistance and low gate-drain coupling capacitance. Shielded gate trench MOSFETs are a new type of power semiconductor device that combines the low conduction losses of traditional deep trench MOSFETs with even lower switching losses. As switching devices, shielded gate trench MOSFETs are used in motor drive systems, inverter systems, and power management systems in fields such as new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances, serving as core power control components.

[0003] Existing shielded gate trench MOSFET technology is relatively complex and has a narrow process window, which can easily lead to problems such as increased device leakage current.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a shielded gate trench MOSFET, which solves the problems of complex process, narrow process window and easy increase in leakage current of the device in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a shielded gate trench field-effect transistor. The method includes: providing a substrate; forming a barrier stack on the substrate, the barrier stack including a first barrier layer, a second barrier layer, and a third barrier layer stacked sequentially; forming a patterned window in the barrier stack; etching a first trench in the substrate based on the patterned window; retaining the first barrier layer, the second barrier layer, and a portion of the third barrier layer; forming a field plate at the bottom and sidewalls of the first trench; depositing a polysilicon layer that fills the first trench; removing the polysilicon layer above the top surface of the third barrier layer; further removing a portion of the polysilicon layer in the first trench to form a second trench at the top of the trench; and performing ion implantation using the retained portion of the third barrier layer, the second barrier layer, and the first barrier layer as a mask to achieve ion doping of the polysilicon layer within the trench.

[0007] Optionally, the first barrier layer comprises silicon dioxide, the second barrier layer comprises silicon nitride, and the third barrier layer comprises silicon dioxide.

[0008] Optionally, the third barrier layer is deposited using a chemical vapor deposition method to precisely control the deposition thickness of the third barrier layer, wherein the deposition thickness of the third barrier layer is determined based on the depth of the first trench to be etched and the thickness of the third barrier layer to be retained after etching the first trench.

[0009] Optionally, the thickness of the first barrier layer is 100 angstroms to 200 angstroms, the thickness of the second barrier layer is 1500 angstroms to 2500 angstroms, and the thickness of the third barrier layer is 1500 angstroms to 3000 angstroms.

[0010] Optionally, after etching the first trench in the substrate, the remaining portion of the third barrier layer has a thickness of 300 angstroms to 1000 angstroms.

[0011] Optionally, the second barrier layer is deposited using a furnace tube deposition method, and the second barrier layer is simultaneously deposited on the back side of the substrate. The preparation method further includes the step of removing the second barrier layer on the back side of the substrate by spraying an etchant. When spraying the etchant, the substrate is also rotated.

[0012] Optionally, after removing the polysilicon layer above the top surface of the third barrier layer and before forming the second trench, the process further includes a step of etching back the polysilicon layer, wherein the thickness of the polysilicon layer removed by etching back is 50 nanometers to 150 nanometers.

[0013] Optionally, it also includes a terminal region, and before forming the second trench, it further includes the step of forming an anti-etching layer on the first trench of the terminal region.

[0014] Optionally, the depth of the first trench is 4 micrometers to 6 micrometers, and the depth of the second trench is 0.5 micrometers to 1.5 micrometers.

[0015] Optionally, the ions implanted include arsenic, and the implantation energy is between 80 keV and 150 keV.

[0016] As described above, the method for fabricating the shielded gate trench field-effect transistor of the present invention has the following beneficial effects:

[0017] This invention determines the deposition thickness of the third barrier layer based on the required depth of the first trench and the required thickness of the third barrier layer to be retained after etching the first trench. The third barrier layer is deposited using chemical vapor deposition (CVD) to precisely control its deposition thickness. Retaining a certain thickness of the third barrier layer after the first trench etching avoids the need for subsequent steps of forming an additional LPTEOS oxide film as an ion implantation protective layer within the first trench and on the substrate surface. This prevents the LPTEOS oxide film from reducing the quality of the field oxygen layer on the inner wall of the first trench and limiting or altering its thickness. Furthermore, the thickness range of the retained third barrier layer is highly controllable. While effectively protecting the integrity of the morphology of the second barrier layer during ion implantation, it effectively increases the barrier to implanted ions, thereby significantly increasing the ion implantation process window, reducing process difficulty, and saving process costs. Attached Figure Description

[0018] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0019] Figures 1-12 The diagram shows the structural schematics of each step in the fabrication method of the shielded gate trench field-effect transistor according to an embodiment of the present invention.

[0020] Component designation explanation

[0021] 10 Device Area

[0022] 20 Terminal Area

[0023] 101 substrate

[0024] 102 First Barrier Layer

[0025] 103 Second Barrier Layer

[0026] 104 Third Barrier Layer

[0027] 105 Graphical Window

[0028] 106 First trench

[0029] 107 Gate dielectric layer

[0030] 108 polycrystalline silicon layer

[0031] 109 Second trench

[0032] 110 Shallow layer Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the principle of the present invention.

[0034] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0035] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0036] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0038] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] Due to the need to control the complexity and cost of the shielded gate trench field-effect transistor (SGT) process, the Gate OX in the trench and the Inter Poly Oxide (IPO) on the Shield Poly surface are generally formed in a one-step molding process. However, when the IPO thickness is insufficient, the gate-source leakage (GS Leakage) will increase. Arsenic implantation (As IMP) is introduced to thicken the IPO thickness, thereby improving the gate-source leakage performance. This process typically involves growing an additional 250A to 600A LPTEOS oxide film before arsenic implantation (As IMP) and annealing it for further oxidation and drive-in. This serves as a barrier layer for arsenic implantation (As IMP) on the Mesa surface of the Cell region, thus not interfering with the concentration and depth of subsequent Body IMP and Source IMP implantation (NP IMP) in the substrate region. However, additional LPTEOS oxide film increases process steps and costs. On the other hand, the thickness of LPTEOS oxide film on the substrate surface is limited by the thickness of LPTEOS oxide film in the trench (LPTEOS oxide film in the trench has strict thickness limitations), which limits the implantation energy of arsenic implantation (As IMP) (excessive implantation energy will allow arsenic ions to pass through the LPTEOS oxide film and implantation barrier layer into the Mesa substrate, thus affecting device performance) and reduces the process window for arsenic implantation (As IMP).

[0041] To solve the above problems, such as Figures 1-12 As shown, this embodiment provides a method for fabricating a shielded gate trench field-effect transistor, the method comprising:

[0042] like Figures 1-4As shown, step 1) is performed first, a substrate 101 is provided, and a barrier stack is formed on the substrate 101. The barrier stack includes a first barrier layer 102, a second barrier layer 103 and a third barrier layer 104 stacked in sequence.

[0043] The substrate 101 can be a silicon substrate, germanium substrate, germanium-silicon substrate, group III-V compound substrate, silicon carbide substrate, etc. The substrate 101 can be doped or undoped. In one embodiment, the substrate 101 is selected as an N-type doped silicon substrate.

[0044] In one embodiment, the first barrier layer 102 is a silicon dioxide layer, which can be formed on the surface of the substrate 101 by means such as thermal oxidation, or by means such as chemical vapor deposition. The thickness of the first barrier layer 102 can be in the range of 100 angstroms to 200 angstroms. In a specific example, the thickness of the first barrier layer 102 is 130 angstroms.

[0045] In one embodiment, the second barrier layer 103 is a silicon nitride layer, and the thickness of the second barrier layer 103 can be in the range of 1500 angstroms to 2500 angstroms. In a specific example, the thickness of the second barrier layer 103 is 1800 angstroms.

[0046] In one embodiment, the second barrier layer 103 can be deposited using a furnace tube deposition method. The second barrier layer 103 is simultaneously deposited on the back side of the substrate 101. The fabrication method further includes a step of removing the second barrier layer 103 on the back side of the substrate 101 by spraying an etchant. During the etchant spraying, the substrate 101 is rotated. This method can etch only the back side of the substrate 101 without affecting the silicon nitride layer on the front side of the substrate 101. While removing the silicon nitride layer on the back side of the substrate 101, the morphological integrity of the silicon nitride layer on the front side of the substrate 101 can be effectively maintained.

[0047] In one embodiment, the third barrier layer 104 is a silicon dioxide layer, which can be formed by chemical vapor deposition, such as plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma deposition (HDP-CVD), to more precisely control the deposition thickness of the third barrier layer 104 and improve the quality of the silicon dioxide layer. In one embodiment, the thickness of the third barrier layer 104 is 1500 angstroms to 3000 angstroms; in a specific example, the thickness of the third barrier layer 104 is 2000 angstroms.

[0048] It should be noted that the thicknesses of the first barrier layer 102, the second barrier layer 103, and the third barrier layer 104 can be determined according to actual process requirements and are not limited to the examples listed above.

[0049] like Figures 5-6 As shown, then step 2) is performed, a patterned window 105 is formed in the barrier stack, and a first trench 106 is etched in the substrate 101 based on the patterned window 105, while retaining the first barrier layer 102, the second barrier layer 103 and part of the third barrier layer 104.

[0050] In one embodiment, forming a graphical window 105 in the blocking stack includes the following steps:

[0051] Step 2-1): A photoresist layer is formed on the barrier stack by spin coating.

[0052] Step 2-2): A photolithographic window is formed in the photoresist layer through an exposure process and a development process;

[0053] Steps 2-3) are performed by sequentially etching the third barrier layer 104, the second barrier layer 103 and the first barrier layer 102 using a dry etching process to form a patterned window 105 in the barrier stack.

[0054] Next, a first trench 106 is etched into the substrate 101 using a dry etching process. The depth of the first trench 106 is, for example, 4 to 6 micrometers, but in actual manufacturing, the depth of the first trench 106 can be determined according to actual needs. During the etching process, a portion of the thickness of the third barrier layer 104 is etched away, while a portion of the thickness is retained. This retained portion of the thickness can be, for example, 300 to 1000 angstroms. In one embodiment, the deposition thickness of the third barrier layer 104 in the above steps is determined based on the required depth of the first trench 106 and the required thickness of the third barrier layer 104 after etching the first trench 106. In a specific example, the deposition thickness of the third barrier layer 104 is 2000 angstroms, the etching depth of the first trench 106 is 5 micrometers, and after the first trench 106 is etched, the retained thickness of the third barrier layer 104 is 700 angstroms.

[0055] like Figure 7 As shown, then step 3) is performed to form a field plate 107 at the bottom and sidewall of the first trench 106.

[0056] In one embodiment, a field plate 107, which is a silicon dioxide layer, can be formed on the bottom and sidewalls of the first trench 106 by a thermal oxidation process. The thickness of the field plate 107 is, for example, 4500 angstroms.

[0057] like Figure 8 As shown, then step 4) is performed to deposit a polysilicon layer 108, which fills the first trench 106.

[0058] In one embodiment, the polysilicon layer 108 can be deposited by furnace tube deposition, and the deposition thickness of the polysilicon layer 108 can be, for example, between 7,000 Å and 12,000 Å. In a specific example, the deposition thickness of the polysilicon layer 108 is 8,000 Å.

[0059] like Figures 9-10 As shown, step 5) is then performed, removing the polysilicon layer 108 above the top surface of the third barrier layer 104, and further removing a portion of the polysilicon layer 108 in the first trench 106 to form a second trench 109 at the top of the trench.

[0060] In one embodiment, the polysilicon layer 108 above the top surface of the third barrier layer 104 can be removed by a chemical mechanical polishing (CMP) process.

[0061] In one embodiment, after removing the polysilicon layer 108 above the top surface of the third barrier layer 104 and before forming the second trench 109, a step of etching back the polysilicon layer 108 is included. The thickness of the polysilicon layer 108 removed by etching back is 50 nanometers to 150 nanometers. This step can ensure that the polysilicon layer 108 above the top surface of the third barrier layer 104 can be completely removed and a groove is formed on the top of the polysilicon in the first trench 106 to improve the surface defect morphology of the polysilicon layer 108.

[0062] In one embodiment, the shielded gate trench field-effect transistor includes a device region 10 and a termination region 20. Before forming the second trench 109, the step further includes forming an etch-resistant layer on the first trench 106 of the termination region 20. That is, the second trench 109 is formed only on the top of the first trench 106 of the device region 10, and the top of the first trench 106 of the termination region 20 will not be etched out of the second trench 109 due to the etch-resistant layer. Figure 10 As shown.

[0063] In one embodiment, the depth of the second trench 109 is 0.5 micrometers to 1.5 micrometers, and in a specific example, the depth of the second trench 109 is 1 micrometer.

[0064] like Figures 11-12As shown, in step 6), the remaining portion of the third barrier layer 104, the second barrier layer 103, and the first barrier layer 102 are used as a mask for ion implantation to achieve shallow 110 ion doping of the polysilicon layer ShieldPoly 108 in the trench.

[0065] In one embodiment, the ions implanted include arsenic, and the implantation energy is between 80 keV and 150 keV.

[0066] Specifically, in this embodiment, based on the depth of the first trench 106 to be etched and the thickness of the third barrier layer 104 to be retained after etching the first trench 106, the deposition thickness of the third barrier layer 104 is calculated backward, and the third barrier layer 104 is deposited using chemical vapor deposition to precisely control the deposition thickness of the third barrier layer 104. After the first trench 106 is etched, a certain thickness of the third barrier layer 104 is retained. On the one hand, this avoids the need to form an additional LPTEOS oxide film as an ion implantation protective layer in the first trench 106 and on the surface of the substrate 101, thus avoiding the reduction in the quality of the field oxygen layer on the inner wall of the first trench 106 and the limitation and change of the field oxygen layer thickness caused by the LPTEOS oxide film. On the other hand, the thickness range of the retained third barrier layer 104 is highly controllable. While effectively protecting the integrity of the morphology of the second barrier layer 103 during ion implantation, it effectively increases the barrier to implanted ions, thereby effectively increasing the process window for ion implantation, reducing process difficulty, and saving process costs.

[0067] As described above, the method for fabricating the shielded gate trench field-effect transistor of the present invention has the following beneficial effects:

[0068] This invention determines the deposition thickness of the third barrier layer 104 based on the required depth of the first trench 106 and the required thickness of the third barrier layer 104 to be retained after etching the first trench 106. The third barrier layer 104 is deposited using chemical vapor deposition (CVD) to precisely control its deposition thickness. Retaining a certain thickness of the third barrier layer 104 after etching the first trench 106 avoids the need for subsequent steps of forming an additional LPTEOS oxide film as an ion implantation protective layer within the first trench 106 and on the substrate 101. This prevents the LPTEOS oxide film from reducing the quality of the field oxygen layer on the inner wall of the first trench 106 and limiting or altering its thickness. Furthermore, the thickness range of the retained third barrier layer 104 is highly controllable. While effectively protecting the integrity of the morphology of the second barrier layer 103 during ion implantation, it effectively increases the barrier to implanted ions, thereby significantly increasing the ion implantation process window, reducing process difficulty, and saving process costs. Simultaneously, this process does not interfere with front-end design simulation results and has virtually no impact on electrical parameters.

[0069] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the principles and technical concepts disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a shielded gate trench field-effect transistor, characterized in that, The preparation method includes: A substrate is provided, and a barrier stack is formed on the substrate, the barrier stack comprising a first barrier layer, a second barrier layer and a third barrier layer stacked sequentially; A patterned window is formed in the barrier stack, and a first trench is etched in the substrate based on the patterned window, while retaining the first barrier layer, the second barrier layer and part of the third barrier layer; Field plates are formed at the bottom and sidewalls of the first trench; A polycrystalline silicon layer is deposited, the polycrystalline silicon layer filling the first trench; Remove the polysilicon layer above the top surface of the third barrier layer, and further remove a portion of the polysilicon layer in the first trench to form a second trench at the top of the trench. The shielded gate trench field-effect transistor includes a device region and a terminal region. Before forming the second trench, the step of forming an etch-resistant layer on the first trench of the terminal region is also included. Using the remaining portions of the third, second, and first barrier layers as masks, ion implantation is performed to achieve ion doping of the polysilicon layer within the trench.

2. The method for fabricating a shielded gate trench field-effect transistor according to claim 1, characterized in that: The first barrier layer comprises silicon dioxide, the second barrier layer comprises silicon nitride, and the third barrier layer comprises silicon dioxide.

3. The method for fabricating a shielded gate trench field-effect transistor according to claim 1, characterized in that: The third barrier layer is deposited using a chemical vapor deposition method to precisely control the deposition thickness of the third barrier layer. The deposition thickness of the third barrier layer is determined based on the depth of the first trench to be etched and the thickness of the third barrier layer to be retained after etching the first trench.

4. The method for fabricating a shielded gate trench field-effect transistor according to claim 3, characterized in that: The thickness of the first barrier layer is 100 angstroms to 200 angstroms, the thickness of the second barrier layer is 1500 angstroms to 2500 angstroms, and the thickness of the third barrier layer is 1500 angstroms to 3000 angstroms.

5. The method for fabricating a shielded gate trench field-effect transistor according to claim 3, characterized in that: After the first trench is etched in the substrate, the remaining portion of the third barrier layer has a thickness of 300 angstroms to 1000 angstroms.

6. The method for fabricating a shielded gate trench field-effect transistor according to claim 1, characterized in that: The second barrier layer is deposited using a furnace tube deposition method, and the second barrier layer is simultaneously deposited on the back side of the substrate. The preparation method further includes the step of removing the second barrier layer on the back side of the substrate by spraying an etchant. When spraying the etchant, the substrate is also rotated.

7. The method for fabricating a shielded gate trench field-effect transistor according to claim 1, characterized in that: After removing the polysilicon layer above the top surface of the third barrier layer and before forming the second trench, the process further includes a step of etching back the polysilicon layer, wherein the thickness of the polysilicon layer removed by etching back is 50 nanometers to 150 nanometers.

8. The method for fabricating a shielded gate trench field-effect transistor according to claim 1, characterized in that: The depth of the first trench is 4 micrometers to 6 micrometers, and the depth of the second trench is 0.5 micrometers to 1.5 micrometers.

9. The method for fabricating a shielded gate trench field-effect transistor according to claim 1, characterized in that: The ions implanted include arsenic, and the implantation energy is between 80 keV and 150 keV.

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