Bipolar junction transistor with wrap-around base layer

Abstract

The present application relates to a bipolar junction transistor having a wrap-around base layer, and discloses a device structure and a method of manufacturing a bipolar junction transistor. The device structure includes a substrate and a trench isolation region in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure also includes a collector in the active region of the substrate, a base layer having a first section disposed on the active region and a second section oriented at an angle with respect to the first section, an emitter disposed on the first section of the base layer, and an extrinsic base layer disposed over the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally disposed between the extrinsic base layer and the emitter.

Description

Technical Field

[0001] This invention generally relates to the manufacture of semiconductor devices and integrated circuits, and more particularly to the device structure and manufacturing method of bipolar junction transistors. Background Technology

[0002] A bipolar junction transistor (BJT) is a three-terminal electronic device comprising an emitter, a collector, and an intrinsic base defining the respective junctions of the emitter and collector. In a PNP BJT, the emitter and collector are made of p-type semiconductor material, while the intrinsic base is made of n-type semiconductor material. In an NPN BJT, the emitter and collector are made of n-type semiconductor material, while the intrinsic base is made of p-type semiconductor material. During operation, the base-emitter junction is forward biased, the base-collector junction is reverse biased, and the collector-emitter current can be controlled by the base-emitter voltage.

[0003] A heterojunction bipolar transistor (HBT) is a variant of the bipolar junction transistor (BJT) in which the semiconductor materials have different band gaps, thus forming a heterojunction. For example, the collector and emitter of a HBT can be made of silicon, while the intrinsic base of the HBT can be made of silicon-germanium, characterized by a narrower band gap than that of silicon.

[0004] Although the existing structure has proven suitable for its intended purpose, improvements to the structure and manufacturing method of bipolar junction transistors are needed. Summary of the Invention

[0005] In one embodiment of the present invention, a device structure for a bipolar junction transistor is provided. The device structure includes a substrate and a trench isolation region located in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure also includes a collector located in the active region of the substrate, a base layer having a first segment disposed on the active region and a second segment oriented at an angle relative to the first segment, an emitter disposed on the first segment of the base layer, and an extrinsic base layer disposed above the trench isolation region and adjacent to the emitter. The second segment of the base layer is laterally disposed between the extrinsic base layer and the emitter.

[0006] In one embodiment of the present invention, a method for forming a device structure for a bipolar junction transistor is provided. The method includes forming a trench isolation region surrounding an active region of a substrate. The method further includes forming a collector in the active region of the substrate, forming an intrinsic base layer disposed above the trench isolation region, forming a base layer including a first segment disposed on the active region and a second segment oriented at an angle relative to the first segment, and forming an emitter disposed on the first segment of the base layer. The intrinsic base layer is disposed adjacent to the emitter, and the second segment of the base layer is laterally disposed between the intrinsic base layer and the emitter. Attached Figure Description

[0007] The accompanying drawings, which are included in and form part of this specification, illustrate various embodiments of the invention and, together with the foregoing general description of the invention and the following detailed description of those embodiments, serve to explain those embodiments of the invention.

[0008] Figures 1-5 This shows a cross-sectional view of the apparatus structure in the continuous manufacturing stage of the processing method according to an embodiment of the present invention.

[0009] Figure 6 A cross-sectional view showing the structure of a device according to an alternative embodiment of the present invention.

[0010] Figures 7-11 This shows a cross-sectional view of an apparatus structure in the continuous manufacturing stage of a processing method according to an alternative embodiment of the present invention. Detailed Implementation

[0011] Please refer to Figure 1 According to an embodiment of the present invention, the substrate 10 is composed of a single-crystal semiconductor material suitable for manufacturing a device structure for an integrated circuit. The semiconductor material constituting the substrate 10 may include an epitaxial layer on its top surface, and this epitaxial layer may be doped with an electroactive dopant to modify its conductivity. For example, an epitaxial layer composed of single-crystal silicon may be epitaxially grown on the substrate 10 and doped with an n-type dopant (e.g., phosphorus or arsenic) to provide n-type conductivity.

[0012] A trench isolation region 12 is formed in the substrate 10. The trench isolation region 12 surrounds an active region 14 comprised of a portion of the semiconductor material of the substrate 10. The trench isolation region 12 can be formed using a shallow trench isolation technique, which involves patterning trenches in the substrate 10 using photolithography and etching processes, depositing dielectric material to overfill the trenches, and planarizing the dielectric material using chemical mechanical polishing and / or etch back to remove excess dielectric material from the site. The dielectric material can be composed of an electrically insulating material (e.g., silicon dioxide), which is deposited by chemical vapor deposition.

[0013] Collector 16 is disposed in active region 14 and may constitute all or part of active region 14. The conductivity of collector 16 relative to substrate 10 can be improved, for example, by selectively implanting dopants (e.g., n-type dopants) into the central region of active region 14. Sub-collector 18 extends laterally into substrate 10 below trench isolation region 12 to couple collector 16 to collector contact region 20 disposed outside trench isolation region 12. Sub-collector 18 can be formed below the top surface of substrate 10 by introducing electroactive dopants (e.g., n-type dopants (e.g., phosphorus or arsenic)) to form n-type conductivity. In one embodiment, sub-collector 18 can be formed in substrate 10 by performing masked high-current ion implantation followed by high-temperature thermal annealing.

[0014] A dielectric layer 22 is formed covering the trench isolation region 12 and the substrate 10. The dielectric layer 22 may be composed of an electrically insulating material (e.g., silicon nitride). A semiconductor layer 24 is formed covering the dielectric layer 22. The semiconductor layer 24 may be composed of a semiconductor material, such as polysilicon, polysilicon-germanium, or a combination of these materials, and is heavily doped with an electrically active dopant (e.g., a p-type dopant (e.g., boron)) to produce p-type conductivity. The semiconductor layer 24 is finally formed in the completed device structure 40. Figure 5 The non-intrinsic base layer is provided in the ).

[0015] An opening 26 is patterned using photolithography and etching processes, extending through the dielectric layer 22 and the semiconductor layer 24 to the substrate 10 in the active region 14. The opening 26 defines an emitter window, which may partially overlap with the trench isolation region 12 at its periphery. More specifically, the opening 26 has a sidewall 27 that extends from the top surface 25 of the semiconductor layer 24 through the dielectric layer 22 and the semiconductor layer 24 to the trench isolation region 12. The dielectric layer 22 and the semiconductor layer 24 have respective side surfaces that extend together with the sidewall 27 of the opening 26.

[0016] Please refer to Figure 2 In which similar reference numerals indicate Figure 1 Similar features are found in the previous process, and in the next manufacturing stage of this process, the base layer 28 is formed as a continuous film above the semiconductor layer 24 and inside the opening 26. The base layer 28 follows the contour provided by the opening 26 and is bent around the sidewall 27 of the opening 26 in an encapsulating manner. In particular, the base layer 28 encapsulates the semiconductor layer 24. A segment 70 of the base layer 28 is disposed inside the opening 26, on the substrate 10 in the active region 14 and on the exposed portion of the trench isolation region 12 surrounding the active region 14. The opening 26 extends through the dielectric layer 22 and the semiconductor layer 24 to the segment 70 of the base layer 28.

[0017] A segment 72 of the base layer 28 is disposed inside the opening 26, laterally adjacent to the sidewall 27 and directly contacting the side surface of the semiconductor layer 24 at the sidewall 27. The segment 72 of the base layer 28 is oriented at an angle relative to a segment 70 of the base layer 28 and extends away from the active region 14 of the substrate 10. In one embodiment, the segment 72 of the base layer 28 may be laterally oriented relative to a segment 70 of the base layer 28.

[0018] A segment 74 of the base layer 28 is disposed outside the opening 26 and adjacent to and above the top surface 25 of the semiconductor layer 24. In one embodiment, a segment 72 of the base layer 28 may directly contact the top surface 25 of the semiconductor layer 24. The segment 72 of the base layer 28 may physically connect segments 70 and 74 of the base layer 28. The semiconductor layer 24 is disposed vertically between the segment 74 of the base layer 28 and the trench isolation region 12.

[0019] The base layer 28 may be composed of a semiconductor material, such as silicon-germanium (SiGe), comprising silicon and germanium alloyed together, with the silicon content varying from 95 atomic percent to 50 atomic percent and the germanium content varying from 5 atomic percent to 50 atomic percent. The germanium content of the base layer 28 may be uniform, or may have graded and / or stepped sections without germanium along its thickness. The base layer 28 may be doped with a certain concentration of electroactive dopant (e.g., p-type dopant (e.g., boron)) to provide p-type conductivity. The base layer 28 may be formed using an epitaxial growth process and may be provided with a conformal coating. The base layer 28 may include a single-crystal semiconductor material epitaxially grown on the active region 14 and a polycrystalline semiconductor material formed on the semiconductor layer 24. In one embodiment, different segments 70, 72, and 74 of the base layer 28 may have equal thicknesses. In one embodiment, different segments 70, 72, 74 of the base layer 28 may have substantially the same thickness.

[0020] Please refer to Figure 3 In which similar reference numerals indicate Figure 2 Similar features are present in the next manufacturing stage of this process, where a dielectric layer 30 is formed in the space located inside the opening 26, on the segment 70 of the base layer 28 inside the opening 26, and between the segment 72 of the base layer 28 inside the opening 26. The dielectric layer 30 may be composed of a dielectric material, such as silicon nitride. The dielectric layer 30 may be formed by depositing a dielectric material coating layer and polishing and / or etching back the coating layer. The thickness of the dielectric layer 30 is sufficient to cover the segment 72 of the base layer 28. After the dielectric layer 30 is formed, the top surface 29 of the base layer 28 is exposed adjacent to the opening 26.

[0021] A dielectric layer 32 may be formed on the exposed top surface 29 of the base layer 28. In one embodiment, the dielectric layer 32 may be composed of silicon dioxide formed by a thermal oxidation process. The dielectric layer 30 is composed of a material that can be selectively removed relative to the material of the dielectric layer 32.

[0022] Please refer to Figure 4 In which similar reference numerals indicate Figure 3 Similar characteristics are found in the process, and in the next manufacturing stage of this process, the dielectric layer 30 is removed by a selective etching process relative to the dielectric layer 32. The terms “selective” and “selective” as used herein when referring to a material removal process (e.g., etching) mean that the material removal rate of the target material (i.e., the etching rate) is higher than the material removal rate (i.e., the etching rate) of at least one other material exposed to the material removal process. This removal of the dielectric layer 30 exposes segments 70, 72 of the base layer 28.

[0023] A spacer wall 34 is formed within the opening 26, on a segment 70 of the base layer 28, and adjacent to the sidewall 27 of the opening 26. The spacer wall 34 covers a portion of both the segment 72 and the segment 70 of the base layer 28. The spacer wall 34 may be a double-layer spacer wall composed of various dielectric materials, such as silicon dioxide and silicon nitride, deposited as conformal layers by atomic layer deposition or chemical vapor deposition, followed by etching using one or more anisotropic etching processes (e.g., reactive ion etching). The segment 72 of the base layer 28 serves to self-align the spacer wall 34 with the opening 26 during this etching process.

[0024] An emitter 36 is formed inside the opening 26, on a segment 70 of the base layer 28, and laterally between the sidewalls 27 of the opening 26. The emitter 36 may be composed of a single-crystal semiconductor material (e.g., single-crystal silicon) grown by an epitaxial growth process. In one embodiment, the emitter 36 may be formed by a selective epitaxial growth (SEG) process, wherein the semiconductor material is epitaxially grown from the exposed surface of the substrate 10, but not from the surface of the insulator (e.g., the dielectric layer 32 and the spacer 34). The emitter 36 may be composed of a single-crystal semiconductor material (e.g., single-crystal silicon) and may be in-situ doped with an electroactive dopant (e.g., an n-type dopant (e.g., phosphorus or arsenic)) during epitaxial growth.

[0025] In one embodiment, the emitter 36 has a top surface 37 that is coplanar with the top surface 29 of the segment 74 of the base layer 28. In another embodiment, the emitter 36 has a top surface 37 that is substantially coplanar with the top surface 29 of the segment 74 of the base layer 28. A spacer wall 34 is laterally disposed between the emitter 36 and the segment 72 of the base layer 28, thereby establishing the boundary of the emitter-base junction.

[0026] Please refer to Figure 5 In which similar reference numerals indicate Figure 4 Similar features are found in the previous process, and in the next manufacturing stage of this process, the device structure 40 of the bipolar junction transistor is patterned by photolithography and etching processes. This patterning of the device structure 40 opens the collector contact region 20. The dielectric layer 32 can be removed from the segment 74 of the base layer 28 by an etching process. A silicide layer 41 is formed on the collector contact region 20, the semiconductor layer 24, and the emitter 36 by a silicide process.

[0027] Device structure 40 includes a collector 16, an emitter 36, and an intrinsic base provided by a segment 70 of a base layer 28 disposed between the emitter 36 and the collector 16. A spacer wall 34 separates the segment 70 of the base layer 28 from the emitter 36 and provides electrical isolation. One junction is located between the segment 70 of the base layer 28 and the upper emitter 36, and another junction is located between the segment 70 of the base layer 28 and the lower collector 16. For example, if the base layer 28 is composed of silicon-germanium, device structure 40 can be considered as a heterojunction bipolar transistor. Device structure 40 can be divided into an intrinsic region including these junctions and an intrinsic region surrounding the intrinsic region.

[0028] Semiconductor layer 24 provides an intrinsic base layer for device structure 40. Semiconductor layer 24 is disposed above trench isolation region 12, adjacent to a segment 72 of base layer 28 at sidewall 27 of opening 26. Spacer wall 34 (latitudinally disposed between segment 72 of base layer 28 and emitter 36) defines the boundary of the emitter-base junction. Segment 72 of base layer 28 is laterally disposed between spacer wall 34 and semiconductor layer 24 for providing the intrinsic base layer.

[0029] Next, middle-of-line and back-end-of-line processes are performed, including forming contacts, vias, and lines for interconnect structures coupled to device structure 40. This interconnect structure may include a dielectric layer 42 formed over device structure 40. Dielectric layer 42 may be composed of a dielectric material (e.g., silicon dioxide), which is planarized by chemical vapor deposition. To form contacts 44 that are physically and electrically coupled to the silicide layer 41 on collector contact region 20, base layer 28, and emitter 36, contact openings formed in dielectric layer 42 are patterned using photolithography and etching processes, and then the contact openings are filled with a conductor (e.g., tungsten).

[0030] The device structure 40 has a self-aligned and planar configuration obtained through a simplified process flow. A semiconductor layer 24 providing the intrinsic base layer is formed prior to the formation of the base layer 28; therefore, the semiconductor layer 24 is disposed vertically between the trench isolation region 12 and the segment 74 of the base layer 28. The segments 72, 74 of the base layer 28 cover the semiconductor layer 24 providing the intrinsic base. Due to the formation sequence, the semiconductor layer 24 can be formed via a non-selective growth process. The spacer wall 34 (defining the emitter-base junction at its surrounding edges) is self-aligned during formation at the surrounding edges of the opening 26 via the segment 72 of the base layer 28, wherein the emitter 36 is subsequently formed in a fully self-aligned manner as well.

[0031] Device structure 40 can exhibit reduced collector-base capacitance because, for example, the pull-down of trench isolation region 12 during device formation can be reduced or eliminated. This reduction in collector-base capacitance (Ccb) can improve the operational quality factors of device structure 40, such as maximum frequency, transit frequency, and gain. Device structure 40 can exhibit reduced base resistance (Rb) due to the highly doped intrinsic base layer provided by semiconductor layer 24 and the complete self-alignment provided by spacer wall 34 during emitter 36 formation. The collector 16 and emitter 36 are scaled to have approximately equal dimensions, which can help reduce base resistance and collector-base capacitance.

[0032] Please refer to Figure 6 In which similar reference numerals indicate Figure 5 Similar features are present in the embodiment, and according to an alternative embodiment, the emitter 46 can be formed by depositing and patterning a conductor layer (e.g., doped polysilicon). Unlike the emitter 36 replaced by the emitter 46 in the device structure 40, the emitter 46 is formed in a partially self-aligned manner due to its deposition and patterning. Processing continues to shape the device structure 40 and form an interconnect structure coupled to the device structure 40.

[0033] Please refer to Figure 7 According to embodiments of the present invention, a dielectric layer 48 may be formed covering the top surface 25 of the semiconductor layer 24. The dielectric layer 48 may be composed of an electrically insulating material (e.g., silicon dioxide). When patterned, openings 26 extend through the dielectric layer 48, as well as the dielectric layer 22 and the semiconductor layer 24, to the substrate 10 in the active region 14.

[0034] Please refer to Figure 8 In which similar reference numerals indicate Figure 7 Similar features are present in the next manufacturing stage of this process, whereby the base layer 28 is formed as a continuous film over the dielectric layer 48 and inside the opening 26. The base layer 28 follows the contour provided by the opening 26 and is bent around the sidewall 27 of the opening 26 in an encapsulating manner. The base layer 28 includes a segment 70 formed on the substrate 10 in the active region 14 and on the exposed portion of the trench isolation region 12 surrounding the active region 14, a segment 72 formed on the sidewall 27 of the opening 26, and a segment 74 formed on the dielectric layer 48 but not on the top surface 25 of the semiconductor layer 24.

[0035] Please refer to Figure 9 In which similar reference numerals indicate Figure 8 Similar characteristics, and in the next manufacturing stage of this processing method, such as combining Figure 4 The aforementioned method forms a spacer wall 34 inside the opening 26. A layer 50 composed of a conductor (e.g., doped polysilicon) is deposited, which covers the dielectric layer 48 and includes a portion filling the opening 26.

[0036] Please refer to Figure 10 In which similar reference numerals indicate Figure 9 Similar features are found in the next manufacturing stage of this process, where the base layer 28, spacer wall 34, and layer 50 are planarized via a chemical mechanical polishing process. This planarization defines the emitter 52 from the polished portion of layer 50 residing within the opening 26. The section 74 of the base layer 28 is completely removed by the dielectric layer 48. Figure 8 Sections 70 and 72 of the base layer 28 are preserved intact inside the opening 26.

[0037] Please refer to Figure 11 In which similar reference numerals indicate Figure 10 Similar features are found in the next manufacturing stage of this process, where the device structure 40 is patterned by photolithography and etching processes to open the collector contact region 20, a dielectric layer 42 is formed over the device structure 40, and contacts 44 are formed in the dielectric layer 42. Before depositing the dielectric layer 42, the dielectric layer 48 can be removed to expose the semiconductor layer 24. Before depositing the dielectric layer 42, a silicide layer 41 can be formed.

[0038] The method described above is used for the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product including the integrated circuit chip, such as a computer product with a central processing unit or a smartphone.

[0039] The terms used herein, modified by approximate language such as “approximately,” “roughly,” and “substantially,” are not limited to the specified precise values. This approximate language may correspond to the accuracy of the instrument used to measure the value, and may represent + / - 10% of the value unless otherwise dependent on the accuracy of that instrument.

[0040] The terms "vertical" and "horizontal" are used in this document as examples to establish a reference framework and are not intended to be limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as defined above. The term "lateral" refers to a direction within that horizontal plane.

[0041] A feature “connected” or “coupled” to another feature may be directly connected or coupled to that other feature, or one or more intermediate features may exist. If no intermediate feature exists, the feature may be “directly connected” or “directly coupled” to the other feature. If at least one intermediate feature exists, the feature may be “indirectly connected” or “indirectly coupled” to the other feature. A feature “on” or “in contact” with another feature may be directly on or in contact with that other feature, or one or more intermediate features may exist. If no intermediate feature exists, the feature may be directly on or in contact with the other feature. If at least one intermediate feature exists, the feature may not be “directly” on or in contact with the other feature. If one feature extends over and covers a portion of another feature, the different features overlap.

[0042] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device structure for a bipolar junction transistor, characterized in that, The device structure includes: Substrate; A trench isolation region is located in the substrate and surrounds the active region of the substrate; The collector is located in the active region of the substrate; The base layer includes a first segment disposed on the active region and a second segment oriented at an angle relative to the first segment; An emitter is disposed on the first segment of the base layer; and An intrinsic base layer is disposed above the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally disposed between the intrinsic base layer and the emitter, and the base layer includes a third section disposed adjacent to the emitter and above the intrinsic base layer.

2. The device structure as described in claim 1, characterized in that, The third segment of the base layer has a top surface, and the emitter has a top surface that is substantially coplanar with the top surface of the third segment of the base layer.

3. The device structure as described in claim 1, characterized in that, The second segment of the base layer connects the first segment of the base layer to the third segment of the base layer.

4. The device structure as described in claim 1, characterized in that, Also includes: A dielectric spacer is laterally disposed between the second section of the base layer and the emitter.

5. The device structure as described in claim 1, characterized in that, The second segment of the base layer is laterally oriented relative to the first segment of the base layer.

6. The device structure as described in claim 1, characterized in that, The first segment and the second segment of the base layer have substantially the same thickness.

7. The device structure as described in claim 1, characterized in that, The non-intrinsic base layer includes an opening extending into the first segment of the base layer.

8. The device structure as described in claim 7, characterized in that, The first and second sections of the base layer are disposed inside the opening.

9. The device structure as described in claim 7, characterized in that, The emitter is located inside the opening.

10. The device structure as described in claim 9, characterized in that, Also includes: The first dielectric spacer wall is laterally located between the second section of the base layer and the emitter and is disposed inside the opening.

11. The device structure as described in claim 10, characterized in that, The opening has a sidewall, and the first dielectric gap wall is located on the first section of the base layer and disposed inside the opening adjacent to the sidewall.

12. The device structure as described in claim 10, characterized in that, The opening has a sidewall, the first dielectric gap wall is disposed inside the opening adjacent to the sidewall, and the second segment of the base layer is laterally disposed between the first dielectric gap wall and the intrinsic base layer.

13. The device structure as described in claim 10, characterized in that, The opening has a first sidewall and a second sidewall, the first dielectric spacer wall being adjacent to the first sidewall and laterally disposed within the opening between the second segment of the emitter and the base layer, and further comprising: The second dielectric spacer wall is disposed inside the opening, adjacent to the second sidewall. The base layer includes a third segment oriented at an angle relative to the first segment, and the second dielectric spacer is laterally disposed between the emitter and the third segment of the base layer.

14. The device structure as described in claim 13, characterized in that, The second and third segments of the base layer are laterally oriented relative to the first segment of the base layer.

15. A method for forming a device structure for a bipolar junction transistor, characterized in that, The method includes: A trench isolation region is formed in the substrate, wherein the trench isolation region surrounds the active region of the substrate; A collector electrode is formed in the active region of the substrate; An intrinsic base layer is formed above the trench isolation zone; Forming a base layer comprising a first segment disposed on the active region and a second segment oriented at an angle relative to the first segment; and An emitter is formed on the first segment of the base layer. The intrinsic base layer is disposed adjacent to the emitter, and the second section of the base layer is laterally disposed between the intrinsic base layer and the emitter. The base layer includes a third section disposed adjacent to the emitter and above the intrinsic base layer.

16. The method as described in claim 15, characterized in that, Also includes: A dielectric spacer is formed between the second section of the base layer and the emitter.

17. The method as described in claim 15, characterized in that, Also includes: A patterned opening that extends through the intrinsic base layer to the first segment of the base layer.

18. The method as described in claim 17, characterized in that, The first and second segments of the base layer are disposed inside the opening, and the emitter is disposed inside the opening, while the second segment of the base layer is laterally located between the emitter and the intrinsic base layer.

19. The method as described in claim 15, characterized in that, The third segment of the base layer has a top surface, and the emitter has a top surface that is substantially coplanar with the top surface of the third segment of the base layer.

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