Inductor current shunt linear control technique for mitigating dc-dc regulator load dump transients

Abstract

The present disclosure relates to inductor current shunt linear control techniques for mitigating DC-DC regulator load dump transients. For inductor-based DC-DC converters, a current shunt switch can provide a backup path for inductor current that does not include the output capacitor. An amplifier circuit can be included and coupled with a control node of the current shunt switch to adjust a voltage on the control node to control the amount of inductor current shunted from the output node. A fast linear loop can be included to ensure smooth transitions when turning on or off the current shunt switch. These techniques can minimize the subsequent negative output voltage excursion and duration when the final value of a step-down load transient is not zero, depending on the specific ESL and ESR values of the output voltage capacitor. These techniques can improve the positive output voltage response caused by output load transients in the negative direction.

Description

Technical Field

[0001] This document relates to regulator circuits, particularly to mitigating output transients in DC-DC regulator circuits. Background Technology

[0002] Regulator circuits can be used to generate a regulated output from a circuit input. For example, a buck voltage regulator circuit uses an input voltage to produce a regulated output voltage that is lower than the input voltage, while a boost voltage regulator circuit produces a regulated output voltage that is higher than the input voltage. Switches are used to charge and discharge the circuit's inductor to generate a regulated output. In these types of circuits, and in non-inductor-based regulator circuits, transients in the output load current can cause undesirable voltage transients on the regulated output voltage. Summary of the Invention

[0003] For inductor-based DC-DC converters, a current shunt switch can provide an alternative path for inductor current, excluding the output capacitor. Amplifier circuitry can be included and coupled to the control node of the current shunt switch to adjust the voltage at the control node to control the amount of inductor current shunted from the output node. A fast linear loop can be included to ensure a smooth transition when the current shunt switch is switched on or off. These techniques can minimize the subsequent negative output voltage offset and duration, depending on the specific ESL and ESR values ​​of the output voltage capacitor, when the final value of the buck load transient is not zero. These techniques can improve the positive output voltage response caused by negative-direction output load transients.

[0004] In some aspects, the present invention relates to a voltage regulator circuit, comprising: a switching circuit for adjusting a switching duty cycle to regulate the output voltage at an output node of the voltage regulator circuit using an error signal representing the difference between a target voltage value and an output voltage; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit coupled in parallel to the inductor, wherein when the output voltage exceeds a predetermined maximum output voltage, the shunt circuit transfers the inductor current from the output node, the shunt circuit including a shunt switch coupled in parallel to the inductor, the shunt switch... The switch includes a control node and a shunt circuit control circuit, including an amplifier circuit and a comparator circuit. The amplifier circuit has an output coupled to the control node of the shunt switch. The comparator circuit is used to compare the output voltage with a specified maximum output voltage and a target voltage less than the specified maximum output voltage. When the output voltage exceeds the specified maximum output voltage, the amplifier circuit is activated to adjust the voltage on the shunt switch control node to control the amount of inductor current shunt from the output node. When the output voltage drops to the target voltage, the amplifier circuit is disabled after the shunt switch is activated.

[0005] In some aspects, this disclosure relates to a method of operating a voltage regulator circuit, comprising: activating and deactivating a switching circuit to charge and discharge an inductor to generate an output voltage and provide an inductor current to an output node of the voltage regulator circuit; adjusting the switching duty cycle of the switching circuit to regulate the output voltage using an error signal representing the difference between a target voltage value and an output voltage; comparing the output voltage with a specified maximum output voltage; and adjusting the voltage at a control node of a shunt switch by using the comparison of the output voltage with the specified maximum output voltage to control the amount of inductor current shunt from the output node when the output voltage exceeds the specified maximum output voltage.

[0006] In some aspects, this disclosure relates to a voltage regulator circuit, comprising: a drive circuit for activating and deactivating a switching circuit to charge and discharge an inductor to generate an output voltage and provide an inductor current to an output node of the voltage regulator circuit, the drive circuit being configured to regulate the output voltage at the output node of the voltage regulator circuit using an error signal representing the difference between a target voltage value and an output voltage; a component for comparing the output voltage with a specified maximum output voltage; and a component for adjusting the voltage at a control node of a shunt switch by comparing the output voltage with the specified maximum output voltage to control the amount of inductor current shunt from the output node when the output voltage exceeds the specified maximum output voltage. Attached Figure Description

[0007] In accompanying drawings that are not necessarily drawn to scale, similar numbers may describe similar parts in different views. Similar numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0008] Figure 1 This is a schematic diagram of an example voltage regulator circuit.

[0009] Figure 2 illustrate Figure 1 The current and voltage waveforms of the voltage regulator circuit under load sudden drop.

[0010] Figure 3 This is a schematic diagram of another example of a voltage regulator circuit.

[0011] Figure 4 illustrate Figure 3 The current and voltage waveforms of the voltage regulator circuit under load sudden drop.

[0012] Figure 5 illustrate Figure 3The current and voltage waveforms of the voltage regulator circuit when subjected to a partial load drop.

[0013] Figure 6 yes Figure 3 A schematic diagram of an example voltage regulator circuit, where the ESR is in the output capacitor.

[0014] Figure 7 illustrate Figure 6 The current and voltage waveforms of the voltage regulator circuit when subjected to a partial load drop.

[0015] Figure 8 This is a schematic diagram of an example of a voltage regulator circuit that can implement the various techniques disclosed herein.

[0016] Figure 9 illustrate Figure 8 The current and voltage waveforms of the voltage regulator circuit when subjected to a partial load drop.

[0017] Figure 10 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein.

[0018] Figure 11 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein.

[0019] Figure 12 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein.

[0020] Figure 13 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein.

[0021] Figure 14 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein. Detailed Implementation

[0022] The technology disclosed herein relates to DC-DC regulator topologies using a single inductor, such as buck, boost, and buck-boost. In each of these regulator topologies, and also common for inductor-based regulators, negative-direction output load transients (e.g., load sags) can cause positive voltage transients in the regulated output voltage. This is due to a) the finite response time of the regulator for correcting the amount of delivered current and b) the combined near-instantaneous effects of the series resistance (ESR) and series inductance (ESL) in the output capacitor.

[0023] In the case of inductor-based DC-DC regulators, the positive voltage transient problem on the regulated output voltage can be exacerbated because the inductor current itself cannot change immediately. This current often continues to propagate to the output capacitor for an additional cycle until it can be reduced to zero. This can lead to a further increase in the regulated output voltage, potentially violating stringent output voltage specifications, causing the system to shut down due to overvoltage monitoring circuitry tripping, or, in the worst case, damaging the circuitry connected to the output due to overvoltage stress. Some methods attempt to limit the positive output voltage offset by adding more output capacitors. The disadvantages of these methods may be the additional cost of the capacitors and the extra physical board space required.

[0024] In another approach, such as in U.S. Patent No. 10,790,747, jointly assigned to Vitunic et al., the entire contents of which are incorporated herein by reference, a shunt switch can be implemented to provide an alternative path for the inductor current that does not include the output capacitor. Such a configuration can further minimize any positive output voltage offset.

[0025] The inventors have recognized that, in certain circumstances, the ESR (and ESL) of the output capacitor can adversely affect the performance of the current shunt switch solution of U.S. Patent No. 10,790,747, which will be described in more detail below. The inventors have recognized that an amplifier circuit may be included and coupled to the control node of the current shunt switch. The amplifier circuit can adjust the voltage at the control node of the shunt switch to control the amount of inductor current shunted from the output node. Using various techniques of the present invention, a fast linear loop may be included to ensure a smooth transition when engaging or disengaging the current shunt switch. For cases where the final value of the buck load transient is not zero, these techniques can minimize the amount and duration of subsequent negative output voltage offsets, which may depend on the specific ESL and ESR values ​​of the output voltage capacitor. In this way, the techniques of the present invention can improve the positive output voltage response caused by output load transients in the negative direction.

[0026] Figure 1 This is a schematic diagram of an example voltage regulator circuit. Figure 1 The voltage regulator circuit 100 in the circuit is a buck DC-DC regulator. The buck DC-DC regulator 100 can be controlled by an input voltage V. IN The power supply mainly consists of transistors M1 and M2, inductor L, and output capacitor C. OUT and output load I LOAD .

[0027] The voltage regulator circuit 100 includes a switching circuit 102 having a gate driver 104 and including transistors M1 and M2. The gate driver 104 is configured (e.g., via logic circuitry) to use a clock signal to provide a switching duty cycle including a charging portion and a discharging portion. The voltage regulator circuit 100 receives electrical energy during the charging portion of the switching duty cycle.

[0028] Output voltage V OUT It can be fed back to the error amplifier EA, which is part of the control loop, to output the voltage V. OUT Adjust to DC value V REG The error amplifier EA senses the output voltage and adjusts the duty cycle of the voltage regulator circuit 100 by turning transistors M1 and M2 on and off.

[0029] Figure 2 illustrate Figure 1 The voltage regulator circuit 100 exhibits current and voltage waveforms under load surges. The diagram above illustrates the load current I. LOAD The relationship between the y-axis and time (x-axis), illustrated in the intermediate graph. Figure 1 The graph at the bottom shows the relationship between the inductor current IL (y-axis) of the inductor L and time (x-axis). The graph also illustrates the output voltage V. OUT The relationship between the y-axis and time (x-axis).

[0030] Just before the load descent event, the inductor current waveform I in the middle chart L It exhibits normal ripple at the DC-DC switching frequency, but due to C OUT Received L The influence of the AC component (because I) COUT =I L -I LOAD Therefore, the output voltage V OUT At the same frequency, a corresponding voltage ripple will appear. After t1, all inductor currents 200 (including the DC component, I) will be present. MAX The current is transferred to the output capacitor until the inductor current 200 can be reduced to zero. This is correct regardless of whether the buck regulator control scheme is to turn off M1 and M2 or simply turn on M2.

[0031] As shown in the chart at the bottom Figure 2 As shown, the output voltage response to this additional current is a voltage overshoot 202. The overshoot depends on C. OUT The value of C is higher. OUT This value will reduce voltage overshoot by 204. However, it increases the bill of materials (BOM) and board space costs associated with increasing the output capacitor. Furthermore, increasing C will increase the cost of the output capacitor as inductor current continues to flow to the output node. OUT The capacitor cannot eliminate the extra overshoot, it can only reduce it.

[0032] To eliminate or limit voltage overshoot, the inductor current can be diverted from the output capacitor C. OUT and output node V OUT The current is transferred out. This allows the inductor current to drop to zero without the output voltage increasing further.

[0033] Figure 3 This is a schematic diagram of another example of a voltage regulator circuit 300. The circuit includes a top-gate transistor M1, a bottom-gate transistor M2, and an inductor 302(L). In this example, transistors M1 and M2 are shown as field-effect transistors (FETs), but are not limited to FETs. The voltage regulator circuit 300 may include an output capacitor 304 (C) electrically coupled to the output node. OUT ) and can output voltage V OUT The voltage regulator circuit 300 provides power to the output load. It includes a switching circuit 306 with a gate driver 308 and transistors M1 and M2. The gate driver 308 is configured (e.g., via logic circuitry) to use a clock signal to provide a switching duty cycle that includes charging and discharging portions. The voltage regulator circuit 300 receives electrical energy during the charging portion of the switching duty cycle.

[0034] Inductor 302 can be coupled between output capacitor 304 and switching circuit node 310. Bottom-gate transistor M2 can be electrically coupled between switching circuit node 310 and circuit ground, while top-gate transistor M1 can be electrically coupled between switching circuit node 310 and the input voltage V. IN Between the input nodes.

[0035] During the continuous charging phase, transistor M1 is turned on or activated to raise the voltage at switch node 310 to almost the input voltage V. IN The initial activation drives a gradually increasing current through inductor 302 and to output capacitor 304 and the load. During the discharge portion of the switching duty cycle, transistor M2 turns on to pull switching circuit node 310 almost to circuit ground. This second activation provides a gradually decreasing current from the energy stored in inductor 302 to output capacitor 304 and the load.

[0036] The duration of the charging section can be automatically adjusted to control the switching duty cycle, thereby increasing the output voltage V. OUT Maintaining the specified level. This adjustment can be accomplished using a circuit feedback loop including error amplifier circuit 312. Error amplifier circuit 312 generates a voltage V representing the target voltage value and the voltage at the output node of voltage regulator circuit 300. OUTThe error signal is the difference between the two values. The output voltage can be scaled (e.g., using a resistor divider) to provide a scaled representation of the output voltage to the error amplifier circuit 312, instead of the actual output voltage as the feedback voltage. FB ) and voltage reference (V REG A comparison is made to generate an error signal. Voltage V REG It can be the desired regulated output voltage or a scaled voltage derived from the desired regulated output voltage.

[0037] The switching circuit 306 may include logic circuitry for implementing pulse width modulation (PWM) switching control. The switching circuit 306 sets the duration of the charging and discharging portions of the switching duty cycle based on the output voltage. For example, the switching circuit 306 may turn on the top-gate transistor M1 for a period of time based on a comparison of an error signal and a reference waveform signal, and then activate the bottom-gate transistor M2 for the remainder of each clock cycle.

[0038] During each switching duty cycle, activation of transistor M1 generates a gradually increasing current in the inductor, while activation of transistor M2 generates a gradually decreasing current. This increasing and then decreasing current maintains the feedback voltage at approximately equal to the reference voltage V. REF The value of . Regardless of the current demand on the load, this activation sequence will output the output voltage V at the output port. OUT Maintain at the desired level.

[0039] exist Figure 3 In the example shown, the circuit topology and the target voltage value are V. OUT A regulated voltage is generated that is less than the input V of the voltage regulator circuit (e.g., a buck regulator circuit). IN The voltage at that location. Among other examples, other examples may include those used to generate voltages greater than V. IN The adjusted V OUT Voltage regulator circuit topologies (e.g., boost regulator circuits), and methods for generating voltages less than or greater than V. IN The adjusted V OUT Circuit topology (e.g., buck-boost regulator circuit).

[0040] DC-DC voltage regulator output load transients in the negative direction (e.g., load is removed and load current I...) LOAD A load sag to zero (typically occurs at the regulated output voltage V) OUTA positive voltage transient occurs. This is due to a) the finite response time of the voltage regulator to correct the amount of current supplied to the load; and b) the near-instantaneous effect of the combination of the series resistance (ESR) and series inductance (ESL) in the output capacitor. This problem is more pronounced in inductor-based DC-DC regulators, where the inductor current I... L This cannot be changed immediately, and the inductor current will typically continue to flow to the output capacitor for an additional cycle until the current can be reduced to zero. This continuous flow of inductor current to a reduced load will cause the regulated output voltage to increase further, which may violate output voltage specifications; especially if the application requires tight control of the output voltage. This positive voltage transient may cause the system to shut down due to overvoltage monitoring circuitry tripping, or worse, may damage the circuitry connected to the output node due to overvoltage stress.

[0041] To transfer inductor current, voltage regulator circuit 300 includes a shunt circuit that transfers inductor current from the output node and output capacitor when the output voltage exceeds a specified maximum output voltage. The shunt circuit includes a transistor M3 connected in parallel with inductor 302. Transistor M3 acts as a shunt switch controlled by hysteresis comparator 314. When the output voltage rises to the specified maximum output voltage value (V... HI When the voltage is high, the output of comparator 314 is either active or low. Due to its hysteresis, the output of comparator 314 will not return to inactive or low until the output voltage drops below V. HI The value (e.g., the required regulating voltage level V) REG ).

[0042] Figure 4 illustrate Figure 3 The voltage regulator circuit exhibits current and voltage waveforms under load surges. The figure above illustrates the load current I. LOAD The relationship between the y-axis and time (x-axis). The chart immediately below the top chart illustrates this. Figure 3 The inductor current I of inductor L L The relationship between the y-axis and time (x-axis). The chart immediately above the bottom chart illustrates the relationship through... Figure 3 The current I of transistor M3 in M3 The relationship between the y-axis and time (x-axis) is illustrated in the following figure. OUT The relationship between the y-axis and time (x-axis).

[0043] Figure 3 The voltage regulator circuit 300 undergoes a voltage regulation at time t1. Figure 2 The same load sudden drop transient occurs. The inductor current I before time t1... L and output voltage V OUT The waveform is also similar to Figure 2The same as in the previous section. Immediately following time t1, all inductor currents are 400 (including the DC component, I...). MAX It was initially transferred to the output capacitor C. OUT This leads to V OUT Initially it rises. However, when the output voltage V... OUT Rise to voltage V HI (As shown at time t2), Figure 3 The hysteresis comparator 314 trips and turns on transistor M3. The inductor current I... L Then from the output capacitor C OUT Instead of transferring, it circulates in transistor M3 (“load drop shunt”).

[0044] When transistor M3 is turned on, transistors M1 and M2 in the main control circuit should be turned off. With transistor M3 on, the inductor current I... L It can be reduced to zero, and the output voltage 402 no longer increases. This is because the circulating inductor current I... L It will not flow to the output capacitor C OUT Therefore, it doesn't need to quickly become zero. Inductor current I L The rate at which the degradation reaches zero depends on the size of transistor M3. A smaller M3 (e.g., a higher R) DS(ON) This can accelerate decay to zero and is less expensive in terms of silicon chip area, but transistor M3 should not be too small because it must consume the energy E (E = 1 / 2LI) stored in the inductor. MAX 2 ).

[0045] Furthermore, if the voltage drop across transistor M3 exceeds voltage V OUT With the diode voltage drop applied, the body diode of transistor M2 will turn on, thereby limiting the voltage drop across transistor M3 and potentially causing C to... OUT Reposition it in the current loop. The decay follows an exponential curve as the changing current in transistor M3 multiplies the resistance (I×R). An example of achieving a good performance trade-off between cost and energy dissipation is to adjust the size of transistor M3 to approximately 5-10% of the size of M2. A low hysteresis voltage level should be set for comparator 314 so that if the output voltage subsequently drops to the target voltage value V... REG Nearby (due to leakage or a new load being turned on), transistor M3 turns off, which can restore the normal operation of the control circuit.

[0046] Figure 5 illustrate Figure 3 The voltage regulator circuit exhibits current and voltage waveforms when subjected to a partial load sag. The figure above illustrates the load current I. LOAD The relationship between the y-axis and time (x-axis). The chart immediately below the top chart illustrates this. Figure 3 The inductor current I of inductor L L The graph shows the relationship between the y-axis and time (x-axis). The middle graph illustrates the output capacitor current I. COUT The chart immediately above the bottom chart illustrates the process through... Figure 3 The current I of transistor M3 in M3 The relationship between the y-axis and time (x-axis) is illustrated in the following figure. OUT The relationship between the y-axis and time (x-axis).

[0047] exist Figure 5 In the example, a partial load drop at time t1 causes the load current I to decrease. LOAD 500 from I MAX Gradually decrease to I MAX / 2. Inductor current I L 502 decays to zero. As seen at 504, the load draws current I from the output capacitor from time t1 to t3. COUT In the event of a sudden drop in partial load, with Figure 4 In comparison, the output voltage 506 may take longer to reach V. HI Threshold. However, when considering the ESR of the output capacitor, V OUT The significant differences in the waveforms are obvious.

[0048] Figure 6 yes Figure 3 A schematic diagram of an example voltage regulator circuit, where the ESR is in the output capacitor. Figure 6 Many components of the voltage regulator circuit 600 in the middle are related to Figure 3 The components of the voltage regulator circuit 300 are similar and will not be described further for the sake of brevity.

[0049] like Figure 6 As shown, the voltage regulator circuit 600 has an output capacitor C OUT This includes ESR602. The inventors have recognized that, in certain situations, the output capacitor C... OUT ESR (and ESL) will undesirably affect Figure 3 The performance of the current shunt switch solution.

[0050] Figure 7 illustrate Figure 6 The voltage regulator circuit 600 exhibits current and voltage waveforms when subjected to a partial load sag. The figure above illustrates the load current I. LOAD The relationship between the y-axis and time (x-axis). See the chart description immediately below the top chart. Figure 6 The inductor current I of inductor L LThe graph shows the relationship between the y-axis and time (x-axis). The middle graph illustrates the output capacitor current I. COUT The diagram immediately above the bottom image illustrates the process. Figure 6 The current I of transistor M3 M3 The relationship between the y-axis and time (x-axis) is illustrated in the following figure. OUT The relationship between the y-axis and time (x-axis).

[0051] A partial load drop at time t1 causes the load current I to... LOAD 700 from I MAX Gradually decrease to I MAX / 2. Output voltage V OUT 702 increases at time t1 and Figure 6 The time t4 causes the hysteresis comparator 314 to trip. When transistor M3 is turned on at time t4, the inductor current I... L (704) The current is redirected through transistor M3 instead of flowing to the output, and the output capacitor C OUT All remaining load current 706 must be supplied, which in this case is equal to I. MAX / 2. When this occurs, the output voltage 702 drops immediately at time t4 because the current in the ESR of the output capacitor reverses from positive to negative. Depending on the magnitude of the remaining output current (after time t4) and the ESR value, this negative shift in the output voltage can be very large and may exceed the output voltage V. OUT The allowable low voltage tolerance. If the output voltage V OUT Descending to Figure 6 Outside the hysteresis window of comparator 314, comparator 314 trips again and shuts down transistor M3 and the shunt path. This can lead to subsequent instability and unwanted tripping and untripping of comparator 314.

[0052] One possible solution is to make comparator 314 hysteretic so that the low threshold is below the regulation voltage V. REG Thus, transistor M3 now only operates at the output voltage V. OUT Drops below the regulation voltage V REG The voltage is adjusted to a certain value to turn off, and this adjustment voltage can be determined based on the ESR resistor R. ESR The value of needs to be adjusted. However, this will force the specific ESR resistor R for the output capacitor to be adjusted. ESR The value is specifically adjusted for the hysteresis value, which is usually not strictly controlled. It must be considered that the maximum value may require setting the low threshold much lower than the regulated voltage V. REG This, in turn, forces the output voltage V to... OUT Negative offset has a large tolerance, which reduces the accuracy of the output voltage guaranteed during transients.

[0053] Furthermore, during a single negative load step event, this hysteresis behavior when turning transistor M3 on and off may engage the shunt switch multiple times during some unpredictable frequency bursts.

[0054] As described above, to ensure a smooth transition when the shunt switch is switched on or off, the inventors have recognized that an amplifier circuit can be included and coupled to the control node of the shunt switch. The amplifier circuit can adjust the voltage at the control node of the shunt switch to control the amount of inductor current shunt from the output node. For cases where the final value of the buck load transient is not zero, these techniques can minimize the amount and duration of negative output voltage offset, which may depend on the specific ESL and ESR values ​​of the output voltage capacitor. In this way, the techniques of the present invention improve the positive output voltage response caused by negative-direction output load transients.

[0055] Figure 8 This is a schematic diagram of an example of a voltage regulator circuit that can implement the various techniques disclosed herein. Figure 8 Many components of the voltage regulator circuit 800 in the middle are related to Figure 6 The components of the voltage regulator circuit 600 are similar and will not be described further for the sake of brevity.

[0056] Figure 8 The voltage regulator circuit 800 may include a switching circuit 306 to use a signal representing a target voltage value (V). REG ) and output voltage (V FB The error signal 804, representing the difference between the two signals, adjusts the duty cycle of the switch to regulate the output voltage V at the output node 802 of the voltage regulator circuit. OUT In, for example Figure 8 In the buck configuration shown, the switching circuit 306 may include the input node V of the switching circuit node 310 and the voltage regulator circuit. IN The coupled top switching circuit includes, for example, transistor M1. The switching circuit 306 may also include a bottom switching circuit, for example, transistor M2, coupled to the switching circuit node 310, and a circuit ground node, wherein the shunt switch M3 is connected in parallel with the inductor and coupled to the switching circuit node 310 and the output node.

[0057] Voltage regulator circuit 800 may include an inductor current I coupled to switching circuit 306 and configured to provide inductor current I to output node 802. L Inductor 302.

[0058] As mentioned above Figure 6The voltage regulator circuit 800 may include a shunt circuit coupled in parallel to the inductor. When the output voltage exceeds a specified maximum output voltage, the shunt circuit can transfer the inductor current from the output node. The shunt circuit may include a shunt switch M3 coupled in parallel to the inductor 302, and the shunt switch includes a control node 806.

[0059] Using the various techniques of this invention, the shunt circuit can be controlled by a shunt circuit control circuit, which may include an amplifier circuit 808 and a comparator circuit 314. The amplifier circuit 808 may have an output coupled to the control node 806 of the shunt switch M3.

[0060] Comparator circuit 314, such as a hysteresis comparator, can convert the output voltage (V) FB ) and the specified maximum output voltage (V HI The comparator circuit 314 can activate the amplifier circuit 808 to adjust the voltage at the control node 806 of the shunt switch M3 to control the inductor current I transferred from the output node when the output voltage exceeds the specified maximum output voltage. L The quantity. When the output voltage drops to the target voltage, the comparator circuit 314 can disable the amplifier circuit 808 after the shunt switch M3 is enabled.

[0061] In some examples, the shunt circuit control circuit may include a latch circuit 812, such as an SR latch, which is coupled to the output of the comparator circuit 314 and the enable input EN of the amplifier circuit 808.

[0062] In some examples, the shunt circuit control circuit may include a current comparator circuit 814, such as a hysteresis current comparator, for comparing the current through the shunt switch M3 with the target current I. SMALL The comparison is performed, and a reset signal 816 is output to the latch circuit 812 when the current through the shunt switch M3 decreases to below the target current.

[0063] In some examples, the shunt circuit control circuit may include a current source circuit 818, such as a single-trigger pull-up circuit, coupled to the control node 806 of the shunt switch M3 and the output of the comparator circuit 314. The comparator circuit 314 may enable the current source circuit 818 when the output voltage exceeds a specified maximum output voltage.

[0064] In some examples, the voltage regulator circuit 800 may include a feedback circuit that includes an error amplifier circuit 312 to generate a representation of the target voltage (V). REG ) and output voltage (V FB The error signal 804 is the difference between the two.

[0065] In some examples, the voltage regulator circuit 800 may include a one-time voltage pulse generator 820 coupled between the output of the current comparator circuit 814 and the latch circuit 812.

[0066] exist Figure 8 In the example shown, amplifiers 312 and 808 both share the same V. FB and V REG Input. Error amplifier circuit 312 and amplifier circuit 808 have separate input stage circuits and output stage circuits.

[0067] In some examples, the voltage regulator circuit 800 may include an output capacitor C coupled to the output node. OUT When the output voltage exceeds the specified maximum output voltage, the shunt circuit can transfer the inductor current from the output capacitor.

[0068] When the output voltage rises to the specified maximum output voltage value (V) HI When the comparator circuit 314 outputs, it immediately turns on transistor M3 by engaging a short-duration single-trigger pull-up 818 at the gate 806 of transistor M3. Simultaneously, amplifier 808 is also enabled by setting the output of the SR latch to a high level (using the enable line EN of amplifier 808). The function of amplifier 808 is to immediately adjust the gate voltage of transistor M3 (from the initial fully on state set by the single-trigger current) to only turn on from C. OUT Transfer (shunt) sufficient inductor current (I) L -I LOAD To maintain the output voltage at its desired regulated value (V) REG The initial fully on state of transistor M3 is crucial to ensuring that the output voltage does not increase beyond voltage V. HI It is very important.

[0069] In this example, when transistor M3 is on, transistor M1 is off and transistor M2 is on (and...). Figure 3 Conversely, when transistor M3 is on, both transistors M1 and M2 are off. This may be desirable because some inductor current I... L (and output current I) LOAD The final value (matching) is still flowing to the output. Transistor M2 can be turned on to provide a current return path, thus preventing the body diode of transistor M2 from being forced on.

[0070] When transistor M3 is turned on, the current flowing through it will slowly decrease. When the shunt current drops to a small value (I... SMALLWhen the current comparator 814 shuts down amplifier 808 via a positive (low-to-high) edge-sensitive single-trigger voltage pulse generator 820 connected to its output, it drives the reset line of latch circuit 812. Shunt switch M3 can then be immediately closed, and normal control loop operation can be restored (shunt "exit" condition).

[0071] This method is used when transistor M3 is turned on at V REG Recommended techniques for regulating output voltage, inductor current I L The optimal amount can be transferred from the output capacitor to maintain the output voltage at V. REG Place.

[0072] It should be noted that the inductor current decay rate using this technology no longer depends solely on the size of transistor M3, because the switching node 310 is now fixed near ground, transistor M2 is turned on, and the output voltage is regulated to V. REG The transistor M3 should be large enough that it can shunt the maximum permissible inductor current and V when its gate is driven to the highest voltage (fully on). REG Voltage. Under this criterion, amplifier 808 can adjust the gate voltage of transistor M3 so that transistor M3 only shunts a current higher than the output current requirement (I0). L -I LOAD Excess inductor current.

[0073] Using this technique, the hysteresis of comparator 314 can be reset so that if the output voltage subsequently drops below V... REG At a certain small value (due to leakage or a new load being turned on), transistor M3 turns off, and normal control loop operation resumes.

[0074] Figure 14 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein. Figure 14 Many components of the voltage regulator circuit 1400 are similar to Figure 8 The components of the voltage regulator circuit 800 will not be described further for the sake of brevity. (And...) Figure 8 The voltage regulator circuit is different from the 800. Figure 14 The shunt switch M3 is not coupled to the switching circuit node 310. Therefore, the path from the shunt switch M3 to ground, for example, does not pass through the transistor M2, as... Figure 8 As shown, it is not directly grounded. Figure 14 The operation of the voltage regulator circuit 1400 is otherwise similar to Figure 8 The voltage regulator circuit 800.

[0075] Figure 9 illustrate Figure 8The voltage regulator circuit 800 exhibits current and voltage waveforms when subjected to a partial load sag. The figure above illustrates the load current I. LOAD The relationship between the y-axis and time (x-axis). The chart immediately below the top chart illustrates this. Figure 8 The inductor current I of inductor L L The graph shows the relationship between the y-axis and time (x-axis). The middle graph illustrates the output capacitor current I. COUT The diagram immediately above the bottom image illustrates the process. Figure 8 The current I of transistor M3 in M3 The relationship between the y-axis and time (x-axis) is illustrated in the following figure. OUT The relationship between the y-axis and time (x-axis).

[0076] A partial load drop at time t1 causes the load current I to... LOAD 900 from I MAX Gradually decrease to I MAX / 2. Due to the ESR of the output capacitor, the output voltage V OUT 902 increases after time t1 and when the voltage exceeds V HI Shishi Figure 8 The hysteresis comparator 314 in the circuit tripped. Figure 8 The output of comparator 314 uses current source circuit 818 to fully turn on transistor M3. In addition, the output of comparator 818 uses latch circuit 812 to immediately enable amplifier 808, so that amplifier 808 begins to regulate the gate of transistor M3.

[0077] Transistor M2 is turned on and coupled to ground; therefore, the voltage across inductor 302 is V. OUT This results in the fixed inductor current decay rate seen at 904. Once the current I... M3 I is reached at time t5. SMALL The current comparator 814 can enable... Figure 8 The latch circuit 812 in the circuit trips and resets.

[0078] The shunt circuit is now disabled, resulting in current I SMALL It is transmitted to the output node, and immediately after time t5, a very small positive offset appears in the output voltage 902. The output voltage 902 is... Figure 7 The situation in the middle is closer to the regulation voltage V. REG In addition, utilizing Figure 8 The technology eliminates the need for additional output capacitors, thus maintaining a small footprint and reducing costs.

[0079] Figure 10 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein. Figure 10Many components of the voltage regulator circuit 1000 in the circuit are related to Figure 8 The components of the voltage regulator circuit 800 are similar and will not be described further for the sake of brevity.

[0080] exist Figure 8 In the example shown, error amplifier circuit 312 and amplifier circuit 808 have separate input and output stage circuits. However, because error amplifier circuit 312 and amplifier circuit 808 share the same V... FB and V REG Input, so Figure 8 Error amplifier circuit 312 and Figure 8 The amplifier circuit 808 can share the input stage circuitry. This configuration is... Figure 10 The diagram shows a shared input stage circuit 1002, and an error amplifier 1004 (executing...). Figure 8 The error amplifier circuit 312 (function) and amplifier circuit 1006 (execute) Figure 8 The separate output stage circuit of the amplifier circuit 808.

[0081] Figure 11 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein. Figure 11 Many components of the voltage regulator circuit 1100 in the middle are related to Figure 8 The components of the voltage regulator circuit 800 are similar and will not be described further for the sake of brevity.

[0082] exist Figure 8 In the embodiments shown, there is no Figure 8 Error amplifier circuit 312 and Figure 8 The amplifier circuit 808 requires both to operate simultaneously for a specific period of time. Therefore, in situations such as... Figure 11 In the alternative configuration shown, the two amplifiers can be combined into a single amplifier, wherein a multiplexer circuit coupled to the output of the amplifier drives different portions of the circuit 1100 at different times depending on the operating mode.

[0083] For example, Figure 8 Error amplifier circuit 312 and Figure 8 The amplifier circuit 808 can be combined into a single amplifier circuit 1102 (with an input stage and an output stage) and has an output 1104 coupled to a multiplexer circuit 1106. The multiplexer circuit 1106 can use an enable signal from the latch circuit 812 to selectively couple the output of the amplifier circuit 1102 to a switching circuit (the "B" output of the multiplexer circuit) or the control node of the shunt switch M3 (the "A" output of the multiplexer circuit).

[0084] Figure 12 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein. Figure 12 Many components of the voltage regulator circuit 1200 in the middle are related to Figure 8 The components of the voltage regulator circuit 800 are similar and will not be described further for the sake of brevity.

[0085] In such Figure 12 In the buck-boost configuration shown, the switching circuit may include four switching circuits. The switching circuit may include a first switching circuit, such as a transistor MA, which is connected to the input node V of the voltage regulator circuit 1200. IN The circuit is coupled to the first switching circuit node 1202. The switching circuit may include a second switching circuit, such as a transistor MB, coupled to the first switching circuit node 1202 and the circuit ground node. The switching circuit may include a third switching circuit, such as a transistor MC, coupled to the second switching circuit node 1204 and the circuit ground node. The switching circuit may include a fourth switching circuit, such as a transistor MD, coupled to the second switching circuit node 1204 and the output node. The inductor and shunt switch M3 may be coupled to the first switching circuit node 1202 and the second switching circuit node 1204.

[0086] Figure 13 This is a schematic diagram of another example of a voltage regulator circuit that can implement the various techniques disclosed herein. Figure 13 Many components of the voltage regulator circuit 1300 in the middle are related to Figure 8 The components of the voltage regulator circuit 800 are similar and will not be described further for the sake of brevity.

[0087] In such Figure 13 In the boost configuration shown, inductor 302 can be connected to the input node V of voltage regulator circuit 1300. IN Coupling. The switching circuit may include a first switching circuit, including transistor M1, coupled to switching circuit node 1302 and circuit ground node. The switching circuit may include a second switching circuit, including transistor M2, coupled to output node 802 and switching circuit node 1302. A shunt switch M3 may be coupled in parallel to inductor 302 and to switching circuit node 1302 and input node V. IN coupling.

[0088] Various annotations

[0089] Each non-limiting aspect or example described herein may exist independently or may be combined with one or more other examples in various permutations or combinations.

[0090] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors have also contemplated examples that provide only those elements shown or described. Furthermore, the inventors have contemplated examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described, or with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0091] In the event of any inconsistency between the usage in this document and any other document incorporated by reference, the usage in this document shall prevail.

[0092] In this document, as is common in patent documents, the terms “a” or “one” are used to include one or more, regardless of any other instances or uses of “at least one” or “one or more.” In this document, the term “or” is used to indicate a non-exclusive “or,” thus “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise stated. In this document, the terms “comprising” and “wherein” are used as simple equivalents to the corresponding terms “comprising” and “wherein.” Furthermore, in the following claims, the terms “comprising” and “including” are open-ended, meaning that a system, device, article, composition, formulation, or process, including elements other than those listed after the term in the claim, is still considered to be within the scope of that claim. Additionally, in the following claims, the terms “first,” “second,” and “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0093] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of these methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. This code may form part of a computer program product. Furthermore, in the examples, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact discs and digital video discs), magnetic tapes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), etc.

[0094] The above description is intended to be illustrative and not restrictive. For example, the examples (or one or more aspects thereof) described above may be used in combination with each other. Other embodiments may be used, for example, by one of ordinary skill in the art after reading the above description. An abstract is provided to conform to 37C.FR §1.72(b) to enable the reader to quickly determine the nature of the technical disclosure. It is understood that this submission is not to be construed as limiting or restricting the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined together to simplify this disclosure. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the invention may not be limited to all features of a particular disclosed embodiment. Therefore, the following claims are incorporated herein by way of example or embodiment, each claim existing independently as a separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A voltage regulator circuit, comprising: A switching circuit is used to adjust the switching duty cycle to regulate the output voltage at the output node of the voltage regulator circuit using an error signal representing the difference between the target voltage value and the output voltage. An inductor, coupled to the switching circuit and configured to provide inductor current to the output node; A shunt circuit is used to shunt the inductor current from the output node when the output voltage exceeds a specified maximum output voltage. The shunt circuit includes a shunt switch with a control node, wherein the shunt circuit is coupled in parallel with the inductor. and The shunt circuit control circuit includes an amplifier circuit and a comparator circuit. The amplifier circuit has an output coupled to the control node of the shunt switch. The comparator circuit is used to compare the output voltage with a specified maximum output voltage and a target voltage less than the specified maximum output voltage. When the output voltage exceeds the specified maximum output voltage, the amplifier circuit is activated to adjust the voltage at the control node of the shunt switch to control the amount of inductor current shunt from the output node. After the shunt switch is activated, the amplifier circuit is disabled when the output voltage drops to the target voltage.

2. The voltage regulator circuit according to claim 1, wherein the shunt circuit control circuit includes a latch circuit coupled to the output of the comparator circuit and the enable input of the amplifier circuit.

3. The voltage regulator circuit according to claim 2, wherein the shunt circuit control circuit includes a current comparator circuit for comparing the current through the shunt switch with a target current, and outputting a reset signal to the latch circuit when the current through the shunt switch decreases below the target current.

4. The voltage regulator circuit according to claim 1, wherein the shunt circuit control circuit includes a current source circuit coupled to the control node of the shunt switch and coupled to the output of the comparator circuit, the comparator circuit being configured to enable the current source circuit when the output voltage exceeds the specified maximum output voltage.

5. The voltage regulator circuit according to claim 1, comprising: The feedback circuit includes an error amplifier circuit for generating an error signal representing the difference between the target voltage and the output voltage, wherein the error amplifier circuit and the amplifier circuit share an input stage circuit.

6. The voltage regulator circuit according to claim 1, comprising: The feedback circuit includes an error amplifier circuit for generating an error signal representing the difference between the target voltage and the output voltage, wherein the error amplifier circuit and the amplifier circuit have separate input stage circuits and output stage circuits.

7. The voltage regulator circuit according to claim 1, comprising: A multiplexer circuit is used to selectively couple the output of the amplifier circuit to the control node of the switching circuit or the shunt switch using an enable signal.

8. The voltage regulator circuit according to claim 1, wherein the inductor is coupled to the output node. The switching circuit mentioned above includes: The top switching circuit is coupled to the input node and the switching circuit node of the voltage regulator circuit; and The bottom switching circuit is coupled to the switching circuit node and the circuit ground node; The shunt switch is coupled in parallel with the inductor and is coupled to the switch circuit node and the output node.

9. The voltage regulator circuit according to claim 1, wherein the inductor is coupled to the input node of the voltage regulator circuit. The switching circuit mentioned above includes: A first switching circuit coupled to a switching circuit node and a circuit ground node; and A second switching circuit coupled to the output node and the switching circuit node; and The shunt switch is coupled in parallel with the inductor and is coupled to the switch circuit node and the input node.

10. The voltage regulator circuit according to claim 1, wherein the switching circuit comprises: A first switching circuit coupled to the input node of the voltage regulator circuit and the first switching circuit node; A second switching circuit coupled to the first switching circuit node and the circuit ground node; A third switching circuit coupled to the second switching circuit node and the circuit ground node; and A fourth switching circuit coupled to the second switching circuit node and the output node; The inductor and the shunt switch are coupled to the first switch circuit node and the second switch circuit node.

11. The voltage regulator circuit according to claim 1, comprising: An output capacitor coupled to the output node, the shunt circuit being used to shunt the inductor current from the output capacitor when the output voltage exceeds the specified maximum output voltage.

12. A method for operating a voltage regulator circuit, comprising: The switching circuit is activated and deactivated to charge and discharge the inductor, thereby generating an output voltage and supplying inductor current to the output node of the voltage regulator circuit. Adjust the switching duty cycle of the switching circuit to regulate the output voltage using an error signal representing the difference between the target voltage value and the output voltage; Compare the output voltage with the specified maximum output voltage; Operate the latch circuit to enable the input of the amplifier circuit; and The amount of inductor current shunt from the output node is controlled by adjusting the voltage at the control node of the shunt switch by comparing the output voltage with the specified maximum output voltage.

13. The method of claim 12, comprising: The current passing through the shunt switch is compared with the target current, and a reset signal is output to the latching circuit when the current passing through the shunt switch drops below the target current.

14. The method of claim 12, comprising: The current source circuit is activated when the output voltage exceeds the specified maximum output voltage.

15. The method of claim 12, comprising: The output of the amplifier circuit is selectively coupled to the control node of the switching circuit or the shunt switch.

16. A voltage regulator circuit, comprising: A drive circuit is used to activate and deactivate a switching circuit to charge and discharge an inductor, thereby generating an output voltage and providing inductor current to the output node of a voltage regulator circuit. The drive circuit is used to regulate the output voltage at the output node of the voltage regulator circuit using an error signal representing the difference between a target voltage value and the output voltage. A component for comparing the output voltage with a specified maximum output voltage; A component for adjusting the voltage at the control node of a shunt switch by comparing the output voltage with the specified maximum output voltage, so as to control the amount of inductor current shunt from the output node when the output voltage exceeds the specified maximum output voltage; and A component for enabling the input of an amplifier circuit, the component for enabling the input of an amplifier circuit being coupled to the output of a comparator circuit and the enable input of the amplifier circuit.

17. The voltage regulator circuit of claim 16, comprising: A component is used to compare the current through the shunt switch with a target current, and to output a reset signal to the component for enabling the amplifier circuit input when the current through the shunt switch decreases below the target current.

18. The voltage regulator circuit of claim 16, comprising a current source circuit coupled to the control node of the shunt switch and coupled to the output of the comparator circuit, the comparator circuit being configured to enable the current source circuit when the output voltage exceeds the specified maximum output voltage.

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