Highly sensitive electromagnetic radiation detection component and method for manufacturing such a component

Abstract

The invention relates to a detection component (1) for electromagnetic radiation (λ), comprising a detection structure (100) and a power supply circuit (350) for the detection structure (100). The detection structure (100) comprises a transistor associated with an absorption element to detect an increase in the temperature of the absorption element during absorption of electromagnetic radiation (λ). The power supply circuit (350) is configured to supply power to the detection structure (100) during operation, so that a channel region (113) of the structure has a layer (114) on a first face or a second face, in which carriers of a second conductivity type are opposite to carriers of a first conductivity type of a source region (111) and a drain region (112), the layer (114) being referred to as a blocking layer. The invention also relates to a method for manufacturing such a component.

Description

Technical Field

[0001] The present invention relates to the fields of optoelectronics and electromagnetic radiation detection.

[0002] Therefore, the present invention relates more particularly to a component for detecting electromagnetic radiation and to a method for manufacturing such a component. Background Art

[0003] From document US 16 / 334109 it is known to use a bolometer based on a MOS-FET transducer to enable the detection of electromagnetic radiation.

[0004] According to the teaching of document US16 / 334109, such a component comprises a detection structure, which comprises:

[0005] at least one absorption element, the at least one absorption element being configured to absorb electromagnetic radiation,

[0006] a transistor associated with the absorption element, the transistor being used to detect a rise in the temperature of said absorption element when electromagnetic radiation is absorbed, the transistor comprising:

[0007] ○ at least one first semiconductor region and at least one second region, the first semiconductor region is called a source region, the second region is called a drain region, the at least one first semiconductor region and the at least one second region have a first conductivity type,

[0008] at least one third semiconductor region, the third semiconductor region is referred to as a channel region, the at least one third semiconductor region separates the source region and the drain region from each other, the at least one third semiconductor region has a first surface and a second surface, the first surface and the second surface are opposite surfaces, the first surface and the second surface extend between the source region and the drain region,

[0009] a first gate arranged opposite to a first face of the channel region to bias the channel region, the first gate forming an absorption element,

[0010] o A second gate, the second gate being arranged opposite to the second face of the channel region to bias the channel region.

[0011] According to the teaching of this document, the detection structure is connected to a reading circuit via a first conductive track and a second conductive track, the reading circuit serving as a circuit for power supply, the first conductive track biasing the source region, the first gate and the second gate, the second conductive track biasing the drain region (as a variant, it is also arranged so that the first gate is short-circuited to the drain). Thus, by this connection of the reading circuit, the reading circuit is constructed so that in the operation of the structure, the voltage of the second gate electrode, which is usually called the back gate, is placed at the same potential as the first gate electrode. Thus, the detection structure is able to operate at a voltage between the main gate and the source region, which is between 50mV and 75mV.

[0012] Although such detection means enable the provision of means for detecting electromagnetic radiation having increased sensitivity relative to the prior art, it is still worthwhile to provide means for detecting electromagnetic radiation having increased sensitivity relative to current detection means, such as the detection means taught by document US 16 / 334109. Summary of the invention

[0013] The present invention aims to reduce this drawback and therefore aims to provide a detection component having an increased sensitivity with respect to components of the prior art, in particular with respect to the component taught by document US 16 / 334109.

[0014] To this end, the invention relates to a component for detecting electromagnetic radiation, comprising a detection structure and a power supply circuit for said detection structure,

[0015] The detection structure includes:

[0016] at least one absorption element, the at least one absorption element being configured to absorb electromagnetic radiation,

[0017] a transistor associated with the absorption element, the transistor being used to detect a rise in the temperature of the absorption element when electromagnetic radiation is absorbed, the transistor comprising:

[0018] ○ at least one first semiconductor region and at least one second region, the first semiconductor region is called a source region, the second region is called a drain region, the at least one first semiconductor region and the at least one second region each have a first conductivity type,

[0019] at least one third semiconductor region, the third semiconductor region is referred to as a channel region, the at least one third semiconductor region separates the source region and the drain region from each other, the at least one third semiconductor region has a first surface and a second surface, the first surface and the second surface are opposite surfaces, the first surface and the second surface extend between the source region and the drain region,

[0020] a first gate electrode, the first gate electrode being arranged opposite to the first face of the channel region to bias the channel region, the first gate electrode being separated from the channel region by a first gate dielectric layer,

[0021] ○ A second gate electrode, the second gate electrode is arranged opposite to the second surface of the channel region to bias the channel region, the second gate electrode is separated from the channel region by a second gate dielectric layer, wherein the power supply circuit is configured to supply power to each of these regions by being connected to the source region, the drain region, and the first gate electrode and the second gate electrode of the detection structure, the power supply circuit is configured to supply power to the detection structure during operation, so that the channel region has a layer at a position on one of the first surface and the second surface, in which carriers of a second conductivity type opposite to the first conductivity type are dominant, and the layer is called a blocking layer.

[0022] As the inventors have discovered, this configuration of the supply circuit and the barrier layer produced by this configuration make it possible to reduce the effectiveness (strength) of the coupling between the gate voltage and the surface potential of the channel face, which is the face opposite to the face on which the barrier layer is formed. Therefore, compared with the features of the prior art, the variation of the surface potential is less restricted by the gate voltage and can better vary with temperature. Therefore, this leads to a detection structure with better sensitivity relative to the components of the prior art (for example, the components taught by the document US16 / 334109 that do not include such a supply circuit).

[0023] As in Figure 1C and Figure 5C As shown in the following part of the relevant document, the inventors have thus obtained an increase in the thermal current coefficient (TCC) which can be greater than 1%. -1 .

[0024] The feature that "the channel region has a layer at the position of one of the first face and the second face" represents a barrier layer must be understood to mean that the barrier layer includes the face. In other words, the barrier layer extends from the face into the channel region.

[0025] The thickness of the second gate dielectric layer may be between 10 nm and 150 nm. Preferably, the thickness of the second gate dielectric layer is between 30 nm and 70 nm.

[0026] With such a value for the thickness of the second gate dielectric layer, the increase in the sensitivity of the detection element relative to detection elements of the prior art is particularly large.

[0027] At least one of the first gate dielectric layer and the second gate dielectric layer may include a first sublayer and a second sublayer respectively formed of a first dielectric material and a second dielectric material, and the first sublayer and the second sublayer may form an electrostatic dipole between the first sublayer and the second sublayer. Preferably, the first material and the second material are silicon dioxide and aluminum oxide respectively.

[0028] By means of such an electrostatic dipole, the voltage applied to the gate electrode during operation can be reduced, thereby reducing the heating caused by the Joule effect of the detection structure. Furthermore, since the electrostatic dipole can generate a potential difference between the electrostatic dipoles, such a reduction in the applied voltage makes it possible to envisage arranging the gate electrode and the source region in a short circuit.

[0029] The channel region may include a concentration of the doping element greater than a concentration of the doping element in a portion of the channel region arranged to form the barrier layer than a remaining portion of the channel region.

[0030] Since the channel region comprises an excess of majority carriers to enable the formation of the barrier layer, such overdoping of the portion of the channel region for forming the barrier layer enables the applied voltage to be reduced. It is thus possible to reduce the voltage applied to the corresponding gate electrode in operation, thereby reducing the heating caused by the Joule effect of the detection structure. Furthermore, since electrostatic dipoles can generate a potential difference between the electrostatic dipoles, such a reduction in the applied voltage enables the gate electrode to be arranged in a short circuit with the source region to be envisaged.

[0031] The source region and the first gate electrode may be short-circuited.

[0032] The source region and the second gate electrode may be short-circuited.

[0033] In this way, the number of connections to the power supply circuit can be reduced, thereby facilitating thermal insulation of the connection structure relative to the power supply circuit and a possible support in which the circuit will be arranged.

[0034] The drain region and the second gate electrode may be short-circuited.

[0035] The drain region and the first gate electrode may be short-circuited.

[0036] In this way, the number of connections to the power supply circuit can be reduced, thereby facilitating thermal insulation of the connection structure relative to the power supply circuit and a possible support in which the circuit will be arranged.

[0037] The channel region may have a first conductivity type, the barrier layer is an inversion layer, and the second gate electrode is short-circuited with the first gate electrode and short-circuited with the source region.

[0038] With such a configuration, it is possible to apply a zero bias to the first and second gate electrodes and the source region, and then only the drain region is biased.

[0039] The channel region may have a second conductivity type and the barrier layer is an accumulation layer.

[0040] The channel region may have a first conductivity type and the barrier layer is an inversion layer.

[0041] These configurations correspond to enhancement mode transistors and depletion mode transistors, respectively. It should be noted that the depletion mode transistor configuration is particularly advantageous for providing the detection structure with a first gate having a relatively low bias voltage, which in some configurations can even be zero (i.e. the potential difference between the source region and the first gate is zero).

[0042] The absorbing element comprises at least one of the following:

[0043] - at least one portion of the first gate electrode,

[0044] - at least a portion of the second gate electrode, and

[0045] - At least one conductive track, at least one conductive track connecting the detection structure and the power supply circuit.

[0046] The invention also relates to a method for producing a component for detecting electromagnetic radiation, the method comprising the following steps:

[0047] -Provide a detection structure, the detection structure includes:

[0048] o at least one absorption element, the at least one absorption element being configured to absorb electromagnetic radiation,

[0049] o a transistor associated with an absorbing element, the transistor being configured to detect a rise in temperature of the absorbing element when electromagnetic radiation is absorbed, the transistor comprising:

[0050] ■ at least one first semiconductor region and at least one second semiconductor region, the first semiconductor region being referred to as a source region and the second semiconductor region being referred to as a drain region, the at least one first semiconductor region and the at least one second semiconductor region having a first conductivity type,

[0051] ■ at least one third semiconductor region, the third semiconductor region being referred to as a channel region, the at least one third semiconductor region separating the source region and the drain region from each other, the at least one third semiconductor region having a first face and a second face, the first face and the second face being opposite faces and extending between the source region and the drain region,

[0052] ■ a first gate electrode, the first gate electrode being arranged opposite to the first face of the channel region to bias the channel region,

[0053] ■ a second gate electrode, the second gate electrode being arranged opposite to the second face of the channel region to bias the channel region,

[0054] - providing a power supply circuit configured to supply power to each of the source region, the drain region, and the first gate electrode and the second gate electrode of the detection structure,

[0055] The method comprises a step of connecting the detection structure to the power supply circuit, said step being independent of the step of providing the detection structure and the step of providing the power supply circuit, or being performed simultaneously with at least one of these steps,

[0056] When a power supply circuit is provided, the power supply circuit is configured to supply power to the detection structure during operation so that the channel region has a layer at a position on one of the first surface and the second surface, in which carriers of a second conductivity type opposite to the first conductivity type are dominant, and the layer is called a blocking layer.

[0057] This method makes it possible to provide a component according to the invention and to benefit from the advantages associated with this component.

[0058] The step of providing a detection structure may include a sub-step of forming at least one of a first gate dielectric layer and a second gate dielectric layer, wherein the gate dielectric layer includes a first sublayer and a second sublayer respectively composed of a first dielectric material and a second dielectric material, and the first sublayer and the second sublayer can form an electrostatic dipole between the first sublayer and the second sublayer, and preferably, the first material and the second material are silicon dioxide and aluminum oxide, respectively.

[0059] By utilizing such an electrostatic dipole, the detection structure can have a reduced corresponding gate electrode voltage relative to the detection structure of the prior art, thereby having reduced Joule effect induced heating. In addition, since the electrostatic dipole can generate a potential difference between the electrostatic dipoles, this reduction in the applied voltage can arrange the gate electrode and the source region into a short circuit.

[0060] The step of providing the detection structure may include a sub-step of doping the channel region to form a portion of the channel region arranged for forming the barrier layer having a concentration of the doping element higher than a concentration of the doping element in a remaining portion of the channel region.

[0061] Since the channel region includes an excess of majority carriers to enable the formation of the barrier layer, this overdoping of the portion of the channel region used to form the barrier layer enables the detection structure of the formed component to have a reduced applied voltage. Therefore, the detection component formed in this way can have a reduced voltage applied to the corresponding gate electrode and therefore have reduced heat caused by the Joule effect of the detection structure. In addition, since electrostatic dipoles can generate a potential difference between electrostatic dipoles, this reduction in applied voltage enables the gate electrode to be arranged as a short circuit with the source region.

[0062] One of the steps of forming the detection structure and connecting the detection structure to the power supply circuit may include arranging the source region and the first gate electrode to be short-circuited.

[0063] One of the steps of forming the detection structure and connecting the detection structure to the power supply circuit may include arranging the source region and the second gate electrode to be short-circuited.

[0064] One of the steps of forming the detection structure and connecting the detection structure to the power supply circuit may include arranging the drain region and the second gate electrode to be short-circuited.

[0065] One of the steps of forming the detection structure and connecting the detection structure to the power supply circuit may include arranging the drain region and the first gate electrode to be short-circuited.

[0066] Thus, with a connection component thus formed, the number of connections between the supply circuit and the detection structure can be reduced, thereby facilitating thermal insulation of the connection structure relative to the supply circuit and a possible support in which the circuit will be arranged. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The invention will be better understood by reading the description of an exemplary embodiment given by way of illustration only and in no way limiting, and with reference to the accompanying drawings, in which:

[0068] - Figures 1A to 1C The operating principle of the detection component according to the first possible embodiment of the present invention is shown, wherein: Figure 1A The power supply of the detection structure according to this first possible embodiment is shown by a cross-sectional view, Figure 1B The operating principle of this detection structure is shown. Figure 1C The sensitivity of this detection structure as a function of the drain current is shown in a diagram compared with the sensitivity of the detection structure taught by document US 16 / 334109,

[0069] - Figure 2The operating principle of the detection component according to the second possible embodiment of the present invention is illustrated by showing the power supply of the detection structure according to the second possible embodiment of the present invention by a cross-sectional view,

[0070] - Figure 3 The operating principle of the detection component according to the third possible embodiment of the present invention is illustrated by showing the power supply of the detection structure according to the third possible embodiment of the present invention by a cross-sectional view,

[0071] - Figure 4A and Figure 4B By Figure 4A The power supply of the detection structure according to a fourth possible embodiment of the present invention and the Figure 4B , a detection structure is shown in FIG. 1 to illustrate the operating principle of the detection component according to a fourth possible implementation of the present invention, wherein the detection structure has an optimized ratio of the channel length L to the channel width W.

[0072] - FIG. 5A to FIG. 5C The operating principle of the detection component according to the fifth possible implementation mode of the present invention is shown, wherein: Figure 5A The power supply of the detection structure according to this fifth possible embodiment is shown by a cross-sectional view, Figure 5B The operating principle of this detection structure is shown. Figure 5C The sensitivity of this detection structure as a function of the drain current is shown in a diagram compared with the sensitivity of the detection structure according to the document US 16 / 334109.

[0073] - Figure 6 The operating principle of the detection component according to the sixth possible embodiment of the present invention is illustrated by showing the power supply of the detection structure according to the sixth possible embodiment of the present invention by a cross-sectional view,

[0074] - Figure 7 The operating principle of the detection component according to the seventh possible embodiment of the present invention is illustrated by showing the power supply of the detection structure according to the seventh possible embodiment of the present invention by a cross-sectional view,

[0075] - Figure 8 The operating principle of the detection component according to the eighth possible embodiment of the present invention is illustrated by showing the power supply of the detection structure according to the eighth possible embodiment of the present invention through a cross-sectional view,

[0076] - Fig.9A and Fig. 9B By Fig.9A The power supply of the detection structure according to the ninth possible embodiment of the present invention and the Fig. 9B, a detection structure is shown in FIG. 1 to illustrate the operating principle of the detection component according to the ninth possible implementation of the present invention, and the detection structure has an optimized ratio of the channel length L to the channel width W.

[0077] - Fig.10 A detection component according to a first embodiment of a first possible implementation mode of the present invention is shown.

[0078] - FIG. 11A to FIG. 11H The main steps of the method for manufacturing the detection component according to the first embodiment are shown.

[0079] - Fig.12 shows a detection component according to a second embodiment of a third possible implementation mode of the present invention,

[0080] - FIG. 13A to FIG. 13B The first specific step and the second specific step of the method for manufacturing the detection component according to the second embodiment are respectively shown,

[0081] - Fig.14 shows a modified detection component of the second embodiment according to a modification of the third possible implementation mode of the present invention,

[0082] - FIG. 15A to FIG. 15C for Fig.15A and Fig. 15B The first and second specific steps of the method for manufacturing a detection component according to a modification of the second embodiment are shown, and for Fig. 15C shows a graph illustrating the doping principle implemented in the case of manufacturing a detection component according to a variant of the second embodiment of the invention,

[0083] - Fig.16A and Fig. 16B Components of the third embodiment according to a fourth possible implementation of the present invention and components according to a variation of the third embodiment are respectively shown, Fig.16A A cross-sectional view of such a detection component is shown, Fig. 16B shows a view from below showing a contact track of the variant, which contact track enables biasing of the source and drain regions and the first and second gate electrodes,

[0084] - Fig.17 shows a detection component according to a fourth embodiment of a fifth possible implementation of the present invention,

[0085] - Fig.18 shows a detection component according to a fifth embodiment of a seventh possible implementation mode of the present invention,

[0086] - FIG. 19A to FIG. 19BThe first specific step and the second specific step of the method for manufacturing the detection component according to the fifth embodiment are respectively shown,

[0087] - Fig. 20 shows a detection component of a modification of the fifth embodiment according to a modification of the seventh possible implementation mode of the present invention,

[0088] - FIG. 21A to FIG. 21B The first and second specific steps of the method for manufacturing a detection component according to a variation of the fifth embodiment are respectively shown,

[0089] - Fig. 22 shows components of a sixth embodiment according to an eighth possible implementation of the present invention,

[0090] - Fig.23A and Fig. 23B respectively show a cross-sectional view of a component of a seventh embodiment according to a ninth possible implementation of the invention and a view of the same component from below, said views showing contact tracks enabling biasing of the source and drain regions and the first and second gate electrodes,

[0091] - FIG. 24A to FIG. 24C The first specific step and the third specific step of the method for manufacturing the detection component according to the seventh embodiment are respectively shown.

[0092] The same, similar or equivalent parts of the various figures have the same reference numerals to facilitate transitioning from one figure to another.

[0093] The various components shown in the drawings are not necessarily to uniform scale in order to make the drawings easier to read.

[0094] The various possible implementations (variants and embodiments) must be understood as not excluding one another and as being combinable with one another. DETAILED DESCRIPTION

[0095] Figure 1A and Figure 1B A cross-sectional view of a detection structure 100 and a cross-sectional view of a detection component 1 are respectively shown, which comprises such a structure according to the principles of the present invention, and which is configured for detecting electromagnetic radiation λ.

[0096] More particularly, such a detection component 1 is used to detect electromagnetic radiation in the infrared wavelength range. Therefore, the different values ​​shown in the embodiments described below relate to this practical application, wherein the wavelengths involved are far infrared wavelengths, i.e. between 8 μm and 12 μm. Of course, based on the present disclosure, a person skilled in the art is fully capable of adjusting these values ​​so that such a detection structure 100 can be used to optimize the detection of electromagnetic radiation in a wavelength range other than the infrared wavelength range.

[0097] It should be noted that the present invention particularly relates to detection components comprising a plurality of detection structures which are arranged in an array with a network pitch of 10 μm or less of the array. Therefore, if in this specification the component is described in relation to a single detection structure, the present invention naturally gives the possibility of a component comprising a plurality of detection structures, and a person skilled in the art will be able to extrapolate the present teaching to such a configuration.

[0098] Principle of the Invention

[0099] Therefore, according to the principle of the present invention, Figure 1B As shown in FIG. 1 , the detection component according to the present invention includes a detection structure 100 and a power supply circuit (350) of the detection structure 100.

[0100] The detection structure 100 comprises:

[0101] at least one absorption element, the at least one absorption element being configured to absorb electromagnetic radiation,

[0102] a transistor associated with the absorption element, the transistor being intended to detect a rise in the temperature of said absorption element when electromagnetic radiation λ is absorbed, the transistor comprising:

[0103] ○ At least one first semiconductor region 111 and at least one second region 112, the first semiconductor region is called a source region, the second region is called a drain region, the at least one first semiconductor region and the at least one second region each have a first conductivity type,

[0104] ○ At least one third semiconductor region 113, the third semiconductor region is called a channel region, the at least one third semiconductor region separates the source region 111 and the drain region 112 from each other, the at least one third semiconductor region has a first surface and a second surface, the first surface and the second surface are opposite surfaces, and the first surface and the second surface extend between the source region 111 and the drain region 112,

[0105] ○ A first gate electrode 121, the first gate electrode is arranged opposite to the first surface of the channel region 113 to bias the channel region 113, and the first gate electrode 121 is separated from the first surface of the channel region 113 by a first gate dielectric layer 131,

[0106] ○ A second gate electrode 125 , which is arranged opposite to the second surface of the channel region 113 to bias the channel region 113 , and the second gate electrode 125 is separated from the second surface of the channel region 113 by a second gate dielectric layer 135 .

[0107] The power supply circuit 350 is configured to supply power to the detection structure 100 at the locations of the source region 111, the drain region 112, and the first gate electrode 121 and the second gate electrode 125. More specifically, the power supply circuit 350 is configured to supply power to the detection structure 100 during operation, so that the channel region 113 has a layer 114 at a location of one of the first surface and the second surface, in which carriers of a second conductivity type opposite to the first conductivity type are dominant, and the layer 114 is called a blocking layer.

[0108] Of course, if according to the first possible embodiment of the present invention, and according to other possible embodiments described in this document, the power supply circuit 350 is configured to supply power to the detection structure 100 with a voltage, then without departing from the scope of the present invention, it is also conceivable to supply power to the structure at least partially with a current. Although this variant may not be further described in this document, a person skilled in the art can easily implement this variant based on this teaching.

[0109] According to Figure 1B In a first possible embodiment shown in FIG. 1 , the absorption element comprises a second gate electrode 125. Of course, according to the teaching of document US 16 / 334109, the absorption element can be provided by another element of the detection structure 100 (e.g., the first gate electrode 121 or a plurality of interconnection tracks), which enable the detection structure 100 to be connected to a power supply circuit 350, and the absorption element is in thermal contact with the transistor.

[0110] It should be noted that for such a detection element 1, the channel region may be:

[0111] (i) It has the second conductivity type or the intrinsic type, so the transistor is an NPN type or PNP type transistor, and the barrier layer 114 is an accumulation layer.

[0112] (ii) or having a first conductivity type, wherein the concentration of majority carriers is reduced relative to the concentrations of the source region 111 and the drain region 112 so that the barrier layer is an inversion layer.

[0113] Configuration (ii) is a configuration in which the transistor of the detection structure is a so-called depleted or depletion-type transistor. Such a transistor of the N+NN+ type or P+PP+ type is in the on-state in the absence of a voltage on the gate, the channel region having the same conductivity type as the source and drain regions. By appropriately biasing the gate relative to the source, that is, typically biasing the gate negatively in the case of an N+NN+ transistor, biasing the gate positively in the case of a P+PP+ transistor, or even zero biasing the gate in both cases, the channel region can be depleted, or even the conductivity type of the channel region can be reversed, to block conduction in the channel region.

[0114] In the case of an electromagnetic radiation detector type component, the inventors provide the use of depletion mode transistors to obtain the required operating current of the transistor with a zero biased gate even in the presence of a blocking layer.

[0115] In fact, for a depletion-mode transistor, the threshold voltage of the transistor without a barrier layer is negative or close to zero, while for an enhancement-mode transistor, the threshold voltage of the transistor without a barrier layer is positive or close to zero. Fabricating a barrier layer causes the threshold voltage of the transistor to increase. Therefore, even in the presence of a barrier layer, an enhancement-mode transistor is not suitable for obtaining the operating current of a transistor with a zero-biased gate. Therefore, a depletion-mode transistor with a barrier layer whose threshold voltage becomes positive or close to zero is used, so that the required operating current of a transistor with a zero-biased gate can be obtained even in the presence of a barrier layer.

[0116] This arrangement for detecting electromagnetic radiation using a depletion transistor according to the bolometer principle is novel with respect to prior art components, such as provided by document US 16 / 334109.

[0117] Therefore, according to the principles of the present invention, the supply voltage provided to the structure by the power supply circuit 350 is such that: for arrangement (i), the blocking layer 114 is an accumulation layer, and for arrangement (ii), the blocking layer is an inversion layer. In other words, for arrangement (i) and arrangement (ii), the blocking layer 114 is a layer in which, during operation of the component, the conductivity and current between the source region 111 and the drain region 112 are blocked, and the current passing through the channel region 113 must pass through the rest of the channel region 113. Therefore, according to the present invention, the power supply circuit is thus configured to supply power to the detection structure 100 so that: for configuration (i), the rest of the channel region 113 is in an inversion state, or for configuration (ii), the rest of the channel region is in a depletion state, a neutral state, or an accumulation state depending on the voltage applied to the gate opposite to the blocking layer.

[0118] Therefore, the general principle of the present invention can be applied in Figures 1A to 9BThe various methods shown in FIG. Figures 1A to 4B involving arrangement (i), FIG. 5A to FIG. 9B Involving arrangement (ii).

[0119] In describing these various possible embodiments of the present invention, in order to define the relative voltages applied by the power supply circuit to the detection structure 100, the features of the exemplary detection structure 100 that have been constructed are as follows:

[0120] - A source region 111 and a drain region 112 having a first conductivity type, wherein electrons are the majority carriers, i.e. N-type doping, and the concentration of the electron donor doping element is equal to 1.10 20 cm -3 ,

[0121] - Channel region 113, for the first to fourth possible embodiments corresponding to arrangement (i), the channel region has a second conductivity type, ie, P-type doping, wherein the concentration of the electron acceptor doping element is 1.10 15 cm -3 For the fifth to ninth possible embodiments corresponding to arrangement (ii), the channel region has a first conductivity type, wherein the concentration of the electron donor doping element is equal to between 1.10 16 cm -3 to 1.10 17 cm -3 The concentration between

[0122] - the source region 111, the drain region 112 and the channel region 113 are made of silicon and have a thickness of 50 nm,

[0123] - a first gate dielectric layer 131, unless otherwise specified, the first gate dielectric layer has a thickness of 9 nm and is made of silicon dioxide,

[0124] - a second gate dielectric layer 135, the second gate dielectric layer has a thickness between 10 nm and 150 nm and is made of silicon dioxide,

[0125] A first gate electrode 121 and a second gate electrode 125 , the first gate electrode and the second gate electrode comprising a conductor material of the mid-gap type for the channel region 113 .

[0126] In the above and in the rest of this document, "mid-gap type conductor material" means that the conductor material is selected such that, without biasing the structure, the Fermi energy of the conductor material is in the bandgap region of the third region, more particularly near the middle of the bandgap region of the third region, typically at an energy level far from the middle of the bandgap, between -25% and +25% of the gap of the bandgap. Those skilled in the art usually refer to this gate configuration as "mid-gap". Thus, if the third region is made of silicon, "mid-gap type conductor material" particularly includes titanium nitride, tantalum nitride and molybdenum silicide.

[0127] The features of the detection structure 100 described above have been constructed for an N-type transistor. The features of the detection structure described above may be constructed to suit a P-type transistor without departing from the scope of the present invention.

[0128] It should also be noted that the different values / configurations listed above are given only by way of example to illustrate different possible embodiments of the present invention, and therefore, different values / configurations may be used without departing from the scope of the present invention, as long as these values ​​are capable of forming the barrier layer 114 when the detection structure is powered by the power supply circuit according to the principles of the present invention. Thus, for example, without departing from the scope of the present invention, at least one of the first gate electrode 121 and the second gate electrode 125 may not include a conductor material of the middle gap type for the channel region, or both of the first gate electrode and the second gate electrode may not include a conductor material of the middle gap type for the channel region.

[0129] First possible implementation:

[0130] According to the present invention Figures 1A to 1C In the first possible implementation shown in FIG. 1 , the power supply circuit 350 may be arranged to independently supply power to each of the source region 111 , the drain region 112 , the first electrode 121 and the second electrode 125 , and form a barrier layer 114 at the position of the second surface of the channel region 113 .

[0131] According to this first possible implementation and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0132] - Applying a source voltage Vs of zero (0V) to the source region 111,

[0133] - Apply a drain voltage Vd of 100 mV to the drain region 112,

[0134] - applying a gate voltage Vg, for example a voltage Vg of 800 mV, to the first gate electrode 121, the gate voltage being arranged to regulate the operating current of the transistor, and

[0135] A negative back gate voltage Vb between −1 V and −12.5 V is applied to the second gate electrode 125 . The gate voltage Vb must be adjusted according to the thickness of the second gate dielectric layer 135 .

[0136] Of course, these values ​​are only valid for the exemplary configurations described in the principles of the invention and in no way limit the invention. Thus, it should be noted that, for example, if one of the first and second gates is not made of a "mid-gap" material, the corresponding voltage must be adjusted.

[0137] In this way, the negative back gate voltage Vb enables the formation of the barrier layer 114 in the form of an accumulation layer at the level of the second face of the channel region 113 .

[0138] According to the principles of the invention and as the inventors have discovered, such a barrier layer 114 makes it possible to reduce the effectiveness (strength) of the coupling between the gate voltage and the surface potential of the channel face, which is the face opposite to the face on which the barrier layer is formed. Therefore, compared with the features of the prior art, the variation of the surface potential is less restricted by the gate voltage and can better vary with temperature. Therefore, this results in a detection structure with better sensitivity relative to the components of the prior art (e.g., taught by document US16 / 334109).

[0139] Therefore, to illustrate this improvement in sensitivity, Figure 1C The variation of the thermal current coefficient (TCC) is shown, for a component according to this first possible implementation, normalizing the transistor current by the ratio of the width to the length of the transistor, this variation is marked 401, and for a transistor with the same characteristics, according to the teaching of document US 16 / 334109, this variation is marked 402. In addition to the characteristics already listed, the common characteristics are: the channel length is 500 nm to normalize the current, and the thickness of the second oxide layer is 145 nm.

[0140] Therefore, in Figure 1C It is observed that for the configuration of the present invention, the increase in the thermal current coefficient is greater than 0.9% for normalized currents in the range of 100 pA to 1 nA. -1 , and for normalized currents between 10nA and 50nA, the increase in thermal current coefficient is about 0.5%.K -1. In addition, the inventors have found that this increase is accompanied by a reduction in the 1 / f noise of the transistor. Therefore, with an increase in sensitivity and a reduction in 1 / f noise, the detection component 1 according to the invention has a particularly optimized signal / noise ratio relative to the components of the prior art. This reduction in 1 / f noise can be attributed to the use of the barrier layer 114 and is therefore also obtained by other possible embodiments of the invention.

[0141] Second possible implementation:

[0142] According to the present invention Figure 2 In the second possible implementation shown in FIG. 1 , the power supply circuit 350 may be arranged to independently supply power to each of the source region 111 , the drain region 112 , the first electrode 121 and the second electrode 125 , and form a barrier layer 114 at the location of the first surface of the channel region 113 .

[0143] According to this second possible implementation and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0144] - Applying a source voltage Vs of zero (0V) to the source region 111,

[0145] - Apply a drain voltage Vd of 100 mV to the drain region 112,

[0146] - applying a gate voltage Vg of -1V to the first gate electrode 121, and

[0147] A positive back gate voltage Vb between 500 mV and 7 V is applied to the second gate electrode 125 , and the back gate voltage Vb must be adjusted according to the thickness of the second gate dielectric layer 135 and the operating current of the transistor.

[0148] In this way, the negative gate voltage Vb enables the formation of the barrier layer 114 in the form of an accumulation layer at the level of the first face of the channel region 113 .

[0149] It should be noted that according to variations of the first possible embodiment and the second possible embodiment, the power supply circuit 350 can be configured to supply power to the detection structure according to the first possible embodiment and according to the second possible embodiment, and the power supply circuit 350 can be controlled to transition from one embodiment to another, or be configured to transition from one embodiment to another according to some circumstances (for example, circumstances inside the component, such as the source-drain current Ids, or circumstances outside the component, such as instructions for transitioning from one of the first possible embodiment and the second possible embodiment to another).

[0150] A third possible implementation:

[0151] According to the present invention Figure 3 In the third possible implementation shown in FIG, the power supply circuit 350 can be arranged to apply the same voltage to the source region 111 and the first gate electrode 121, the drain region 112 and the second gate electrode 125 are powered independently of each other, and the source region 111 / first gate electrode pair is powered independently to form a blocking layer 114 at the position of the first surface of the channel layer 113. In addition, in order to achieve such bias, according to the third possible implementation, the detection structure 100 has a "pre-bias" of the blocking layer 114, that is, a device for applying an "internal" potential to reduce the threshold voltage of the first gate electrode 121, and the "pre-bias" of the blocking layer 114:

[0152] - provided by a first gate dielectric layer 121, the first gate dielectric layer comprising a first sublayer and a second sublayer, the first sublayer and the second sublayer being respectively composed of a first dielectric material and a second dielectric material, the first sublayer and the second sublayer being suitable for forming a dipole interface together by forming an electrostatic dipole between the first sublayer and the second sublayer,

[0153] - or provided by overdoping the portion of the channel region arranged to form the barrier layer with an electron acceptor doping element, such as indium atoms or boron atoms obtained by ion implantation of indium ions In, boron fluoride ions BF2 or boron B.

[0154] Therefore, with this dipole interface of the first oxide layer of the gate electrode 121 or this overdoping of the portion of the channel region 113 arranged to form the barrier layer 114, both of which are equivalent to pre-biasing the channel region 113 at the location of the first face of the channel region, this can shift the threshold voltage of the first gate electrode by +1 V, or if both possible embodiments are combined, this can even shift the threshold voltage of the first gate electrode 121 by +2 V. With this "pre-bias" at the location of the first gate electrode 121, this results in the need not to apply a negative voltage to form the barrier layer as in the second possible embodiment.

[0155] According to this third possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0156] - applying a source voltage Vs and a gate voltage Vg of zero (0V) to the source region 111 and the first gate electrode 121,

[0157] - Applying a drain voltage Vd of 100 mV to the drain region 112, and

[0158] A positive back gate voltage Vb between 500 mV and 7 V is applied to the second gate electrode 125 , and the back gate voltage Vb must be adjusted according to the thickness of the second gate dielectric layer 135 and the operating current of the transistor.

[0159] The advantage of this third possible embodiment is that, when the source region 111 and the first gate electrode 121 are short-circuited, only three interconnections need to be provided between the detection structure 100 and the supply circuit 350. In this way, the heat exchange between the detection structure and the supply circuit 350 is limited, which can reduce the temperature reached by the absorber and therefore reduce the sensitivity of the detection component 1.

[0160] Fourth possible implementation method:

[0161] According to the present invention Figure 4A and Figure 4B In the fourth possible implementation shown in FIG. 3 , the power supply circuit 350 may be arranged to supply power to the source region 111 and the first gate electrode 121 together, to supply power to the drain region 112 and the second gate electrode 125 together, and to form the barrier layer 114 at the location of the first surface of the channel layer 113. Furthermore, in order to achieve such bias, according to this fourth possible implementation, the detection structure 100 has a “pre-bias” of the barrier layer 114 similar to that described in the case of the third possible implementation.

[0162] According to the fourth possible implementation, in order to minimize the bias voltage of the second gate electrode 125 and the voltage applied to the drain region 112, the thickness of the second gate dielectric layer 131 is selected to be relatively low, which may be between 20nm and 50nm, preferably between 25nm and 35nm, or even substantially equal to 30nm. In addition, the bias voltage of the second gate electrode 125 and the voltage applied to the drain region 112 can also be reduced by optimizing the ratio of the width of the channel region to the length of the channel region, preferably, the ratio is greater than 150, or even greater than 250, or even greater than 300.

[0163] According to this fourth possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0164] - applying a source voltage Vs and a gate voltage Vg of zero (0V) to the source region 111 and the first gate electrode 121,

[0165] - A drain voltage Vd and a back gate voltage Vb between 200 mV and 2 V are applied to the drain region 112 and the second gate electrode 125, which voltages must be configured according to the thickness of the second gate dielectric layer 135 and the operating current of the transistor and therefore the operating current of the detection structure.

[0166] The advantage of this fourth possible embodiment is that, when the source region 111 and the first gate electrode 121 are short-circuited and the drain region 112 and the second gate electrode 125 are short-circuited, only two interconnections need to be provided between the detection structure 100 and the power supply circuit 350. In this way, the heat exchange between the detection structure and the power supply circuit 350 is limited, which can reduce the temperature reached by the absorber and thus reduce the sensitivity of the detection component 1.

[0167] Figure 4B 1 shows a specific configuration of the detection structure 100 according to the fourth possible embodiment, in which the detection structure 100 has an optimized ratio of the width of the channel region to the length of the channel region. This optimization is achieved by a three-gate or "three-tooth comb" configuration (see Fig. 16B , Fig. 16B The double gate or "two-tooth comb" example is shown) to obtain a structure including double the source region 111 and the drain region 112, and triple the channel region. In fact, as Figure 4B As shown, the detection structure is formed by a continuous portion of a “first” source sub-region 111 , a “first” channel sub-region 113 , a “first” drain sub-region 112 , a “second” channel sub-region 113 , a “second” source sub-region 111 , a “third” channel sub-region 113 and a “second” drain sub-region 112 .

[0168] Of course, based on this example, a person skilled in the art can generalize this configuration, and in order to optimize the ratio of the width / length of the channel region, a multi-gate or "multi-tooth comb" configuration can be used, and the number of gates or "teeth" can be greater than or equal to 2.

[0169] Fifth possible implementation method:

[0170] The fifth possible embodiment corresponds to the first possible embodiment of the invention applied to a structure comprising a depletion-mode transistor.

[0171] Therefore, according to the present invention FIG. 5A to FIG. 5C In the fifth possible implementation shown in FIG. 1 , the power supply circuit 350 may be arranged to independently supply power to each of the source region 111 , the drain region 112 , the first electrode 121 , and the second electrode 125 , and form a barrier layer 114 at the position of the second surface of the channel region 113 .

[0172] According to this fifth possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0173] - Applying a source voltage Vs of zero (0V) to the source region 111,

[0174] - Apply a drain voltage Vd of 200mV to the drain region 112,

[0175] - applying a gate voltage Vg, for example a voltage Vg of 400 mV, to the first gate electrode 121, the gate voltage being arranged to regulate the operating current of the transistor, and

[0176] A negative back gate voltage Vb between −1 V and −12.5 V is applied to the second gate electrode 125 . The gate voltage Vb must be adjusted according to the thickness of the second gate dielectric layer 135 .

[0177] In this way, the negative back gate voltage Vb enables the formation of a barrier layer 114 in the form of an inversion layer at the level of the second face of the channel region 113 .

[0178] In the same manner as the structure of a conventional transistor of the MOSFET type according to the first possible embodiment, according to the principles of the invention and as the inventors have discovered, such a barrier layer 114 makes it possible to reduce the effectiveness (strength) of the coupling between the gate voltage and the surface potential of the channel face, which is the face opposite to the face on which the barrier layer is formed. Therefore, the variation of the surface potential is less restricted by the gate voltage and can vary better with temperature than the features of the prior art. Therefore, relative to the components of the prior art (for example taught by document US16 / 334109), this leads to a better sensitivity of the detection structure.

[0179] Therefore, to illustrate this improvement in sensitivity, Figure 5C The variation of the thermal current coefficient (abbreviated TCC) is shown, for a component according to this fifth possible implementation, normalizing the transistor current by the ratio of the width to the length of the transistor, which variation is marked 411, and for a transistor with the same characteristics, according to the teaching of document US 16 / 334109 applied to depletion transistors, which variation is marked 412. In addition to the characteristics already listed, the common characteristics are: the channel length is 500nm to normalize the current, and the thickness of the second oxide layer is 145nm.

[0180] Therefore, in Figure 1C It is observed that for the configuration of the present invention, the increase in the thermal current coefficient is greater than 1% for normalized currents in the range of 100 pA to 1 nA. -1 , and for normalized currents between 10nA and 100nA, the increase in thermal current coefficient is greater than 0.5%.K -1Furthermore, the inventors have found that, also in the case of depletion-mode transistors, this increase is accompanied by a reduction in the 1 / f noise of the transistor. Thus, with an increase in sensitivity and a reduction in 1 / f noise, the detection component 1 according to the invention has a particularly optimized signal / noise ratio relative to components of the prior art.

[0181] Sixth possible implementation method:

[0182] According to the present invention Figure 6 In the sixth possible implementation shown in FIG. 1 , the power supply circuit 350 may be arranged to independently supply power to each of the source region 111 , the drain region 112 , the first electrode 121 and the second electrode 125 , and a barrier layer 114 is formed at the position of the first surface of the channel region 113 .

[0183] According to this sixth possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0184] - Applying a source voltage Vs of zero (0V) to the source region 111,

[0185] - Apply a drain voltage Vd of 200mV to the drain region 112,

[0186] - applying a gate voltage Vg of -1V to the first gate electrode 121, and

[0187] A positive back gate voltage Vb between 150 mV and 2.5 V is applied to the second gate electrode 125 , and the back gate voltage Vb must be adjusted according to the thickness of the second gate dielectric layer 135 and the operating current of the transistor.

[0188] Therefore, the negative gate voltage Vg enables the formation of a blocking layer 114 in the form of an inversion layer at the position of the first surface of the channel region 113, and the back gate voltage is selected to put the rest of the channel region in a depletion state, a neutral state or an accumulation state depending on the voltage applied to the gate opposite to the blocking layer.

[0189] According to the first possible embodiment and the second possible embodiment described above, and according to variations of the fifth possible embodiment and the sixth possible embodiment, the power supply circuit 350 can be configured to supply power to the detection structure according to the fifth possible embodiment and according to the sixth possible embodiment, and the power supply circuit can be controlled to transition from one embodiment to another, or be configured to transition from one embodiment to another according to some circumstances (for example, circumstances inside the component, such as the source-drain current Ids, or circumstances outside the component, such as instructions for transitioning from one of the first possible embodiment and the second possible embodiment to another).

[0190] Seventh possible implementation method:

[0191] According to the present invention Figure 7 In the seventh possible implementation shown in FIG. 1 , the power supply circuit 350 can be arranged to supply power to the source region 111 and the first gate electrode 121 together, and the drain region 112 and the second gate electrode 125 are independently supplied with power, and the source region 111 / first gate electrode pair is independently supplied with power, so as to form a blocking layer 114 at the position of the first surface of the channel layer 113. In addition, according to the third possible implementation and the fourth possible implementation described previously for realizing such biasing, according to the seventh possible implementation, the detection structure 100 has a "pre-bias" of the blocking layer 114, and the "pre-bias" of the blocking layer is:

[0192] - provided by a first gate dielectric layer 121, the first gate dielectric layer comprising a first sublayer and a second sublayer, the first sublayer and the second sublayer being respectively composed of a first dielectric material and a second dielectric material, the first sublayer and the second sublayer being suitable for forming a dipole interface together by forming an electrostatic dipole between the first sublayer and the second sublayer,

[0193] - or provided by overdoping a portion of the channel region 113 arranged to form a barrier layer with an electron acceptor doping element, such as indium atoms or boron atoms obtained by ion implantation of boron B ions, boron fluoride BF2 ions or indium In ions.

[0194] Therefore, with such a dipole interface of the first oxide layer 121 or such an overdoping of the portion of the channel region 113 arranged to form the barrier layer 114, both of which are equivalent to pre-biasing the channel region 113 at the position of the first face of the channel region, it is possible to obtain a shift of the threshold voltage of the first gate electrode by +1 V, or if both possible embodiments are combined, it is even possible to obtain a shift of the threshold voltage of the first gate electrode 121 by +2 V. With such a "pre-bias" at the position of the first gate electrode 121, it results in that there is no need to apply a negative voltage to form a barrier layer as in the sixth possible embodiment.

[0195] According to this seventh possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0196] - applying a source voltage Vs and a gate voltage Vg of zero (0V) to the source region 111 and the first gate electrode 121,

[0197] - Applying a drain voltage Vd of 200 mV to the drain region 112, and

[0198] A positive back gate voltage Vb between 150 mV and 2.5 V is applied to the second gate electrode 125 , and the back gate voltage Vb must be adjusted according to the thickness of the second gate dielectric layer 135 and the operating current of the transistor.

[0199] The advantage of this seventh possible embodiment is that, when the source region 111 and the first gate electrode 121 are short-circuited, only three interconnections need to be provided between the detection structure 100 and the power supply circuit 350. In this way, the heat exchange between the detection structure and the power supply circuit 350 is limited, which can reduce the temperature reached by the absorber and thus reduce the sensitivity of the detection component 1.

[0200] Eighth possible implementation method:

[0201] According to the present invention Figure 8 In the eighth possible implementation shown in FIG. 3 , the power supply circuit 350 may be arranged to supply power to the source region 111 and the first gate electrode 121 together, to supply power to the drain region 112 and the second gate electrode 125 together, and to form a blocking layer 114 at the position of the first surface of the channel layer 113. In addition, in order to achieve such bias, according to the eighth possible implementation, the detection structure 100 has a “pre-bias” of the blocking layer 114 similar to that described in the third possible implementation, the fourth possible implementation, and the seventh possible implementation.

[0202] According to the eighth possible implementation, in order to minimize the bias voltage of the second gate electrode 125 and the voltage applied to the drain region 112, the thickness of the second gate dielectric layer 131 is selected to be relatively low, which may be between 20nm and 50nm, preferably between 25nm and 35nm, or even substantially equal to 30nm. In addition, the bias voltage of the second gate electrode 125 and the voltage applied to the drain region 112 can also be reduced by optimizing the ratio of the width of the channel region to the length of the channel region, preferably, the ratio is greater than 150, or even greater than 250, or even greater than 300.

[0203] According to this eighth possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0204] - applying a source voltage Vs and a gate voltage Vg of zero (0V) to the source region 111 and the first gate electrode 121,

[0205] - A drain voltage Vd and a back gate voltage Vb between 150 mV and 2 V are applied to the drain region 112 and the second gate electrode 125 , and the voltage must be configured according to the thickness of the second gate dielectric layer 135 and the operating current of the transistor.

[0206] Ninth possible implementation method:

[0207] According to the present invention Fig.9A and Fig. 9B In the ninth possible implementation shown in FIG. 3 , the power supply circuit 350 may be arranged to supply power to the source region 111, the first gate electrode 121, and the second gate electrode 125 together, to supply power to the drain region 112 separately, and to form a blocking layer 114 at the position of the first surface of the channel layer 113. In addition, in order to achieve such bias, according to the ninth possible implementation, the detection structure 100 has a “pre-bias” of the blocking layer 114 similar to that described in the third possible implementation, the fourth possible implementation, the seventh possible implementation, and the eighth possible implementation.

[0208] According to the ninth possible implementation, in order to reduce the bias voltage of the second gate electrode 125 to zero, the thickness of the second gate dielectric layer 131 is selected to be relatively low, which may be between 20nm and 50nm, preferably between 25nm and 35nm, or even substantially equal to 30nm. In addition, the bias voltage of the second gate electrode 125 can also be reduced to zero by optimizing the ratio of the width of the channel region to the length of the channel region, preferably, the ratio is greater than 150, or even greater than 250, or even greater than 300.

[0209] According to this ninth possible implementation of the present invention and using the exemplary configuration described in the “Principles of the Invention” section, the power supply circuit 350 may be configured to:

[0210] - applying a source voltage Vs, a gate voltage Vg and a back gate voltage of zero (0V) to the source region 111, the first gate electrode 121 and the second gate 125,

[0211] - Apply a drain voltage Vd typically equal to 200mV.

[0212] The advantage of this ninth possible embodiment is that, when the source region 111, the first gate electrode 121 and the second gate electrode 125 are short-circuited, and the drain region 112 is independent, only two interconnections need to be provided between the detection structure 100 and the power supply circuit 350. In this way, the heat exchange between the detection structure and the power supply circuit 350 is limited, which can reduce the temperature reached by the absorber and thus reduce the sensitivity of the detection component 1.

[0213] Fig. 9B FIG. 1 shows a specific configuration of the detection structure 100 according to the ninth possible embodiment. In the ninth possible embodiment, the detection structure 100 has an optimized ratio of the width of the channel region to the length of the channel region. This optimization is achieved here by a "three-transistor" or "three-tooth comb" configuration (see FIG. 1 ). Fig. 23B , Fig. 23B The double gate or "two-tooth comb" example is shown) to obtain a structure including double the source region 111 and the drain region 112, and triple the channel region. In fact, as Fig. 9B As shown, the detection structure is formed by a continuous portion of a “first” source region 111 , a “first” channel region 113 , a “first” drain region 112 , a “second” channel region 113 , a “second” source region 111 , a “third” channel region 113 and a “second” drain region 112 .

[0214] In the same manner as for the fourth possible embodiment, a person skilled in the art will be able to generalize this configuration and will be able to use a multi-grid or "multi-tooth comb" configuration with any number of grids / teeth, the number of grids or "teeth" being greater than or equal to two.

[0215] In order to illustrate these different possible implementations of the invention, a practical example of the invention is described below.

[0216] First embodiment

[0217] therefore, Fig.10 A first example of the present invention according to a first possible implementation and a second possible implementation of the present invention is shown.

[0218] Therefore, according to this first embodiment, and as in Fig.10 As shown in FIG. 1 , the detection component 1 includes:

[0219] a detection structure 100 in which the second gate electrode 125 forms part of an absorption element,

[0220] a first connecting arm 310, a second connecting arm 320, a third connecting arm 330 and a fourth connecting arm 340, the first connecting arm, the second connecting arm, the third connecting arm and the fourth connecting arm are used to connect the power supply circuit 350 to the source region 111, the drain region 112, the first gate electrode 121 and the second gate electrode respectively,

[0221] a reading substrate 351 in which a supply circuit 350 is at least partially arranged, which in the present embodiment forms a reading circuit for the detection component 350 .

[0222] More specifically, the detection structure 100 includes:

[0223] - a second oxide layer 135,

[0224] a first semiconductor layer 115 in which an active region 111 , a drain region 112 , a channel region 113 and a connection region 126 for a second gate electrode 125 are arranged, the first semiconductor layer 115 being arranged in contact with the second oxide layer 125 ,

[0225] a first oxide layer 131, which according to this first embodiment comprises a layer of silicon dioxide, the first oxide layer 131 being arranged in contact with the first semiconductor layer 115 on a face of the semiconductor layer 115 opposite to the second oxide layer 135, the first oxide layer being positioned opposite to the channel region 113 and the first portion 111a, 112a of each of the source region 111 and the drain region 112,

[0226] a first gate electrode 121 comprising a first conductor layer 122 (for example a layer of titanium nitride TiN) in contact with the first gate oxide layer and a second layer 123 of doped polysilicon pSi,

[0227] a first spacer element and a second spacer element 134, which are arranged on opposite sides of the first gate electrode 121 covering the remaining part of the first oxide layer 131, the remaining part of the first oxide layer not being covered by the first gate electrode,

[0228] a second gate electrode 125 , which covers the second gate dielectric layer 135 on a surface of the second gate dielectric layer 135 opposite to the first semiconductor layer 115 ,

[0229] - optional first stop layer 141, second stop layer 142 and third stop layer 143, for example layers of aluminum oxide Al2O3 or aluminum nitride AlN, the first stop layer, the second stop layer and the third stop layer are arranged to protect the rest of the structure during chemical attack, such as etching operations with hydrofluoric acid in the manufacturing method.

[0230] More particularly, the second gate dielectric layer 135 is a layer of silicon dioxide SiO2, for example a buried oxide layer of a substrate of semiconductor on oxide (semiconducteur sur oxyde, hereinafter abbreviated as SOI) type. The thickness of the second gate dielectric layer 125 is between 10nm and 150nm, or even between 50nm and 100nm, and advantageously between 60nm and 80nm. Typically, the thickness of the second gate dielectric layer can therefore be approximately equal to 70nm. Such a thickness can be provided by a step of thinning the buried oxide layer of the SOI substrate.

[0231] The first semiconductor layer 115 may be a layer of silicon Si from an SOI substrate, the thickness of the layer of silicon Si from an SOI substrate being less than or equal to 100 nm, for example 70 nm. The thickness of the first semiconductor layer may also be less than 50 nm or even substantially equal to 30 nm, which is achieved by a previous step of thinning the first semiconductor layer 115. This step may be performed, for example, by thermally oxidizing the first semiconductor layer 115.

[0232] The source region 111, the drain region 112, and the channel region 113 are arranged in the first semiconductor layer 115. The source region 111 and the drain region 112 are of the first conductivity type, and for the first conductivity type, the majority carriers are electrons. In other words, the source region and the drain region are N-type doped. Each of the source region 111 and the drain region 112 has a relatively weakly doped first portion 111a, 112a and a relatively strongly doped second portion 111b, 112b to facilitate contact. Therefore, the first portion 111a of the source region 111 and the first portion 112a of the drain region may have a concentration of majority carriers of the first conductivity type between 5.10 16 cm -3 to 1.10 18 cm -3 Between, preferably between 1.10 17 cm -3 to 5.10 17 cm -3 In the same manner, the second portion 111b of the source region 111 and the second portion 112b of the drain region 112 may have a concentration of majority carriers of the first conductivity type between 5.10 19 cm -3 to 5.10 20 cm -3 Between, preferably between 1.10 20 cm -3 To 2.10 20 cm -3 between.

[0233] The channel region 113 has a second conductivity type, that is, the channel region is P-type doped, and the concentration of the majority carriers of the second conductivity type is less than 1.10 16 cm -3 , preferably less than 5.10 15 cm -3 Therefore, the concentration of the channel region 113 may be approximately equal to 1.10 15 cm -3 As a variant, the channel region 113 may have an intrinsic doping.

[0234] The first semiconductor layer 115 further comprises an electrically insulating portion of the source region 111, the drain region 112 and the channel region 113. The electrically insulating portion forms a connection region 126 for the second gate electrode 125. The concentration of majority carriers in the electrically insulating portion is preferably greater than 1.10 19 cm -3 , or even greater than 1.10 20 cm -3 , so as to have a reduced resistivity. Preferably, the connecting region is degenerated.

[0235] To facilitate contact, the second portion 111b of the source region 111 and the second portion 112b of the drain region 112 and each connection region 126 may each be arranged with an interface including silicide on the surface opposite to the second gate dielectric layer 135, for example, an interface 111c, 112c, 127 composed of nickel silicide SiNi2.

[0236] Therefore, in the first embodiment, the second portion 111b of the source region 111 and the second portion 112b of the drain region 112 and the connection region 126 are in contact with the first connection arm 310, the second connection arm 320 and the fourth connection arm 340 respectively through their respective interfaces including silicide.

[0237] The channel region 113 and the first portion 111a of the source region 111 and the first portion 112a of the drain region 112 are covered by a first gate oxide layer 131. The first oxide layer is formed of silicon dioxide and has a thickness between 5 nm and 15 nm.

[0238] According to a variation of the first embodiment not shown, the first gate dielectric layer 131 may include a first gate dielectric sublayer formed of silicon dioxide in contact with the channel region 113, and a second gate dielectric sublayer formed of a "dielectric insulator with a high dielectric constant (more broadly referred to as a "high-K" dielectric, such as hafnium dioxide HfO2)", the second sublayer being arranged between the first gate dielectric sublayer and the first conductor layer 122. According to this variation, the thickness of the first gate dielectric sublayer may be between 5nm and 15nm, while the thickness of the second gate dielectric layer may be between 1nm and 5nm, for example, 3nm.

[0239] It should be understood that in the above and the rest of this document, "a dielectric insulator with a high dielectric constant" or, according to the name "high-K" dielectric material commonly used by those skilled in the art, refers to an insulating material with a higher dielectric constant relative to the dielectric constant of silicon dioxide (which is equal to 3.9). Therefore, if the dielectric constant of a dielectric material is greater than or equal to at least 1.5 times, or even 2 to 3 times, the dielectric constant of silicon dioxide, then the dielectric material can be considered to have a high dielectric constant.

[0240] The gate electrode 121 includes a first conductor layer 122 and a second conductor layer 123 .

[0241] Preferably, the first conductor layer 122 is made of a conductor material of the “mid-gap” type for the channel region 113. Preferably, the first conductor layer 122 is made of a conductor material selected from the group consisting of titanium nitride TiN, tantalum nitride TaN and molybdenum silicide MoSi2 for the channel region 113 made of silicon. Advantageously, the first conductor layer 122 is made of titanium nitride TiN for the channel region 113 made of silicon.

[0242] By considering the configuration of the first conductor layer 122 of the gate electrode 121 to improve the absorption capability of the first conductor layer 122 of the gate electrode 121, the first conductor layer 122 and the first gate oxide layer 131 supporting the first conductor layer may be selected to satisfy the following inequality:

[0243] (1)

[0244] Wherein, ρ is the equivalent resistivity of the first gate electrode conductor layer 121, E p is the thickness of the first conductor layer 122 of the first gate electrode 121. It should be noted that, more preferably, ρ / E p is chosen to be close to or even equal to 376.9Ω.

[0245] Therefore, the first conductor layer 122 may be made of titanium nitride TiN and have a thickness between 5 nm and 15 nm, or even substantially equal to 10 nm.

[0246] The second conductor layer 123 may be made of doped polysilicon pSi and have a thickness between 50 nm and 100 nm.

[0247] In order to facilitate contact with the third connection arm 330 , the second conductor layer 123 may have an interface including silicide, for example, an interface 124 composed of nickel silicide SiNi 2 , on the surface opposite to the first conductor layer 121 .

[0248] Therefore, in this first embodiment, the second conductor layer 123 is in contact with the third connection arm through the interface including silicide of the second conductor layer.

[0249] The first gate electrode 121 is extended through a spacer 134 made of a dielectric material (eg, silicon nitride Si 3 N 4 ) to contact the first portion 111 a of the source region 111 and the first portion 112 a of the drain region 112 , respectively.

[0250] like Fig.10 As shown, the following parts are covered by the first stopping layer 141: a portion of the connection region 126, a portion of the second portion 111b of the source region 111, a portion of the second portion 112b of the drain region 112, a side surface of the first gate dielectric layer 131, a portion of the second conductor layer 123 that is not in contact with one of the first connecting arm 310, the second connecting arm 320, the third connecting arm 330 and the fourth connecting arm 340, a portion of the spacer element 134 and the second gate 135 that is not in contact with the first semiconductor layer 115.

[0251] The second gate dielectric layer 135 is in contact with the second gate electrode 125 on the face of the second gate dielectric layer opposite to the first semiconductor layer 115. In the same manner as the first conductor layer 122, preferably, the second gate electrode 125 is made of a conductor material of the "mid-gap" type for the channel region 113, preferably, the second gate electrode 125 is made of a conductor material selected from the group consisting of titanium nitride TiN, tantalum nitride TaN and molybdenum silicide MoSi2 for the channel region 113 made of silicon, advantageously, the first conductor layer 122 is made of titanium nitride TiN for the channel region 113 made of silicon.

[0252] By considering the configuration of the second gate electrode 125 to improve the absorption capability of the second gate electrode, the gate electrode and the second gate oxide layer supporting the gate electrode may be selected to satisfy the following inequality:

[0253] (1)

[0254] Wherein, ρ is the equivalent resistivity of the second gate electrode 125, E p is the thickness of the second gate electrode 125. It should be noted that, more preferably, ρ / E p is chosen to be close to or even equal to 376.9Ω.

[0255] Therefore, the second gate electrode 125 may be made of titanium nitride TiN and have a thickness between 5 nm and 15 nm, or even substantially equal to 10 nm.

[0256] The second gate electrode 125 is covered by the second stopping layer 142 on the surface of the second gate electrode opposite to the second gate dielectric layer 135 .

[0257] As in Fig.10 As shown in FIG. 1 , the first connecting arm 310 , the second connecting arm 320 , the third connecting arm 330 and the fourth connecting arm 340 enable the detection structure to be connected to the power supply circuit 350 while thermally insulating the reading substrate 351 including the power supply circuit 350 .

[0258] Each of the first connecting arm 310, the second connecting arm 320, the third connecting arm 330 and the fourth connecting arm 340 includes:

[0259] - first contact portions 315, 325, 335, 345, which are in electrical contact with the source region 111, the drain region 112, the first gate electrode 121 and the connection region 126, respectively;

[0260] a second insulating portion 314, 324, 334, 344, which consists of a single thin layer or a group of thin layers, which is consistent with the insulating arm taught by document US 16 / 334109, and which enables thermal insulation between the first contact portion 315, 325, 335, 345 and the third bonding portion 313, 323, 333, 343,

[0261] a third bonding portion 313, 323, 333, 343 configured so as to be bondable to a fourth bonding portion 311, 321, 331, 341 of a reading medium 351,

[0262] A fourth bonding portion 311 , 321 , 331 , 341 configured so as to be bondable to the third portion and connected to the power supply circuit 350 .

[0263] Each first contact portion 315, 325, 335, 345 of the connecting arms 310, 320, 330, 340 includes:

[0264] - bodies 315a, 325a, 335a, 345a made of tungsten W,

[0265] a first conductor coating 315b, 325b, 335b, 345b made of titanium nitride TiN, which covers the tungsten body,

[0266] a second conductor coating 315c, 325c, 335c, 345c made of titanium Ti, which covers the first conductor coating 315b, 325b, 335b, 345b,

[0267] The thickness of the first conductor coating 315b, 325b, 335b, 345b and the second conductor coating 315c, 325c, 335c, 345c may be between 30nm and 90nm, preferably approximately equal to 60nm, and between 20nm and 40nm, preferably approximately equal to 30nm, respectively.

[0268] Each second insulation portion 314, 324, 334, 344 comprises:

[0269] - a first reinforcement layer (not shown), the first reinforcement layer is opposite to the second gate dielectric layer 135,

[0270] - a corresponding conductive track (not shown), the conductive track being in contact with the first reinforcement layer on the surface of the first reinforcement layer 312, 322 opposite to the second gate dielectric layer 135,

[0271] - a second reinforcement layer (not shown) which is in contact with the corresponding conductive track on its face opposite to the first reinforcement layer.

[0272] The first conductive track of each second thermal insulation portion 314, 324, 334, 344 is in electrical contact with each of the first connection portion 315, 325, 335, 345 and the third bonding portion 313, 323, 333, 343. The first conductive track of each second thermal insulation portion 314, 324, 334, 344 is connected to the corresponding first connection portion 315, 325, 335, 345 at one of the ends of the first conductive track and is connected to the corresponding third bonding portion 313, 323, 333, 343 at the other end of the first conductive track.

[0273] To provide a thermal insulation function, the second thermal insulation portions 314 , 324 , 334 , 344 may extend in a serpentine configuration within a plane substantially parallel to the plane of the first semiconductor layer 115 .

[0274] Each third contact portion 313, 323, 333, 343 is formed of a material configured to enable molecular bonding with the fourth contact portion 311, 321, 331, 341. Thus, for example, each third contact portion 313, 323, 333, 343 may be made of copper, for example, to enable molecular bonding of a mixed copper / sacrificial material on the copper / sacrificial material. Fig.10 As shown in FIG. 3 , each third keying portion 313 , 323 , 333 , 343 may take the form of a tubular column.

[0275] In the same manner, each fourth bonding portion 311, 321, 331, 341 may be made of the same material as the third bonding portion 313, 323, 333, 343 to enable molecular bonding between the fourth bonding portion and the third bonding portion. Thus, each of the fourth contact portions 313, 323, 333, 343 may be made of copper, for example. Fig.10 Furthermore, each fourth keying portion 311, 321, 331, 344 may take the form of a tubular column having a configuration complementary to the third complementary keying portion.

[0276] It should be noted that by way of illustration and to enable a better understanding of the principle of the assembly used in the context of this embodiment, a molecular bonding interface 312, 322, 332, 342 is shown between the fourth bonding portion 313, 323, 333, 343 and the third bonding portion 311, 321, 331, 341. Of course, according to the molecular bonding principle, such an interface is not shown on the detection device 1.

[0277] Of course, this configuration of the connecting arms is given only by way of example, and other configurations are fully conceivable without departing from the scope of the present invention. It should be noted that, in particular, in a variant not shown, it is conceivable that the detection component according to this first embodiment comprises only three connecting arms, or even only two connecting arms, at least one of the two connecting arms, or even at least one of the three connecting arms, comprises a plurality of connecting tracks so as to be able to connect the source region 111 and the drain region 112 and to connect the first gate electrode 121 and the second gate electrode 125.

[0278] The fourth bonding parts 311, 321, 331, and 341 of the connecting arms 310, 320, 330, and 340 are respectively in contact with the first connection area, the second connection area, the third connection area, and the fourth connection area for powering the power supply circuit 350, and the first connection area, the second connection area, the third connection area, and the fourth connection area are flush with the surface of the reading substrate 351.

[0279] In the present embodiment, the reading substrate 351 is a silicon substrate, and a power supply circuit 350 is arranged in the silicon substrate. In the context of the present embodiment, the power supply circuit is a reading circuit, which is configured to supply power to the detection structure according to at least one of the first possible implementation and the second possible implementation of the present invention. According to a variation of the first possible implementation and the second possible implementation of the present invention, the power supply circuit can also be configured to supply power to the detection structure according to the first possible implementation and the second possible implementation, and the power supply circuit 350 can be controlled to change from one implementation to another, or be configured to change from one implementation to another according to some circumstances.

[0280] It should be noted that according to the method for manufacturing such a detection component 1 described below, the reading substrate 351 can have a third stopper layer 143 on the surface on which the first, second, third and fourth power supply connection areas of the power supply circuit 350 are flush, the third stopper layer covering the portion of the surface that is not in contact with the connection arms 310, 320, 330, 340. The third stopper layer 143 (for example a layer of aluminum oxide Al2O3 or aluminum nitride AlN) is arranged to protect the reading substrate 351 during chemical attack (for example etching with hydrofluoric acid).

[0281] This detection component 1 can be manufactured by the following manufacturing method. The main steps of the manufacturing method are as follows: FIG. 11A to FIG. 11H and consists of three stages:

[0282] - manufacturing a detection support 101 , configured as a first stage for manufacturing a detection structure 100 ,

[0283] - a second stage of manufacturing the reading support 352 , and

[0284] A third stage of assembling the detection support 100 and the reading support 352 to form the detection member 1 .

[0285] The first stage of manufacturing the detection structure 100 includes the following steps:

[0286] - providing an SOI substrate, the SOI substrate comprising: a semiconductor substrate 361; an oxide layer, the oxide layer being configured to form a second gate dielectric layer 135; and a first semiconductor layer 115, the first semiconductor layer 115 having a concentration of majority carriers of a second conductivity type channel region 113, as in Fig.11A It is shown in

[0287] - optionally, thinning the first semiconductor layer 115, for example by means of thermal oxidation and etching of said thermal oxide,

[0288] - Partially etching the first semiconductor layer 115 to retain a portion of the first semiconductor layer 115 configured to form the connection region 126 and the source region 111, the drain region 112, and the channel region 113, as in Fig. 11B It is shown in

[0289] - thermally oxidizing the semiconductor layer 115 to form a first gate dielectric layer 131,

[0290] - continuously depositing a first conductor layer 122 and a second conductor layer 123, wherein the first conductor layer contacts the first gate dielectric layer 131, and the second conductor layer contacts the first conductor layer 122, and after the deposition step, a local etching step is performed to form a first gate electrode 121 opposite to the channel region 113,

[0291] - implanting a doping element of the first conductivity type into the portion of the semiconductor layer 115 corresponding to the source region 111, the drain region 112 and the connection region 126, the channel region 113 is protected by the first gate electrode 121, thereby forming a first portion 111a of the source region 111 and a first portion 112a of the drain region,

[0292] - locally depositing a spacer element 134 in line with the first gate electrode 121 and opposite to the first portion 111a of the source region 111 and the first portion 112a of the drain region 112, respectively,

[0293] - additionally implanting a doping element of the first conductivity type in a portion of the semiconductor layer 115 corresponding to the second portion 111 b of the source region 111 and the second portion 112 b of the drain region 112 and at the connection region 126, the channel region 113 and the first portion 111 a of the source region 111 and the first portion 112 b of the drain region 112 being protected by the first gate electrode 121 and the spacer element 134,

[0294] - Performing an activation thermal annealing, for example a thermal annealing under nitrogen, to activate and diffuse the doping elements implanted in the source region 111, the drain region 112 and the connection region 126, said annealing being a type commonly referred to by those skilled in the art as "rapid thermal annealing" of between 1s and 15s.

[0295] - Forming corresponding interfaces 124, 111c, 112c, 127, which include silicides that are in contact with the first gate electrode 121, the second part of the source region 111, the second part of the drain region and the connection region 126, respectively, these interfaces are formed by the deposition of nickel or titanium and annealing of the type commonly referred to by those skilled in the art as "rapid thermal process".

[0296] - depositing a first stopping layer 141, the first stopping layer being in contact with the connection region 126, the second portion 111b of the source region 111, the second portion 112b of the drain region 112, the side surface of the first gate dielectric layer 131, the second conductor layer 123, the spacer element 134 and the second gate dielectric layer 135,

[0297] - Depositing a layer 371 of sacrificial material (eg silicon dioxide) to cover the assembly formed by the first semiconductor layer 115, the first gate dielectric layer 131, the first gate electrode 121 and the stop layer 141, as in Fig. 11C It is shown in

[0298] - planarizing the layer 37 of sacrificial material;

[0299] - locally etching the layer 371 of sacrificial material to form respective openings corresponding to the first portion 315 of the first connecting arm 310, the first portion 325 of the second connecting arm 320, the first portion 335 of the third connecting arm 330 and the first portion 345 of the fourth connecting arm 340, the openings leading to the first stopper portions opposite the second portion 111 b of the source region 111, the second portion 112 b of the drain region 112, the first gate electrode 121 and the connection region 126, respectively,

[0300] - etching the portion of the first stop layer 371 which is free of sacrificial material,

[0301] depositing a layer of titanium Ti through the opening formed in the layer of sacrificial material to form a second conductor coating 315c, 325c, 335c, 345c composed of titanium Ti for each of the first connecting portion of the first connecting arm 310, the first connecting portion of the second connecting arm 320, the first connecting portion of the third connecting arm 330, and the first connecting portion of the fourth connecting arm 340,

[0302] - depositing a layer of titanium nitride TiN through the opening formed in the layer of sacrificial material, the layer of titanium nitride TiN being in contact with the second conductor coating 315c, 325c, 335c, 345c composed of titanium Ti to form a first conductor coating 315b, 325b, 335b, 345b composed of titanium nitride for each of the first connecting portion of the first connecting arm 310, the first connecting portion of the second connecting arm 320, the first connecting portion of the third connecting arm 330, and the first connecting portion of the fourth connecting arm 340,

[0303] - filling the opening formed in the layer 371 of sacrificial material with tungsten W to form a body 315a, 325a, 335a, 345a of tungsten in each of the first connecting arm 310, the second connecting arm 320, the third connecting arm 330 and the fourth connecting arm 340,

[0304] - Planarizing the titanium, titanium nitride, tungsten and sacrificial material layers 371 to remove excess titanium, titanium nitride and tungsten layers, as in Fig.11D It is shown in

[0305] - forming the second heat-insulating parts 314, 324, 334, 344 of the connecting arms 310, 320, 330, 340 according to the teaching of document US 16 / 334109,

[0306] - depositing an additional layer 371 of sacrificial material, the additional layer of sacrificial material being in contact with the layer 371 of sacrificial material and the second thermal insulation portion 314 , 324 , 334 , 344 ,

[0307] - locally etching the layer 371 of sacrificial material to form respective openings corresponding to the third bonding portions 313, 323, 333, 343 of each of the first connecting arm 310, the second connecting arm 320, the third connecting arm 330 and the fourth connecting arm 340,

[0308] - filling the opening formed in the layer 371 of additional sacrificial material by a conductor coating composed of titanium nitride TiN (not shown in the drawings and conventional to a person skilled in the art) and copper Cu to form the third bonding portion 313, 323, 333, 343 of each of the first connecting arm 310, the second connecting arm 320, the third connecting arm 330 and the fourth connecting arm 340,

[0309] - Planarizing the layer of titanium nitride, the layer of copper and the layer of additional sacrificial material 371 to remove excess copper and titanium nitride, thereby forming the detection support 101, as in Fig.11E Shown in.

[0310] The second stage of manufacturing the reading support 352 may include the following steps:

[0311] - providing a first reading substrate 351, in which a power supply circuit 350 is arranged, and the power supply circuit 350 includes a first power supply connection area, a second power supply connection area, a third power supply connection area, and a fourth power supply connection area (not shown) on the first surface of the first reading support portion 351, and the first power supply connection area, the second power supply connection area, the third power supply connection area, and the fourth power supply connection area correspond to the source region 111, the drain region 112, and the first gate electrode 121 and the second gate electrode 125, respectively,

[0312] - depositing a third stop layer 143 (a layer of Al2O3 or AlN), the third stop layer being in contact with the first face of the reading support 351,

[0313] - depositing a layer 372 of sacrificial material, the layer of sacrificial material being in contact with the third stopping layer 143,

[0314] - locally etching the layer of sacrificial material and the third stop layer 143 to form a first opening, a second opening, a third opening and a fourth opening in the layer of sacrificial material 372, the openings leading to the first power supply connection area, the second power supply connection area, the third power supply connection area and the fourth power supply connection area, respectively,

[0315] - filling the first opening, the second opening, the third opening, and the fourth opening with a conductor coating (not shown) made of titanium nitride TiN and copper Cu to form the fourth portion 311 of the first connecting arm 310, the fourth portion 321 of the second connecting arm 320, the fourth portion 331 of the third connecting arm 330, and the fourth portion 341 of the fourth connecting arm 340,

[0316] - Planarizing the layer of sacrificial material to remove excess titanium nitride and copper to form the read support 352, as in Fig.11F Shown in.

[0317] The third stage of assembling the detection structure with the reading substrate includes the following steps:

[0318] - When assembling the face of the detection support 101 with the face of the reading support 352, the detection support 101 is bonded to the reading support 352 by molecular bonding of the mixed copper / copper and sacrificial material / sacrificial material, the face of the detection support including the third detection portion 313, 323, 333, 343 of the connecting arms 310, 320, 330, 340, and the face of the reading support including the fourth detection portion 312, 322, 332, 342 of the connecting arms 310, 320, 330, 340, as in Fig.11G Shown in.

[0319] - removing the semiconductor substrate 361,

[0320] - Optionally, partially etching the second gate dielectric layer 135 to reduce the thickness of the second gate dielectric layer 135,

[0321] - forming an opening in the second gate dielectric layer 135, the opening leading to the connection region 126,

[0322] - depositing a layer of titanium nitride TiN to form a second gate electrode 125 in contact with the second gate dielectric layer 135,

[0323] - performing local etching at the periphery of the detection structure 100, the periphery of the second gate electrode 125 and the periphery of the second gate dielectric layer 135, and stopping the etching on the first stop layer,

[0324] - Deposition of a second stop layer 142, such as in Fig.11H It is shown in

[0325] - optionally, in particular in the case of collective production of detectors, for example in the form of an array, the detection structure 100 is individualized by local etching at the periphery of the detection structure, at the periphery of the second stop layer 142 and at the periphery of the first stop layer 141, the etching being stopped at the layer 371 of sacrificial material,

[0326] - forming the detection component 1 by removing the sacrificial materials 371 , 372 by selective etching, in particular by placing the assembly of the detection support 101 / reading support 252 in contact with hydrofluoric acid in the gas phase, as in Fig.10 Shown in.

[0327] Second embodiment

[0328] Fig.12 An electromagnetic radiation detecting component 1 according to a second example of a third possible implementation of the present invention is shown.

[0329] Therefore, according to a third possible implementation of the present invention, the difference between the detection component 1 according to the second embodiment and the detection component 1 according to the first embodiment is that the source region 111 and the first gate electrode 121 are short-circuited, the source region and the first gate electrode share a first connecting arm 310, the first connecting arm has a partition portion to apply the same bias to the source region and the first gate electrode in parallel, the first gate dielectric layer 131 has a dipole interface, and the power supply circuit 350 enables power to be supplied to the detection structure 1 according to the third possible implementation of the present invention.

[0330] Therefore, if Fig.12 , in order to enable the dipole interface to be formed in this way, the first gate dielectric layer 131 includes a first sublayer 132 and a second sublayer 133 respectively composed of a first dielectric material and a second dielectric material, and the first sublayer and the second sublayer can form a dipole interface together by generating an electrostatic dipole between the first sublayer and the second sublayer. In this second embodiment, the first sublayer 132 is a layer of silicon dioxide, and the second sublayer 133 is made of aluminum oxide Al2O3, the first sublayer is a layer covering the channel region 113 and the first part 111a of the source region 111 and the first part 112a of the drain region 112, and the second sublayer is arranged between the first sublayer 132 and the gate electrode.

[0331] The thickness of the first sub-layer 132 may be between 5 nm and 15 nm, and the thickness of the second sub-layer 133 may be between 3 nm and 15 nm.

[0332] Similarly, as in Fig.12 As shown in FIG. 1 , the first connection arm 310 has a double fifth connection portion 315 , one fifth connection portion extending between the second insulation portion 314 and the first connection gate 121 , and the other fifth connection portion extending between the second insulation portion 314 and the second portion 111 b of the source region 111 .

[0333] Therefore, the detection component only includes the first connecting arm 310, the second connecting arm 320 and the fourth connecting arm 340, and the connecting circuit 350 only includes the first power supply connection area, the second power supply connection area and the third power supply connection area connected to the first connecting arm 310, the second connecting arm 320 and the fourth connecting arm 310, 320, 340.

[0334] The method for manufacturing the detection component 1 according to the second manufacturing method is different from the manufacturing method according to the first embodiment in that:

[0335] - a step of thermally oxidizing the semiconductor layer 115 so as to form the first sublayer 132 of the first gate dielectric layer 131,

[0336] - providing an additional step of locally depositing the second sub-layer 133 in contact with the first sub-layer 132 between the step of thermally oxidizing the semiconductor layer 115 and the step of continuously and locally depositing the first conductor layer 122 and the second conductor layer 123,

[0337] - In the step of forming the third heat insulating parts 314, 324, 344 of the connecting arms 310, 320, 340 according to the teaching of document US16 / 334109, only the first heat insulating part 314, the second heat insulating part 324 and the third heat insulating part 344 are formed, as in Fig.12 and Fig.13A It is shown in

[0338] - in the step of providing the reading substrate, the power supply circuit 351 includes only the first power supply area and the third power supply area, and the power supply circuit is a power supply circuit according to a third possible embodiment of the present invention,

[0339] - In the steps related to manufacturing the fourth bonding portion and the third bonding portion 311, 321, 331, 322, 322, 332 of the connecting arms 310, 320, 340, only the first bonding portion, the second bonding portion, the fourth bonding portion and the third bonding portion 311, 321, 331, 322, 322, 332 are manufactured, as in Fig. 13B Shown in.

[0340] Fig.14 A detection device 1 according to a variation of the second embodiment is shown, in which the detection structure 100 includes overdoping a portion 116 of the channel region configured to form a barrier layer 114 with a doping element of the second conductivity type without including a dipole interface, i.e., in this embodiment, the electron acceptor doping element is, for example, boron atoms or indium atoms obtained by ion implantation of boron B ions, boron fluoride BF2 ions or indium In ions,

[0341] Therefore, according to this variant, this detection device 1 differs from the detection device 1 according to the second embodiment in that:

[0342] - the first gate dielectric layer 131 comprises a single dielectric layer, which in this variant comprises silicon dioxide according to the teaching of the first embodiment,

[0343] The channel region 113 includes a portion 116 which is configured to form the barrier layer 114 and has an overdoping of an electron acceptor element, for example, about 1.10 19 cm -3 of overdoping.

[0344] Therefore, the method for manufacturing a detection device according to this variation of the second embodiment differs from the method for manufacturing a device according to the second embodiment in that:

[0345] - before the step of oxidizing the first semiconductor layer 115 to form the first gate dielectric layer 131, an additional step of forming a layer of sacrificial oxide, implanting the channel region 113 with a doping element of the second conductivity type over a portion of the depth of the channel region 113, and removing the layer of sacrificial oxide is provided, the step of activating thermal annealing also making it possible to activate the doping element of the second conductivity type, which is implanted in the portion of the channel region 113 configured to form a barrier layer, such as in Fig.15A It is shown in

[0346] No additional step of locally depositing the second sub-layer 133 , which is in contact with the first sub-layer 132 , is provided.

[0347] Therefore, in this variation of the second embodiment, according to the second embodiment, the first thermally insulating arm is arranged so that a voltage supply can be provided to the source region 111 and the first gate electrode 121, as in Fig. 15B The manufacturing of the component is shown just before the step of selectively etching the sacrificial material.

[0348] Fig. 15C The principle of local implantation which can be implemented in this variant of the second embodiment is illustrated using a graph. In fact, the graph shows the local implantation of boron fluoride ions BF2 + Implanted through a 10 nm thick layer of silicon dioxide with an implant dose of 1.10 15 cm -2 , the implantation energy is 3keV, the first layer of silicon is 67nm, and the simulation results of activation thermal annealing at 1050℃ for 1s.

[0349] In the graph showing the change in the concentration of the doping element Cd according to the depth obtained by such a step, it can be seen that the portion 116 configured to form the barrier layer 114, which is capable of forming the channel region 113, has a concentration of majority carriers of the second conductivity type of about 10 at a thickness of 20 nm. 19 cm -3 , the rest of the layer has a concentration of majority carriers of the second conductivity type approaching 10 15 cm -3 It should be noted that, according to the manufacturing method, the portion 116 also extends in the first portion 111 a of the source region 111 and in the first portion 112 a of the drain region 112 .

[0350] Therefore, according to this variant of the second embodiment, in an additional step of local implantation of the channel region, boron fluoride ions BF2 can be implemented. +The injection dose is between 1.10 14 cm -2 to 1.10 15 cm -2 and the implantation energy is between 3keV and 8keV.

[0351] Third embodiment

[0352] Fig.16A and Fig. 16B The electromagnetic radiation detection component 1 according to the third embodiment of the fourth possible implementation of the present invention is shown, and the electromagnetic radiation detection component is in the following configuration: in this configuration, the detection structure has a similar Figure 4B The principle is to optimize the ratio of the width of the channel region to the length of the channel region.

[0353] The difference between the detection component 1 according to the third embodiment and the detection component according to the second embodiment is that:

[0354] - providing an overdoping of a portion 116 of the channel region 113 configured for forming a barrier layer 114 according to a variant of the second embodiment,

[0355] - The second gate electrode 125 is short-circuited with the drain region 112, as in Fig.16A and Fig. 16B As shown in FIG. 1 , in the present embodiment, such a configuration is provided by replacing the connection region 126 with the drain region 112, so the detection structure 100 does not have such a connection region 126.

[0356] - The source region 111 and the channel region 113 are doubled into two source sub-regions and two channel sub-regions, respectively, and the source sub-region and the channel sub-region are arranged on opposite sides of the drain region to form a double transistor. According to the doubling of the channel region 113, the first gate electrode 121 is also doubled, as shown in Fig.16A and Fig. 16B As shown in

[0357] A power supply circuit 350 makes it possible to supply power to the detection structure 1 according to a fourth possible embodiment of the invention.

[0358] It should be noted that in the third embodiment, according to the manufacturing method, the overdoped portion 116 also extends in the first portion 111 a of the source region 111 and the first portion 112 a of the drain region 112 .

[0359] It can thus be seen that in this third embodiment, in a similar manner to the variant of the second embodiment, the channel region 113 has an overdoping of a doping element of the second conductivity type in a portion 116 of the channel region 113 configured to form the barrier layer 114, for example, about 1.10 nm at a thickness of 20 nm. 19 cm-3 of overdoping.

[0360] Similarly, as in Fig.16A As shown in the figure, in order to optimize the ratio of the width of the channel region to the length of the channel region, the detection structure has a central drain region 112, a first source sub-region and a channel sub-region component on one side of the central drain region, and a second source sub-region and a channel sub-region component on the other side of the central drain region.

[0361] exist Fig.16A and Fig. 16B It can also be seen that in this embodiment, in a manner similar to the second embodiment, the first connecting arm 310 has four times the first connecting portion 315 so as to be able to connect each source sub-region in the source sub-region 111 and each gate sub-electrode in the gate sub-electrode 121, and the second thermal insulation portion 314 extends over the entire width of the detection structure 100, and even extends beyond the entire width so as to be able to connect all elements of the first connecting portion 315 that is four times the first connecting arm 310.

[0362] The method for manufacturing the detection component 1 according to the third embodiment differs from the method for manufacturing the detection component 1 according to the second embodiment in that:

[0363] - in the step of locally etching the first semiconductor layer 115, the etching is performed so as to retain a portion of the first semiconductor layer 115 configured to form the source sub-region 111 and the channel sub-region 113 and the central drain region 112, which portion does not have any such connection region, because the connection region used as the second gate electrode 121 is the drain region 112,

[0364] - before the step of oxidizing the first semiconductor layer 115 to form the first gate dielectric layer 131, an additional step of forming a layer of sacrificial oxide, locally implanting the channel region 113 with a doping element of the second conductivity type over a portion of the depth of the channel region 113, and removing the layer of sacrificial oxide is provided, the step of activating thermal annealing also making it possible to activate the doping element of the second conductivity type, the doping element of the second conductivity type being implanted in the barrier layer,

[0365] - In the step of locally etching the layer 371 of sacrificial material to form respective openings corresponding to the first portions 315, 325 of each connecting arm 310, 320, four openings for the first connecting portion 315 of the first connecting arm 310 and a single opening for the first connecting portion 325 of the second connecting arm 320 are provided, the four openings leading to each of the source sub-region 111 and the sub-first gate electrode 121, respectively, the single opening corresponding to the drain region 112, so that the second gate electrode 125 contacts the drain region 112 through the opening 313 passing through the second oxide layer 135, the two openings on the drain region being provided at Fig.16A In the case of overlap, Fig. 16B In the case of offset,

[0366] - in the step of forming the second heat insulating portions 314, 324 of the connecting arms 310, 320 according to the teaching of document US 16 / 334109, only the first heat insulating portion 314 and the second heat insulating portion 324 are formed, the second heat insulating portion 314 of the first connecting arm 310 being in contact with each of the elements of the first connecting portion 315 of the connecting arm 310,

[0367] - in the step of providing the reading substrate, the power supply circuit comprises only the first power supply region and the second power supply region, and the power supply circuit is a power supply circuit according to a fourth possible embodiment of the present invention,

[0368] In the steps related to manufacturing the fourth and third bonding portions 311 , 321 , 322 , 322 of the connecting arms 310 , 320 , only the fourth and third bonding portions 311 , 321 , 322 , 322 of the first and second connecting arms 310 , 320 are manufactured.

[0369] Of course, this third embodiment is provided in particular to illustrate the possibility of optimizing the ratio of the width / length of the channel region by providing a transistor with a channel multi-region or multi-gate or, for example, a transistor with a "multi-tooth comb" gate in the context of the present invention, in this embodiment, the structure has two channel sub-regions 113 and double the gate electrode. According to the same principle and as already described in Figure 4B As shown in FIG. 1 , without departing from the scope of the present invention, it is well conceivable to provide a detection component 1 having a plurality of channel sub-regions 113 and a gate, the number of channel sub-regions 113 being greater than 2 ( Figure 4B ), for example, 3, or even 4, or even 7, the number of grids is greater than 2. This configuration is also called a "multi-tooth comb" grid.

[0370] Fourth embodiment

[0371] Fig.17A detection device 1 according to a fourth embodiment of a fifth possible implementation and a sixth possible implementation of the present invention is shown.

[0372] Therefore, the detection device 1 according to the fourth embodiment differs from the detection device 1 according to the first embodiment in that the channel region has a first conductivity type, that is, in this fourth embodiment, the channel region is N-type doped, and the power supply circuit is constructed to supply power to the detection structure 100 according to one of the fifth possible implementation and the sixth possible implementation of the present invention.

[0373] The method for manufacturing the detection device 1 according to the fourth embodiment differs from the method for manufacturing the detection device 1 according to the first embodiment in that:

[0374] - in the step of providing an SOI substrate including a semiconductor substrate 361, a layer configured to form an oxide of the second gate dielectric layer 135, and a first semiconductor layer 115, the first semiconductor layer has a first conductivity type, and

[0375] - In the step of providing the first reading substrate 351, the power supply circuit is the power supply circuit according to the fifth possible embodiment or the sixth possible embodiment.

[0376] Of course, according to the first embodiment, as a variation, the power supply circuit can also be configured to supply power to the detection structure according to the fifth possible implementation and the sixth possible implementation, and the power supply circuit 350 can be controlled to transition from one implementation to another or be configured to transition from one implementation to another according to some circumstances.

[0377] Fifth embodiment

[0378] Fig.18 Components of a fifth embodiment according to a seventh possible implementation of the present invention are shown.

[0379] Therefore, the detection device 1 according to the fifth embodiment differs from the detection device 1 according to the second embodiment in that the channel region has a first conductivity type, that is, in this fourth embodiment, the channel region is N-type doped, and the power supply circuit is configured to supply power to the detection structure 100 according to the seventh possible implementation of the present invention.

[0380] The method for manufacturing the detection device 1 according to the fifth embodiment differs from the method for manufacturing the detection device 1 according to the second embodiment in that:

[0381] - in the step of providing an SOI substrate including a semiconductor substrate 361, a layer configured to form an oxide of the second gate dielectric layer 135, and a first semiconductor layer 115, the first semiconductor layer has the same conductivity type, and

[0382] - In the step of providing the first reading substrate 351, the power supply circuit is a power supply circuit according to the seventh possible implementation.

[0383] In particular, it should be noted that according to the second embodiment and as in Fig.19A , in order to enable the dipole interface to be formed in this way, the first gate dielectric layer 131 includes a first sublayer 132 and a second sublayer 133 respectively composed of a first dielectric material and a second dielectric material, and the first sublayer and the second sublayer can form a dipole interface together by generating an electrostatic dipole between the first sublayer and the second sublayer. In the fifth embodiment, the first sublayer 132 is a layer of silicon dioxide, and the second sublayer 133 is made of aluminum oxide Al2O3, the first sublayer is a layer covering the channel region 113 and the first part 111a of the source region 111 and the first part 112a of the drain region 112, and the second sublayer is arranged between the first sublayer 132 and the gate electrode.

[0384] In addition, if Fig.19B As shown, in this fifth embodiment, the detection component 1 only includes the second thermal insulation portion 314 of the first connecting arm 310, the second thermal insulation portion 324 of the second connecting arm 320 and the second thermal insulation portion 344 of the fourth connecting arm 340. The second thermal insulation portion of the first connecting arm, the second thermal insulation portion of the second connecting arm and the second thermal insulation portion of the fourth connecting arm are formed so that the second thermal insulation portion 314 of the first connecting arm 310 can be connected to the double first connecting portion of the first connecting arm 310.

[0385] Fig. 20 Components of a modification of the fifth embodiment according to a modification of a seventh possible implementation of the present invention are shown.

[0386] Therefore, the difference between the detection device 1 according to this variant of the fifth embodiment and the detection device 1 according to the variant of the second embodiment is that the channel region has a first conductivity type, that is, in this variant of the fifth embodiment, the channel region is N-type doped, and the power supply circuit is constructed to supply power to the detection structure 100 according to the seventh possible implementation of the present invention.

[0387] The method for manufacturing the detection device 1 according to the fifth embodiment differs from the method for manufacturing the detection device 1 according to the second embodiment in that:

[0388] - in the step of providing an SOI substrate including a semiconductor substrate 361, a layer configured to form an oxide of the second gate dielectric layer 135, and a first semiconductor layer 115, the first semiconductor layer has the same conductivity type, and

[0389] - In the step of providing the first reading substrate 351, the power supply circuit is a power supply circuit according to the seventh possible embodiment of the present invention.

[0390] According to the case of the modification of the second embodiment Fig. 15C The principle has been proposed that the detection component forming the barrier layer by overdoping the portion of the channel region 113 configured to form the barrier layer can be formed by implanting boron fluoride ions BF2 + or indium In ions, with an implantation dose between 1.10 14 cm -2 to 1.10 15 cm -2 and the implant energy is between 3keV and 8keV, such as Fig.21A Shown in.

[0391] Furthermore, according to this modification and according to the fifth embodiment, the detection component 1 only includes the second heat insulating portion 314 of the first connecting arm 310, the second heat insulating portion 324 of the second connecting arm 320, and the second heat insulating portion 344 of the fourth connecting arm 340. Fig.21B As shown in FIG. 1 , the second heat insulating portion 314 enables connecting the double first connection portion of the first connection arm 310 , thereby connecting the source region 111 and the first gate electrode 121 .

[0392] Sixth embodiment

[0393] Fig. 22 A detection component 1 according to a sixth embodiment of an eighth possible implementation of the present invention is shown.

[0394] Therefore, the difference between the detection device 1 according to the sixth embodiment and the detection device 1 according to the third embodiment is that the channel region 113 has a first conductivity type, that is, in this fourth embodiment, the channel region is N-type doped, and the power supply circuit is constructed to supply power to the detection structure 100 according to the eighth possible implementation of the present invention.

[0395] Therefore, if Fig. 22 As shown, in the sixth embodiment, the first connection portion is quadrupled to supply voltage to two source sub-regions 111 and two sub-first gate electrodes 121. As for the second gate electrode 125, power supply to the second gate electrode is provided through the drain region 112.

[0396] The method for manufacturing the detection device 1 according to the sixth embodiment differs from the method for manufacturing the detection device 1 according to the second embodiment in that:

[0397] - in the step of providing an SOI substrate including a semiconductor substrate 361, a layer configured to form an oxide of the second gate dielectric layer 135, and a first semiconductor layer 115, the first semiconductor layer has the same conductivity type, and

[0398] - In the step of providing the first reading substrate 351, the power supply circuit is a power supply circuit according to an eighth possible embodiment of the present invention.

[0399] Seventh embodiment

[0400] Fig.23A and Fig. 23B A detection component 1 according to a seventh embodiment of a ninth possible implementation of the present invention is shown.

[0401] Therefore, the detection device 1 according to the seventh embodiment differs from the detection device 1 according to the sixth embodiment in that the source sub-region 111, the first gate electrode 121 and the second gate electrode 122 are short-circuited, and the power supply circuit is configured to supply power to the detection structure 100 according to the ninth possible implementation of the present invention.

[0402] In this seventh embodiment, in the same manner as the sixth embodiment, in order to optimize the ratio of the width of the channel region to the length of the channel region, the detection structure has a central drain region 112, an assembly of a first source sub-region and a channel sub-region on one side of the central drain region, and an assembly of a second source sub-region and a channel sub-region on the other side of the central drain region.

[0403] The first connection arm 310 has four times the first connection portion 315 to enable connection between each of the source sub-regions 111 and each of the sub-first gate electrodes 121. The second gate electrode 125 partially extends in the opening of the second gate dielectric layer 135, which contacts one of the source sub-regions 111, thereby forming a connection region for the second gate electrode 125.

[0404] The method for manufacturing the detection component 1 according to the seventh embodiment is different from the method for manufacturing the detection component 1 according to the sixth embodiment in that:

[0405] - performing an additional implantation step on the portion 116 of the layer 115, so that the portion 116 of each of the two channel sub-regions 113 configured to form the barrier layer 114 has said overdoping, as in Fig.24A It is shown in

[0406] - In the step of locally etching the layer 371 of sacrificial material to form respective openings corresponding to the first portions 315, 325 of each connecting arm 310, 320, four openings for the first connecting portion 315 of the first connecting arm 310 and a single opening for the first connecting portion 325 of the second connecting arm 320 are provided, the four openings leading to each of the source sub-regions 111 and each of the sub-first gate electrodes 121, respectively, and the single opening leading to the drain region 112, as in Fig. 23B and Fig. 24B Shown in.

[0407] - The following steps are provided: forming an opening in the second gate dielectric layer 135 so that the second gate electrode 125 can be in contact with one of the source sub-regions 111, and forming a single opening for the first connection portion 325 of the second connection arm 320 leading to the drain region 112, such as in Fig. 24B It is shown in

[0408] In the step of forming the second heat insulating portions 314, 324 of the connecting arms 310, 320 according to the teaching of document US16 / 334109, only the second heat insulating portion 314 of the first connecting arm 310 and the second heat insulating portion 324 of the second connecting arm 320 are formed, and the second heat insulating portion 314 of the first connecting arm 310 is in contact with each element of the first connecting portion 315 of the first connecting arm 310, as in Fig.24C It is shown in

[0409] In the step of providing the reading substrate 351 , the power supply circuit 350 includes only the first power supply region and the second power supply region, and the power supply circuit is the power supply circuit according to the ninth possible embodiment of the present invention.

[0410] In particular, in the same way as the third and sixth embodiments, this seventh embodiment is provided in order to illustrate the possibility of optimizing the ratio of the width of the channel region to the length of the channel region in the context of the present invention by providing a transistor with a channel multi-region or a multi-gate or, for example, a transistor with a "multi-tooth comb" gate, in this embodiment, the structure has two channel sub-regions 113. According to the same principle and as already described in Fig. 9B As shown in FIG. 1 , without departing from the scope of the present invention, it is well conceivable to provide a detection component 1 having a plurality of channel sub-regions 113 and a gate, the number of channel sub-regions 113 being greater than 2, for example, 3 (as in FIG. 1 ). Fig. 9B ), or even 4, or even 7, the number of grids is greater than 2. This configuration is also called a "multi-tooth comb" grid.

[0411] Of course, although in the present possible implementations, embodiments and variants of the embodiments of the present invention, it has been chosen to describe a detection structure as follows: the first conductivity type of the detection structure is a conductivity type in which electrons are the majority carriers, in other words, the first conductivity type of the detection structure corresponds to N-type doping, it is also well conceivable that the first conductivity type is a conductivity type in which holes are the majority carriers, in other words, the first conductivity type constitutes P-type doping without departing from the scope of the present invention. In fact, a person skilled in the art will be able to infer the current teaching of this equivalent configuration only from routine testing.

[0412] In addition, although in the second, third, fifth, sixth and seventh embodiments, the "pre-bias" provided by the electrostatic dipole or overdoping is used to form a blocking layer at the position of the first surface of the channel region, without departing from the scope of the present invention, it is of course also conceivable to use such "pre-bias" to form a blocking layer at the position of the second surface of the channel region.

Claims

1. A component (1) for detecting electromagnetic radiation (λ), the component comprising a detection structure (100) and a power supply circuit (350) for the detection structure (100), The detection structure (100) comprises: - at least one absorption element, said at least one absorption element being configured to absorb said electromagnetic radiation, - a transistor associated with the absorption element, the transistor being used to detect a rise in the temperature of the absorption element when the electromagnetic radiation (λ) is absorbed, the transistor comprising: o at least one first semiconductor region (111) and at least one second semiconductor region (112), the first semiconductor region being referred to as a source region and the second semiconductor region being referred to as a drain region, the at least one first semiconductor region and the at least one second semiconductor region each having a first conductivity type, o at least one third semiconductor region (113), the third semiconductor region being referred to as a channel region, the at least one third semiconductor region separating the source region and the drain region from each other, the at least one third semiconductor region having a first surface and a second surface, the first surface and the second surface being opposite surfaces, the first surface and the second surface extending between the source region and the drain region, a first gate electrode (121), the first gate electrode being arranged opposite to the first surface of the channel region so as to bias the channel region, the first gate electrode (121) being separated from the channel region by a first gate dielectric layer (131), a second gate electrode (125), the second gate electrode being arranged opposite to the second surface of the channel region so as to bias the channel region, the second gate electrode (125) being separated from the channel region by a second gate dielectric layer (135), wherein the power supply circuit (350) is configured to supply power to each of the source region, the drain region, the first gate electrode (121) and the second gate electrode (125) of the detection structure (100), The power supply circuit (350) is configured to supply power to the detection structure (100) during operation, so that the channel region has a layer (114) at a position on one of the first surface and the second surface, in which carriers of a second conductivity type opposite to the first conductivity type are dominant, and the layer (114) is called a blocking layer.

2. The component (1) according to claim 1, wherein The thickness of the second gate dielectric layer (135) is between 10 nm and 150 nm.

3. The component (1) according to claim 1, wherein At least one of the first gate dielectric layer (131) and the second gate dielectric layer (135) comprises a first sublayer and a second sublayer respectively formed of a first dielectric material and a second dielectric material, and the first sublayer and the second sublayer are capable of forming an electrostatic dipole between the first sublayer and the second sublayer.

4. The component (1) according to claim 1, wherein The channel region includes a doping element having a concentration greater than that of the remaining portion of the channel region in a portion (116) arranged to form the barrier layer.

5. The component (1) according to claim 3, wherein The source region and the first gate electrode (121) are short-circuited.

6. A component (1) according to claim 5, wherein The drain region and the second gate electrode (125) are short-circuited.

7. The component according to claim 5, wherein: The channel region has the first conductivity type, the barrier layer is an inversion layer, and wherein the second gate electrode (125) is short-circuited with the first gate electrode (121) and with the source region.

8. A component (1) according to any one of claims 1 to 6, wherein: The channel region has the second conductivity type, and the barrier layer is an accumulation layer.

9. A component (1) according to any one of claims 1 to 6, wherein: The channel region has the first conductivity type, and the barrier layer is an inversion layer.

10. The component (1) according to claim 1, wherein The absorption element comprises at least one of the following: - at least one portion of the first gate electrode (121), - at least one portion of the second gate electrode (125), and - at least one conductive track connecting the detection structure (100) and the power supply circuit (350).

11. The component (1) according to claim 2, wherein The thickness of the second gate dielectric layer (135) is between 30 nm and 70 nm.

12. The component (1) according to claim 3, wherein The first dielectric material and the second dielectric material are silicon dioxide and aluminum oxide, respectively.

13. A method for producing a component (1) for detecting electromagnetic radiation, the method comprising the following steps: - providing a detection structure (100), the detection structure (100) comprising: o at least one absorbing element, the at least one absorbing element being configured to absorb the electromagnetic radiation, o a transistor associated with the absorbing element, the transistor being configured to detect a rise in temperature of the absorbing element when the electromagnetic radiation is absorbed, the transistor comprising: ■ at least one first semiconductor region (111) and at least one second semiconductor region (112), the first semiconductor region being referred to as a source region and the second semiconductor region being referred to as a drain region, the at least one first semiconductor region and the at least one second semiconductor region having a first conductivity type, ■ at least one third semiconductor region (113), the third semiconductor region being referred to as a channel region, the at least one third semiconductor region separating the source region and the drain region from each other, the at least one third semiconductor region having a first face and a second face, the first face and the second face being opposite faces and extending between the source region and the drain region, ■ a first gate electrode (121) arranged opposite the first face of the channel region to bias the channel region, ■ a second gate electrode (125) arranged opposite the second face of the channel region to bias the channel region, - providing a power supply circuit (350) configured to supply power to the source region, the drain region, and each of the first gate electrode (121) and the second gate electrode (125) of the detection structure (100), The method comprises a step of connecting the detection structure (100) to the power supply circuit (350), which step is independent of the step of providing the detection structure (100) and the step of providing the power supply circuit (350), or is performed simultaneously with at least one of these steps. The manufacturing method comprises providing the power supply circuit (350), wherein the power supply circuit (350) is configured to supply power to the detection structure (100) during operation, so that the channel region has a layer (114) at a position on one of the first surface and the second surface, in which carriers of a second conductivity type opposite to the first conductivity type are dominant, and the layer (114) is called a blocking layer.

14. The method according to claim 13, wherein: The step of providing the detection structure (100) includes a sub-step of forming at least one of a first gate dielectric layer (131) and a second gate dielectric layer (135), wherein at least one of the first gate dielectric layer (131) and the second gate dielectric layer (135) includes a first sub-layer (132) and a second sub-layer (133) respectively formed of a first dielectric material and a second dielectric material, and the first sub-layer and the second sub-layer are capable of forming an electrostatic dipole between the first sub-layer and the second sub-layer.

15. The method according to claim 13, wherein: The step of providing the detection structure (100) comprises the following sub-steps: doping the channel region to form a portion of the channel region arranged to form the barrier layer, the portion of the channel region having a concentration of a doping element higher than the concentration of a doping element in a remaining portion of the channel region.

16. The method according to claim 14, wherein: One of the steps of forming the detection structure (100) and connecting the detection structure (100) to the power supply circuit (350) includes arranging the source region and the first gate electrode (121) to be short-circuited.

17. The method according to claim 16, wherein: One of the steps of forming the detection structure (100) and connecting the detection structure (100) to the power supply circuit (350) includes arranging the drain region and the second gate electrode (125) to be short-circuited.

18. The method according to claim 14, wherein: The first dielectric material and the second dielectric material are silicon dioxide and aluminum oxide, respectively.

Images