Imaging element and method for manufacturing the imaging element

Abstract

An imaging element according to an embodiment includes: a first wiring layer having a plurality of first wirings extending in one direction; a first insulating film laminated on the first wiring layer and forming a gap between adjacent ones of the plurality of first wirings; a second insulating film laminated on the first insulating film and having a flat surface; and a first conductive film facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween.

Description

Technical Field

[0001] The present disclosure relates, for example, to an imaging element having a gap between wirings and a method for manufacturing the imaging element. Background Art

[0002] With the manufacture of finer semiconductor integrated circuit elements, in a semiconductor device, the interval between elements and the interval between wirings connecting the elements become narrower. Regarding this, for example, Patent Document 1 discloses a semiconductor device in which the capacitance between wirings is reduced by forming a gap (air gap) between the wirings.

[0003] Citation List

[0004] Patent Document

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2008 - 193104 Summary of the Invention

[0006] Incidentally, in recent years, stacked image sensors have been widely used, and a requirement for reducing wiring capacitance has been proposed.

[0007] There is a desire to provide an imaging element capable of reducing wiring capacitance and a method for manufacturing the imaging element.

[0008] An imaging element according to an embodiment of the present invention includes: a first wiring layer; a first insulating film; a second insulating film; and a first conductive film. The first wiring layer includes a plurality of first wirings extending in one direction. The first insulating film is stacked on the first wiring layer, and the first insulating film forms a gap between adjacent ones of the plurality of first wirings. The second insulating film is stacked on the first insulating film. The second insulating film has a flat surface. The first conductive film faces at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween.

[0009] A method for manufacturing an imaging element according to an embodiment of the present invention includes: forming a first wiring layer including a plurality of first wirings extending in one direction; forming a first opening in a predetermined region of the first wiring layer between adjacent ones of the plurality of first wirings; forming a gap between adjacent ones of the plurality of first wirings by forming a first insulating film; forming a second insulating film and then planarizing the surface of the second insulating film; and forming a first conductive film at a position facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween. The second insulating film covers the first insulating film.

[0010] In an imaging element according to an embodiment of the present disclosure and a method for manufacturing an imaging element according to an embodiment, the first insulating film is provided on a first wiring layer including a plurality of first wirings extending in one direction. In addition, a second insulating film having a flat surface is provided. The first insulating film forms gaps between adjacent first wirings. Thus, a first conductive film can be formed at a position directly opposite to at least a portion of the plurality of first wirings via the first insulating film and the second insulating film. The first conductive film can be used as a pad electrode for bonding, for example. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram illustrating an example of a cross-sectional structure of a wiring structure in a vertical direction according to an embodiment of the present disclosure.

[0012] Figure 2A It is shown Figure 1 The diagram shown is a schematic diagram of an example of a cross-sectional configuration of a wiring structure in the horizontal direction.

[0013] Figure 2B It is shown Figure 1 FIG. 2 is a schematic diagram showing another example of a cross-sectional structure of a wiring structure in the horizontal direction.

[0014] Figure 3A It is shown in Figure 1 Schematic cross-sectional view of an example of a manufacturing process of a wiring structure shown in FIG.

[0015] Figure 3B It is shown in Figure 3A A schematic cross-sectional view showing an example of subsequent manufacturing steps.

[0016] Figure 3C It is shown in Figure 3B A schematic cross-sectional view showing an example of subsequent manufacturing steps.

[0017] Figure 3D It is shown in Figure 3C A schematic cross-sectional view showing an example of subsequent manufacturing steps.

[0018] Figure 3E It is shown in Figure 3D A schematic cross-sectional view showing an example of subsequent manufacturing steps.

[0019] Figure 3F It is shown in Figure 3E A schematic cross-sectional view showing an example of subsequent manufacturing steps.

[0020] Figure 3G It is shown in Figure 3F A schematic cross-sectional view showing an example of subsequent manufacturing steps.

[0021] Figure 4It is a diagram showing an example of a cross-sectional structure of an imaging element in the vertical direction according to an embodiment of the present disclosure.

[0022] Figure 5 It is a diagram showing Figure 4 an example of a schematic structure of the imaging element shown.

[0023] Figure 6 It is Figure 1 an application diagram in which the wiring structure shown is applied to the imaging element shown. Figure 4 an application diagram in which the wiring structure shown is applied to the imaging element shown.

[0024] Figure 7 It is a diagram showing Figure 5 an example of a sensor pixel and a readout circuit shown.

[0025] Figure 8 It is a diagram showing Figure 5 an example of a sensor pixel and a readout circuit shown.

[0026] Figure 9 It is a diagram showing Figure 5 an example of a sensor pixel and a readout circuit shown.

[0027] Figure 10 It is a diagram showing Figure 5 an example of a sensor pixel and a readout circuit shown.

[0028] Figure 11 It is a diagram showing an example of a coupling mode between a plurality of readout circuits and a plurality of vertical signal lines.

[0029] Figure 12 It is a diagram showing Figure 4 an example of a cross-sectional structure of the imaging element in the horizontal direction shown.

[0030] Figure 13 It is a diagram showing Figure 4 an example of a cross-sectional structure of the imaging element in the horizontal direction shown.

[0031] Figure 14 It is a diagram showing Figure 4 an example of a wiring layout of the imaging element in the horizontal plane shown.

[0032] Figure 15 It is a diagram showing Figure 4 an example of a wiring layout of the imaging element in the horizontal plane shown.

[0033] Figure 16 It is a diagram showing Figure 4 an example of a wiring layout of the imaging element in the horizontal plane shown.

[0034] Figure 17 It is a diagram showingFigure 4 A diagram showing an example of the wiring layout of the imaging element in the horizontal plane.

[0035] Figure 18A It shows Figure 4 A diagram showing an example of the manufacturing process of the imaging element shown.

[0036] Figure 18B It shows Figure 18A A diagram showing an example of the manufacturing process after that.

[0037] Figure 18C It shows Figure 18B A diagram showing an example of the manufacturing process after that.

[0038] Figure 18D It shows Figure 18C A diagram showing an example of the manufacturing process after that.

[0039] Figure 18E It shows Figure 18D A diagram showing an example of the manufacturing process after that.

[0040] Figure 18F It shows Figure 18E A diagram showing an example of the manufacturing process after that.

[0041] Figure 18G It shows Figure 18F A diagram showing an example of the manufacturing process after that.

[0042] Figure 19A A cross-sectional schematic diagram showing an example of the manufacturing steps of the wiring structure according to Modification 1 of the present disclosure.

[0043] Figure 19B It shows during Figure 19A A cross-sectional schematic diagram showing an example of the manufacturing process after that.

[0044] Figure 19C It shows during Figure 19B A cross-sectional schematic diagram showing an example of the manufacturing process after that.

[0045] Figure 19D It shows during Figure 19C A cross-sectional schematic diagram showing an example of the manufacturing process after that.

[0046] Figure 19E It shows during Figure 19D A cross-sectional schematic diagram showing an example of the manufacturing process after that.

[0047] Figure 19F It shows during Figure 19E A cross-sectional schematic diagram showing an example of the manufacturing process after that.

[0048] Figure 19G It shows duringFigure 19F Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0049] Figure 19H It shows Figure 19G Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0050] Figure 19I It shows Figure 19H Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0051] Figure 19J It shows Figure 19I Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0052] Figure 19K It shows Figure 19J Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0053] Figure 20 Cross-sectional schematic diagram of the manufacturing steps of a wiring structure as a reference example.

[0054] Figure 21A Cross-sectional schematic diagram of an example of the manufacturing steps of a wiring structure according to Modification 2 of the present disclosure.

[0055] Figure 21B It illustrates Figure 21A Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0056] Figure 21C It illustrates Figure 21B Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0057] Figure 21D It illustrates Figure 21C Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0058] Figure 21E It illustrates Figure 21D Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0059] Figure 21F It illustrates Figure 21E Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0060] Figure 22A Cross-sectional schematic diagram of an example of the manufacturing steps of a wiring structure according to Modification 3 of the present disclosure.

[0061] Figure 22B It shows Figure 22A Cross-sectional schematic diagram of an example of a subsequent manufacturing process.

[0062] Figure 22C is a cross-sectional schematic view showing an example of a manufacturing process after Figure 22B

[0063] Figure 22D is a cross-sectional schematic view showing an example of a manufacturing process after Figure 22C

[0064] Figure 22E is a cross-sectional schematic view showing an example of a manufacturing process after Figure 22D

[0065] Figure 22F is a cross-sectional schematic view showing an example of a manufacturing process after Figure 22E

[0066] Figure 22G is a cross-sectional schematic view showing an example of a manufacturing process after Figure 22F

[0067] Figure 22H is a cross-sectional schematic view showing an example of a manufacturing process after Figure 22G

[0068] Figure 23A is a cross-sectional schematic view showing an example of the manufacturing steps of a wiring structure according to Modification Example 4 of the present disclosure.

[0069] Figure 23B is a cross-sectional schematic view showing an example of a manufacturing process after Figure 23A

[0070] Figure 23C is a cross-sectional schematic view showing an example of a manufacturing process after Figure 23B

[0071] Figure 23D is a cross-sectional schematic view showing an example of a manufacturing process after Figure 23C

[0072] Figure 23E is a cross-sectional schematic view showing an example of a manufacturing process after Figure 23D

[0073] Figure 23F is a cross-sectional schematic view showing an example of a manufacturing process after Figure 23E

[0074] Figure 23G is a cross-sectional schematic view showing an example of a manufacturing process after Figure 23F

[0075] Figure 24 is a view showing an example of the cross-sectional structure of an imaging element in the vertical direction according to Modification Example 5 of the present disclosure.​​​​​​​​​​​​

[0076] Figure 25 This is a diagram showing an example of the cross-sectional structure of the imaging element according to Modification 6 of the present disclosure in the vertical direction.

[0077] Figure 26 This is a diagram showing an example of the cross-sectional structure of the imaging element according to Modification 7 of the present disclosure in the horizontal direction.

[0078] Figure 27 This is a diagram showing another example of the cross-sectional structure of the imaging element according to Modification 7 of the present disclosure in the horizontal direction.

[0079] Figure 28 This is a diagram showing an example of the cross-sectional structure of the imaging element according to Modification 8 of the present disclosure in the horizontal direction.

[0080] Figure 29 This is a diagram showing an example of the cross-sectional structure of the imaging element according to Modification 9 of the present disclosure in the horizontal direction.

[0081] Figure 30 This is a diagram showing an example of the cross-sectional structure of the imaging element according to Modification 10 of the present disclosure in the horizontal direction.

[0082] Figure 31 This is a diagram showing another example of the cross-sectional structure of the imaging element according to Modification 10 of the present invention in the horizontal direction.

[0083] Figure 32 This is a diagram showing another example of the cross-sectional structure of the imaging element according to Modification 10 of the present invention in the horizontal direction.

[0084] Figure 33 This is a diagram showing an example of the circuit structure of the imaging element for the imaging element according to Modification 11 of the present invention.

[0085] Figure 34 This is a diagram showing an example of the imaging element according to Modification 12 of the present disclosure in Figure 33 which the imaging element includes three stacked substrates.

[0086] Figure 35 This is a diagram showing an example in which the logic circuits according to Modification 13 of the present disclosure are respectively formed on the substrate having sensor pixels and the substrate having a readout circuit.

[0087] Figure 36 This is a diagram showing an example in which the logic circuit according to Modification 14 of the present disclosure is formed on a third substrate.

[0088] Figure 37This is a diagram showing an example of the schematic configuration of an imaging system including an imaging element according to any one of the above-described embodiments and its modifications.

[0089] Figure 38 This is a diagram showing Figure 37 an example of the imaging process in the imaging system in

[0090] Figure 39 This is a diagram showing an overview of example configurations of a non-stacked solid-state imaging element and a stacked solid-state imaging element to which the technology according to the present disclosure can be applied.

[0091] Figure 40 This is a cross-sectional view showing a first example configuration of a stacked solid-state imaging element.

[0092] Figure 41 This is a cross-sectional view showing a second example configuration of a stacked solid-state imaging element.

[0093] Figure 42 This is a cross-sectional view showing a third example configuration of a stacked solid-state imaging element.

[0094] Figure 43 This is a cross-sectional view showing another example configuration of a stacked solid-state imaging element to which the technology according to the present disclosure can be applied.

[0095] Figure 44 This is a block diagram showing an example of the schematic configuration of a vehicle control system.

[0096] Figure 45 This is a schematic diagram assisting in explaining an example of the installation positions of an external information detection unit and an imaging unit.

[0097] Figure 46 This is a diagram showing an example of the schematic configuration of an endoscopic surgery system.

[0098] Figure 47 This is a block diagram showing an example of the functional configuration of a camera and a camera control unit (CCU). Detailed Description of Embodiments

[0099] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following description is a specific example of the present disclosure, but the present disclosure is not limited to the following modes. In addition, the present disclosure is not limited to the configuration, dimensions, dimensional ratios, etc. of each component shown in the respective drawings. Note that the order of explanation is as follows.

[0100] 1. Embodiment (Example of an imaging element in which an insulating film made of different materials is laminated on a wiring layer, the wiring layer includes a plurality of wirings extending in one direction and has a gap between adjacent wirings, and a conductive film such as a pad electrode for bonding is included above the plurality of wirings, and the insulating film is located between the conductive film and the multilayer wiring)

[0101] 1-1. Structure of Wiring Structure

[0102] 1-2. Manufacturing Method of Wiring Structure

[0103] 1-3. Structure of Imaging Element

[0104] 1-4. Manufacturing Method of Imaging Element

[0105] 1-5. Function and Effect

[0106] 2. Variation Example

[0107] 2-1. Variation Example 1 (Another Example of Manufacturing Steps of Wiring Structure)

[0108] 2-2. Variation Example 2 (Another Example of Manufacturing Steps of Wiring Structure)

[0109] 2-3. Variation Example 3 (Another Example of Manufacturing Steps of Wiring Structure)

[0110] 2-4. Variation Example 4 (Another Example of Manufacturing Steps of Wiring Structure)

[0111] 2-5. Variation Example 5 (Example of Using Planar TG)

[0112] 2-6. Variation Example 6 (Example of Using Cu-Cu Bonding at Panel Outer Edge)

[0113] 2-7. Variation Example 7 (Example with Offset between Sensor Pixel and Readout Circuit)

[0114] 2-8. Variation Example 8 (Example where Silicon Substrate with Readout Circuit is Island-Shaped)

[0115] 2-9. Variation Example 9 (Example where Silicon Substrate with Readout Circuit is Island-Shaped)

[0116] 2-10. Variation Example 10 (Example where FD is Shared by Eight Sensor Pixels)

[0117] 2-11. Variation Example 11 (Example where Column Signal Processing Circuit Includes Typical Column ADC Circuit)

[0118] 2-12. Variation Example 12 (Example where Imaging Device Includes Three Stacked Substrates)

[0119] 2-13. Variation Example 13 (Example of Setting Logic Circuit on First and Second Substrates)

[0120] 2-14. Variation Example 14 (Example of Setting Logic Circuit on Third Substrate)

[0121] 3. Application Example

[0122] 4. Practical application examples

[0123] <1. Example>

[0124] Figure 1 An example of a cross-sectional configuration in the vertical direction of a wiring structure (wiring structure 100 ) according to an embodiment of the present disclosure is schematically shown. Figure 2A Schematically shows Figure 1 An example of a cross-sectional configuration of the wiring structure 100 in the horizontal direction is shown in FIG. Figure 2B Schematically shows Figure 1 Another example of the cross-sectional configuration of the wiring structure 100 in the horizontal direction is shown in FIG. Figure 1 Corresponding to the Figure 2A The wiring structure 100 is a cross section taken along the line II shown in FIG. The wiring structure 100 has, for example, a multilayer wiring structure in which a plurality of wiring layers are stacked. The wiring structure 100 is preferably used in, for example, the imaging element 1 described below.

[0125] In the wiring structure 100 according to the present embodiment, the insulating film 123 and the insulating film 124 are sequentially stacked on the wiring layer 112, and the wiring layer 112 includes a plurality of wirings (e.g., wirings 112X1 to 112X6) extending in one direction (e.g., the Y-axis direction). The insulating film 123 is formed with corresponding gaps G, for example, between the adjacent wirings 112X2 and 112X3, between the adjacent wirings 112X3 and 112X4, and between the adjacent wirings 112X4 and 112X5. The insulating film 124 has a flat surface. In addition, in contact with at least a portion of the plurality of wirings 112X1 to 112X6 extending in one direction (e.g., Figure 1 A conductive film 127 (specifically, a conductive film 127X1) is provided at a position directly opposite to the wiring 112X1 to the wiring 112X4) in the wiring layer 112 through the insulating film 123 and the insulating film 124. These multiple wirings 112X1 to 112X6 and the wiring layer 112 respectively correspond to specific examples of the “first wiring” and the “first wiring layer” according to the present disclosure. The insulating film 123 corresponds to a specific example of the “first insulating film” according to the present disclosure and the insulating film 124 corresponds to a specific example of the “second insulating film” according to the present disclosure. In addition, the conductive film 127X1 corresponds to a specific example of the “first conductive film” according to the present disclosure.

[0126] (1-1. Structure of wiring structure)

[0127] The wiring structure 100 has a structure in which a first layer 110 and a second layer 120 are stacked in this order on, for example, a silicon substrate (not shown) or the like. The first layer 110 includes a wiring layer 112 having a plurality of wirings (for example, wirings 112X1 to 112X6). The second layer 120 includes an insulating film 122, an insulating film 123, and a conductive film 127. The insulating film 122 and the insulating film 123 are formed between the conductive film 127 and the wiring layer 112. The insulating film 122 forms a gap G, for example, between adjacent wirings of the plurality of wirings 112X1 to 112X5 provided in the first layer 110. The insulating film 123 covers the insulating film 122 and has a flat surface. The conductive film 127 includes, for example, a conductive film 127X1 and a conductive film 127X2. The conductive film 127X1 is provided above a gap formation region 100X where the gap G is formed. The conductive film 127X2 is provided above a wiring (for example, wiring 112X6) where the gap G is not formed.

[0128] In the first layer 110, an insulating film 111 is formed by embedding, and the insulating film 111 has a plurality of wirings (for example, wirings 112X1 to 112X6).

[0129] The insulating film 111 is formed, for example, using a low dielectric constant material (low-k material) having a relative dielectric constant (k) of 3.0 or less. Specifically, examples of the material of the insulating film 111 include organic polymers such as SiOC, SiOCH, porous silicon, SiOF, inorganic SOG, organic SOG, and polyallyl ether.

[0130] The wiring layer 112 includes, for example, a plurality of wirings extending in one direction. The wiring layer 112 includes, for example, wirings 112X1 to 112X6 extending in the Y-axis direction. The wirings 112X1 to 112X6 are formed in parallel and, for example, satisfy Line (L) / Space (S) = 40 to 200 nm / 40 to 200 nm. The wirings 112X1 to 112X6 are formed to fill an opening H1 provided in the insulating film 111, for example. Each of the wirings 112X1 to 112X6 includes, for example, a barrier metal 112A formed on the side surface and the bottom surface of the opening H1 and a metal film 112B filling the opening H1. Examples of the material of the barrier metal 112A include monomers of Ti (titanium) or Ta (tantalum), nitrides, and their alloys. Examples of the material of the metal film 112B include metal materials mainly including low-resistance metals such as Cu (copper), W (tungsten), or Al (aluminum).

[0131] The first layer 110 also has openings H2 provided in the insulating film 111 between adjacent wirings. Specifically, the first layer 110 also has openings H2 provided in the insulating film 111, for example, between wiring 112X2 and wiring 112X3, between wiring 112X3 and wiring 112X4, and between wiring 112V4 and wiring 112X5.

[0132] In the second layer 120, a plurality of insulating films (insulating films 121 to 126) are stacked and a conductive film 127 is formed, for example, embedded in the insulating film 126 as the uppermost layer. Specifically, the insulating film 121, the insulating film 122, the insulating film 123, the insulating film 124, the insulating film 125, and the insulating film 126 are stacked in sequence from the first layer 110 side. The above-mentioned openings H2 provided between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5 are closed by the insulating film 123 included in the second layer 120. This forms respective gaps G between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5. The gaps G reduce the capacitance between the wirings extending side by side. For example, as Figure 2A and Figure 2B As shown, the gap G is formed in a partial region or the entire region (gap forming region 100X) between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5.

[0133] For example, in the case where the wirings 112X1 to 112X6 are formed of copper (Cu), the insulating film 121 is used to prevent the diffusion of copper (Cu). The insulating film 121 is provided to cover the insulating film 111 except for the above-mentioned opening H2, the wirings 112X1 and 112X6 formed to be embedded, and a part of the wirings 112X2 and 112X5 with the opening H2 provided between the wirings. The insulating film 121 is made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) or SiC x N y etc. are formed.

[0134] For example, in the case where the wiring 112X1 to the wiring 112X6 are formed of copper (Cu), the insulating film 122 is used to prevent the diffusion of copper (Cu) as in the insulating film 121. The insulating film 122 is provided on the insulating film 121. In addition, the insulating film 122 is formed to extend and cover the side surface and the bottom surface of the opening H2. As described above, the insulating film 122 can be formed by using an insulating material that prevents the diffusion of copper (Cu) by a manufacturing method with excellent step difference coverage. Specifically, the insulating film 122 is formed by using silicon oxide (SiO x ), silicon nitride (SiN x )、SiC x N y The like are formed by an ALD (atomic layer deposition) method.

[0135] The insulating film 123 is disposed on the insulating film 122. The insulating film 123 is used to form a gap G in the opening H2. The coverage rate of the insulating film 123 is low and it is formed of, for example, a low-k material having a relative dielectric constant (k) of 3.0 or less. Specifically, examples of the material of the insulating film 132A include organic polymers such as SiOC, SiOCH, porous silica, SiOF, inorganic SOG, organic SOG, and polyallyl ether.

[0136] The insulating film 124 is disposed on the insulating film 123. The irregularities of the insulating film 123 above the gap G are filled with the insulating film 124. Although described in detail below, the insulating film 124 is used to form a flat surface above the gap G to allow a hybrid bonding such as Cu-Cu bonding to be laminated with a device thereon. As the material of the insulating film 124, a material having, for example, a higher polishing rate than the polishing rate of the insulating film 123 and a relative dielectric constant (k) close to 4.0, for example, is preferably used. Examples of such a material include silicon oxide (SiO x ), SiOC, SiOF, SiON, etc. It should be noted that the insulating film 124 may be a single-layer film including any one of the above materials, or may be formed as a laminated film including two or more of the above materials.

[0137] The insulating film 125 is used to reduce warping caused by stress generated when forming the following conductive film 127. For example, the insulating film 125 is formed by a CVD (chemical vapor deposition) method. For example, it can be formed by using, for example, silicon oxide (SiO x ) having a relative dielectric constant (k) of 7.0 or more, silicon nitride (SiN x ), etc.

[0138] The insulating film 126 is disposed on the insulating film 125. The insulating film 126 forms a bonding surface between, for example, the second substrate 20 and the third substrate 30 of the following imaging element 1. A material having, for example, a higher polishing rate than the polishing rate of the insulating film 123 and a relative dielectric constant (k) close to 4.0, for example, is preferably used as the material of the insulating film 126 to allow the bonding surface to be flattened. Examples of such a material include silicon oxide (SiO x ), SiOC, SiOF, SiON, etc. It should be noted that the insulating film 126 may be a single-layer film including any one of the above materials, or may be formed as a laminated film including two or more of the above materials.

[0139] The conductive film 127 is a wiring layer provided directly above, for example, a wiring layer 112 including wirings 112X1 to 112X6 extending in one direction. For example, the conductive film 127 is formed to fill the opening H3. The conductive film 127 forms a plane flush with the insulating film 126. The opening H3 is provided in the insulating film 126 and a part of the insulating film 125. The conductive film 127 includes a plurality of conductive films (for example, conductive film 127X1 and conductive film 127X2). At least a part of the conductive film 127 is arranged to extend in one direction and face at least a part of the wirings 112X1 to 112X6. For example, in Figure 1 the conductive film 127X1 is formed at a position facing, for example, the wirings 112X2, 112X3, and 112X4 and extends in the Y-axis direction in the same manner as the wirings 112X2 and 112X3. The wirings 112X2, 112X3, and 112X4 have a gap G between the wirings. In addition, an opening H4 is provided in the opening H3. The opening H4 extends through the insulating film 121 to the insulating film 125 and reaches the wiring 112X1. The opening H4 is also filled with the conductive film 127X1 and the conductive film 127X1 is electrically coupled to the wiring 112X1.

[0140] The conductive film 127 includes a barrier metal 127A formed on the side surfaces and bottom surface of the opening H3 and the opening H4, and a metal film 127B filling the opening H3 and the opening H4. Examples of the material of the barrier metal 127A include monomers of Ti (titanium) or Ta (tantalum), nitrides, and their alloys, etc. Examples of the material of the metal film 127B include metal materials mainly including low-resistance metals such as Cu (copper), W (tungsten), or aluminum (Al).

[0141] (1-2. Manufacturing method of the wiring structure)

[0142] First, the wiring layer 112 including the wirings 112X1 to 112X6 is formed to be embedded in the insulating film 111, and then its surface is polished by using, for example, a CMP (chemical mechanical polishing) method to form the first layer 110. Subsequently, as Figure 3A shown, an insulating film 121 having a thickness of, for example, 5 nm to 250 nm is formed on the first layer 110 by using, for example, a PVD (physical vapor deposition) method or a CVD (chemical vapor deposition) method.

[0143] Next, as Figure 3B shown, a resist film 131 having openings at positions corresponding to the wirings 121X2 to 112X5 is patterned on the insulating film 121 by using photolithography technology. Subsequently, as Figure 3CAs shown, dry etching is performed, for example, on the insulating film 121 exposed from the resist film 131, a part of the wirings 112X2 to 112X5, and the insulating film 111 to form an opening H2.

[0144] Next, the resist film 131 is removed, and then as Figure 3D shown, an insulating film 122 having a thickness of, for example, 0.5 nm to 15 nm is formed by using, for example, the ALD method to cover the top of the insulating film 121 and the side and bottom surfaces of the opening H2. Subsequently, as Figure 3E shown, an insulating film 123 having a film thickness of, for example, 100 nm to 500 nm is formed by using, for example, a CVD method. The insulating film 123 includes, for example, SiOC or silicon nitride. This closes the opening H2 and forms gaps G between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5.

[0145] Next, as Figure 3F shown, an insulating film 124 is formed on the insulating film 123 by using, for example, a CVD method. The insulating film 124 includes, for example, SiO x . The insulating film 124 has a film thickness of, for example, 200 nm to 300 nm. Subsequently, the insulating film 124 is polished by using, for example, Figure 3G the CMP method shown and its surface is flattened.

[0146] Next, an insulating film 125 having a thickness of, for example, 50 nm to 500 nm is formed on the insulating film 124 by using, for example, a CVD method, and then an insulating film 126 having a thickness of 100 nm to 2 μm is formed on the insulating film 125 by using, for example, a CVD method. Next, by using a method similar to that of the opening H2, a part of the insulating film 126 and the insulating film 125 is dry-etched to form an opening H3, and then an opening H4 is further formed in the opening H3. The opening H4 extends through the insulating film 121 to the insulating film 125 and reaches the wiring 112X1. After that, on the side and bottom surfaces of the opening H3 and the opening H4, a barrier metal 127A is formed by using, for example, sputtering, and then a metal film 127B is formed in the opening H3 and the opening H4 by using, for example, electroplating. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished and removed to form a flat surface that makes the insulating film 126 and the conductive film 127 flush. As described above, the Figure 1 shown wiring structure 100 is completed.

[0147] (1 - 3. Structure of the imaging element)

[0148] Figure 4Shows an example of the cross-sectional structure of an imaging element (imaging element 1) in the vertical direction according to an embodiment of the present disclosure. Figure 5 Shows Figure 4 An example of the schematic structure of the imaging element 1 shown in. The imaging element 1 is an imaging element having a three-dimensional structure formed by laminating a first substrate 10, a second substrate 20, and a third substrate 30. The first substrate 10 includes sensor pixels 12 on a semiconductor substrate 11. The sensor pixels 12 perform photoelectric conversion. The second substrate 20 includes a readout circuit 22 on a semiconductor substrate 21. The readout circuit 22 outputs an image signal based on the charge output from the sensor pixels 12. The third substrate 30 includes a logic circuit 32 on a semiconductor substrate 31. The logic circuit 32 processes pixel signals. For example, as Figure 6 Shown, the wiring structure 100 is a wiring structure applicable to the vicinity of the bonding surface of the second substrate 20 bonded to the third substrate 30.

[0149] As described above, the first substrate 10 includes a plurality of sensor pixels 12 on the semiconductor substrate 11. Each of the plurality of sensor pixels 12 performs photoelectric conversion. The semiconductor substrate 11 corresponds to a specific example of the "first semiconductor substrate" according to the present disclosure. The plurality of sensor pixels 12 are arranged in a matrix form in the pixel region 13 on the first substrate 10. The second substrate 20 includes one readout circuit 22 for every four sensor pixels 12 on the semiconductor substrate 21. The readout circuit 22 outputs a pixel signal based on the charge output from each sensor pixel 12. The semiconductor substrate 21 corresponds to a specific example of the "second semiconductor substrate" according to the present disclosure. The second substrate 20 includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 includes a logic circuit 32 on the semiconductor substrate 31. The logic circuit 32 processes pixel signals. The semiconductor substrate 31 corresponds to a specific example of the "third semiconductor substrate" according to the present disclosure. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs the output voltage Vout of each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low-resistance region containing silicide and formed by using a Salicide (self-aligned silicide) process such as CoSi2 and NiSi can be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0150] The vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12 row by row, for example. The column signal processing circuit 34 performs correlated double sampling (CDS) processing on the pixel signals output from each of the sensor pixels 12 in the row selected by the vertical drive circuit 33, for example. The column signal processing circuit 34 performs CDS processing, for example, to extract the signal level of the pixel signal. The column signal processing circuit 34 holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35 outputs the plurality of pixel data held in the column signal processing circuit 34 to the outside sequentially, for example. The system control circuit 36 controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32, for example.

[0151] Figure 7 An example of the sensor pixel 12 and the readout circuit 22 is shown. The case where four sensor pixels 12 as shown below share one readout circuit 22 is described. Here, "sharing" means that the outputs of the four sensor pixels 12 are input to the common readout circuit 22. Figure 7

[0152] Figure 7 Each sensor pixel 12 includes components that are the same as each other. In order to distinguish the components of each sensor pixel 12 from each other, an identification number (1, 2, 3, or 4) is assigned to the end of the symbol of the component of each sensor pixel 12. In the case where the components of each sensor pixel 12 must be distinguished from each other, the following assigns an identification number to the end of the symbol of the component of each sensor pixel 12. However, in the case where it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification number at the end of the symbol of the component of each sensor pixel 12 is omitted.

[0153] Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR that electrically couples the photodiode PD, and a floating diffusion section FD that temporarily holds the charge output from the photodiode PD through the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically coupled to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically coupled to the reference potential line (for example, ground). The drain of the transfer transistor TR is electrically coupled to the floating diffusion section FD, and the gate of the transfer transistor TR is electrically coupled to the pixel drive line 23. The transfer transistor TR is a CMOS (complementary metal oxide semiconductor) transistor, for example.

[0154] ​The floating diffusion parts FD of respective sensor pixels 12 sharing a readout circuit 22 are electrically coupled to each other and are electrically coupled to the input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. It should be noted that the selection transistor SEL can be omitted as needed. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically coupled to the floating diffusion part FD, and the drain of the reset transistor RST is electrically coupled to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically coupled to the pixel drive line 23. The source of the amplification transistor AMP is electrically coupled to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically coupled to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically coupled to the vertical signal line 24, and the gate of the selection transistor SEL is electrically coupled to the pixel drive line 23.

[0155] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion part FD. For example, as Figure 4 shown, the gate of the transfer transistor TR (transfer gate TG) extends from the surface of the semiconductor substrate 11 to penetrate the p-well layer 42 to reach the depth of the PD41. The reset transistor RST resets the potential of the floating diffusion part FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion part FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the timing of outputting the pixel signal from the readout circuit 22. The amplification transistor AMP generates a voltage signal corresponding to the charge level held in the floating diffusion part FD as the pixel signal. The amplification transistor AMP is included in a source follower type amplifier and outputs a pixel signal whose voltage corresponds to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion part FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 through the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0156] It should be noted that, as Figure 8 shown, the selection transistor SEL can be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically coupled to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically coupled to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically coupled to the pixel drive line 23. The source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically coupled to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically coupled to the source of the reset transistor RST. In addition, asFigure 9 and Figure 10 As shown in Figure 10 , the FD transfer transistor FDG can be disposed between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0157] The FD transfer transistor FDG is used to switch the conversion efficiency. Generally, when shooting in the dark, the pixel signal is small. In the case of charge-voltage conversion based on Q = CV, the floating diffusion section FD with a larger capacitance (FD capacitance C) will result in a smaller V when converted to a voltage by the amplification transistor AMP. However, in a bright place, a large pixel signal is provided. Therefore, the floating diffusion section FD cannot receive the charge of the photodiode PD unless the FD capacitance C is large. In addition, when converted to a voltage by the amplification transistor AMP, the FD capacitance C must be large to prevent V from being too large (i.e., to make V smaller). Considering these, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases. This causes the entire FD capacitance C to become larger. At the same time, when the FD transfer transistor FDG is turned off, the entire FD capacitance C becomes smaller. In this way, switching the on and off of the FD transfer transistor FDG enables the FD capacitance C to be variable. This enables the conversion efficiency to be switched.

[0158] Figure 11 An example of the coupling mode between a plurality of readout circuits 22 and a plurality of vertical signal lines 24 is shown. In the case where a plurality of readout circuits 22 are arranged side by side in the direction in which the vertical signal lines 24 extend (e.g., the column direction), a plurality of vertical signal lines 24 can be allocated to each readout circuit 22 in a one-to-one correspondence. In the case where four readout circuits 22 are arranged side by side in the direction in which the vertical signal lines 24 extend (e.g., the column direction), for example, as Figure 11 shown, four vertical signal lines 24 can be allocated to each readout circuit 22 in a one-to-one correspondence. Note that in Figure 11 , in order to distinguish each vertical signal line 24, an identification number (1, 2, 3, or 4) is allocated at the end of the symbol of each vertical signal line 24.

[0159] Next, with reference to Figure 4 the cross-sectional structure of the imaging element 1 in the vertical direction will be described. As described above, the imaging element 1 has a structure in which a first substrate 10, a second substrate 20, and a third substrate 30 are stacked in sequence and also includes a color filter 40 and an optical receiving lens 50 on the back surface (light incident surface) side of the first substrate 10. The color filter 40 and the optical receiving lens 50 are respectively provided for each sensor pixel 12 one by one. In other words, the imaging element 1 is a back-illuminated imaging element.

[0160] The first substrate 10 includes an insulating layer 46 laminated on the front surface (surface 11S1) of the semiconductor substrate 11. The first substrate 10 includes the insulating layer 46 as part of the interlayer insulating film 51. The insulating layer 46 is provided between the semiconductor substrate 11 and the semiconductor substrate 21 described below. The semiconductor substrate 11 includes a silicon substrate. The semiconductor substrate 11 includes, for example, a p-well layer 42 in a part of the front surface and in a region close to the front surface, and includes a PD 41 of a conductivity type different from that of the p-well layer 42 in another region (a region deeper than the p-well layer 42). The p-well layer 42 includes a p-type semiconductor region. The PD 41 includes a semiconductor region of a conductivity type different from that of the p-well layer 42 (specifically, an n-type). The semiconductor substrate 11 includes a floating diffusion portion FD in the p-well layer 42 as a semiconductor region of a conductivity type different from that of the p-well layer 42 (specifically, an n-type).

[0161] The first substrate 10 includes a photodiode PD, a transfer transistor TR, and a floating diffusion section FD for each sensor pixel 12. The first substrate 10 has a structure in which the transfer transistor TR and the floating diffusion section FD are provided on a part of the surface 11S1 side (the side opposite to the light incident surface or the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 includes an element isolation section 43 that separates the sensor pixels 12 from each other. The element isolation section 43 is formed to extend in the normal direction of the semiconductor substrate 11 (the direction perpendicular to the surface of the semiconductor substrate 11). The element isolation section 43 is provided between two adjacent sensor pixels 12. The element isolation section 43 electrically isolates the adjacent sensor pixels 12 from each other. The element isolation section 43 includes, for example, silicon oxide. The element isolation section 43 penetrates the semiconductor substrate 11, for example. The first substrate 10 further includes, for example, a p-well layer 44 that is on the side surface of the element isolation section 43 and contacts the surface on the photodiode PD side. The p-well layer 44 includes a semiconductor region having a conductivity type different from that of the photodiode PD (specifically, p-type). The first substrate 10 further includes, for example, a fixed charge film 45 that contacts the back surface (surface 11S2 or other surface) of the semiconductor substrate 11. The fixed charge film 45 has a negative fixed charge to suppress the generation of dark current caused by interface states on the light receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is formed using, for example, an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. The electric field induced by the fixed charge film 45 forms a hole accumulation layer at the interface on the light receiving surface side of the semiconductor substrate 11. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed charge film 45 and at a position opposite to the sensor pixel 12 with the fixed charge film 45 interposed therebetween. The light receiving lens 50 is provided, for example, in contact with the color filter 40 and at a position opposite to the sensor pixel 12 with the color filter 40 and the fixed charge film 45 interposed therebetween.

[0162] The second substrate 20 includes an insulating layer 52 laminated on the semiconductor substrate 21. The second substrate 20 includes the insulating layer 52 as a part of the interlayer insulating film 51. The insulating layer 52 is provided between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 includes a silicon substrate. The second substrate 20 includes one readout circuit 22 for every four sensor pixels 12. The second substrate 20 has a structure in which the readout circuit 22 is provided on a part of the front surface (the surface 21S1 opposite to the third substrate 30 or one surface) side of the semiconductor substrate 21. In a state where the back surface (surface 21S2) of the semiconductor substrate 21 faces the front surface (surface 11S1) of the semiconductor substrate 11, the second substrate 20 is bonded to the first substrate 10. In other words, the second substrate 20 is bonded to the first substrate 10 in a back-to-back manner. The second substrate 20 further includes an insulating layer 53 that is on the same layer as the semiconductor substrate 21. The insulating layer 53 penetrates the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as a part of the interlayer insulating film 51. The insulating layer 53 is provided to cover the side surface of a through-wiring 54 described later.

[0163] The laminate including the first substrate 10 and the second substrate 20 includes an interlayer insulating film 51 and a through-wiring 54 provided in the interlayer insulating film 51. The above laminate includes one through-wiring 54 for each sensor pixel 12. The through-wiring 54 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a part of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically coupled to each other through the through-wiring 54. Specifically, the through-wiring 54 is electrically coupled to the floating diffusion portion FD and a coupling wiring 55 described later.

[0164] The laminate including the first substrate 10 and the second substrate 20 further includes through-wirings 47 and 48 provided in the interlayer insulating film 51 (see below Figure 12 described). The above laminate includes one through-wiring 47 and one through-wiring 48 for each sensor pixel 12. Each of the through-wirings 47 and 48 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a part of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically coupled to each other through the through-wirings 47 and 48. Specifically, the through-wiring 47 is electrically coupled to the p-well layer 42 of the semiconductor substrate 11 and is electrically coupled to a wiring in the second substrate 20. The through-wiring 48 is electrically coupled to the transfer gate TG and the pixel driving line 23.

[0165] The second substrate 20 includes, for example, a plurality of coupling portions 59 in the insulating layer 52. The plurality of coupling portions 59 are electrically coupled to the readout circuit 22 and the semiconductor substrate 21. The second substrate 20 further includes, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 includes, for example, an insulating layer 57 and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24. The plurality of pixel driving lines 23 and the plurality of vertical signal lines 24 are provided in the insulating layer 57. The wiring layer 56 further includes, for example, a plurality of coupling wirings 55 in the insulating layer 57. One coupling wiring 55 is provided for every four sensor pixels 12. The coupling wirings 55 electrically couple the respective corresponding through wirings 54 to each other. The through wirings 54 are electrically coupled to the floating diffusion portions FD included in the four sensor pixels 12 of the common readout circuit 22. Here, the total number of the through wirings 54 and 48 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is twice the total number of the sensor pixels 12 included in the first substrate 10. Further, the total number of the through wirings 54, 48, 47 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is three times the total number of the sensor pixels 12 included in the first substrate 10.

[0166] The wiring layer 56 further includes, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed by using a metal such as copper (Cu), tungsten (W), and aluminum (Al). Each pad electrode 58 exposes from the surface of the wiring layer 56. Each pad electrode 58 is used to electrically couple the second substrate 20 and the third substrate 30 and bond the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 are provided one by one, for example, for the respective corresponding pixel driving lines 23 and the respective corresponding vertical signal lines 24. Here, the total number of the pad electrodes 58 (or the total number of the bonds between the pad electrodes 58 and the pad electrodes 64 (described below)) is less than, for example, the total number of the sensor pixels 12 included in the first substrate 10.

[0167] Figure 6 The cross-sectional structure in which the above-described wiring structure 100 is applied to the imaging element 1 is schematically shown. For example, in the present embodiment, the plurality of vertical signal lines 24 correspond to the wirings 112X3 and 112X4 in the above-described wiring structure 100, and the power supply line VSS corresponds to the wirings 112X2 and 112X5 in the above-described wiring structure 100. Although not shown in Figure 4 the insulating layer 57 includes a plurality of insulating films 151 to 157 as shown in Figure 6 The insulating film 154 among them forms a gap G between the power supply line VSS and the vertical signal lines 24 extending side by side and between the wirings of the plurality of vertical signal lines 24. Each pad electrode 58 exposed on the surface of the wiring layer 56 corresponds to the conductive films 127X1 and 127X2 in the above-described wiring structure 100.

[0168] A part of each pad electrode 58 (pad electrode 58X1) is electrically coupled to a ground line (wiring 112X1). Although not shown, the ground line is coupled to, for example, a p-well or ground (GND) of the semiconductor substrate 11. This enables the pad electrode 58X1 to be used as a shielding wiring in the stacking direction of the vertical signal line 24 and reduces the noise that appears in the vertical signal line 24.

[0169] In addition, the pad electrode 58X1 serving as a shielding wiring is joined to a pad electrode 64X1 on the third substrate 30 side described later. This enables the impedance of the shielding wiring to be reduced as compared with a shielding wiring formed by using only the pad electrode 58X1. In addition, the pad electrode 58X1 serving as a shielding wiring is, for example, arranged to extend vertically through the pixel region 13 in the same manner as the vertical signal line 24, and terminates near the periphery of the pixel region beyond the region end of the pixel region 13.

[0170] For example, the third substrate 30 includes an interlayer insulating film 61 laminated on the semiconductor substrate 31. Note that, as described below, the third substrate 30 is joined to the second substrate 20 on the front surface. Therefore, in the case of describing components in the third substrate 30, the vertical relationship to be described is opposite to the vertical direction in the drawing. The semiconductor substrate 31 includes a silicon substrate. The third substrate 30 has a structure in which a logic circuit 32 is provided on a part of the front surface (surface 31S1) side of the semiconductor substrate 31. The third substrate 30 also includes, for example, a wiring layer 62 located on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 (for example, pad electrode 64X1 and pad electrode 64X2) provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically coupled to the logic circuit 32. Each pad electrode 64 is formed by using, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used to electrically couple the second substrate 20 and the third substrate 30 and join the second substrate 20 and the third substrate 30 together. In addition, the pad electrodes 64 do not necessarily have to be a plurality of pad electrodes. Even one pad electrode can be electrically coupled to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically coupled to each other by joining the pad electrodes 58 and 64 to each other. In other words, the gate of the transfer transistor TR (transfer gate TG) is electrically coupled to the logic circuit 32 through the through-wiring 54 and the pad electrodes 58 and 64. The third substrate 30 is joined to the second substrate 20 such that the front surface (surface 31S1) of the semiconductor substrate 31 faces the front surface (surface 21S1) side of the semiconductor substrate 21. In other words, the third substrate 30 is joined to the second substrate 20 in a face-to-face manner.

[0171] Figure 12 and Figure 13Each shows an example of the cross-sectional structure of the imaging element 1 in the horizontal direction. Figure 12 and Figure 13 The upper diagrams of Figure 4 are each a diagram showing an example of the cross-sectional structure taken along the cross-section Sec1 in Figure 12 and Figure 13 The lower diagrams of Figure 4 are each a diagram showing the cross-sectional structure taken along the cross-section Sec2 in Figure 12 shows a structure in which two sets of 2×2 or four sensor pixels 12 are arranged in the second direction H, and Figure 13 shows a structure in which four sets of 2×2 or four sensor pixels 12 are arranged in the first direction V and the second direction H. Note that in the upper cross-sectional views of each of Figure 12 and Figure 13 , a diagram showing an example of the front surface structure of the semiconductor substrate 11 is superimposed on a diagram showing an example of the cross-sectional structure taken along the cross-section Sec1 in Figure 4 , and the insulating layer 46 is omitted. In addition, in the lower cross-sectional views of each of Figure 12 and Figure 13 , a diagram showing an example of the front surface structure of the semiconductor substrate 21 is superimposed on a diagram showing an example of the cross-sectional structure taken along the cross-section Sec2 in Figure 4 .

[0172] As Figure 12 and Figure 13 show, a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in a strip shape in the plane of the first substrate 10 in the first direction V ( Figure 12 the up-down direction of Figure 13 and the left-right direction of Figure 12 and Figure 13 both show the case where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged in two rows in the first direction V. The first direction V is parallel to one of the two arrangement directions (e.g., row direction and column direction) of the plurality of sensor pixels 12 arranged in a matrix (e.g., column direction). Among the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusion portions FD are provided close to each other with the element isolation portion 43 therebetween, for example. Among the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG are provided to surround the four floating diffusion portions FD, and the four transfer gates TG form a ring shape, for example.

[0173] The insulating layer 53 includes a plurality of blocks extending in the first direction V. The semiconductor substrate 21 extends in the first direction V and includes a plurality of island-like blocks 21A arranged side by side in the second direction H orthogonal to the first direction V with the insulating layer 53 interposed therebetween. For example, each of the blocks 21A is provided with a plurality of sets of reset transistors RST, amplifier transistors AMP, and selection transistors SEL. One readout circuit 22 shared by four sensor pixels 12 includes, for example, reset transistors RST, amplifier transistors AMP, and selection transistors SEL in a region facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 includes, for example, amplifier transistors AMP in the left adjacent block 21A of the insulating layer 53 and reset transistors RST and selection transistors SEL in the right adjacent block 21A of the insulating layer 53.

[0174] Figure 14 , Figure 15 , Figure 16 and Figure 17 Each of them shows an example of the wiring layout of the imaging element 1 in the horizontal plane. Figures 14 to 17 Each of them shows, as an example, the case where one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12. Figures 14 to 17 The wirings shown, for example, are provided in different layers of the wiring layer 56.

[0175] For example, as shown in Figure 14 , four through wirings 54 adjacent to each other are electrically coupled to the coupling wiring 55. The four through wirings 54 adjacent to each other are further electrically coupled to the gates of the amplifier transistors AMP included in the left adjacent block 21A of the insulating layer 53 and the gates of the reset transistors RST included in the right adjacent block 21A of the insulating layer 53 through the coupling wiring 55 and the coupling portion 59. For example, as shown in Figure 14 .

[0176] The power supply line VDD is provided, for example, at a position facing the readout circuits 22 arranged side by side in the second direction H as shown in Figure 15 . For example, as shown in Figure 15 , the power supply line VDD is electrically coupled to the drains of the amplifier transistors AMP and the drains of the reset transistors RST of each readout circuit 22 arranged side by side in the second direction H through the coupling portion 59. For example, as shown in Figure 15 , two pixel drive lines 23 are provided at positions facing the readout circuits 22 arranged side by side in the second direction H. For example, as shown in Figure 15 , one of the pixel drive lines 23 (the second control line) is a wiring RSTG electrically coupled to the gates of the reset transistors RST of each readout circuit 22 arranged side by side in the second direction H. For example, as shown in Figure 15As shown, another one (third control line) in the pixel driving line 23 is a wiring SELG that is electrically coupled to the gates of the selection transistors SEL of the respective readout circuits 22 arranged side by side in the second direction H. For example, as Figure 15 shown, in each readout circuit 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically coupled to each other through the wiring 25.

[0177] For example, as Figure 16 shown, two power supply lines VSS are arranged at positions opposite to the readout circuits 22 arranged side by side in the second direction H. For example, as Figure 16 shown, each power supply line VSS is electrically coupled to a plurality of through wirings 47 at positions opposite to the respective sensor pixels 12 arranged side by side in the second direction H. For example, as Figure 16 shown, four pixel driving lines 23 are arranged at positions opposite to the readout circuits 22 arranged side by side in the second direction H. For example, as Figure 16 shown, each of the four pixel driving lines 23 is a wiring TRG that is electrically coupled to a through wiring 48 of one of the four sensor pixels 12 corresponding to each of the readout circuits 22 arranged side by side in the second direction H. In other words, the four pixel driving lines 23 (first control lines) are all electrically coupled to the gates (transfer gates TG) of the transfer transistors TR of each sensor pixel 12 arranged side by side along the second direction H. In Figure 16 , in order to distinguish the wirings TRG from each other, an identifier (1, 2, 3, or 4) is assigned to the end of each of the wirings TRG.

[0178] As Figure 17 shown, the vertical signal lines 24 are arranged at positions opposite to the readout circuits 22 arranged side by side in the first direction V. For example, as Figure 17 shown, the vertical signal lines 24 (output lines) are electrically coupled to the output ends (the sources of the amplification transistors AMP) of each of the readout circuits 22 arranged side by side in the first direction V.

[0179] (1 - 4. Manufacturing method of the imaging element)

[0180] Next, the manufacturing method of the imaging element 1 will be described. Figures 18A to 18G Each of

[0181] shows an example of the manufacturing process of the imaging element 1. Figure 18A First, a p-well layer 42, an element isolation portion 43, and a p-well layer 44 are formed on the semiconductor substrate 11. Then, a photodiode PD, a transfer transistor TR, and a floating diffusion portion FD are formed on the semiconductor substrate 11 ( Figure 18A)。This forms the sensor pixel 12 on the semiconductor substrate 11. In this case, it is preferably prevented that materials with low heat resistance such as CoSi2 and NiSi by the Salicide process are used as the electrode material for the sensor pixel 12. Instead, a material with high heat resistance is preferably used as the electrode material to be used for the sensor pixel 12. Examples of materials with high heat resistance include polysilicon. Then, an insulating layer 46 is formed on the semiconductor substrate 11( Figure 18A )。In this way, the first substrate 10 is formed.

[0182] Next, the semiconductor substrate 21 is bonded to the first substrate 10 (insulating layer 46B)( Figure 18B )。Then, the semiconductor substrate 21 is thinned as needed. In this case, the thickness of the semiconductor substrate 21 is set to the film thickness required to form the readout circuit 22. The thickness of the semiconductor substrate 21 is generally about several hundred nm. However, according to the concept of the readout circuit 22, the FD (fully depleted) type can also be used. In this case, the semiconductor substrate 21 can have a thickness in the range of several nm to several μm.

[0183] Subsequently, an insulating layer 53 is formed in the same layer as the semiconductor substrate 21( Figure 18C )。For example, the insulating layer 53 is formed at a position opposite to the floating diffusion portion FD. For example, a slit (opening 21H) penetrating the semiconductor substrate 21 is formed in the semiconductor substrate 21 to separate the semiconductor substrate 21 into a plurality of blocks 21A. Then, the insulating layer 53 is formed to fill the slit. Then, the readout circuit 22 including the amplification transistor AMP, etc. is formed in each block 21A of the semiconductor substrate 21( Figure 18C )。In this case, in the case of using a metal material with high heat resistance as the electrode material for the sensor pixel 12, the gate insulating film of the readout circuit 22 can be formed by thermal oxidation.

[0184] Next, an insulating layer 52 is formed on the semiconductor substrate 21. In this way, the interlayer insulating film 51 including the insulating layers 46, 52, and 53 is formed. Subsequently, in the interlayer insulating film 51( Figure 18D ) through holes 51A and 51B are formed. Specifically, the through hole 51B extending through the insulating layer 52 is formed in the portion of the insulating layer 52 opposite to the readout circuit 22. In addition, the through hole 51A extending through the interlayer insulating film 51 is formed in the portion of the interlayer insulating film 51 opposite to the floating diffusion portion FD (that is, the portion opposite to the insulating layer 53).

[0185] Subsequently, the through holes 51A and 51B are filled with a conductive material, so that a through wiring 54 is formed in the through hole 51A, and a coupling portion 59 is formed in the through hole 51B( Figure 18E)。In addition, a coupling wiring 55 is formed on the insulating layer 52 to electrically couple the through wiring 54 and the coupling portion 59 to each other. Figure 18E )。Then, a wiring layer 56 is formed on the insulating layer 52. Figure 18F )。In this way, the second substrate 20 is formed.

[0186] Next, the second substrate 20 is bonded to the third substrate 30 such that the front surface of the semiconductor substrate 21 faces the front surface side of the semiconductor substrate 31. Figure 18G )。The logic circuit 32 and the wiring layer 62 are formed on the third substrate 30. In this case, the pad electrodes 58 of the second substrate 20 and the pad electrodes 64 of the third substrate 30 are bonded to each other, thereby electrically coupling the second substrate 20 and the third substrate 30 to each other. In this way, the imaging element 1 is manufactured.

[0187] (1-5. Function and effect)

[0188] In the wiring structure 100 according to the present embodiment and the imaging element 1 applying the wiring structure 100, the insulating films 123 and 124 are sequentially stacked on the wiring layer 112 including a plurality of wirings (for example, wirings 112X1 to 112X6) extending in one direction (for example, the Y-axis direction). The insulating film 123 forms corresponding gaps G, for example, between adjacent wirings 112X2 and 112X3, between adjacent wirings 112X3 and 112X4, and between adjacent wirings 112X4 and 112X5. The insulating film 124 has a flat surface. In addition, the conductive film 127 is disposed at a position facing at least a part of the plurality of wirings 112X1 to 112X6 (for example, wirings 112X2, 112X3, and 112X4 having gaps G between the wirings) with the insulating films 123 and 124 interposed therebetween. This enables the wiring structure 100 to be applied to the wiring structure at the bonding surface between the second substrate 20 and the third substrate 30 of the imaging element 1 and in the vicinity thereof. Specifically, the conductive film 127 can be used as the pad electrode 58 for Cu-Cu bonding between the second substrate 20 and the third substrate 30. This will be described below.

[0189] As described above, in recent years, as semiconductor integrated circuit elements are manufactured with higher fineness, the intervals between elements and the intervals between the wirings connecting the elements have become narrower in semiconductor devices. The capacitance (parasitic capacitance) between the wirings has a tendency to increase. Therefore, in typical semiconductor devices, the wirings in the stacking direction are electrically insulated by using a low-k material and gaps are provided between the side-by-side wirings to reduce the parasitic capacitance between the wirings. In such semiconductor devices, irregularities are formed on the surface of the insulating film containing the low-k material for forming the gaps and located above the gaps.

[0190] In the case of applying the hybrid bonding technology, which is one of the three-dimensional coupling technologies, to the semiconductor device as described above, the step difference above the gap immediately above the wiring layer having gaps between the wirings significantly deteriorates the bonding property of wafer-on-wafer (WoW). A possible method for improving the bonding property of WoW is to perform a process of flattening the surface of the insulating film, but it is difficult to flatten the surface of the insulating film including a low-k material enough to achieve WoW bonding.

[0191] In contrast, in the present embodiment, an insulating film 124 having a flat surface is provided on an insulating film 123, the insulating film 123 forms a gap G between the wirings of the plurality of wirings 112X1 to 112X6 extending in one direction, and a conductive film 127 that can be used for WoW bonding is formed across the insulating film 123 and the insulating film 124. The conductive film 127 is formed so as to be embedded in the insulating film 126 stacked on the insulating film 124, and the conductive film 127 and the insulating film 126 can form a plane for WoW bonding. This makes it possible to form a gap G between the wirings of the plurality of vertical signal lines 24 extending vertically, for example, through the pixel region 13 in the image pickup element 1 having a three-dimensional structure, and to form a pad electrode 58 for Cu-Cu bonding just above the plurality of vertical signal lines 24.

[0192] As described above, in the image pickup element 1 according to the present embodiment, the wiring capacitance between the wirings of the plurality of vertical signal lines 24 extending vertically through the pixel region 13 can be reduced. In addition, it is possible to form the pad electrode 58 for Cu-Cu bonding, for example, just above the vertical signal line 24 having the gap G between the wirings, without interposing any other wiring layer therebetween. For example, it is thus possible to reduce the length of the through wirings 47 and 48 extending in the normal direction of the semiconductor substrate 21 or the like. This makes it possible to reduce the wiring capacitance between the through wirings 47 and 48.

[0193] Furthermore, in the present embodiment, one of the pad electrodes 58 for Cu-Cu bonding with the third substrate 30 (for example, the pad electrode 58X1) is electrically coupled to a ground line that is coupled to the p-well or ground (GND) of the semiconductor substrate 11. This makes it possible to provide the pad electrode 58X1 having a shield wiring function with respect to the stacking direction of the vertical signal line 24. Therefore, noise occurring in the vertical signal line 24 is reduced and it is possible to improve, for example, the image quality of the imaging element 1.

[0194] In addition, by using the pad electrode 58X1 for Cu-Cu bonding as a shielding wiring, it is also possible to use the pad electrode 64X1 on the third substrate 30 side connected to the pad electrode 58X1 as a shielding wiring in the stacking direction for the vertical signal line 24. This makes it possible to reduce the impedance of the shielding wiring. Therefore, it is possible to further reduce the noise occurring in the vertical signal line 24.

[0195] Modifications 1 to 14 are described below. It should be noted that the following description uses the same reference numerals as those of the same components in the above-described embodiments, and descriptions thereof are appropriately omitted.

[0196] <2. Modification>

[0197] (2-1. Modification 1)

[0198] Figures 19A to 19K A modification (Modification 1) of the manufacturing steps of the wiring structure (wiring structure 100A) according to the present invention is shown respectively.

[0199] First, as in the above-described embodiment, an insulating film 123 ([[]] Figure 3E ) in which a gap G is formed between the wirings 112X2 and 112X3, between the wirings 112X3 and 112X4, and between the wirings 112X4 and 112X5 is formed, and then, as shown in the cross-sectional view (A) and the plan view (B) of [[[]]] Figure 19A , a resist film 132 having an opening with a wiring width greater than or equal to that of the wiring 112X1 is patterned by lithography at a position on the insulating film 123 facing the wiring 112X1.

[0200] Subsequently, as shown in [[[]]] Figure 19B , dry etching is performed on the top of the wiring 112X1, the insulating film 123, and a part of the insulating film 122 exposed from the resist film 132 to form an opening H5. For example, the resist film 132 is removed by ashing. Next, as shown in [[[]]] Figure 19C , an insulating film 124 including, for example, SiO [[[]]] x and having a film thickness of 50 nm to 2 μm is formed in the opening H5 and on the insulating film 123 by using, for example, a CVD method, and as shown in [[[]]] Figure 19D , the insulating film 124 is polished by using, for example, a CMP method, and its surface is flattened.

[0201] Subsequently, as shown in [[[]]] Figure 19E , an insulating film 125 and an insulating film 126 are formed on the insulating film 124 by using a method similar to that of the above-described embodiment, and then, for example, a resist film 133 is patterned on the insulating film 126 by lithography. The resist film 133 has openings at positions facing the wirings 112X1 to 112X4 and above the wiring 112X6.

[0202] Next, as shown in [[[]]] Figure 19F , a part of the insulating film 126 and the insulating film 125 is subjected to, for example, dry etching to form an opening H6, and then the resist film 133 is removed by ashing. Then, as shown in [[[]]] Figure 19GAs shown, for example, by lithography, a resist film 134 having an opening at a position opposite to the wiring 112X1 is patterned on the insulating films 125 and 126 in the opening H6. Subsequently, as Figure 19H shown, the insulating films 122 to 125 on the wiring 112X1 are etched to form an opening H7.

[0203] Subsequently, as Figure 19I shown, for example, the resist film 134 is removed by ashing, and then as Figure 19J shown, for example, the insulating film 121 exposed in the opening H7 is removed by dry etching, thereby exposing the surface of the wiring 112X1. Next, a barrier metal 127A is formed on the side surfaces and bottom surfaces of the openings H6 and H7 by using, for example, sputtering, and then a metal film 127B is formed in the openings H6 and H7 by using, for example, electroplating. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished. As described above, the wiring structure 100A shown in Figure 19K is completed, which does not include the insulating film 123 containing a low dielectric constant material (low-k material) around the coupling portion of the electrically coupled wiring 112X1 and the conductive film 127.

[0204] Generally, in the case of forming an opening for electrically coupling a lower-layer wiring (wiring 112X1) and an upper-layer wiring (conductive film 127) as shown in Figure 1 , as a post-treatment after the opening process, the ashing step of removing the residual resist film is performed under normal temperature conditions.

[0205] Incidentally, as Figure 4 shown, the imaging element 1 includes pad electrodes 58 and 64 for Cu-Cu bonding between the second substrate 20 and the third substrate 30, and the size of the pad electrodes is several μm. From the perspective of cost, the lithography step requires an exposure apparatus that selects a long-wavelength light source. In the case of selecting an exposure apparatus for a long-wavelength light source, a thicker resist film is required. In this case, for example, in the step of removing the resist film after dry etching, ashing in an atmosphere of 200 °C or higher is required.

[0206] As Figure 1 in the wiring structure, in the case where the insulating film 123 including a low dielectric constant material (low-k material) is exposed in the opening (a coupling portion where the electrically coupled wiring 112X1 and the conductive film 127X1 are formed in the opening), the ashing under the high-temperature conditions as described above causes a part of the insulating film 123 to have, for example, Figure 20 shown a bent shape. This is because the methyl group (Si-CH x)And the phenomenon that occurs when the decline of the film is further accelerated by subsequent wet processing.

[0207] In this state, the formation of the barrier metal 127A in the opening H7 deteriorates the coverage of the barrier metal 127A in the bent shape portion and deteriorates the barrier characteristics. If a metal film 127B including, for example, copper (Cu) is embedded in the case of deteriorated barrier characteristics, copper is more likely to diffuse in the insulating film, and concerns about, for example, TDDB (time-dependent dielectric breakdown) increase. In addition, in the deformed bent shape portion, the metal film 127B is more likely to be embedded in a defective manner. For example, this may cause poor conductivity between wirings, etc.

[0208] On the contrary, in this modification, the insulating film 123 around the openings H7 of the electrically coupled wirings 112x1 and the conductive film 127 is removed in advance, and an insulating film 124 including, for example, SiO x is embedded, which has higher ashing resistance than the insulating film 123 containing a low dielectric constant material (low-k material). This enables the formation of the opening H7 having a desired shape. This enables the improvement of Figure 19K the manufacturing yield and electrical reliability of the wiring structure 100A shown in and the imaging device 1 applying the wiring structure 100A.

[0209] (2-2. Modification 2)

[0210] Figures 21A to 21F Each of shows a modification (Modification 2) of the manufacturing steps of the wiring structure (wiring structure 100B) according to the present disclosure.

[0211] First, similar to the above-described embodiment, the surface of the insulating film 124 is planarized, and then the insulating film 125 and the insulating film 126 are formed in sequence ( Figure 3G ). Next, similar to Modification 1 above, a portion of the insulating film 126 and the insulating film 125 is etched to form the opening H6, and then, for example, a resist film 134 having an opening at a position facing the wiring 112X1 is patterned in the opening H6 and on the insulating film 126 by, for example, photolithography. As Figure 21A shown, the insulating films 123 to 126 on the wiring 112X1 are etched to form the opening H7.

[0212] Next, as Figure 21B shown, the resist film 134 is removed, for example, by room-temperature ashing. In the case where the resist film 134 is formed thick, for example, as Figure 21B shown, the resist film 134 having a large formation area sometimes remains partially. Subsequently, as Figure 21CAs shown, for example, a protective film 128 including, for example, SiO is formed on the upper surface of the remaining resist film 134, the upper surface of the insulating film 126, and the side surfaces and bottom surfaces of the openings H6 and H7 by using, for example, an ALD method. x It should be noted that the protective film 128 may include any insulating material as long as the insulating material has ashing resistance. As the material of the protective film 128, in addition to SiO x , for example, SiN, SiCN, etc. may also be used.

[0213] Next, as Figure 21D shown, for example, the protective film 128 formed on the upper surface is removed by etching back the entire surface. Subsequently, as Figure 21E shown, the resist film 134 remaining at the outer peripheral end portion and its vicinity is removed by ashing at a high temperature, and the insulating films 121 and 122 exposed in the opening H7 are removed. In this case, the insulating film 123 including a low dielectric constant material (low-k material) in the opening H7 is covered with the protective film 128, preventing the recession of the insulating film 123 as described above.

[0214] Next, a barrier metal 127A is formed on the side surfaces and bottom surfaces of the openings H6 and H7 by using, for example, sputtering, and then a metal film 127B is formed in the openings H6 and H7 by using, for example, electroplating. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished. As described above, the wiring structure 100B as Figure 21F shown is completed. The wiring structure 100B includes the protective film 128 around the coupling portion that electrically couples the wiring 112X1 and the conductive film 127. This can improve the manufacturing yield and electrical reliability of the wiring structure 100B applied in the above-described modification 1 and the imaging element 1 using the wiring structure 100B.

[0215] (2-3. Modification 3)

[0216] Figures 22A to 22H Each of

[0217] illustrates a modification (modification 3) of the manufacturing steps of a wiring structure (wiring structure 100C) according to the present disclosure. Figure 3G First, as in the above-described embodiment, after forming up to the insulating film 124, the surface of the insulating film 124 is planarized ( Figure 22A )). Subsequently, as

[0218] shown, as in the above-described modification 1, a resist film 135 having an opening is formed at a position on the insulating film 124 facing the wiring 112X1 by photolithography. Figure 22B ​As shown, the insulating films 121 to 124 on the etched wiring 112X1 are etched to form an opening H8, and then the resist film 135 is removed by ashing. In this case, ashing is performed at room temperature, and the insulating film 123 containing a low dielectric constant material (low-k material) does not recede as a result. Subsequently, as Figure 22C shown, a barrier metal 129A is formed on the side surface and bottom surface of the opening H8 and on the insulating film 124 by, for example, sputtering, and then a metal film 129B containing tungsten (W) is formed in the opening H8 and on the barrier metal 129A by, for example, CVD or sputtering.

[0219] Next, as Figure 22D shown, the barrier metal 129A and the metal film 129B on the insulating film 124 are polished and removed by, for example, CMP. Thereby, a coupling portion (via 129) that electrically couples the wiring 112X1 and the conductive film 127 is formed. Subsequently, as Figure 22E shown, for example, an insulating film 125 and an insulating film 126 are formed on the insulating film 124 and the via 129 by, for example, a CVD method, and then as Figure 22F shown, a resist film 136 is patterned on the insulating film 126 by, for example, photolithography. The resist film 136 has openings at positions facing the wirings 112X1 to 112X4 and above the wiring 112X6.

[0220] Next, as [[ID=274 shown, an opening 9 is formed by dry etching. The opening 9 extends through the insulating film 126 and the insulating film 125 and exposes the via 129. Subsequently, as ​ shown, a conductive film 127 (conductive films 127X1 and 127X2) containing a barrier metal 127A and a metal film 127B is formed by using a method similar to that of the above-described modification 2. As described above, the wiring structure 100C is completed, in which the wiring 112X1 and the conductive film 127 are electrically coupled through a via 129 containing tungsten (W). This can improve the manufacturing yield and electrical reliability of the wiring structure 100C applied in the above-described modification 1 and the imaging element 1 using the wiring structure 100C.

[0221] In addition, in this modification, unlike the wiring structure 100A according to the above-described embodiment, the wiring 112X1, the conductive film 127, and the coupling portion (via 129) are not formed simultaneously. However, the coupling portion (via 129) is formed by using tungsten (W). This makes it possible to omit the formation of an insulating film for preventing the diffusion of copper (Cu). An insulating film having a copper diffusion prevention property is a relatively high dielectric constant film having a relative dielectric constant of, for example, 5.0 or more. This increases the effective dielectric constant. In contrast, in this modification, the wiring structure 100C can be formed without increasing the effective dielectric constant.

[0222] (2-4. Variant Example 4)

[0223] ​ Each of to ​ shows a variant example (variant example 4) of the manufacturing steps of the wiring structure (wiring structure 100D) according to the present disclosure.

[0224] First, as shown in ​ , the insulating films 121 to 124 on the wiring 112X1 are etched to form an opening H8, and then the resist film 135 is removed by ashing at room temperature as in the above-described variant example 3. Subsequently, as shown in ​ , a barrier metal 130A is formed on the side surface and bottom surface of the opening H8 and on the insulating film 124 by using, for example, sputtering. Then, a metal film 130B containing, for example, copper (Cu) is formed in the opening H8 and on the barrier metal 130A by, for example, electroplating.

[0225] Next, as shown in ​ , the barrier metal 130A and the metal film 130B on the insulating film 124 are polished and removed by, for example, CMP. This forms a via hole 130 that electrically couples the wiring 112X1 and the conductive film 127. Subsequently, as shown in ​ , insulating films 141, 125, and 126 are sequentially formed on the insulating film 124 and the via hole 130 by, for example, a CVD method. The insulating film 141 is used to prevent the diffusion of copper (Cu). The insulating film 141 has a relative dielectric constant (k) of 5.0 or more, for example. The insulating film 141 is formed by using, for example, silicon nitride (SiN x ) or SiC x N y or the like.

[0226] Subsequently, as shown in ​ , a resist film 137 is patterned on the insulating film 126 by, for example, photolithography. The resist film 137 has openings at positions facing the wirings 112X1 to 112X4 and above the wiring 112X6. Next, as shown in ​ , an opening H9 is formed by, for example, dry etching. The opening H9 extends through the insulating film 126, the insulating film 125, and the insulating film 141 and exposes the via hole 130.

[0227] Subsequently, as shown in ​ ​ ​​​​​​​​​​​​As shown, a conductive film 127 (conductive films 127X1 and 127X2) including a barrier metal 127A and a metal film 127B is formed by using a method similar to the above-described Modification Example 2. As described above, a wiring structure 100D in which wirings 112X1 and the conductive film 127 are electrically coupled is completed without causing the insulating film 123 containing a low dielectric constant material (low-k material) to recede during ashing. This can improve the manufacturing yield and electrical reliability of the wiring structure 100D applied in the above-described Modification Example 1 and the imaging element 1 using the wiring structure 100D.

[0228] (2-5. Modification Example 5)

[0229] ​ An example of a cross-sectional structure in the vertical direction of an imaging element (imaging element 1) according to a modification (Modification Example 5) of the above-described present embodiment is shown. In this modification, the transfer transistor TR includes a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the p-well layer 42 but is formed only on the front surface of the semiconductor substrate 11. Even when the planar transfer gate TG is used for the transfer transistor TR, the imaging element 1 has an effect similar to that of the above-described embodiment.

[0230] (2-6. Modification Example 6)

[0231] ​ An example of a cross-sectional structure in the vertical direction of an imaging element (camera device 1) according to a modification (Modification Example 6) of the above-described present embodiment is shown. In this modification, the second substrate 20 and the third substrate 30 are electrically coupled in a region opposite to the peripheral region 14 on the first substrate 10. The peripheral region 14 corresponds to a frame region of the first substrate 10 and is provided on the periphery of the pixel region 13. In this modification, the second substrate 20 includes a plurality of pad electrodes 58 in a region opposite to the peripheral region 14, and the third substrate 30 includes a plurality of pad electrodes 64 in a region opposite to the peripheral region 14. By joining the pad electrodes 58 and 64 to each other, the second substrate 20 and the third substrate 30 are electrically coupled to each other. The pad electrodes 58 and 64 are provided in a region opposite to the peripheral region 14.

[0232] In this way, in this modification, by joining the pad electrodes 58 and 64 to each other, the second substrate 20 and the third substrate 30 are electrically coupled to each other. The pad electrodes 58 and 64 are provided in a region opposite to the peripheral region 14. Compared with the case where the pad electrodes 58 and 64 are joined to each other in a region opposite to the pixel region 13, this can reduce the possibility of hindering the area reduction of one pixel. Therefore, in addition to the effects of the above-described embodiment, an imaging element 1 having a three-layer structure can be provided, which does not hinder one pixel from having a smaller area while maintaining a chip size equal to that of the existing chip size.

[0233] (2-7. Variant Example 7)

[0234] ​ Shows an example of the cross-sectional structure of the imaging element (camera device 1) according to the variant example (variant example 7) of the above-described present embodiment in the vertical direction. ​ Shows another example of the cross-sectional structure of the imaging element (imaging element 1) according to the variant example (variant example 7) of the above-described present embodiment in the vertical direction. ​ And ​ The upper-side figure of ​ is a variant example of the cross-sectional structure taken along the cross-section Sec1 in ​ and ​ the lower-side figure of ​ is a variant example of the cross-sectional structure taken along the cross-section Sec2 in ​ It should be noted that the figure showing the variant example of the front surface structure of the semiconductor substrate 11 in ​ and ​ is superimposed on the figure showing the variant example of the cross-sectional structure taken along the cross-section Sec1 in ​ and ​ the insulating layer 46 is omitted in the upper-side cross-sectional views of ​ each. In addition, the figure showing the variant example of the front surface structure of the semiconductor substrate 21 is superimposed on

[0235] As Figure 26 and Figure 27 shown, a plurality of through wirings 54, a plurality of through wirings 48, and a through wiring 47 (a plurality of dots arranged in the figure) are arranged side by side in a bar shape in the plane of the first substrate 10 along the first direction V ( Figure 26 and Figure 27 the left / right direction in Figure 26 and Figure 27 each shows as an example the case where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in two rows in the first direction V. Among the four sensor pixels 12 of the shared readout circuit 22, the four floating diffusion portions FD are arranged close to each other with the element isolation portion 43 therebetween, for example. Among the four sensor pixels 12 of the shared readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, and TG4) are arranged to surround the four floating diffusion portions FD, and the four transfer gates TG form a ring shape, for example.

[0236] The insulating layer 53 includes a plurality of blocks extending in the first direction V. The semiconductor substrate 21 extends in the first direction V and includes a plurality of island-shaped blocks 21A arranged side by side in a second direction H orthogonal to the first direction V with the insulating layer 53 interposed therebetween. Each of the blocks 21A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by the four sensor pixels 12 is not arranged to face the four sensor pixels 12 directly, but is arranged to be offset in the second direction H.

[0237] In Figure 26 , one readout circuit 22 shared by the four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL, which are located in a region obtained by offsetting in the second direction H from a region facing the four sensor pixels 12 on the second substrate 20. One readout circuit 22 shared by the four sensor pixels 12 includes, for example, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL in one of the blocks 21A.

[0238] In Figure 27 , one readout circuit 22 shared by the four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG, which are located in a region obtained by offsetting in the second direction H from a region facing the four sensor pixels 12 on the second substrate 20. One readout circuit 22 shared by the four sensor pixels 12 includes, for example, the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD transfer transistor FDG in one of the blocks 21A.

[0239] In this modification example, for example, one readout circuit 22 shared by the four sensor pixels 12 is not arranged to face the four sensor pixels 12 directly, but is arranged to be offset in the second direction H from a position facing the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted, and the source of the amplification transistor AMP and the drain of the selection transistor SEL include a shared impurity region. As a result, the size of the readout circuit 22 can be reduced or the size of other components in the readout circuit 22 can be increased.

[0240] (2-8. Modification Example 8)

[0241] Figure 28 An example of the cross-sectional structure in the horizontal direction of an imaging element (imaging element 1) according to a modification example (modification example 8) of the above embodiment is shown. Figure 28 Shows Figure 14 A modification example of the cross-sectional structure in

[0242] In this modification example, the semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side with an insulating layer 53 interposed therebetween in a first direction V and a second direction H. Each block 21A is provided with, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this case, the insulating layer 53 can suppress crosstalk between adjacent readout circuits 22, thereby suppressing image quality degradation caused by a reduction in the resolution of a reproduced image and color mixing.

[0243] (2-9. Modification Example 9)

[0244] Figure 29 An example of a cross-sectional structure of an imaging element (imaging element 1) according to a modification example (modification example 9) of the present embodiment in a horizontal direction is shown. Figure 29 Shows Figure 28 a modification example of the cross-sectional structure in

[0245] In this modification example, one readout circuit 22 shared by four sensor pixels 12 is not arranged to face the four sensor pixels 12, for example, but is arranged to be offset in the first direction V. Further, in this modification example, similar to modification example 8, the semiconductor substrate 21 includes a plurality of island-shaped blocks 21A, and these island-shaped blocks 21A are arranged side by side with an insulating layer 53 interposed therebetween in the first direction V and the second direction H. Each of the blocks 21A is provided with, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this modification example, a plurality of through wirings 47 and a plurality of through wirings 54 are further uniformly arranged in the second direction H. Specifically, the plurality of through wirings 47 are arranged between four through wirings 54 that share a certain readout circuit 22 and four through wirings 54 that share another readout circuit 22 adjacent to the certain specific readout circuit 22 in the H direction. In this case, the insulating layer 53 and the through wirings 47 can suppress crosstalk between adjacent readout circuits 22, such that image quality degradation caused by a reduction in resolution and color mixing on a reproduced image can be suppressed.

[0246] (2-10. Modification Example 10)

[0247] Figure 30 An example of a cross-sectional structure of an imaging element (imaging element 1) according to a modification example (modification example 10) of the present embodiment in a horizontal direction is shown. Figure 30 Shows Figure 12 a modification example of the cross-sectional structure in

[0248] In this modification example, the first substrate 10 includes a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion portion FD is shared among four sensor pixels 12. Therefore, in this modification example, a through wiring 54 is provided for every four sensor pixels 12.

[0249] Among a plurality of sensor pixels 12 arranged in a matrix, for convenience, the four sensor pixels 12 corresponding to the region obtained by shifting the unit region corresponding to the four sensor pixels 12 sharing a floating diffusion section FD by one sensor pixel 12 in the first direction V are referred to as four sensor pixels 12A. In this case, in the present modification example, the first substrate 10 shares the through-wiring 47 between the four sensor pixels 12A. Therefore, in the present modification example, one through-wiring 47 is provided for every four sensor pixels 12A.

[0250] In the present modification example, the first substrate 10 includes an element isolation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation section 43 does not completely surround the sensor pixel 12. The element isolation section 43 has gaps (unformed regions) near the floating diffusion section FD (through-wiring 54) and near the through-wiring 47. The gaps allow the four sensor pixels 12 to share one through-wiring 54 and allow the four sensor pixels 12A to share one through-wiring 47. In the present modification example, the second substrate 20 includes a readout circuit 22 for every four sensor pixels 12. The four sensor pixels 12 share the floating diffusion section FD.

[0251] Figure 31 Another example of the cross-sectional structure of the imaging element 1 according to the present modification example in the horizontal direction is shown. Figure 31 Shown is Figure 28 a modified example of the cross-sectional structure. In the present modification example, the first substrate 10 includes a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion section FD is shared among the four sensor pixels 12. In addition, the first substrate 10 includes an element isolation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0252] Figure 32 Another example of the cross-sectional structure of the imaging element 1 according to the present modification example in the horizontal direction is shown. Figure 32 Shown is Figure 29 a modified example of the cross-sectional structure. In the present modification example, the first substrate 10 includes a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion section FD is shared among the four sensor pixels 12. In addition, the first substrate 10 includes an element isolation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0253] (2-11. Modification Example 11)

[0254] Figure 33Shows an example of the circuit configuration of an imaging element (imaging element 1) according to the present embodiment and modification examples 5 to 6 (modification example 11) above. The imaging element 1 according to this modification example is a CMOS image sensor equipped with a column-parallel ADC.

[0255] As Figure 33 shown, in addition to the pixel region 13 where a plurality of sensor pixels 12 are two-dimensionally formed in a matrix (matrix shape), the imaging element 1 according to this modification example further includes a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36. Each of the plurality of sensor pixels 12 includes a photoelectric conversion unit.

[0256] In this system configuration, based on the main clock MCK, the system control circuit 36 generates clock signals or control signals, etc., which serve as operation references for the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., and supplies the clock signals or control signals, etc., to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0257] Furthermore, the vertical drive circuit 33 is formed together with each sensor pixel 12 of the pixel region 13 on the first substrate 10, and is even further formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 are formed on the third substrate 30.

[0258] Although not shown here, for example, a component that includes a transfer transistor TR in addition to a photodiode PD can be used as the sensor pixel 12, and the transfer transistor TR transfers the charge obtained by the photoelectric conversion of the photodiode PD to the floating diffusion section FD. Furthermore, although not shown here, as the readout circuit 22, for example, a component having a three-transistor structure can be used, which includes a reset transistor RST that controls the potential of the floating diffusion section FD, an amplification transistor AMP that outputs a signal corresponding to the potential of the floating diffusion section FD, and a selection transistor SEL for selecting a pixel.

[0259] In the pixel region 13, the sensor pixels 12 are two-dimensionally arranged. Regarding this m-row and n-column pixel structure, pixel drive lines 23 are connected to respective rows, and vertical signal lines 24 are connected to respective columns. Each end of the plurality of pixel drive lines 23 is coupled to the corresponding output end of the row of the vertical drive circuit 33. The vertical drive circuit 33 includes a shift register, etc., and controls the row address and row scanning of the pixel region 13 through the plurality of pixel drive lines 23.

[0260] The column signal processing circuit 34 includes, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for respective pixel columns or respective vertical signal lines 24 of the pixel region 13. The column signal processing circuit 34 converts the analog signals output column by column from the respective sensor pixels 12 of the pixel region 13 into digital signals and outputs the digital signals.

[0261] The reference voltage supply unit 38 includes, for example, a DAC (digital-to-analog conversion circuit) 38A as a device for generating a reference voltage Vref having a so-called ramp waveform with a level that changes in an inclined manner over time. It should be noted that the device for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0262] Under the control of the control signal CS1 provided by the system control circuit 36, the DAC 38A generates the reference voltage Vref having a ramp waveform based on the clock CK provided by the system control circuit 36 and supplies the generated reference voltage Vref to each of the ADCs 34-1 to 34-m of the column signal processing circuit 34.

[0263] It should be noted that each of the ADCs 34-1 to 34-m is configured to selectively perform an AD conversion operation corresponding to each of the operation modes in the normal frame rate mode and the high-speed frame rate mode. The normal frame rate mode in the progressive scan system is used to read information of all the sensor pixels 12. Compared with the normal frame rate mode, the high-speed frame rate mode is used to set the exposure time of the sensor pixels 12 to 1 / N to increase the frame rate by N times (for example, twice). This switching between the operation modes is performed according to the control executed by the control signals CS2 and CS3 provided by the system control circuit 36. In addition, instruction information for switching between the operation modes of the normal frame rate mode and the high-speed frame rate mode is provided from an external system controller (not shown) to the system control circuit 36.

[0264] All of the ADCs 34-1 to 34-m have the same configuration. Here, the ADC 34-m is taken as an example for description. The ADC 34-m includes a comparator 34A, an up / down counter (referred to as U / D CNT in the figure) 34B as a counting device, a transmission switch 34C, and a memory 34D.

[0265] Comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signals output from each sensor pixel 12 in the n-th column of the pixel region 13 with the reference voltage Vref of the ramp waveform provided from the reference voltage supply unit 38. For example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco goes to the "H" level. When the reference voltage Vref is equal to or less than the signal voltage Vx, the output voltage Vco goes to the "L" level.

[0266] The up / down counter 34B is an asynchronous counter. Under the control of the control signal CS2 provided by the system control circuit 36, the up / down counter 34B is supplied with the clock CK from the system control circuit 36 simultaneously with the DAC 18A. The up / down counter 34B performs down (DOWN) counting or up (UP) counting synchronously with the clock CK, thereby measuring the comparison period from the start to the end of the comparison operation in the comparator 34A.

[0267] Specifically, in the read operation of the signal from one sensor pixel 12, down counting is performed at the first read operation in the normal frame rate mode, thereby measuring the comparison time at the first read. Up counting is performed at the second read operation, thereby measuring the comparison time at the second read.

[0268] Meanwhile, when in the high-speed frame rate mode, the counting result of the sensor pixel 12 in a specific row is held. Subsequently, at the first read operation from the previous counting result, down counting is performed on the sensor pixel 12 in the next row, thereby measuring the comparison time at the first read. Up counting is performed at the second read operation, thereby measuring the comparison time at the second read.

[0269] Under the control of the control signal CS3 provided by the system control circuit 36, after the counting operation of the up / down counter 34B of the sensor pixel 12 is completed, the transfer switch turns on (closes) in the normal frame rate mode, and the counting result of the up / down counter 34B is transferred to the memory 34D.

[0270] Meanwhile, for example, in the high-speed frame rate with N = 2, when the counting operation of the up / down counter 34B of the sensor pixel 12 in a specific row is completed, the transfer switch 34C remains off (open). Subsequently, it turns on when the counting operation of the up / down counter 34B of the sensor pixel 12 in the next row is completed. The transfer switch 34C transfers the counting results of the up / down counters 34B of two vertical pixels to the memory 34D.

[0271] In this way, the analog signals supplied to the respective columns from the respective sensor pixels 12 in the pixel region 13 through the vertical signal lines 24 are converted into N-bit digital signals by the corresponding operations of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m and stored in the memory 34D.

[0272] The horizontal drive circuit 35 includes a shift register or the like and controls the column addresses and column scans of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the N-bit digital signals AD-converted in the respective ADCs 34-1 to 34-m are sequentially read out to the horizontal output line 37 and output as imaging data through the horizontal output line 37.

[0273] It should be noted that, in addition to the above components, a circuit or the like that performs various signal processes on the imaging data output through the horizontal output line 37 may be provided, but since it has no direct relation to the present disclosure, it is not particularly described.

[0274] In the imaging element 1 equipped with the column-parallel ADC according to this modification having the above structure, the counting result of the up / down counter 34B can be selectively transmitted to the memory 34D through the transmission switch 34C. This enables independent control of the counting operation of the up / down counter 34B and the reading operation of the counting result of the up / down counter 34B to the horizontal output line 37.

[0275] (2-12. Modification 12)

[0276] Figure 34 An example is shown in which Figure 33 the imaging element in includes three stacked substrates (the first substrate 10, the second substrate 20, and the third substrate 30). In this modification, the pixel region 13 is formed in the middle part of the first substrate 10. The vertical drive circuit 33 is formed around the pixel region 13. A pixel region 13 including a plurality of sensor pixels 12 is formed. In addition, the readout circuit region 15 is formed in the middle part of the second substrate 20. The vertical drive circuit 33 is formed around the readout circuit region 15. The readout circuit region 15 includes a plurality of readout circuits 22. In the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed. Therefore, similarly to the above-described embodiments and their modifications, the chip size is not increased due to the structure for electrically coupling the substrates to each other, and the miniaturization of the area of one pixel is not hindered. Thus, it is possible to provide an imaging element 1 having a three-layer structure that has the same chip size as the existing one while not hindering one pixel from having a smaller area. Note that the vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0277] (2-13. Variation 13)

[0278] Figure 35 An example of the cross-sectional structure of the imaging element (imaging element 1) according to the present embodiment and Variations 5 to 12 (Variation 13) described above is shown. In the above-described embodiment and its Variations 5 to 12, the imaging element 1 includes three stacked substrates (first substrate 10, second substrate 20, and third substrate 30). However, as in the imaging elements 5 and 6 according to the above-described Fifth Embodiment, the imaging element may include two stacked substrates (first substrate 10 and second substrate 20). In this case, for example, as Figure 35 shown, logic circuits 32 can be formed on the first substrate 10 and the second substrate 20, respectively. Here, the circuit 32A of the logic circuit 32 is provided with a transistor having a gate structure, in which a high-k dielectric film including a material (e.g., high-k) capable of withstanding high-temperature processing and a metal gate electrode are stacked. The circuit 32A is provided on the first substrate 10 side. At the same time, in the circuit 32B provided on the second substrate 20 side, a low-resistance region 26 including a silicide and formed by using a Salicide (self-aligned silicide) process such as CoSi2 and NiSi is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region including the silicide is formed by using a compound of a semiconductor substrate material and a metal. This enables the formation of the sensor pixel 12 by using a high-temperature process such as thermal oxidation. In addition, in the circuit 32B of the logic circuit 32, when the low-resistance region 26 including the silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. The circuit 32B is provided on the second substrate 20 side. As a result, the speed of arithmetic operations in the logic circuit 32 can be increased.

[0279] (2-14. Variation 14)

[0280] Figure 36 A variation of the cross-sectional structure according to the present embodiment and Variations 5 to 12 (Variation 14) is shown. In the logic circuit 32 of the third substrate 30 according to any one of the above-described embodiment and its Variations 5 to 12, a low-resistance region 37 including a silicide and formed by using a Salicide (self-aligned silicide) process such as CoS2 and NiSi can be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. This enables the formation of the sensor pixel 12 by using a high-temperature process such as thermal oxidation. In addition, when the low-resistance region 37 including the silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32, the contact resistance can be reduced. As a result, the speed of arithmetic operations in the logic circuit 32 can be increased.

[0281] Note that in the above-described embodiments and their modification examples 5 to 14, the conduction types may be opposite. For example, in the description of the above-described embodiments and their modification examples 5 to 14, the P-type may be replaced with the n-type, and the n-type may be replaced with the p-type. Even in such a case, effects similar to those of the above-described embodiments and their modification examples 5 to 14 can be obtained.

[0282] <3. Application Example>

[0283] Figure 37 An example of a schematic configuration of an imaging system 7 including an imaging element (imaging element 1) according to any of the above-described embodiments and their modification examples 5 to 14 is shown.

[0284] The imaging system 7 is an electronic device including, for example, an imaging element such as a digital camera or a video camera, and a portable terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, an optical system 241, a shutter unit 242, an imaging element 1, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the shutter unit 242, the imaging element 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are coupled to each other via a bus 249.

[0285] The imaging element 1 outputs image data corresponding to incident light. The optical system 241 includes one or more lenses and guides light (incident light) from an object to the imaging element 1 to form an image on the light receiving surface of the imaging element 1. The shutter unit 242 is provided between the optical system 241 and the imaging element 1, and controls the period during which the imaging element 1 is irradiated with light and the period during which it is shielded from light under the control of the operation unit 247. The DSP circuit 243 is a signal processing circuit that processes signals (image data) output from the imaging element 1. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in frame units. The display unit 245 includes, for example, a panel-type display unit such as a liquid crystal panel or an organic EL (electroluminescence) panel, and displays a moving image or a still image captured by the imaging element 1. The storage unit 246 records the image data of the moving image or the still image captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation instructions for various functions of the imaging system 7 according to user operations. The power supply unit 248 appropriately supplies power for various operations to the imaging element 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 as supply targets.

[0286] Next, the imaging process in the imaging system 7 is described.

[0287] Figure 38 FIG. 1 shows an example of a flowchart of an imaging operation in the imaging system 7. The user issues a command to start imaging by operating the operation unit 247 (step S101). Then, the operation unit 247 sends an imaging command to the imaging element 1 (step S102). After receiving the imaging command, the imaging element 1 (specifically, the system control circuit 36) performs imaging according to a predetermined imaging scheme (step S103).

[0288] The imaging element 1 outputs light (image data) formed on the light receiving surface through the optical system 241 and the shutter unit 242 to the DSP circuit 243. Here, the image data refers to data of pixel signals of all pixels generated based on the charges temporarily held in the floating diffusion section FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) according to the image data input from the imaging element 1 (step S104). The DSP circuit 243 causes the frame memory 244 to store the image data that has undergone the predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). Thus, imaging in the imaging system 7 is performed.

[0289] In this application example, the imaging device 1 is applied to the imaging system 7. This enables the imaging element 1 to be smaller or have a higher resolution. This makes it possible to provide a miniaturized or high-resolution imaging system 7.

[0290] Figure 39 FIG. 2 is a diagram showing an overview of a configuration example of a non-stack type solid-state imaging element (solid-state imaging element 23210) and a stack type solid-state imaging element (solid-state imaging element 23020) to which the technology according to the present invention can be applied.

[0291] Figure 39 A in FIG. 2 shows a schematic configuration example of a non-stack type solid-state imaging element. As shown in Figure 39 A in FIG. 2, the solid-state imaging element 23010 includes a single chip (semiconductor substrate) 23011. The chip 23011 is mounted with a pixel region 23012 in which pixels are arranged in an array, a control circuit 23013 for driving the pixels and performing any other various controls, and a logic circuit 23014 for signal processing.

[0292] Figure 39 B and C in FIG. 2 show schematic configuration examples of a stack type solid-state imaging element. As shown in Figure 39 B and C in FIG. 2, in the solid-state imaging element 23020, two chips, a sensor chip 23021 and a logic chip 23024, are stacked and electrically coupled to form a single semiconductor chip. These sensor chip 23021 and logic chip 23024 correspond to specific examples of the "first substrate" and "second substrate" according to the present invention.

[0293] In Figure 39 of B, the sensor chip 23021 is equipped with the pixel region 23012 and the control circuit 23013, and the logic chip 23024 is equipped with the logic circuit 23014 including the signal processing circuit that performs signal processing. In addition, the sensor chip 23021 may also be equipped with the above-mentioned readout circuit 22 or the like.

[0294] In Figure 39 of C, the sensor chip 23021 is equipped with the pixel region 23012 and the logic chip 23024 is equipped with the control circuit 23013 and the logic circuit 23014.

[0295] Figure 40 is a cross-sectional view showing a first structural example of the stacked solid-state imaging device 23020.

[0296] In the sensor chip 23021, PD (photodiode), FD (floating diffusion section), Tr (MOSFET), and Tr serving as the control circuit 23013 are formed in each pixel that is the pixel region 23012. In addition, the wiring layer 23101 including the wiring 23110 having a plurality of layers is formed in the sensor chip 23021. In this example, the wiring 23110 includes three layers. It should be noted that the control circuit 23013 (Tr serving as the control circuit 23013) may be included in the logic chip 23024 instead of the sensor chip 23021.

[0297] The Tr included in the logic circuit 23014 is formed in the logic chip 23024. In addition, the wiring layer 23161 including the wiring 23170 having a plurality of layers is formed in the logic chip 23024. In this example, the wiring 23170 includes three layers. In addition, the coupling hole 23171 is formed in the logic chip 23024, and the insulating film 23172 is formed on the inner wall surface of the coupling hole 23171. The coupling hole 23171 is filled with the interconnect conductor 23173 that is coupled to the wiring 23170 or the like.

[0298] The sensor chip 23021 and the logic chip 23024 are joined together in a state where their wiring layers 23101 and 23161 face each other. This forms the stacked solid-state imaging device 23020 in which the sensor chip 23021 and the logic chip 23024 are stacked. A film 23191 such as a protective film is formed on the surface where the sensor chip 23021 and the logic chip 23024 are joined together.

[0299] A coupling hole 23111 is formed in the sensor chip 23021. The coupling hole 23111 extends through the sensor chip 23021 from the back surface side (the side where light enters the PD) (the upper side) of the sensor chip 23021 and reaches the uppermost layer of the wiring 23170 of the logic chip 23024. Further, a coupling hole 23121 is formed in the sensor chip 23021. The coupling hole 23121 is close to the coupling hole 23111 and reaches the first layer of the wiring 23110 from the back surface side of the sensor chip 23021. An insulating film 23112 is formed on the inner wall surface of the coupling hole 23111, and an insulating film 23122 is formed on the inner wall surface of the coupling hole 23121. Then, the coupling holes 23111 and 23121 are filled with interconnect conductors 23113 and 23123, respectively. The interconnect conductor 23113 and the interconnect conductor 23123 are electrically coupled on the back surface side of the sensor chip 23021. The sensor chip 23021 and the logic chip 23024 are electrically coupled through the wiring layer 23101, the coupling hole 23121, the coupling hole 23111, and the wiring layer 23161.

[0300] Figure 41 FIG. is a cross-sectional view showing a second structural example of the stacked solid-state imaging device 23020.

[0301] In the second structural example of the solid-state imaging device 23020, one coupling hole 23211 formed in the sensor chip 23021 electrically couples the wiring layer 23101 (the wiring 23110) of the sensor chip 23021 and the wiring layer 23161 (the wiring 23170) of the logic chip 23024.

[0302] In other words, in Figure 41 the coupling hole 23211 is formed to extend through the sensor chip 23021 from the back surface side of the sensor chip 23021 and reach the uppermost layer of the wiring 23170 of the logic chip 23024, and also reach the uppermost layer of the wiring 23110 of the sensor chip 23021. An insulating film 23212 is formed on the inner wall surface of the coupling hole 23211, and the coupling hole 23211 is filled with an interconnect conductor 23213. In the above Figure 40 the sensor chip 23021 and the logic chip 23024 are electrically coupled through two coupling holes 23111 and 23121, but in Figure 41 the sensor chip 23021 and the logic chip 23024 are electrically coupled through one coupling hole 23211.

[0303] Figure 42 FIG. is a cross-sectional view showing a third structural example of the stacked solid-state imaging device 23020.

[0304] Figure 42 The solid-state imaging device 23020 inFigure 40 The difference in the case is that a film 23191 such as a protective film is not formed on the surface where the sensor chip 23021 and the logic chip 23024 are joined together. In Figure 40 the case, a film 23191 such as a protective film is formed on the surface where the sensor chip 23021 and the logic chip 23024 are joined together.

[0305] Figure 42 The solid-state imaging device 23020 in

[0306] Figure 43 is formed by directly contacting the wirings 23110 and 23170 to laminate the sensor chip 23021 and the logic chip 23024, and applying a required load and heating them to directly join the wirings 23110 and 23170.

[0307] In Figure 43 , the solid-state imaging device 23401 has a three-layer stacked structure in which three chips, namely, a sensor chip 23411, a logic chip 23412, and a memory chip 23413, are stacked.

[0308] The memory chip 23413 includes, for example, a memory circuit that stores data. This data is temporarily required in the signal processing performed in the logic chip 23412.

[0309] In Figure 43 , the logic chip 23412 and the memory chip 23413 are stacked in this order below the sensor chip 23411, but the logic chip 23412 and the memory chip 23413 can be stacked in the reverse order below the sensor chip 23411. In other words, the memory chip 23413 and the logic chip 23412 can be stacked in the following order.

[0310] Note that in Figure 43 , a PD, which is a photoelectric conversion unit serving as a pixel, and source / drain regions of pixel Trs are formed in the sensor chip 23411.

[0311] A gate electrode is formed around the PD with a gate insulating film interposed therebetween. The gate electrode and the paired source / drain regions form pixel Trs 23421 and 23422.

[0312] The pixel Tr 23421 adjacent to the PD is a transfer Tr, and one of the paired source / drain regions included in the pixel Tr 23421 is an FD.

[0313] In addition, an interlayer insulating film is formed in the sensor chip 23411, and coupling holes are formed in the interlayer insulating film. Interconnect conductors 23431 connected to the pixel Tr 23421 and the pixel Tr 23422 are formed in the coupling holes.

[0314] In addition, a wiring layer 23433 including wirings 23432 connected to each of the interconnect conductors 23431 is formed in the sensor chip 23411. The wirings 23432 include multiple layers.

[0315] Furthermore, aluminum pads 23434 serving as external coupling electrodes are formed in the lowermost layer of the wiring layer 23433 in the sensor chip 23411. In other words, the aluminum pads 23434 are formed at positions closer to the bonding surface 23440 with the logic chip 23412 than the wirings 23432 in the sensor chip 23411. The aluminum pads 23434 serve as ends of wirings for inputting and outputting signals from the outside.

[0316] In addition, contacts 23441 are formed in the sensor chip 23411. The contacts 23441 are used for electrical coupling to the logic chip 23412. The contacts 23441 are coupled to the contacts 23451 in the logic chip 23412 and are also coupled to the aluminum pads 23442 in the sensor chip 23411.

[0317] In the sensor chip 23411, pad holes 23443 are formed to reach the aluminum pads 23442 from the back surface side (upper side) of the sensor chip 23411.

[0318] The technology according to the present disclosure is applicable to the solid-state imaging device as described above. For example, the wiring 23110 or the wiring layer 23161 may be provided with, for example, the above-described multiple pixel driving lines 23 and multiple vertical signal lines 24. In this case, as Figure 1 shown, a gap G is formed between the wirings of the multiple vertical signal lines 24. This can reduce the capacitance between the wirings. In addition, suppressing the increase in the capacitance between the wirings enables the reduction of the deviation of the wiring capacitance.

[0319] <4. Practical Application Examples>

[0320] (Practical Application Example 1)

[0321] The technology (this technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure can be implemented as a device installed in any type of moving body such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0322] Figure 44FIG. is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0323] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. In Figure 44 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as functional configurations of the integrated control unit 12050.

[0324] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a driving force generation device that generates the driving force of the vehicle, such as an internal combustion engine or a drive motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle.

[0325] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights (such as headlights, reverse lights, brake lights, turn signal lights, or fog lights). In this case, radio waves or signals from various switches transmitted from a mobile device that replaces the key can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle door lock device, electric window device, lights, etc.

[0326] The outside vehicle information detection unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside vehicle information detection unit 12030 is connected to a camera unit 12031. The outside vehicle information detection unit 12030 causes the camera unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside vehicle information detection unit 12030 can perform detection processing on objects such as people, vehicles, obstacles, signs, words on the road surface, etc., or perform processing to detect their distances.

[0327] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information related to the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

[0328] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver, or can determine whether the driver is dozing off.

[0329] The microcomputer 12051 can calculate control target values for a driving force generation device, a steering mechanism, or a braking device based on information about the interior or exterior of the vehicle obtained through the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), which includes collision avoidance or impact mitigation of the vehicle, following driving based on the following distance, constant speed cruise, vehicle collision warning, vehicle lane departure warning, etc.

[0330] In addition, the microcomputer 12051 can perform cooperative control for autonomous driving by controlling a driving force generation device, a steering mechanism, and a braking device based on information about the exterior or interior of the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, so that the vehicle can travel autonomously without relying on the operation of the driver.

[0331] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the out-vehicle information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control to prevent glare by changing the high beam to the low beam by controlling the headlamp according to the position of the vehicle ahead or the oncoming vehicle detected by the out-vehicle information detection unit 12030.

[0332] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of notifying information visually or audibly to the occupants of the vehicle or the outside of the vehicle. Figure 44In the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0333] Figure 45 FIG. shows an example of the installation position of the imaging unit 12031.

[0334] In Figure 45 the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0335] The imaging units 12101, 12102, 12103, 12104, and 12105 are arranged, for example, at positions on the front nose, rearview mirror, rear bumper, and rear door of the vehicle 12100 and at a position above the windshield inside the vehicle. The imaging unit 12101 arranged on the front nose and the imaging unit 12105 arranged above the windshield inside the vehicle mainly acquire images of the front part of the vehicle 12100. The imaging units 12102 and 12103 arranged on the rearview mirror mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 arranged on the rear bumper or the rear door mainly acquires images of the rear part of the vehicle 12100. The imaging unit 12105 arranged above the windshield inside the vehicle is mainly used to detect a vehicle ahead, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0336] Incidentally, Figure 45 FIG. shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 arranged on the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 arranged on the rearview mirror, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 arranged on the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0337] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0338] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object that exists particularly on the traveling path of the vehicle 12100 and travels in a direction substantially the same as that of the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h) as the preceding vehicle. In addition, the microcomputer 12051 can preset the following distance to be maintained with the preceding vehicle and perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, it is possible to perform cooperative control for autonomous driving, which enables the vehicle to travel autonomously without relying on the operations of the driver or the like.

[0339] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatically avoiding obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or greater than the set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062 and performs forced deceleration or avoidance steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0340] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may identify a pedestrian, for example, by determining whether there is a pedestrian in the images captured by the imaging units 12101 to 12104. The identification of such a pedestrian is performed, for example, through the following process: extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras; and performing feature matching processing on a series of feature points representing the outline of the object to determine whether it is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square outline for emphasis so that it is superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing the pedestrian or the like is displayed at a desired position.

[0341] Examples of a mobile body control system to which the technology according to the present disclosure can be applied have been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above components. Specifically, the imaging elements 1 according to the above-described embodiments and their modifications are all applicable to the imaging unit 12031. Applying the technology according to the present invention to the imaging unit 12031 enables acquisition of a high-resolution captured image with less noise, and thus enables high-precision control to be performed using the captured image in the mobile body control system.

[0342] (Practical Application Example 2)

[0343] Figure 46 is a view showing an example of a schematic configuration of an endoscopic surgery system to which the technology (this technology) according to the embodiments of the present disclosure can be applied.

[0344] In Figure 46 it shows a state in which a surgeon (physician) 11131 is performing surgery on a patient 11132 on a hospital bed 11133 using an endoscopic surgery system 11000. As shown, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are loaded.

[0345] The endoscope 11100 includes an endoscope tube 11101 having a region of a predetermined length starting from its distal end for insertion into the body cavity of a patient 11132; and a camera 11102 connected to the proximal end of the endoscope tube 11101. In the illustrated example, the endoscope 11100 including the endoscope tube 11101 having a rigid type is illustrated as a rigid endoscope. However, the endoscope 11100 may also include an endoscope tube 11101 of a flexible type as a flexible endoscope.

[0346] The endoscope tube 11101 has an opening at its distal end, and an objective lens is mounted in the opening. A light source device 11203 is connected to the endoscope 11100 such that the light generated by the light source device 11203 is introduced into the distal end of the endoscope tube 11101 through an optical fiber extending inside the endoscope tube 11101 and irradiated toward an observation target in the body cavity of the patient 11132 through the objective lens. Note that the endoscope 11100 may be a forward-view endoscope, or may be an oblique-view endoscope or a side-view endoscope.

[0347] An optical system and an imaging element are provided inside the camera 11102 such that the reflected light (observation light) from the observation target is converged on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as RAW data.

[0348] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives the image signal from the camera 11102 and performs various image processes such as a development process (demosaicing process) on the image signal, for example, for displaying an image based on the image signal.

[0349] The display device 11202 displays an image based on the image signal that has been subjected to image processing by the CCU 1121 under the control of the CCU 11201.

[0350] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED), and the irradiation light at the time of imaging the surgical area is supplied to the endoscope 11100.

[0351] The input device 11204 is an input interface for the endoscope surgical system 11000. A user can perform the input of various information or instructions input to the endoscope surgical system 11000 through the input device 11204. For example, the user can input instructions or the like to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0352] The treatment tool control device 11205 controls the drive of the energy device 11112 to perform cauterization or cutting of tissues, sealing of blood vessels, etc. The pneumoperitoneum device 11206 sends gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the viewing field of the endoscope 11100 and ensuring the working space for the surgeon. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, images, or graphics.

[0353] Note that when photographing the surgical site, the light source device 1203 that provides illumination light to the endoscope 11100 may include a white light source, which includes, for example, an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output time can be controlled with high precision for each color (each wavelength), the light source device 11203 can perform adjustment of the white balance of the captured image. In addition, in this case, if the laser beams from the respective RGB laser sources are irradiated on the observation target in a time-division manner and the drive of the imaging element of the camera 11102 is controlled in synchronization with the irradiation time. Then it is also possible to capture images corresponding to the R, G, and B colors respectively in a time-division manner. According to this method, a color image can be obtained even without providing a color filter for the imaging element.

[0354] In addition, the light source device 11203 can be controlled so that the light intensity to be output changes at predetermined intervals. By controlling the drive of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity, thereby obtaining images in a time-division manner and synthesizing the images, a high-dynamic-range image can be created, such an image having no occluding shadows of underexposure and no highlights of overexposure.

[0355] In addition, the light source device 11203 can be configured to provide light in a predetermined wavelength band for special light observation. In special light observation, for example, by utilizing the wavelength dependence of the absorption of light in body tissues, light having a narrower irradiation band than the irradiation light (i.e., white light) during normal observation is irradiated to perform narrow-band observation (narrow-band imaging) of imaging a predetermined tissue such as blood vessels in the surface layer portion of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation can be performed by irradiating excitation light to generate fluorescence to obtain an image. In fluorescence observation, fluorescence from human tissue can be observed by irradiating excitation light onto human tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into human tissue and irradiating excitation light corresponding to the fluorescence wavelength of the reagent onto human tissue. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for special light observation as described above.

[0356] Figure 47 is a block diagram showing Figure 46 an example of the functional configuration of the camera 11102 and the CCU 11201 shown therein.

[0357] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are interconnected via a transmission cable 11400 for communication.

[0358] The lens unit 11401 is an optical system provided at the connection position with the lens barrel 11101. Observation light incident from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of multiple lenses, including a zoom lens and a focusing lens.

[0359] The number of imaging elements included in the imaging unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the imaging unit 11402 is configured as a multi-board type, for example, image signals corresponding to R, G, and B are generated by the imaging elements, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 may also be configured to have a pair of imaging elements for acquiring a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. Note that in the case where the imaging unit 11402 is configured as a multi-board type, a system in which multiple lens units 11401 are provided corresponding to the respective imaging elements.

[0360] In addition, the imaging unit 11402 does not have to be provided on the camera 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.

[0361] The drive unit 11403 includes an actuator and, under the control of the camera control unit 11405, moves the zoom lens and the focusing lens of the lens unit 11401 a predetermined distance along the optical axis. Accordingly, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0362] The communication unit 11404 includes a communication device for transmitting various information to the CCU 11201 and receiving various information from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 as RAW data through the transmission cable 11400.

[0363] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201 and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, for example, information specifying the frame rate of the captured image, information specifying the exposure value at the time of image capture, and / or information specifying the magnification and focus at the time of image capture.

[0364] It should be noted that imaging conditions such as the frame rate, exposure value, magnification, or focus can be specified by the user or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is built with an automatic exposure (AE) function, an automatic focusing (AF) function, and an automatic white balance (AWB) function.

[0365] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0366] The communication unit 11411 includes a communication device for transmitting various information to the camera 11102 and receiving various information from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 to it through the transmission cable 11400.

[0367] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0368] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data transmitted from the camera 11102.

[0369] The control unit 11413 performs various controls related to imaging the surgical area, etc. through the endoscope 11100 and displaying the captured image obtained by imaging the surgical area, etc. For example, the control unit 11413 creates a control signal for controlling the driving of the camera 11102.

[0370] In addition, the control unit 11413 controls the display device 11202 to display a captured image that images a surgical area or the like based on an image signal on which image processing has been performed by the image processing unit 11412. Then, the control unit 11413 can use various image recognition techniques to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, a specific living body area, bleeding, and fog when using the energy device 11112 by detecting the shape and color of the object edges included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical support information in a superimposed manner with the image of the surgical area. In the case where the surgical support information is displayed in a superimposed manner and provided to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0371] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 to each other is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable for both electrical communication and optical communication.

[0372] Here, although in the illustrated example, communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 can be performed by wireless communication.

[0373] Examples of the endoscopic surgery system to which the technology according to the present disclosure can be applied have been described above. The technology according to the present disclosure can be smoothly applied to the imaging unit 11402 of the camera 11102 provided to the endoscope 11100 among the above components. Applying the technology according to the present invention to the imaging unit 11402 enables miniaturization or higher resolution of the imaging unit 11402, and thus enables the provision of a small or high-resolution endoscope 11100.

[0374] Although the present disclosure has been described above with reference to the embodiments, their modification examples 1 to 14, their application examples, and their practical application examples, the present disclosure is not limited to the above embodiments and the like. Various modifications can be made. For example, in any of the above modification examples 1 to 4, the method of manufacturing the wiring structure 100 is described as a modification example of the wiring structure 100 having the gap G between the wirings as described in the above embodiments, but the present technology is applicable to a wiring structure using an insulating film containing a dielectric constant material (Low-k material), regardless of whether there is a gap G between the wirings. Effects similar to those of the above modification examples 1 to 4 can be obtained.

[0375] In addition, in the above-described embodiments and the like, an example in which a plurality of pixel driving lines 23 extend in the row direction and a plurality of vertical signal lines extend in the column direction has been described. However, the plurality of pixel driving lines 23 and the plurality of vertical signal lines may both extend in the same direction. In addition, the pixel driving lines 23 may appropriately extend in different directions (e.g., the vertical direction).

[0376] In addition, in the above-described embodiments and the like, the present technology has been described by using an imaging element having a three-dimensional structure as an example, but this is not restrictive. The present technology is applicable to any three-dimensional stacked semiconductor device that has been integrated on a large scale (LSI).

[0377] Note that the effects described herein are merely exemplary. The effects according to the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than those described herein.

[0378] It should be noted that the present invention may also have the following configuration. According to the present technology having the following configuration, a first insulating film is provided on a first wiring layer, and the first wiring layer includes a plurality of first wirings extending in one direction. In addition, a second insulating film having a flat surface is provided. This enables a first conductive film to be formed at a position facing at least a part of the plurality of first wirings, and a first insulating film and a second insulating film are formed between the first conductive film and the first wiring. The first insulating film forms a gap between the plurality of adjacent first wirings. The first conductive film can be used as, for example, a pad electrode for bonding. This enables the length of the through-wiring extending in the stacking direction, for example, to be reduced, and the wiring capacitance to be reduced.

[0379] (1) An imaging element, the imaging element comprising:

[0380] A first wiring layer including a plurality of first wirings extending in one direction;

[0381] A first insulating film laminated on the first wiring layer, the first insulating film forming a gap between the plurality of adjacent first wirings;

[0382] A second insulating film laminated on the first insulating film, the second insulating film having a flat surface; and

[0383] A first conductive film facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween. (2)

[0385] The imaging element according to (1), wherein the first insulating film has irregularities above the plurality of first wirings. (3)

[0387] The imaging element according to (1) or (2) further includes a coupling portion that penetrates the first insulating film and the second insulating film, and the coupling portion electrically couples a part of the plurality of first wirings to the first conductive film. (4)

[0389] The imaging element according to (3), wherein the coupling portion is formed integrally with the first conductive film. (5)

[0391] The imaging element according to (3) or (4), wherein the coupling portion is formed by using a material different from the material of the first conductive film. (6)

[0393] The imaging element according to any one of (3) to (5), wherein an insulating film different from the first insulating film is formed around the coupling portion. (7)

[0395] The imaging element according to any one of (1) to (6) further includes a third insulating film, wherein

[0396] the first conductive film is formed to be embedded in the third insulating film, and a surface of the first conductive film forms a plane flush with the third insulating film. (8)

[0398] The imaging element according to any one of (1) to (7), wherein the first insulating film is formed by using a low dielectric constant material having a relative dielectric constant k of 3.0 or less. (9)

[0400] The imaging element according to any one of (1) to (8), wherein the second insulating film is formed by using a material having a higher polishing rate than that of the first insulating film. (10)

[0402] The imaging element according to any one of (1) to (8), wherein the second insulating film is formed by using silicon oxide (SiOx), SiOC, SiOF, or SiON. (11)

[0404] The imaging element according to any one of (7) to (10) further includes a fourth insulating film located between the second insulating film and the third insulating film, and the fourth insulating film corrects warping. (12)

[0406] The imaging element according to any one of (1) to (11) further includes:

[0407] A first substrate, the first substrate including sensor pixels on a first semiconductor substrate, the sensor pixels performing photoelectric conversion;

[0408] A second substrate, the second substrate including a readout circuit on a second semiconductor substrate, the readout circuit outputting a pixel signal based on charges output from the sensor pixels; and

[0409] A third substrate, the third substrate including at least one of a logic circuit and a storage circuit on a third semiconductor substrate, the logic circuit processing the pixel signal, the storage circuit holding the pixel signal, wherein,

[0410] The first substrate, the second substrate, and the third substrate are stacked in this order. (13)

[0412] The imaging element according to (12), wherein,

[0413] The second substrate further includes a multilayer wiring layer on the side facing the third substrate, the multilayer wiring layer including a third insulating film, the first conductive film being formed to be embedded in the third insulating film,

[0414] The third substrate further includes a multilayer wiring layer on the side facing the second substrate, the multilayer wiring layer including a second conductive film, the second conductive film having a plane flush with the surface facing the second substrate, and

[0415] By bonding the first conductive film and the second conductive film, the second substrate and the third substrate are electrically coupled to each other. (14)

[0417] A method of manufacturing an imaging element, the method including:

[0418] Forming a first wiring layer including a plurality of first wirings extending in one direction;

[0419] In a predetermined region of the first wiring layer, forming a first opening between adjacent ones of the plurality of first wirings;

[0420] By forming a first insulating film, forming a gap between adjacent ones of the plurality of first wirings;

[0421] Forming a second insulating film, and then planarizing the surface of the second insulating film, the second insulating film covering the first insulating film; and

[0422] Forming a first conductive film at a position facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film interposed therebetween. (15)

[0424] The manufacturing method of the imaging element according to (14), the method comprising:

[0425] Further forming a third insulating film on the second insulating film; and

[0426] Providing a second opening and a third opening, and then filling the second opening and the third opening with the first conductive film, the second opening extending through the third insulating film, the second insulating film, and the first insulating film and reaching any one of the plurality of first wirings, the third opening extending through a part of the third insulating film. (16)

[0428] The manufacturing method of the imaging element according to (14) or (15), the method comprising: after planarizing the second insulating film, forming a coupling portion to electrically couple the first wiring layer and the first conductive film, the coupling portion penetrating through the second insulating film and the first insulating film and reaching any one of the plurality of first wirings. (17)

[0430] The manufacturing method of the imaging element according to any one of (14) to (16), the method comprising: after forming the first insulating film, forming a fourth opening and forming the second insulating film, the fourth opening reaching any one of the plurality of first wirings. (18)

[0432] The manufacturing method of the imaging element according to (14), the method comprising:

[0433] After further forming a third insulating film on the second insulating film, forming a fifth opening by two-step etching, the fifth opening extending through the second insulating film and the first insulating film and reaching any one of the plurality of first wirings, and

[0434] After forming a protective film covering the side surface and the bottom surface of the fifth opening, forming the first conductive film, the first conductive film facing at least a part of the plurality of first wirings, and the fifth opening being filled with the first conductive film.

[0435] This application claims the benefit of Japanese Patent Application No. 2019-208192, filed with the Japan Patent Office on November 18, 2019, the entire content of which is incorporated herein by reference.

[0436] Those skilled in the art should understand that various deformations, combinations, sub-combinations, and changes may occur according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. An imaging element, the imaging element comprising: A first wiring layer, the first wiring layer including a plurality of first wirings extending in one direction; A first insulating film, the first insulating film laminated on the first wiring layer, the first insulating film forming a gap between adjacent ones of the plurality of first wirings; A second insulating film, the second insulating film laminated on the first insulating film, the second insulating film having a flat surface; And A first conductive film, the first conductive film facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween, wherein the first insulating film has irregularities above the plurality of first wirings and above the gap.

2. The imaging element according to claim 1, further comprising a coupling portion penetrating the first insulating film and the second insulating film, the coupling portion electrically coupling a part of the plurality of first wirings to the first conductive film.

3. The imaging element according to claim 2, wherein, The coupling portion is formed integrally with the first conductive film.

4. The imaging element according to claim 2, wherein, The coupling portion is formed by using a material different from the material of the first conductive film.

5. The imaging element according to claim 2, wherein, An insulating film different from the first insulating film is formed around the coupling portion.

6. The imaging element according to claim 1, further comprising a third insulating film, wherein, The first conductive film is formed to be embedded in the third insulating film, and a surface of the first conductive film forms a plane flush with the third insulating film.

7. The imaging element according to claim 1, wherein, The first insulating film is formed by using a low dielectric constant material having a relative dielectric constant k of 3.0 or less.

8. The imaging element according to claim 1, wherein, The second insulating film is formed by using a material having a higher polishing rate than that of the first insulating film.

9. The imaging element according to claim 1, wherein, The second insulating film is formed by using silicon oxide, SiOC, SiOF, or SiON.

10. The imaging element according to claim 6, further comprising a fourth insulating film located between the second insulating film and the third insulating film, the fourth insulating film correcting warping.

11. The imaging element according to claim 1, further comprising: A first substrate, the first substrate including sensor pixels on a first semiconductor substrate, the sensor pixels performing photoelectric conversion; A second substrate, the second substrate including a readout circuit on a second semiconductor substrate, the readout circuit outputting a pixel signal based on charges output from the sensor pixels; And A third substrate, the third substrate including at least one of a logic circuit and a storage circuit on a third semiconductor substrate, the logic circuit processing the pixel signal, the storage circuit holding the pixel signal, wherein, The first substrate, the second substrate, and the third substrate are laminated in sequence.

12. The imaging element according to claim 11, wherein, The second substrate further includes a multilayer wiring layer on a side facing the third substrate, the multilayer wiring layer including a third insulating film, the first conductive film being formed to be embedded in the third insulating film, The third substrate further includes a multilayer wiring layer on a side facing the second substrate, the multilayer wiring layer of the third substrate including a second conductive film, the second conductive film being formed with a plane flush with a surface facing the second substrate, and By joining the first conductive film and the second conductive film, the second substrate and the third substrate are electrically coupled to each other.

13. A method of manufacturing an imaging element, the method comprising: forming a first wiring layer including a plurality of first wirings extending in one direction; forming a first opening between adjacent ones of the plurality of first wirings in a predetermined region of the first wiring layer; forming a gap between adjacent ones of the plurality of first wirings by forming a first insulating film; forming a second insulating film and then planarizing a surface of the second insulating film, the second insulating film covering the first insulating film; and forming a first conductive film at a position facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween, wherein the first insulating film has irregularities above the plurality of first wirings and above the gap.

14. The method of manufacturing an imaging element according to claim 13, the method comprising: further forming a third insulating film on the second insulating film; and providing a second opening and a third opening, and then filling the second opening and the third opening with the first conductive film, the second opening extending through the third insulating film, the second insulating film, and the first insulating film and reaching any one of the plurality of first wirings, the third opening extending through a part of the third insulating film.

15. The manufacturing method of the imaging element according to claim 13, the method comprising: After planarizing the second insulating film, forming a coupling portion to electrically couple the first wiring layer and the first conductive film, the coupling portion penetrating the second insulating film and the first insulating film and reaching any one of the plurality of first wirings.

16. The manufacturing method of the imaging element according to claim 13, the method comprising: After forming the first insulating film, forming a fourth opening and forming the second insulating film, the fourth opening reaching any one of the plurality of first wirings.

17. The method of manufacturing an imaging element according to claim 13, the method comprising: after further forming a third insulating film on the second insulating film, forming a fifth opening by two-step etching, the fifth opening extending through the second insulating film and the first insulating film and reaching any one of the plurality of first wirings, and forming the first conductive film after forming a protective film covering side surfaces and a bottom surface of the fifth opening, the first conductive film facing at least a part of the plurality of first wirings, the fifth opening being filled with the first conductive film.

Images