An asynchronous capacitance sensor interface circuit with self-calibration function

Abstract

An asynchronous capacitance sensor interface circuit with a self-calibration function relates to an asynchronous capacitance sensor interface circuit. The present invention is to solve the problem of poor performance of existing capacitance sensor detection circuits. The present invention comprises a self-calibration module, a capacitance voltage conversion circuit, a voltage-time converter, a control circuit generation module and a filter sampling circuit; the output end of the self-calibration module is connected to the point capacitance voltage conversion circuit, the output end of the capacitance voltage conversion circuit is connected to the control signal generation module through the voltage-time converter, the control signal generation module outputs a clock CLK signal, and the CLK signal is processed by the filter sampling circuit to finally output the result. The present invention belongs to the field of capacitance sensor interface circuits.

Description

Technical Field

[0001] The invention relates to an asynchronous capacitance sensor interface circuit, belonging to the field of capacitance sensor interface circuits. Background Art

[0002] Microsensors have been around for over sixty years, and a wide variety of categories have emerged, with an increasingly broad range of applications. Examples include magnetic field sensors for monitoring changes in the surrounding magnetic field, temperature sensors for monitoring temperature changes, gas sensors for monitoring gas concentrations, and humidity sensors for detecting humidity. These microsensors are widely used in military, agriculture, industry, healthcare, scientific research, and other fields.

[0003] According to the working principle of micro sensors, that is, the differences in detection factors, they can be mainly divided into the following types: capacitive, piezoelectric, piezoresistive, tunnel current, electromagnetic, etc. Among them, capacitive sensors have many advantages, such as low temperature coefficient, low power consumption, and good compatibility with CMOS technology; in addition, due to the inherent characteristics of the capacitor plate, it can monitor very small input changes, that is, it has extremely high sensitivity and excellent dynamic performance; and due to its simple structure and good adaptability, it can adapt to more extreme environments such as high and low temperatures and strong radiation; it can realize non-contact measurement and has a wide range of applications, especially when the measured parameters change rapidly or the parameter values ​​change slightly and there are high test accuracy requirements.

[0004] The capacitance detection circuit, or the interface circuit of a capacitance sensor, is an essential component. It connects the capacitance sensor to the signal processing circuit and converts the sensor's collected signals into electrical signals. It also includes basic circuit modules such as signal amplification and noise suppression. Since capacitance change signals cannot be directly identified, a detection circuit is required to convert the capacitance change signals into voltage or current signals, which then require amplification and processing. Voltage and current sensors, however, do not require this conversion, making the interface circuit of a capacitance sensor more challenging. Because the capacitance change detected by a capacitance sensor is very small, typically only on the order of femtofarads, the detection circuit requires high sensitivity. The design of the capacitance detection circuit directly impacts the performance of the capacitance sensor and is closely related to the back-end signal processing system. Therefore, research on capacitance sensor interface circuits is of great significance.

[0005] Capacitance detection plays a significant role in practical applications. For example, capacitance detection is a novel method for detecting missed seeds in current precision seed meters. It utilizes the perturbation in the dielectric constant caused by an object passing through the electrode plate to monitor seeding conditions. It offers high reliability, strong resistance to contamination, and is also a non-contact measurement solution. Capacitance detection can also be used for sealing performance testing, verifying the seal condition at various locations. It is also used for liquid level measurement, measuring the height of liquids and for measuring apertures with smaller diameters. It is also used for gas-solid two-phase flow measurement and is widely used in ultrasonic imaging and human health monitoring. In summary, the performance of capacitance sensor detection circuits determines the performance of the entire capacitance sensor chain, from the raw signal to the final signal processing and display results. This represents a bottleneck that must be addressed for the continued advancement of capacitance sensor technology. Consequently, the design of capacitance sensor detection circuits has always been highly valued. Summary of the Invention

[0006] In order to solve the problem of poor performance of existing capacitance sensor detection circuits, the present invention further proposes an asynchronous capacitance sensor interface circuit with a self-calibration function.

[0007] The technical solution adopted by the present invention to solve the above problems is as follows: the present invention includes a self-calibration module, a capacitance-voltage conversion circuit, a voltage-time converter, a control circuit generation module and a filter sampling circuit; the output end of the self-calibration module is connected to the point capacitance-voltage conversion circuit, the output end of the capacitance-voltage conversion circuit is connected to the control signal generation module through the voltage-time converter, the control signal generation module outputs a clock CLK signal, and the CLK signal is processed by the filter sampling circuit to finally output the result.

[0008] Furthermore, the self-calibration module is a capacitance switch array composed of a capacitance to be measured CX, a reference capacitance Cref and a zero capacitance C0, and one end of the capacitance array is connected to the output end of the control signal generating module.

[0009] Furthermore, the capacitance-to-voltage conversion circuit is a switched capacitor proportional amplification structure composed of a low-noise charge amplifier, an integrating capacitor Cf and a switch, and the input end of the capacitance-to-voltage conversion circuit is connected to the output end of the self-calibration module.

[0010] Furthermore, the voltage-to-time converter is a relaxation oscillator consisting of two driving circuits, two constant current sources, capacitors C1, C2, C3, an integrator, a comparator, and a buffer; the input ends of the two driving circuits are connected to the output end of the control signal generating module to form a closed-loop structure, the output end of one driving circuit is connected to capacitor C1, and the other driving circuit is connected to capacitor C2, the output end of the capacitor C1 is connected to two switches controlled by opposite control signals, the outputs of capacitors C2 and C3 are connected to two switches controlled by opposite control signals, and then connected to the negative input end of the integrator, the integrator is connected across the integrating capacitor Cint, the negative input end of the integrator is connected to the two constant current sources to generate constant-time charging and discharging, the output of the integrator is connected to the positive input end of the comparator, the negative input end of the comparator is connected to the common-mode level point, the output of the comparator is shaped by the buffer, controls the constant current source, and is connected to the input end of the control signal generating module.

[0011] Furthermore, the integrator structure in the voltage-to-time converter is a TCFC three-stage operational amplifier structure with a feedforward structure.

[0012] Furthermore, the comparator in the voltage-to-time converter is a low-power comparator structure of a two-ring uncompensated operational amplifier cascaded inverter.

[0013] Furthermore, the control signal generating module includes a buffer, a delay 1 circuit, a delay 2 circuit, a D flip-flop 1, a D flip-flop 2 and a two-phase non-overlapping clock module; the output end of the buffer is connected to the delay 1 circuit, the output end of the delay 1 circuit is connected to the clock ends of the D flip-flop 1 and the D flip-flop 2, the output end of the delay 1 circuit is connected to the delay 2 circuit, the output end of the delay 2 circuit is connected to the D flip-flop 1 and the D flip-flop 2, the D flip-flop 1 and the D flip-flop 2 are connected to their respective Q negative ends, the Q ends of the D flip-flop 1 and the D flip-flop 2 are connected to the exclusive OR gate, the output end of the exclusive OR gate is connected to the two-phase non-overlapping clock module, and the two-phase non-overlapping clock module outputs a non-overlapping clock as the output of the control signal module.

[0014] Furthermore, the filtering sampling circuit is composed of a frequency divider and a counter. The frequency divider is composed of a D flip-flop and uses a frequency divider with a 7-frequency division function. The counter is provided by the MCU and uses a counter with a clock frequency of 50 to 70 MHz. The final output is a digital quantity.

[0015] The beneficial effects of the present invention are as follows: compared with other capacitance sensor interface circuits, the present invention can not only complete capacitance detection, but also applies self-calibration technology, so that it can adapt to changes in ambient temperature and can still maintain normal operation when the ambient temperature changes. At the same time, it has excellent characteristics such as small area and low power consumption, and can completely avoid the coupling of charge removal and capacitance detection circuit, which can effectively improve the capacitance detection accuracy. At the same time, the closed-loop feedback principle is adopted to make the detection accuracy significantly better than the open-loop capacitance detection system, and effectively improve the system linearity. The noise performance also reaches the domestic leading level, which strongly supports the improvement of charge detection accuracy; the present invention has high measurement accuracy, and its resolution can reach more than 14 bits; the circuit structure of the present invention is relatively simple, the circuit construction is convenient and easy, and the circuit connection is intuitive, and the overall power consumption of the system is low; the present invention is easy to physically implement, and the distance between the counter and the host computer can be very far, which is convenient for application in various capacitance measurement occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a logic block diagram of the present invention;

[0017] Figure 2 It is a schematic diagram of the self-calibration module and the capacitance-voltage conversion circuit;

[0018] Figure 3 is a schematic diagram of the control signal generating module. DETAILED DESCRIPTION

[0019] Specific implementation method 1: Combination Figure 1 To illustrate this embodiment, an asynchronous capacitance sensor interface circuit with a self-calibration function described in this embodiment includes a self-calibration module 101, a capacitance-to-voltage conversion circuit 102, a voltage-to-time converter 103, a control circuit generation module 104, and a filter sampling circuit 105; the output end of the self-calibration module 101 is connected to the point capacitance-to-voltage conversion circuit 102, and the output end of the capacitance-to-voltage conversion circuit 102 is connected to the control signal generation module 104 through the voltage-to-time converter 103. The control signal generation module 104 generates a module output clock CLK signal, and the CLK signal is processed by the filter sampling circuit 105 to finally output the result.

[0020] In this embodiment, the output end of the capacitor-voltage conversion circuit 102 is connected to the capacitor C3 in the voltage-time converter 103, and the output of the voltage-time converter 103 is connected to the control signal generating module 104. The control signal generating module 104 outputs the clock CLK signal. The CLK signal is the input signal of the driving circuit of the self-calibration module 101 and the voltage-time converter 103.

[0021] Specific implementation method 2: Combination Figure 1 and Figure 2To describe this embodiment, the self-calibration module 101 of the asynchronous capacitance sensor interface circuit with a self-calibration function described in this embodiment is a capacitance switch array composed of a capacitance to be measured CX, a reference capacitance Cref and a zero capacitance C0, and one end of the capacitance array is connected to the output end of the control signal generating module 104.

[0022] In this embodiment, the control signal of the switch is provided by the external controller when self-calibration is required. The self-calibration module gives three output results Tx, T0, and Tref in three phases. Errors can be eliminated to achieve self-calibration. In the above formula, M represents the capacitance to be measured, C x With reference capacitor C ref The ratio of T x Indicates the capacitance to be measured C x The time corresponding to the entire test process, T0 represents the time corresponding to the reference capacitor C0 during the entire test process, T ref Indicates the reference capacitance C ref During the entire test process, C x Indicates the capacitance to be measured, C ref Represents a high-precision reference capacitor.

[0023] Specific implementation method three: Combination Figure 1 and Figure 2 To describe this embodiment, the capacitance-to-voltage conversion circuit 102 of an asynchronous capacitance sensor interface circuit with a self-calibration function described in this embodiment is a switched capacitor proportional amplification structure composed of a low-noise charge amplifier, an integrating capacitor Cf, and a switch. The input end of the capacitance-to-voltage conversion circuit 102 is connected to the output end of the self-calibration module 101.

[0024] In this embodiment, the output voltage of the capacitor-to-voltage converter circuit 102 drives the capacitor C3 in the voltage-to-time converter 103, as shown by the formula: Complete the conversion of capacitor voltage, V in the above formula x Indicates the amplitude change of the periodic square wave corresponding to the capacitance to be measured, C x Represents the capacitance to be measured, V dd Indicates the power supply voltage, C f Represents the integral feedback capacitor.

[0025] Specific implementation method four: Combination Figure 1 and Figure 3This embodiment describes an asynchronous capacitance sensor interface circuit with a self-calibration function. The voltage-to-time converter 103 of this embodiment is a relaxation oscillator consisting of two drive circuits, two constant current sources, capacitors C1, C2, and C3, an integrator, a comparator, and a buffer. The inputs of the two drive circuits are connected to the output of the control signal generating module 104 to form a closed-loop structure. The output of one drive circuit is connected to capacitor C1, and the output of the other drive circuit is connected to capacitor C2. The output of capacitor C1 is connected to two switches controlled by opposite control signals. The outputs of capacitors C2 and C3 are connected to two switches controlled by opposite control signals, and then connected to the negative input of the integrator. The integrator is connected across an integrating capacitor Cint. The negative input of the integrator is connected to the two constant current sources to generate constant-time charging and discharging. The output of the integrator is connected to the positive input of the comparator, and the negative input of the comparator is connected to a common-mode voltage point. The output of the comparator is shaped by the buffer to control the constant current source and is connected to the input of the control signal generating module.

[0026] In this embodiment, the two opposite control signals refer to CLK and the inverse of CLK.

[0027] Specific implementation method five: Combination Figure 1 and Figure 3 This embodiment is described. The integrator structure in the voltage-to-time converter 103 of the asynchronous capacitance sensor interface circuit with a self-calibration function described in this embodiment is a TCFC three-stage operational amplifier structure with a feedforward structure.

[0028] Specific implementation method six: combination Figure 1 and Figure 3 This embodiment is described. In the voltage-to-time converter 103 of the asynchronous capacitance sensor interface circuit with a self-calibration function described in this embodiment, the comparator is a low-power comparator structure of a two-loop uncompensated operational amplifier cascaded inverter.

[0029] Specific implementation method seven: combination Figure 1To illustrate this embodiment, the control signal generating module 104 of the asynchronous capacitance sensor interface circuit with a self-calibration function described in this embodiment includes a buffer, a delay 1 circuit, a delay 2 circuit, a D flip-flop 1, a D flip-flop 2 and a two-phase non-overlapping clock module; the output end of the buffer is connected to the delay 1 circuit, the output end of the delay 1 circuit is connected to the clock ends of the D flip-flop 1 and the D flip-flop 2, the output end of the delay 1 circuit is connected to the delay 2 circuit, the output end of the delay 2 circuit is connected to the D flip-flop 1 and the D flip-flop 2, the D flip-flop 1 and the D flip-flop 2 are connected to their respective Q negative ends, the Q ends of the D flip-flop 1 and the D flip-flop 2 are connected to an exclusive-OR gate, the output end of the exclusive-OR gate is connected to the two-phase non-overlapping clock module, and the two-phase non-overlapping clock module outputs a non-overlapping clock as the output of the control signal module.

[0030] In this embodiment, the period T of the control signal output clock signal is linearly related to the input capacitance to be measured, and is expressed by the formula The calculation shows that in the above formula, T represents the time corresponding to a complete acquisition cycle, k represents the number of single working cycles contained in the acquisition cycle, and V dd Indicates the power supply voltage, C1 indicates the corresponding drive voltage V 01 The first transfer capacitor, C2, corresponds to the drive voltage V 02 The second transfer capacitance, V x Indicates the amplitude change of the periodic square wave corresponding to the capacitance to be measured, C s Indicates the corresponding V x The transfer capacitance, I int Indicates the integration capacitor C int The constant current value for charging and discharging.

[0031] Specific implementation method eight: combination Figure 1 To describe this embodiment, the filtering sampling circuit 105 of the asynchronous capacitive sensor interface circuit with a self-calibration function described in this embodiment is composed of a frequency divider and a counter. The frequency divider is composed of a D flip-flop and uses a frequency divider with a 7-division function. The counter is provided by the MCU and uses a counter with a clock frequency of 50 to 70 MHz. The final output is a digital quantity.

[0032] How it works

[0033] This circuit design converts the capacitance to be measured into the period of the output pulse signal. The final expression of the two is roughly a linear function relationship, that is, T = aCin + b. Since each capacitor may have a weak residual charge when the circuit starts working, which causes a large error in the experimental results, a self-calibration module 101 is introduced; the self-calibration module 101 works before the capacitor to be measured is connected to the circuit. When the two act separately, the a and b parameters in the expression can be obtained from the output end respectively, so as to obtain a more accurate measurement value; when the capacitor to be measured is connected to the circuit, the driving circuit module is first used to periodically charge and discharge the capacitor to be measured, and the charge in the capacitor to be measured is transferred to Cf, thereby causing the output end of the operational amplifier to generate a periodic square wave related to the capacitor to be measured, and the amplitude of the square wave contains information about the capacitor to be measured; then, this square wave will charge and discharge C3 in the voltage-time converter; when the clock signal is high, C1 loop is connected to the circuit, and the charge in C1 will be instantly transferred to Cint, and then the charge in Cint will be removed by the constant current source; at this time, C1 and C2 will be charged by their respective driving voltages; when the clock signal is low, similarly, C1 and C2 will be connected to the loop to transfer the charge on them The voltage is transferred to Cint and eliminated, and C1 is charged at this time. In the present invention, C1 ensures that there is still voltage output at the output end when the circuit is connected to Coff, preventing the circuit output end from being idle, while C2 prevents some high-frequency stray signals from interfering with the result. Finally, the capacitance-time converter will output a periodic triangular wave signal with a DC level of Vcm. The frequency of this triangular wave signal is related to the input capacitance value. The comparator converts the triangular wave into a square wave. This square wave first generates a signal to control the charging and discharging of the current source. Then, a series of logic conversion circuits convert this square wave into a control clock for the system for self-control. At the same time, since this square wave contains information about the capacitance value to be measured, it is first divided. Frequency division can reduce the frequency of the measurement signal, reduce the frequency requirements of the subsequent counter circuit, and also eliminate the impact of quantization noise on the system. This part of the circuit is also clocked. The circuit after frequency division uses a counter to check the number of cycles within a certain period of time, and then calculate its accurate capacitance value.

[0034] The self-calibration module 101 of the present invention includes three capacitors, wherein Coff and Cref are two high-precision capacitors whose values ​​need to be made very accurate; Cin is the capacitor to be measured, and this part mainly uses the three capacitors to automatically eliminate system errors.

[0035] The capacitance-to-voltage conversion module 102 includes an amplifier, an integrating capacitor Cf, and a switch. This circuit primarily converts the capacitance to be measured into a periodic square wave. The amplitude of the square wave contains information about the capacitance to be measured. The voltage-to-time converter includes three transfer capacitors, an integrating capacitor, an integrator, a comparator, and two constant current sources. This circuit primarily converts the amplitude of the square wave into its period. The clock signal generation circuit includes a logic control circuit, which generates signals that both control the charging and discharging of the constant current source and generate the clock signal for the entire system. The filter sampling circuit consists of a clocked frequency divider and a counter, whose functions are primarily implemented by an external single-chip microcomputer. This circuit reduces quantization noise while also reading the signal period, making it easier for the host computer to obtain the capacitance value.

[0036] When the self-calibration module 101 is working, a periodic clock is input from the outside, and the control switches are turned on in sequence, and the clock charges and discharges Coff, Cref, and Cx in turn; finally, the period of the output signal of the entire system is T=aCin+b; when the system starts working, corresponding to Coff and Cref, since their capacitance values ​​are very accurate, the values ​​of a and b in the expression can be determined first, so that when the value of Cx is formally measured, the system error can be automatically eliminated to ensure that the measured value is very accurate; the specific structure of this part of the switch is that the switch consists of a CMOS transmission gate and two dummy tubes, and the specific connection method is as follows (where M0, M1, and M2 are NMOS tubes, and M3, M4, and M5 are PMOS tubes): the source end of M2 is used as the input vin, and the output end of M2 is used as the input vin. The drain end is connected to the source end of M2, the gate end of M2 is connected to the gate end of M1, the source end of M0 is connected to the drain end of M2, the gate end of M0 serves as the clock control end NMOS, the drain end of M0 is connected to the source end of M1, the drain end of M1 is connected to the source end of M1, the drain end of M1 serves as the output end Vout, the gate end of M1 is connected to the gate end of M3, the source end of M5 is connected to the source end of M2, the drain end of M5 is connected to the source end of M5, the gate end of M5 is connected to the gate end of M4, the source end of M3 is connected to the drain end of M5, the gate end of M3 serves as another clock control end PMOS, the drain end of M3 is connected to the source end of M4, the drain end of M4 is connected to the source end of M4, the drain end of M4 is connected to the drain end of M1, the gate end of M4 is connected to the gate end of M0, the substrates of M0, M1 and M2 are all grounded, and M3, M4 and M5 are all connected to the highest potential Vdd.

[0037] like Figure 2 As shown, at the beginning of the capacitor-to-voltage conversion module 102, the voltage at the left end of Cx is set to 0, and the switch is closed. Since the two input terminals have the characteristics of virtual short and virtual open when the operational amplifier forms feedback, the positive and negative input terminal voltages of the operational amplifier are both the common mode voltage Vcm, where V cm =V dd / 2; at the same time, the output voltage is also stable at Vdd / 2. During this period, the amount of charge Q accumulated by the capacitor Cx to be measured is x =C x ×(V cm -0); in the next state, that is, the left end of Cx is Vdd, when the switch is closed, Cx transfers all the charge stored at the previous moment to the output end, and the charge accumulated by Cx becomes C x ×(V cm -V dd ); Therefore, the amount of charge that changes in Cx during this period is Vdd×Cx. All of this charge is transferred to the feedback capacitor Cf, causing the voltage across Cf to change, thereby causing the output voltage to rise or fall, generating a square wave with an amplitude related to Cx; From the charge conservation equation, it can be obtained that V dd ×C x =(V out -V cm )×C f , therefore, the amplitude of its change V x =(V dd ×C x ) / C f ; When the driving signal changes from Vdd to 0, V x =-(V dd ×C x ) / C f ; Through the capacitor-voltage conversion module 102, the information of the capacitance value to be measured is converted into the amplitude value of the periodic square wave, completing the first conversion of the capacitance value to be measured; in addition, in order to prevent the operational amplifier from having insufficient load capacity, resulting in an overload effect and causing the system to produce large distortion, usually, during the design process, the value of the feedback capacitor Cf is taken to be 3 to 5 times the capacitance value to be measured, that is, Cf = (3 to 5) Cx.

[0038] like Figure 1As shown, the voltage-time converter 103 consists of three transfer capacitors C1, C2, and C3, an integrating capacitor Cint, an integrator, a comparator, two clocked constant current sources, and a first-level buffer. Assume that the state of the circuit is clk=1, clkd=0. At this time, the transfer capacitor C1 is connected to the integrator, while C2 and C3 are disconnected from the integrator; at this time, the periodic signal output by the driving circuit 3 and the capacitor-voltage conversion module will charge the two capacitors C2 and C3 at the same time; and C1 transfers the amount of electricity accumulated at the previous moment to the integrating capacitor Cint, and the amount of charge transferred is still Vdd×C1; after the charge transfer, since the voltage across the integrating capacitor cannot change suddenly, it will cause the voltage at the output of the integrator to jump to a high potential higher than the common mode level; for the comparator, when its positive input signal is higher than the negative input signal, When the comparator outputs a high level Vdd, and when the input signal at its negative input terminal is higher than the signal at the positive input terminal, the comparator outputs a low level 0; therefore, after the output voltage of the integrator passes through the comparator, the output terminal potential will change to Vdd; after passing through the buffer, its driving capability will be enhanced, enabling it to drive switches S1 and S2, thereby better controlling the on and off of the switches; in the above case, the switch S1 will be controlled to be turned on, at which time, the current source will supply power to the negative input node of the integrator, so that the transferred charge in the integrator is removed, and the time for this process is Vdd×C1 / Iint. During this process, the output voltage of the integrator will drop linearly; in the next process, the transfer capacitor C1 will be disconnected, and the capacitors C2 and C3 will be connected to the integrator circuit, which is the same as the situation when C1 is connected to the circuit. At this time, the charge in C2 and C3 will be transferred to the integrating capacitor, and the total amount of charge transferred is V dd ×C2+V x ×C3, this part of the charge will also be discharged by the constant current source, and the time is (V dd ×C2+V x ×C3) / I int ; In circuit design, one cycle contains four such small cycles, that is, such a charging and discharging process will be carried out four times.

[0039] Therefore, in summary, the total amount of charge transferred in one cycle in the circuit is 4 (V dd ×C2+V x ×C3+V dd ×C1), the corresponding cycle time is 4(V dd ×C2+V x ×C3+V dd ×C1) / I intCorrespondingly, the triangular wave formed at the output of the integrator will form a square wave after conversion by the comparator. This square wave controls the on and off of the current source on the one hand, and at the same time, it is also used to generate the circuit's own clock in the next clock circuit generation part to realize automatic control of the system; this part of the circuit realizes the conversion of the voltage quantity Vx into a periodic signal of the system square wave; the structure of the comparator in this part of the circuit is as follows: the comparator is composed of a two-stage amplifier. Its first stage adopts a five-tube operational amplifier, and the second stage adopts a common-source amplifier. The output of the five-tube operational amplifier is directly connected to the input of the common-source amplifier. The specific connection method is as follows (where M0, M1, M2, M6, and M7 are PMOS transistors, and M3, M4, and M5 are NMOS transistors): The drain connection current of M7 is always 5μA A current source, the other end of the current source is grounded, the gate terminal of M7 is connected to the drain terminal of M7, the source terminal of M7 is connected to the highest potential Vdd, the gate terminal of M2 is connected to the gate terminal of M7, the source terminal of M2 is connected to Vdd, the drain terminal of M2 is connected to the source terminals of M0 and M1, the gate terminals of M0 and M1 serve as two input terminals, the gate terminal of M0 serves as the inverting input terminal vin-, the gate terminal of M1 serves as the non-inverting input terminal vin+, the drain terminal of M0 is connected to the drain terminal of M4, the drain terminal of M4 is connected to the gate terminal of M4, the source terminal of M4 is grounded, the drain terminal of M5 is connected to the drain terminal of M6, the drain terminal of M6 serves as the output Vout of the comparator, the gate terminal of M6 is connected to the gate terminal of M7, the source terminal of M6 is connected to the highest potential Vdd, the substrates of M0, M1, M2, M6, and M7 are all connected to the highest potential Vdd, and the substrates of M3, M4, and M5 are all grounded.

[0040] like Figure 3As shown, the clock circuit generation module (104) is implemented by a logic control circuit, which is mainly used to generate a clock signal for the circuit; the output voltage of the comparator passes through a two-stage buffer to enhance its ability to drive the logic gate; first, the comparator output signal is briefly delayed and used as an enable signal for two T' flip-flops to control whether the two flip-flops work; then the signal after a longer delay is used as the signal input of the two T' flip-flops; the two T' flip-flops are triggered by the rising edge of the signal and the falling edge of the signal respectively, and the output signals of the two flip-flops are passed through the exclusive OR operation circuit, and the output signal is the clock signal of the circuit; in order to prevent the situation where two switches in the circuit are turned on at the same time when the clock signal controls the circuit, the clock control of the circuit is controlled by a two-phase non-overlapping clock, so that clk and clkd in the circuit will not be turned on at the same time; through this part of the circuit, the system clock is regenerated and the entire loop is built at the same time; the specific structure of the D flip-flop used in this part of the circuit is as follows: D flip-flop The inverter is composed of four inverters and two transmission gates. The first transmission gate is composed of M0 and M1, and the second transmission gate is composed of M4 and M7. The specific connection method is as follows (where M0 and M7 are PMOS tubes, M1 and M4 are NMOS tubes): the input terminal CLK is connected to the input terminal in of the first inverter, and is also connected to the gate terminals of M0 and M4. The output terminal out of the first inverter is also connected to the gate terminals of M1 and M7. The drain terminals of M0 and M1 are connected as the input terminal D. The source terminals of M0 and M1 are connected and connected. Connected to the input terminal in of the second inverter, the output terminal out of the first inverter is connected to the drain terminals of M4 and M7, the drain terminals of M4 and M7 are connected to each other, the source terminals of M4 and M7 are connected and connected to the input terminal in of the third inverter, the output terminal out of the third inverter is used as the output Q, the output terminal out of the third inverter is connected to the input terminal in of the fourth inverter, the output terminal out of the fourth inverter is used as the output QF, the substrates of M0 and M7 are connected to the highest potential Vdd, and the substrates of M1 and M4 are connected to the ground.

[0041] like Figure 1As shown, the filter sampling circuit 105 is composed of a frequency divider and a counter; it mainly processes the output square wave signal and realizes data transmission with the host computer; first, the output signal is divided, which can reduce the output signal frequency on the one hand, thereby relaxing the requirements on the bandwidth of the counter and reducing the overall cost and power consumption of the system; at the same time, it also reduces the overall quantization noise of the system, making the noise performance of the system better; the function realized by the counter is mainly to measure the number of cycles of the square wave output within a given period of time, and use this physical quantity to characterize the size of the capacitance value to be measured; this part of the circuit has a high degree of functional integration and also needs to realize interaction with the host computer, so in the design, a single-chip microcomputer will be used instead of a conventional circuit design; another advantage of using a single-chip microcomputer to integrate this part of the circuit is that it facilitates the expansion of physical functions. This part of the circuit can be integrated with the overall circuit in blocks, thereby realizing applications in multiple occasions; finally, the output result of the overall circuit is obtained by It is concluded that the error self-elimination function of the circuit is realized; the final output of this part of the circuit can be connected to the host computer terminal, and then the value of the capacitor can be accurately read on the host computer.

[0042] In experiments, multiple cycles are typically selected for period determination to avoid large errors in the selected period, which could lead to significant deviations in the measurement results. The final period result is the ratio of the total measured time to the number of measured periods. Simulation results show that the more periods measured, the more accurate the final period value, and thus the value of the measured capacitance Cin. This means that increasing the measurement time and reducing the current of the constant current source that charges and discharges the integrating capacitor can reduce system errors and increase measurement accuracy.

[0043] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. An asynchronous capacitance sensor interface circuit with self-calibration function, characterized in that: The asynchronous capacitance sensor interface circuit with a self-calibration function comprises a self-calibration module (101), a capacitance-voltage conversion circuit (102), a voltage-time converter (103), a control circuit generation module (104) and a filter sampling circuit (105); the output end of the self-calibration module (101) is connected to the point capacitance-voltage conversion circuit (102), the output end of the capacitance-voltage conversion circuit (102) is connected to the control signal generation module (104) via the voltage-time converter (103), the control signal generation module (104) generates a module output clock CLK signal, and the CLK signal is processed by the filter sampling circuit (105) to finally output a result; The self-calibration module (101) is a capacitance switch array composed of a capacitance to be measured CX, a reference capacitance Cref and a zero capacitance C0, and one end of the capacitance array is connected to the output end of the control signal generating module (104); The capacitor-voltage conversion circuit (102) is a switch capacitor proportional amplification structure composed of a low-noise charge amplifier, an integral capacitor Cf and a switch, and the input end of the capacitor-voltage conversion circuit (102) is connected to the output end of the self-calibration module (101); The voltage-to-time converter (103) is a relaxation oscillator composed of two drive circuits, two constant current sources, a capacitor C1, a capacitor C2, a capacitor C3, an integrator, a comparator and a buffer; the input ends of the two drive circuits are connected to the output end of the control signal generating module (104) to form a closed loop structure, the output end of one drive circuit is connected to the capacitor C1, and the output end of the other drive circuit is connected to the capacitor C2; the output end of the capacitor C1 is connected to two switches controlled by opposite control signals, the outputs of the capacitors C2 and C3 are connected to two switches controlled by opposite control signals, and then connected to the negative input end of the integrator; the integrator is connected across the integration capacitor Cint; the negative input end of the integrator is connected to the two constant current sources to generate constant time charging and discharging; the output of the integrator is connected to the positive input end of the comparator; the negative input end of the comparator is connected to the common mode level point; the output of the comparator is shaped by the buffer to control the constant current source and is connected to the input end of the control signal generating module; The control signal generating module (104) comprises a buffer, a delay 1 circuit, a delay 2 circuit, a D flip-flop 1, a D flip-flop 2 and a two-phase non-overlapping clock module; the output end of the buffer is connected to the delay 1 circuit, the output end of the delay 1 circuit is connected to the clock ends of the D flip-flops 1 and 2, the output end of the delay 1 circuit is connected to the delay 2 circuit, the output end of the delay 2 circuit is connected to the D flip-flops 1 and 2, the D flip-flops 1 and 2 are connected to their respective Q non-ends, the Q ends of the D flip-flops 1 and 2 are connected to an XNOR gate, the output end of the XNOR gate is connected to the two-phase non-overlapping clock module, and the two-phase non-overlapping clock module outputs a non-overlapping clock as the output of the control signal module.

2. The asynchronous capacitance sensor interface circuit with self-calibration function according to claim 1, characterized in that: The integrator structure in the voltage-to-time converter (103) is a TCFC three-stage operational amplifier structure with a feed-forward structure.

3. The asynchronous capacitance sensor interface circuit with self-calibration function according to claim 1, characterized in that: The comparator in the voltage-to-time converter (103) is a low-power comparator structure of a two-ring non-compensated operational amplifier cascaded inverter.

4. The asynchronous capacitance sensor interface circuit with self-calibration function according to claim 1, characterized in that: The filtering sampling circuit (105) is composed of a frequency divider and a counter. The frequency divider is composed of a D flip-flop and uses a frequency divider with a 7-frequency division function. The counter is provided by the MCU and uses a counter with a clock frequency of 50-70 MHz. The final output is a digital quantity.

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