Preparation Method of Defective Samples and Failure Analysis Method of Interconnection Structure Defects

Abstract

The present invention provides a method for preparing a defective sample and a method for failure analysis of interconnect structure defects. The method for preparing the defective sample includes: providing a semiconductor structure having a defect to be analyzed; forming a mark in the interconnect structure, the mark being spaced apart from the defect to be analyzed; grinding the interconnect structure to obtain a defective sample, wherein the interconnect structure around the mark shows a delamination condition along the sidewall of the mark during the grinding process, and the remaining number of layers of the interconnect structure is judged according to the delamination condition by observing with an optical microscope to realize the positioning of the grinding process. In the present invention, by forming a mark around the defect to be analyzed and the sidewall of the mark exposing the interconnect structure, the difference in the grinding degree of the sidewall of the mark during the grinding process causes the interconnect structure near the mark to show a delamination condition, and the grinding process is accurately positioned through this delamination condition, so as to realize the simple and efficient preparation of the defective sample.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a method for preparing a defective sample and a method for failure analysis of interconnect structure defects. Background Art

[0002] In the design and manufacturing process of semiconductor devices, in order to ensure that the semiconductor devices have high reliability and effectiveness, it is generally necessary to perform failure analysis on the detected defects of the semiconductor devices.

[0003] Before performing failure analysis, it is first necessary to prepare a defective sample by using the provided defective (failed) device to expose the defect, so as to facilitate actual analysis.

[0004] Taking the defects in the interconnect structure of semiconductor devices as an example, even if the provider of the defective device accurately provides many background information such as the failure type, process, crystal orientation, number of layers of the interconnect structure, thickness of the interconnect structure, and pattern of the interconnect structure of the device, it is difficult to accurately locate the number of layers of the removed interconnect structure or the number of remaining interconnect structures when removing (grinding) the interconnect structure above the defect, resulting in a low success rate of preparing a failed sample. And the preparation method with a relatively high success rate, such as preparing another backup sample for real-time comparison and confirmation of the two by using SEM during the removal process, not only takes a long time, but also the preparation process is relatively complex. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for preparing a defective sample and a method for failure analysis of interconnect structure defects, so as to achieve the purpose of simply and efficiently preparing a defective sample.

[0006] To solve the above technical problems, the method for preparing a defective sample provided by the present invention includes: providing a semiconductor structure having a defect to be analyzed, the semiconductor structure including a substrate and an interconnect structure formed on the substrate, the interconnect structure including multiple metal layers, and the defect to be analyzed being located in the metal layer; forming at least one mark in the interconnect structure, the mark being spaced a preset distance from the defect to be analyzed, the mark being an opening, and the side wall of the opening exposing the multiple metal layers; grinding the interconnect structure to obtain a defective sample, wherein the interconnect structure around the mark shows a delamination condition along the side wall of the mark during the grinding process, and the remaining number of layers of the interconnect structure is judged by observing the delamination condition through an optical microscope for positioning the grinding process.

[0007] Optionally, the mark is formed on the substrate by laser cutting or focused ion beam, and the mark penetrates through the interconnect structure.

[0008] Optionally, the angle between the laser beam of the laser cutting or the focused ion beam and the substrate is 70° to 110°.

[0009] Optionally, the preset distance is the planar distance between the mark and the defect to be analyzed, and the planar distance is 100 micrometers to 200 micrometers.

[0010] Optionally, the shape of the mark is rectangular, and the side length of the rectangle is 5 micrometers to 20 micrometers.

[0011] Optionally, the number of the marks is one or an even number, and the even number of marks are symmetrically and evenly distributed around the target plane position.

[0012] Optionally, during the grinding process, an etching solution is used to remove the metal interconnect layer in the interconnect structure.

[0013] Optionally, the interconnect structure is ground to the metal layer where the defect to be analyzed is located to obtain the defect sample.

[0014] Optionally, the multi-layer interconnect layer further includes multi-layer dielectric layers, the dielectric layers and the metal layers are arranged alternately, and the interconnect structure is ground to the dielectric layer on the layer above the metal layer where the defect to be analyzed is located to obtain the defect sample.

[0015] Based on another aspect of the present invention, there is also provided a failure analysis method for interconnect structure defects, including:

[0016] Preparing a defect sample including an interconnect structure defect by using the preparation method of the defect sample as described above; and performing a failure analysis on the interconnect structure defect of the defect sample, where the failure analysis includes electrical analysis and physical property analysis.

[0017] In summary, the present invention forms an opening as a mark on the interconnect structure at a preset distance from the defect to be analyzed, and uses the opening to expose the multi-layer metal layer, so that when grinding and removing the interconnect structure on the defect to be analyzed, due to the difference in the grinding degree of the side wall of the mark during the grinding process, the interconnect structure around the mark shows a delamination condition, that is, the interconnect structure closer to the top layer near the mark is ground more to form a delamination condition. Thus, the delamination condition can be relatively easily observed by using an optical microscope to judge the remaining number of layers of the interconnect structure, so as to achieve accurate positioning during the grinding process, and then accurately remove the interconnect structure on the target layer of the defect to be analyzed, so as to achieve the purpose of simply and efficiently preparing the defect sample. Description of the Drawings

[0018] Those of ordinary skill in the art should understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0019] Figure 1 is a flowchart of a method for preparing a defective sample provided by an embodiment of the present application;

[0020] Figures 2 to 6 is a schematic structural diagram corresponding to the corresponding steps of the method for preparing a defective sample provided by an embodiment of the present application.

[0021] In the drawings:

[0022] 10 - substrate; 11 - defect to be analyzed; 20 - mark. Detailed implementation manners

[0023] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis to be shown in each drawing is different, and sometimes different scales are used.

[0024] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features, unless the content clearly indicates otherwise.

[0025] Figure 1 is a flowchart of a method for preparing a defective sample provided by an embodiment of the present application.

[0026] As Figure 1 shown, the method for preparing a defective sample provided by this embodiment includes:

[0027] S01: Provide a semiconductor structure having a defect to be analyzed, the semiconductor structure includes a substrate and an interconnect structure formed on the substrate, the interconnect structure includes multiple metal layers, and the defect to be analyzed is located in the metal layer;

[0028] S02: Form at least one mark in the interconnect structure, the mark is spaced a preset distance from the defect to be analyzed, the mark is an opening, and the sidewalls of the opening expose the multiple metal layers;

[0029] S03: Grind the interconnect structure to obtain a defective sample. During the grinding process, delamination occurs along the sidewalls of the mark in the interconnect structure around the mark. Observe the delamination condition through an optical microscope to determine the remaining number of layers of the interconnect structure for positioning during the grinding process.

[0030] Figures 2 to 6 It is a schematic structural diagram corresponding to the corresponding steps of the method for preparing a defective sample provided by an embodiment of the present application. Next, the method for preparing a defective sample will be described in detail with reference to Figures 2 to 6 the method for preparing a defective sample.

[0031] First, perform step S01. Please refer to Figure 2 , provide a semiconductor structure with a defect to be analyzed. The semiconductor structure includes a substrate 10 and an interconnect structure formed on the substrate 10. The interconnect structure includes multiple metal layers, and the defect to be analyzed is located in the metal layer.

[0032] The semiconductor structure can be a die or a chip after electrical tests such as WAT (Wafer Acceptance Test), CP test, or FT test (Final Test). The semiconductor structure includes a substrate 10 and an interconnect structure. The substrate 10 has an active region and a device structure located on the active region. The interconnect structure is electrically connected to the device structure. The interconnect structure includes multiple interconnect layers, and the multiple interconnect layers are, for example, alternately arranged by multiple metal layers (metal interconnect layers) and multiple dielectric layers (inter-metal dielectrics or inter-layer dielectrics). In this embodiment, the multiple interconnect layers of the interconnect structure are named as the zeroth layer to the Nth layer from bottom to top, N is greater than or equal to 6. The zeroth layer can be an inter-layer dielectric layer, and the Nth layer can be a metal pad. Among them, the thickness of each layer is different, and the thickness of the metal layer and dielectric layer closer to the top layer is thicker. Of course, the naming method of the multiple interconnect layers is not limited to this. For example, the zeroth layer can also be set as a metal layer (the first metal layer).

[0033] Specifically, there is at least one defect 11 to be analyzed in the semiconductor structure. The defect 11 to be analyzed is an interconnect structure defect, such as short-issue or open-issue, etc. After the aforementioned electrical test, the target position information and depth position information of the defect 11 to be analyzed in the semiconductor structure can be obtained. Among them, the target planar position is the planar position coordinate (or within a small range) where the defect 11 to be analyzed is located, and the depth position information is the number of layers (or called the target layer number) of the defect 11 to be analyzed in the multiple interconnect layers. The interconnect structure where the defect 11 to be analyzed is located is a metal layer. For example, if it is in the Mth metal layer, then in this embodiment, it can be denoted as the 2Mth layer, N > 2M > 0.

[0034] In addition, information such as the failure type, the thickness of each interconnect layer, and the pattern of each metal layer of the defective semiconductor structure can be obtained to further improve the rate and success rate of preparing defective samples.

[0035] Next, perform step S02. Please refer to Figure 3a , and form at least one mark 20 in the interconnect structure. The mark 20 is spaced a preset distance from the defect 11 to be analyzed. The mark 20 is an opening, and the opening of the mark 20 exposes multiple metal layers.

[0036] A laser cutter or a focused ion beam (FIB) can be used to remove the interconnect structure in an area near the defect 11 to be analyzed (the target planar position), that is, etch the interconnect structure to form a mark 20 (a groove or an opening). The mark 20 penetrates (drills through) the interconnect structure to the active region on the substrate 10, so as to expose each interconnect layer (including metal layers and dielectric layers) in the interconnect structure by using the side cross-section (opening) of the formed mark 20. Moreover, according to the angle between the laser beam or the focused ion beam of the laser cutting and the substrate 10 being 70° to 110°, the angle between the side wall of the mark 20 and the substrate 10 is 70° to 110°. In this embodiment, the angle between the side wall and the substrate 10 is 90°, which is beneficial to actual operation.

[0037] Furthermore, the planar position of the mark 20 in the interconnect structure is 100 micrometers to 200 micrometers away from the defect 11 to be analyzed (the target planar position), which is beneficial to preparing defective samples. It should be understood that the mark 20 will be further enlarged during the subsequent removal (grinding) process. If the distance between the mark 20 and the defect 11 to be analyzed is too close, it may cause the mark 20 to spread to the defect 11 to be analyzed, which is not conducive to timely discovery of the defect 11 to be analyzed. If the mark 20 is too far away from the defect 11 to be analyzed, it may lead to a large difference in the grinding rate between the area around the mark 20 and the defect 11 to be analyzed, which is not conducive to accurately positioning the grinding process. In addition, if the distance between the mark 20 and the defect 11 to be analyzed is too close, the defect 11 to be analyzed may also be affected by the marking process, which is not conducive to subsequent analysis and judgment.

[0038] Among them, preferably, the shape of the mark 20 is rectangular, and the side lengths of the rectangle are both 5 micrometers to 20 micrometers. Of course, the opening formed by marking 20 can also be other suitable shapes, and in practice, it is difficult for the shape of the etched mark to be as regular as set.

[0039] Furthermore, the number of the marks 20 can also be an even number (≥2), and the even number of marks 20 are symmetrically and evenly distributed around the target plane position, so as to prevent the interconnect structures around the target plane position (the defect 11 to be analyzed) from having structural differences, resulting in different grinding rates of the interconnect structures around the marked plane position during subsequent grinding, which is not conducive to uniformly exposing the defect 11 to be analyzed. Specifically, in a specific embodiment, there are two marks 20, and the distribution of the two marks 20 around the defect 11 to be analyzed is as Figure 3b shown. In another specific embodiment, there are four marks 20, and the distribution of the four marks 20 around the defect to be analyzed is as Figure 3c shown.

[0040] Next, step S03 is executed to grind the interconnect structure to obtain a defect sample. Among them, the interconnect structure around the mark 20 shows a delamination condition along the side wall of the mark 20 during the grinding process, and the delamination condition is observed through an optical microscope to judge the remaining number of layers of the interconnect structure to achieve the positioning of the grinding process.

[0041] Please refer to Figure 4 . Taking the example that the interconnect structure includes N layers and the defect 11 to be analyzed is in the 2Mth layer, a certain thickness (the top layer or near the top layer) of the interconnect structure can be first ground away, so that delamination occurs in the interconnect structure around the mark 20 (side cross-section), and an optical microscope (Optical Microscope, OM) is used to observe the delamination phenomenon to determine the remaining number of layers of the interconnect structure. It is not difficult to understand that, on the one hand, when bombarding the interconnect structure with high energy (laser beam or ion beam) to form the mark 20, the range of the interconnect structure near the mark 20 that is affected by the high energy is relatively larger when it is closer to the top layer (the Nth layer), so it is easier to be ground. On the other hand, during the actual grinding process, the grinding pad and the abrasive enter the pit of the mark 20 partially, and form more severe grinding on each interconnect structure from the side cross-section of the mark 20 as it gets closer to the top layer. Thus, after grinding the interconnect structure with the first thickness, the interconnect structure near the mark 20 delaminates along the side cross-section (depth) direction, that is, the interconnect structure near the mark 20 that is closer to the top layer is ground and spreads out more severely, and the remaining number of layers of the interconnect structure can be counted under the observation of the optical microscope, so as to achieve the grinding positioning of the grinding process.

[0042] Among them, the first thickness can be, for example, 2 to 3 layers, and the grinding thickness can be, for example, 200 to 400 microns, so as to improve the grinding efficiency and help to observe a more obvious delamination phenomenon. Of course, if the target layer of the defect 11 to be analyzed is relatively shallow, such as the (N - 1)th layer or the (N - 2)th layer, the first thickness can be correspondingly reduced.

[0043] Among them, if the thickness to be polished (a certain thickness) of the Nth layer or the N-1th layer is relatively thick, for example, ≥1 μm, a relatively large polishing rate and a high-concentration polishing liquid can be selected to increase the polishing rate and help observe a relatively obvious delamination phenomenon. Of course, if the target layer number of the defect 11 to be analyzed is relatively shallow, for example, the N-1th layer or the N-2th layer, the polishing rate can be correspondingly reduced.

[0044] After polishing the interconnect structure with the first thickness, the layer number of the current polished layer is obtained by observing the delamination phenomenon, that is, the positioning of the layer number of the polished layer in the polishing process is realized, so as to determine the number of layers to be polished between the current polished layer and the target layer (the 2Mth layer), and the thickness of the next polishing is confirmed by using information such as the thickness of the provided interconnect structure, and continue to polish according to the above method until the polished layer stays on the target layer, thereby forming a defect sample that can be used for subsequent electrical or physical property analysis. It should be understood that during the polishing process, if the current polished layer cannot be positioned or accurately positioned, it is extremely difficult to accurately stop the polished layer on the 2Mth layer where the defect 11 to be analyzed is located, resulting in a relatively low success rate of preparing the defect sample.

[0045] Of course, during the above polishing process, the closer the layer number of the current polished layer is to the target layer, the smaller (more precise) the thickness of the next polishing is to prevent over-polishing from harming the defect 11 to be analyzed. Specifically, it can be achieved by reducing the polishing pressure and the polishing time to realize the above precise polishing.

[0046] Please refer to Figure 5a In a specific embodiment, according to the above method in sequence, polish the interconnect structure to the metal layer (for example, the 2Mth layer) where the defect 20 to be analyzed is located to expose the defect 20 to be analyzed, and use the remaining semiconductor structure as a defect sample for subsequent further analysis. As Figure 5b shown, Figure 5b is a SEM image of the label of a defect sample in practice. The optical microscope image (OE image) is actually more convenient to observe in color in practice, but it is not convenient to be shown in the patent. Only the SEM image without color is shown here. Among them, M0 is the metal contact post, M1 is the first metal layer, and M2 is the first metal layer.

[0047] Please continue to refer to Figure 6 In another specific embodiment, the polishing method is the same as the foregoing, but polish the interconnect structure to the dielectric layer (the 2M+1th layer) on the layer above the metal layer where the defect 20 to be analyzed is located to expose the dielectric layer on the layer above the defect 20 to be analyzed, and use the remaining semiconductor structure as a defect sample for subsequent further analysis. Among them, polishing to the dielectric layer on the layer above the defect 20 to be analyzed can prevent over-polishing from harming the defect 11 to be analyzed, and the dielectric layer can also be used as a protective layer for the defect sample.

[0048] Of course, under the condition of a pattern with an interconnect structure, it can also be compared with the metal layer pattern of the current grinding layer scanned by SEM to further confirm the target number of layers. It is worth mentioning that the interconnect structure patterns of several layers near the target number of layers (such as the previous metal layer or the next metal layer) may be the same, and it is difficult to directly judge only from the interconnect structure pattern. It must be combined with the specific number of layers to achieve accurate judgment. On the other hand, this is also one of the reasons why the positioning of the grinding process is inaccurate only relying on the interconnect structure pattern, and multiple SEM scans are relatively more complex and time-consuming than observing through an optical microscope. In this embodiment, the accurate positioning of the grinding process can be completed only by using an optical microscope, which is not only convenient and fast but also has the advantage of low cost.

[0049] In addition, the grinding fluid during the grinding process may include silicon oxide suspension particles, and an acid solution can also be used to corrode the metal layer to increase the rate.

[0050] The embodiment of the present application also provides a failure analysis method for interconnect structure defects, including:

[0051] Preparing a defect sample of the interconnect structure defect by using the method for preparing a defect sample as described above;

[0052] Performing a failure analysis on the interconnect structure defect of the defect sample, where the failure analysis includes electrical analysis and physical property analysis.

[0053] For the defect sample prepared by the foregoing method that exposes the defect to be analyzed, electrical testing and analysis are performed using a nanoprobe to further confirm the planar position of the defect to be analyzed, and a structure for TEM (Transmission Electron Microscope) testing is formed accordingly for physical property testing. Those skilled in the art master the corresponding methods of electrical testing and physical property testing, which will not be elaborated here.

[0054] In summary, the present invention forms an opening as a mark on the interconnect structure at a preset distance from the defect to be analyzed, and uses the opening to expose multiple metal layers. When grinding and removing the interconnect structure on the defect to be analyzed, the difference in the grinding degree of the sidewall of the mark during the grinding process causes the interconnect structure around the mark to be stratified, that is, the interconnect structure closer to the top layer near the mark is ground more to form a stratified condition. Thus, the stratified condition can be relatively easily observed by using an optical microscope to judge the remaining number of layers of the interconnect structure, so as to achieve accurate positioning of the grinding process, and then accurately remove the interconnect structure on the target number of layers of the defect to be analyzed, so as to achieve the purpose of simply and efficiently preparing a defect sample.

[0055] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A method for preparing a defective sample, characterized in that, Comprising: Providing a semiconductor structure having a defect to be analyzed, the semiconductor structure including a substrate and an interconnect structure formed on the substrate, the interconnect structure including multiple metal layers, and the defect to be analyzed being located in the metal layer; Forming an even number of marks in the interconnect structure, the marks being spaced a preset distance from the defect to be analyzed, the marks being an opening that penetrates the interconnect structure and the sidewalls of the opening exposing the multiple metal layers, and the even number of marks being symmetrically and uniformly distributed around the defect to be analyzed; Grinding the interconnect structure to obtain a defect sample. Wherein, the interconnect structure around the marks shows a delamination condition along the sidewalls of the marks during the grinding process, and the remaining number of layers of the interconnect structure is judged by observing the delamination condition through an optical microscope for positioning during the grinding process. The interconnect structure further includes multiple dielectric layers, with the dielectric layers and the metal layers arranged alternately. The interconnect structure is ground to the dielectric layer above the metal layer where the defect to be analyzed is located to obtain the defect sample.

2. The preparation method of the defective sample according to claim 1, characterized in that, Forming the marks on the substrate by laser cutting or focused ion beam.

3. The method for preparing a defective sample according to claim 2, wherein The angle between the laser beam of the laser cutting or the focused ion beam and the substrate is 70° - 110°.

4. The method for preparing a defective sample according to claim 1, wherein The preset distance is the planar distance between the marks and the defect to be analyzed, and the planar distance is 100 microns - 200 microns.

5. The preparation method of the defective sample according to claim 4, characterized in that, The shape of the marks is rectangular, and the side length of the rectangle is 5 microns - 20 microns.

6. The method for preparing a defective sample according to claim 1, characterized in that, Removing the metal interconnect layers in the interconnect structure with an etching solution during the grinding process.

7. A failure analysis method for interconnect structure defects, characterized in that, Comprising: Preparing a defect sample including an interconnect structure defect by using the method for preparing a defect sample according to any one of claims 1 to 6; And, Performing a failure analysis on the interconnect structure defect of the defect sample, the failure analysis including electrical analysis and physical property analysis.

Images