Verification Device for Multi-Protocol Charging Chip

Abstract

The present invention relates to the technical field of charging chip verification, and discloses a verification device for a multi-protocol charging chip. The present invention conducts system verification on the digital circuit part of the multi-protocol charging chip through an FPGA main control unit, and conducts system verification on the analog circuit of the multi-protocol charging chip through a level conversion unit, a charging interface, a protocol detection unit, an analog-to-digital conversion unit, a power management control module, a control switch driving unit, and a discharging unit, so as to replace the traditional simulation software verification, which can more truly discover the defects in the chip circuit design, reduce the risk of chip tape-out processing, save R & D investment, and shorten the R & D cycle; in addition, software developers can develop and debug embedded software based on the present invention. After the chip is tape-out processed, software testing and debugging can be directly carried out on the test board and evaluation board of the chip, thereby further saving the time for software development and system debugging, and shortening the cycle from chip testing to application.

Description

Technical Field

[0001] The present invention relates to the technical field of charging chip verification, and particularly to a verification device for multi-protocol charging chips. Background Art

[0002] For different charging chip R & D companies, due to their different orientations to customers and terminals, the fast charging protocols of different charging chips are also different. Currently, the commonly used fast charging protocols include the PD fast charging protocol of the USB-IF organization, the QC fast charging protocol of Qualcomm, the FCP / SCP protocol of Huawei, the SFCP fast charging protocol of Spreadtrum, the AFC fast charging protocol of Samsung, the VOOC fast charging protocol of OPPO, the PE fast charging protocol of MediaTek, and the UFCS fast charging protocol released by the China Telecom Terminal Industry Association. These protocols were not compatible with each other in the initial stage and had their own mechanisms in connection detection and negotiation communication mechanisms. With the popularization of the Type-C interface standard and the improvement of the extended application mechanism, most of the private fast charging protocols support the PD fast charging protocol standard of the USB-IF organization in the latest version, and multi-protocol charging chips have emerged on the market.

[0003] Before multi-protocol charging chips are put on the market, they will go through the design and manufacturing processes. The design process mainly designs circuits such as the MCU, storage modules (FLASH and RAM), multi-fast charging protocol digital baseband modules, multi-fast charging protocol physical layer modules, power management control modules, and security detection modules of the chip. The manufacturing process maps the chip circuits onto wafers.

[0004] The design and tape-out processing costs of chips are high. For newly developed multi-protocol charging chips, in order to reduce production costs and R & D cycles, it is necessary to verify the circuit modules inside the chip before chip processing to ensure the correctness of the functions and performances of its digital circuits and analog circuits. Currently, most chip verifications are carried out by using FPGA to verify the digital circuits of the chip and using simulation software to verify the analog circuit part. However, the simulation results obtained by the Glory simulation software are only idealized results and there are differences from the actual operating results of the chip. Summary of the Invention

[0005] In view of the deficiencies of the background art, the present invention provides a verification device for multi-protocol charging chips to verify the analog circuits of multi-protocol charging chips.

[0006] To solve the above technical problems, the present invention provides the following technical solutions: A verification device for a multi-protocol charging chip, comprising an FPGA main control unit, an analog-to-digital conversion unit, and at least one charging interface; each charging interface is electrically connected to a protocol detection unit and a power management control module respectively, and the detection signal output end of the protocol detection unit is electrically connected to the FPGA main control unit; the power management control module includes a control switch, a power resistor, a differential amplification unit, and a DC-DC conversion unit;

[0007] The input end of the control switch is configured to input an external voltage, and the FPGA main control unit is electrically connected to the control end of the control switch to input a control signal for controlling its on / off to the control end of the control switch;

[0008] The output end of the control switch is electrically connected to one end of the power resistor, the other end of the power resistor is electrically connected to the input end of the DC-DC conversion unit, and the output end of the DC-DC conversion unit is electrically connected to the analog-to-digital conversion unit and the charging interface respectively; the analog-to-digital conversion unit converts the output voltage of the DC-DC conversion unit into a digital signal and sends it to the FPGA main control unit; the FPGA main control unit inputs an adjustment signal to the control end of the DC-DC conversion unit, and the DC-DC conversion unit responds to the adjustment signal and changes the magnitude of the output voltage;

[0009] One end and the other end of the power resistor are electrically connected to the first input end and the second input end of the differential amplification unit respectively, the output end of the differential amplification unit is electrically connected to the analog-to-digital conversion unit, and the analog-to-digital conversion unit converts the output signal of the differential amplification unit into a digital signal and sends it to the FPGA main control unit.

[0010] As a further technical solution, the present invention further includes a level conversion unit, and the FPGA main control unit is electrically connected to the analog-to-digital conversion unit and the protocol conversion unit through the level conversion unit.

[0011] As a further technical solution, the present invention further includes a control switch driving unit, the FPGA main control unit is connected to the input end of the control switch driving unit, and the output end of the control switch driving unit is electrically connected to the control end of the control switch.

[0012] As a further technical solution, the control switch includes a first PMOS transistor Q1 and a second PMOS transistor Q2; the drain of the first PMOS transistor Q1 is the input end of the control switch, the source of the first PMOS transistor Q1 is electrically connected to the source of the second PMOS transistor Q2 and one end of a resistor R2 respectively, and the drain of the second PMOS transistor Q2 is the output end of the control switch;

[0013] The control switch driving unit includes a triode Q3, a resistor R1, and a capacitor C3; the collector of the triode Q3 is the output end of the control switch driving unit, and is electrically connected to the gate of the first PMOS transistor Q1, the gate of the second PMOS transistor Q2, and the other end of the resistor R2 respectively; the base of the triode Q3 is electrically connected to one end of the resistor R1 and one end of the capacitor C3 respectively, and the other end of the resistor R1 is the input end of the control switch driving unit; the other end of the capacitor C3 and the emitter of the triode Q3 are grounded.

[0014] As a further technical solution, the present invention further includes a discharging unit, and the FPGA main control unit is electrically connected to one end of a power resistor through the discharging unit; the discharging unit includes a triode Q7, an NMOS transistor Q8, a resistor R3, a resistor R4, and a resistor R5; one end of the resistor R5 is electrically connected to one end of the power resistor, and the other end of the resistor R5 is electrically connected to one end of the resistor R4 and the drain of the NMOS transistor Q8 respectively, the other end of the resistor R4 is electrically connected to the collector of the triode Q7 and the gate of the NMOS transistor Q8 respectively, the base of the triode Q7 is electrically connected to one end of the resistor R3, the other end of the resistor R3 is electrically connected to the FPGA main control unit, and the emitter of the triode Q7 and the source of the NMOS transistor Q8 are both grounded.

[0015] As a further technical solution, the DC-DC conversion unit includes a DC-DC conversion chip of model SC8721.

[0016] As a further technical solution, the charging interface is a Type-C interface, and the protocol detection unit includes a CC fast charging protocol detection unit and a DP / DM fast charging protocol detection unit;

[0017] The CC fast charging protocol detection unit includes at least two first comparison units, a first enable switch K11, a first enable switch K12, a pull-up resistor, and a transceiver switching switch;

[0018] The first input end of the first comparison unit is electrically connected to the CC end of the Type-C interface through the first enable switch K11, and the enable end of the first enable switch K11 is electrically connected to the FPGA main control unit through the level conversion unit; the CC end of the Type-C interface is electrically connected to one end of the pull-up resistor through the first enable switch K12, the other end of the pull-up resistor is electrically connected to a 3.3V power supply, and the enable end of the second enable switch K12 is electrically connected to the FPGA main control unit through the level conversion unit; the CC end of the Type-C interface is also electrically connected to the transceiver switching switch, and the control end of the transceiver switching switch is electrically connected to the FPGA main control unit; the second input end of the first comparison unit inputs a reference voltage, and the output end of the first comparison unit is electrically connected to the FPGA main control unit through the level conversion unit;

[0019] The DP / DM fast charging protocol detection unit includes eight second comparison units, second enable switches K21, K22, K23, K24, K25, and an NMOS transistor Q20;

[0020] The first input terminals of four second comparison units are electrically connected to the DP terminal of the Type-C interface through the second enable switch K21, and the first input terminals of the other four second comparison units are electrically connected to the DM terminal of the Type-C interface through the second enable switch K22. The second input terminals of the eight second comparison units respectively input a reference voltage, and the output terminals of the eight second comparison units are electrically connected to the FPGA main control unit through the level conversion unit. The enable terminals of the second switch K21 and the second switch K22 are electrically connected to the FPGA main control unit through the level conversion unit;

[0021] The DP terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q20, the DM terminal of the Type-C interface is electrically connected to the source of the NMOS transistor Q20, the gate of the NMOS transistor Q20 is electrically connected to an NMOS transistor drive circuit, and the control terminal of the NMOS transistor drive circuit is electrically connected to the FPGA main control unit;

[0022] The DP terminal of the Type-C interface is electrically connected to the second enable switch K23, and the input terminal and the enable terminal of the second enable switch K23 are electrically connected to the FPGA main control unit through the level conversion unit; the DP terminal of the Type-C interface is electrically connected to the 2.75V power supply through the second enable switch K24, and the enable terminal of the second enable switch K24 is electrically connected to the FPGA main control unit; the DP terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q201, the source of the NMOS transistor Q201 is grounded through the resistor R13, the gate of the NMOS transistor Q201 is electrically connected to both the FPGA main control unit and one end of the resistor R14, and the other end of the resistor R14 is grounded;

[0023] The DM terminal of the Type-C interface is electrically connected to the second enable switch K25, and the input terminal and the enable terminal of the second enable switch K25 are electrically connected to the FPGA main control unit through the level conversion unit; the DM terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q202, the source of the NMOS transistor Q202 is grounded through the resistor R26, the gate of the NMOS transistor Q202 is electrically connected to both the FPGA main control unit and one end of the resistor R28, and the other end of the resistor R28 is grounded; the DM terminal of the Type-C interface is electrically connected to the 1.2V power supply through the second enable switch K26, and the enable terminal of the second enable switch K26 is electrically connected to the FPGA main control unit.

[0024] As a further technical solution, the present invention further includes a PMU power management unit, and the PMU power management unit is configured to perform power management, including providing a reference voltage.

[0025] The beneficial effects of the present invention compared with the prior art are as follows: By using the present invention, the digital circuits and analog circuits inside the chip can be systematically verified before the multi-protocol charging chip is processed by chip fabrication, so as to replace the verification by traditional simulation software, which can more truly discover the defects in the chip circuit design, reduce the risk of chip fabrication, reduce the design iteration of chip fabrication, save R & D investment and shorten the R & D cycle.

[0026] In addition, software developers can develop and debug embedded software based on the present invention. After the chip is processed by chip fabrication, software testing and debugging can be directly carried out on the test board and evaluation board of the chip, thereby further saving the time of software development and system debugging, and further shortening the cycle from chip testing to application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of the present invention in the embodiment;

[0028] Figure 2 is a circuit diagram of the control switch and the control switch driving unit in the embodiment;

[0029] Figure 3 is a circuit diagram of the discharging unit in the embodiment;

[0030] Figure 4 is a circuit diagram of the DC-DC conversion unit in the embodiment;

[0031] Figure 5 is a circuit diagram of the CC fast charging protocol detection unit in the embodiment;

[0032] Figure 6 is a connection circuit diagram of eight second comparison units, a level conversion unit, a second enable switch K21 and a second enable switch K22 of the DP / DM fast charging protocol detection unit in the embodiment;

[0033] Figure 7 is a circuit diagram of the remaining circuit of the DP / DM fast charging protocol detection unit in the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] Now, the present invention will be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention.

[0035] As Figure 1As shown in the figure, a verification device for a multi-protocol charging chip includes an FPGA main control unit 1, two charging interfaces 3, a protocol detection unit 4, an analog-to-digital conversion unit 5, a control switch driving unit 7, and a discharging unit 8;

[0036] Each charging interface 4 is electrically connected to the protocol detection unit 4 and the power management control module respectively. The detection signal output terminal of the protocol detection unit 4 is electrically connected to the FPGA main control unit;

[0037] Taking a single power management module as an example, a single power management control module includes a control switch 61, a power resistor, a differential amplification unit 62, and a DC-DC conversion unit 60;

[0038] The input terminal of the control switch 61 is configured to input an external voltage. The FPGA main control unit 1 is electrically connected to the control terminal of the control switch 61 to input a control signal for controlling its on / off to the control terminal of the control switch 61. The output terminal of the control switch 61 is electrically connected to one end of the power resistor R1. The other end of the power resistor R1 is electrically connected to the input terminal of the DC-DC conversion unit 60. The output terminal of the DC-DC conversion unit 60 is electrically connected to the analog-to-digital conversion unit 5 and the charging interface 3 respectively. The analog-to-digital conversion unit converts the output voltage of the DC-DC conversion unit into a digital signal and then sends it to the FPGA main control unit 1. The FPGA main control unit 1 inputs an adjustment signal to the control terminal of the DC-DC conversion unit 60, and the DC-DC conversion unit 60 responds to the adjustment signal and changes the magnitude of the output voltage;

[0039] In addition, one end and the other end of the power resistor R1 are electrically connected to the first input terminal and the second input terminal of the differential amplification unit 62 respectively. The output terminal of the differential amplification unit 62 is electrically connected to the analog-to-digital conversion unit 5. The analog-to-digital conversion unit 5 converts the output signal of the differential amplification unit 62 into a digital signal and then sends it to the FPGA main control unit 1 through the level conversion unit 2.

[0040] During actual use, the protocol detection unit 4 determines the current charging protocol type by detecting the voltage at the charging terminal of the charging interface 3 and sends the charging result to the FPGA main control unit 1. The FPGA main control unit 1 adjusts the magnitude of the charging voltage input from the power management control module to the charging interface 3 based on the detected charging protocol type. Specifically, the FPGA main control unit 1 sends an adjustment signal to the DC-DC conversion unit 60, and the DC-DC conversion unit 60 responds to the adjustment signal and changes the magnitude of the voltage input to the charging interface 3.

[0041] During actual use, the multi-protocol charging chip is electrically connected to the charging interface 3. By according to the detected charging protocol, the charging interface 3 can output voltages of different specifications, thereby realizing the simulation circuit verification of the multi-protocol charging chip.

[0042] Refer toFigure 4 , in this embodiment, the DC-DC conversion unit 60 includes a DC-DC conversion chip of model SC8721. The 4th, 5th, and 6th pins of the DC-DC conversion chip are electrically connected to the FPGA main control unit, and the 1st pin of the DC-DC conversion chip is electrically connected to the charging interface.

[0043] During actual use, the differential amplification unit 62 detects the voltage difference across the power resistor R1. The analog-to-digital conversion unit 5 converts the output signal of the differential amplification unit 5 into a digital signal and sends it to the FPGA main control unit 1, enabling the FPGA main control unit 1 to know the current charging current. When the charging current is abnormal, i.e., overcurrent or undercurrent occurs, the control switch 61 can be disconnected to achieve charging current protection. Additionally, the analog-to-digital conversion unit 5 performs analog-to-digital conversion on the output voltage of the DC-DC conversion unit 60 and sends the converted digital signal to the FPGA main control unit 1, enabling the FPGA main control unit 1 to know the magnitude of the current charging voltage. When the charging voltage is abnormal, i.e., overvoltage or undervoltage occurs, the control switch 61 can be disconnected to achieve charging voltage protection.

[0044] During actual use, if the signal processing standards of the FPGA main control unit 1 and the analog-to-digital conversion unit 5, protocol detection unit 4, or other peripheral circuits are different, level conversion is required to ensure the normal operation of the verification device. For example, if the signal output by the IO port of the FPGA main control unit 1 is a 2.5V level signal, while the level signal of the protocol detection unit 4 is 1.2V or 3.3V, the level conversion unit 2 is needed to achieve signal matching conversion between the FPGA main control unit and peripheral circuits such as the protocol detection unit 4, thereby ensuring the normal operation of the verification device. Since the FPGA main control unit 1 in this embodiment uses a chip of model XC7A200T-2FBG676C, the level signal of the IO port of this chip is 2.5V, which is different from Figure 5 , Figure 6 and Figure 7 the level specifications of the protocol detection unit 4 shown, and the level conversion unit 2 is required to ensure the normal operation of the FPGA main control unit 1 and the protocol detection unit 4.

[0045] As a further technical solution, the present invention further includes a control switch driving unit 7 and a discharging unit 8. The FPGA main control unit 1 is electrically connected to the input end of the control switch driving unit 7 and the discharging unit 8. The output end of the control switch driving unit 7 is electrically connected to the control end of the control switch 61, and the discharging unit 8 is electrically connected to one end of the power resistor.

[0046] Specifically, referring to Figure 2, in this embodiment, the control switch 61 includes a first PMOS transistor Q1 and a second PMOS transistor Q2; the drain of the first PMOS transistor Q1 is the input terminal of the control switch 61, the source of the first PMOS transistor Q1 is electrically connected to the source of the second PMOS transistor Q2 and one end of the resistor R2 respectively, and the drain of the second PMOS transistor Q2 is the output terminal of the control switch 61;

[0047] The control switch driving unit 7 includes a transistor Q3, a resistor R1 and a capacitor C3; the collector of the transistor Q3 is the output terminal of the control switch driving unit 7, and is electrically connected to the gate of the first PMOS transistor Q1, the gate of the second PMOS transistor Q2 and the other end of the resistor R2 respectively; the base of the transistor Q3 is electrically connected to one end of the resistor R1 and one end of the capacitor C3 respectively, and the other end of the resistor R1 is the input terminal of the control switch driving unit 7; the other end of the capacitor C3 and the emitter of the transistor Q3 are grounded.

[0048] In actual use, when the transistor Q3 is turned on, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned on, and the control switch 61 is turned on. When the transistor Q3 is turned off, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned off, and the control switch 61 is turned off.

[0049] Refer to Figure 3 , the discharging unit 8 includes a transistor Q7, an NMOS transistor Q8, a resistor R3, a resistor R4 and a resistor R5; one end of the resistor R5 is electrically connected to one end of the power resistor, the other end of the resistor R5 is electrically connected to one end of the resistor R4 and the drain of the NMOS transistor Q8 respectively, the other end of the resistor R4 is electrically connected to the collector of the transistor Q7 and the gate of the NMOS transistor Q8 respectively, the base of the transistor Q7 is electrically connected to one end of the resistor R3, the other end of the resistor R3 is electrically connected to the FPGA main control unit, and the emitter of the transistor Q7 and the source of the NMOS transistor Q8 are both grounded.

[0050] In actual use, when the transistor Q7 is turned on, the NMOS transistor Q8 is turned on, and at this time, the power resistor discharges through the NMOS transistor Q8.

[0051] In this embodiment, the charging interface 3 is a Type-C interface, and the protocol detection unit 4 includes a CC fast charging protocol detection unit and a DP / DM fast charging protocol detection unit;

[0052] The circuit of the CC fast charging protocol detection unit is as Figure 5 shown, and it can be obtained from Figure 5 that the CC fast charging protocol detection unit includes at least two first comparison units, a first enable switch K11, a first enable switch K12, a pull-up resistor and a transceiver switching switch, where the chip U7 is an operational amplifier chip including two-way comparison units;

[0053] The first input terminal of the first comparison unit, namely the 3rd and 5th pins of chip U7, is electrically connected to the CC terminal of the Type-C interface through the first enable switch K11. The enable terminal of the first enable switch K11, namely its 4th pin, is electrically connected to the FPGA main control unit 1 through the level conversion unit 2; the CC terminal of the Type-C interface is electrically connected to one end of the pull-up resistor through the first enable switch K12. The other end of the pull-up resistor is electrically connected to the 3.3V power supply. The pull-up resistor includes resistor R15, resistor R16, and resistor R14. The enable terminal of the second enable switch K12 is electrically connected to the FPGA main control unit 1 through the level conversion unit 2; the CC terminal of the Type-C interface is also electrically connected to the transceiver switching switch K3. The control terminal of the transceiver switching switch K3 is electrically connected to the FPGA main control unit 1; the second input terminal of the first comparison unit inputs a reference voltage. The output terminal of the first comparison unit is electrically connected to the FPGA main control unit 1 through the level conversion unit 2; in this embodiment, the reference voltage input to the second input terminal of the first comparison unit is adjustable. Among them, the 1.8V power supply is grounded through resistor R19 and resistor R18. Resistor R18 is a sliding rheostat. The sliding terminal of the sliding rheostat is electrically connected to the second input terminal of the first comparison unit. By changing the resistance value of the sliding rheostat, the magnitude of the reference voltage input to the second input terminal of the first comparison unit can be adjusted; in actual use, by providing different magnitudes of reference voltages to the second input terminals of the two first comparison units, the detection of different fast charging protocols can be achieved.

[0054] As Figure 6 and Figure 7 shown, the DP / DM fast charging protocol detection unit includes eight second comparison units, second enable switch K21, second enable switch K22, second enable switch K23, second enable switch K24, second enable switch K25, and NMOS transistor Q20; the eight second comparison units are implemented by comparison chips U20, U21, U11, and U12. The comparison chips U20, U21, U11, and U12 all include two comparison units;

[0055] Refer to Figure 6, the first input terminals of the four second comparison units, namely the 3rd and 5th pins of chip U20, the 3rd and 5th pins of chip U21, are electrically connected to the DP terminal of the Type-C interface through the second enable switch K21. The first input terminals of the other four second comparison units, namely the 3rd and 5th pins of U11 and the 3rd and 5th pins of chip U12, are electrically connected to the DM terminal of the Type-C interface through the second enable switch K22. The second input terminals of the eight second comparison units, namely the 2nd and 6th pins of U20, the 2nd and 6th pins of chip U21, the 2nd and 6th pins of U11, and the 2nd and 6th pins of chip U12, respectively input a reference voltage, and this reference voltage is also adjustable. The output terminals of the eight second comparison units, namely the 1st and 7th pins of U20, the 1st and 7th pins of chip U21, the 1st and 7th pins of U11, and the 1st and 7th pins of chip U12, are electrically connected to the FPGA main control unit through the level conversion unit 2. The enable terminals of the second switch K21 and the second switch K22 are electrically connected to the FPGA main control unit 1 through the level conversion unit 2;

[0056] Refer to Figure 7 , the DP terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q20, the DM terminal of the Type-C interface is electrically connected to the source of the NMOS transistor Q20, the gate of the NMOS transistor Q20 is electrically connected to the NMOS transistor drive circuit 40, and the control terminal of the NMOS transistor drive circuit 40 is electrically connected to the FPGA main control unit 1;

[0057] The DP terminal of the Type-C interface is electrically connected to the second enable switch K23. The input terminal and the enable terminal of the second enable switch K23 are electrically connected to the FPGA main control unit 1 through the level conversion unit 2. The DP terminal of the Type-C interface is electrically connected to the 2.75V power supply through the second enable switch K24, and the enable terminal of the second enable switch K24 is electrically connected to the FPGA main control unit 1. The DP terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q201. The source of the NMOS transistor Q201 is grounded through the resistor R13. The gate of the NMOS transistor Q201 is electrically connected to the FPGA main control unit and one end of the resistor R14 respectively, and the other end of the resistor R14 is grounded;

[0058] The DM terminal of the Type-C interface is electrically connected to the second enabling switch K25. The input terminal and the enabling terminal of the second enabling switch K25 are electrically connected to the FPGA main control unit 1 through the level conversion unit 2. The DM terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q202. The source of the NMOS transistor Q202 is grounded through the resistor R26. The gate of the NMOS transistor Q202 is electrically connected to both the FPGA main control unit and one end of the resistor R28, and the other end of the resistor R28 is grounded. The DM terminal of the Type-C interface is electrically connected to the 1.2V power supply through the second enabling switch K26, and the enabling terminal of the second enabling switch K26 is electrically connected to the FPGA main control unit 1.

[0059] During actual use, when the charging protocols are different, the voltages input to the first input terminal of the second comparison unit also vary. By providing different reference voltages to the second input terminals of the eight second comparison units and based on the output signals of the eight second comparison units, the detection of different fast charging protocols can be achieved.

[0060] It should be noted that in Figures 2 - 6 the circuit shown, the electrical node marked as FPGA IO is actually electrically connected to the IO interface of the FPGA main control unit.

[0061] As a further technical solution, the present invention further includes a PMU power management unit, which is configured to perform power management, including providing a reference voltage. During actual use, an external voltage is input to the PMU power management unit, and the PMU power management unit provides reference voltages of different specifications, such as 1.2V DC voltage, 1.8V DC voltage, 2.5V DC voltage, 2.75V DC voltage, 3.3V DC voltage, and -3.3V DC voltage.

[0062] During actual use, through the FPGA main control unit 1, the digital circuit part of the multi-protocol charging chip can be systematically verified, and through the level conversion unit 2, the charging interface 3, the protocol detection unit 4, the analog-to-digital conversion unit 5, the power management control module, the control switch drive unit 7, and the discharge unit 8, the analog circuit of the multi-protocol charging chip can be systematically verified, replacing the traditional simulation software verification. It can more truly discover the defects in the chip circuit design, reduce the risk of chip tape-out processing, reduce the design tape-out iteration, save R & D investment, and shorten the R & D cycle.

[0063] In addition, software developers can develop and debug embedded software based on the present invention. After the chip tape-out processing is completed, software testing and debugging can be directly carried out on the test board and evaluation board of the chip, further saving the time for software development and system debugging, and further shortening the cycle from chip testing to application.

[0064] Based on the inspiration of the present invention, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. Verification device for multi-protocol charging chip, including an FPGA main control unit, characterized in that, It further includes an analog-to-digital conversion unit and at least one charging interface; each charging interface is electrically connected to a protocol detection unit and a power management control module respectively, and the detection signal output end of the protocol detection unit is electrically connected to the FPGA main control unit; the power management control module includes a control switch, a power resistor, a differential amplification unit and a DC-DC conversion unit; The input end of the control switch is configured to input an external voltage, and the FPGA main control unit is electrically connected to the control end of the control switch to input a control signal for controlling its on-off to the control end of the control switch; The output end of the control switch is electrically connected to one end of the power resistor, the other end of the power resistor is electrically connected to the input end of the DC-DC conversion unit, and the output end of the DC-DC conversion unit is electrically connected to the analog-to-digital conversion unit and the charging interface respectively; the analog-to-digital conversion unit converts the output voltage of the DC-DC conversion unit into a digital signal and sends it to the FPGA main control unit; the FPGA main control unit inputs an adjustment signal to the control end of the DC-DC conversion unit, and the DC-DC conversion unit responds to the adjustment signal and changes the magnitude of the output voltage; One end and the other end of the power resistor are electrically connected to the first input end and the second input end of the differential amplification unit respectively, the output end of the differential amplification unit is electrically connected to the analog-to-digital conversion unit, and the analog-to-digital conversion unit converts the output signal of the differential amplification unit into a digital signal and then sends it to the FPGA main control unit; It further includes a level conversion unit, and the FPGA main control unit is electrically connected to the analog-to-digital conversion unit and the protocol conversion unit through the level conversion unit; The DC-DC conversion unit includes a DC-DC conversion chip with the model number SC8721.

2. The verification device for the multi-protocol charging chip according to claim 1, wherein It further includes a control switch driving unit, the FPGA main control unit is electrically connected to the input end of the control switch driving unit, and the output end of the control switch driving unit is electrically connected to the control end of the control switch.

3. The verification device for the multi-protocol charging chip according to claim 2, wherein The control switch includes a first PMOS transistor Q1 and a second PMOS transistor Q2; the drain of the first PMOS transistor Q1 is the input end of the control switch, the source of the first PMOS transistor Q1 is electrically connected to the source of the second PMOS transistor Q2 and one end of a resistor R2 respectively, and the drain of the second PMOS transistor Q2 is the output end of the control switch; The control switch driving unit includes a triode Q3, a resistor R1 and a capacitor C3; the collector of the triode Q3 is the output end of the control switch driving unit, and is electrically connected to the gate of the first PMOS transistor Q1, the gate of the second PMOS transistor Q2 and the other end of the resistor R2 respectively; the base of the triode Q3 is electrically connected to one end of the resistor R1 and one end of the capacitor C3 respectively, and the other end of the resistor R1 is the input end of the control switch driving unit; the other end of the capacitor C3 and the emitter of the triode Q3 are grounded.

4. The verification device for the multi-protocol charging chip according to claim 1, characterized in that It further includes a discharging unit, and the discharging unit includes a triode Q7, an NMOS transistor Q8, a resistor R3, a resistor R4, and a resistor R5; one end of the resistor R5 is electrically connected to one end of the power resistor, the other end of the resistor R5 is respectively electrically connected to one end of the resistor R4 and the drain of the NMOS transistor Q8, the other end of the resistor R4 is respectively electrically connected to the collector of the triode Q7 and the gate of the NMOS transistor Q8, the base of the triode Q7 is electrically connected to one end of the resistor R3, the other end of the resistor R3 is electrically connected to the FPGA main control unit, and the emitter of the triode Q7 and the source of the NMOS transistor Q8 are both grounded.

5. The verification device for the multi-protocol charging chip according to claim 1, wherein The charging interface is a Type-C interface, and the protocol detection unit includes a CC fast charging protocol detection unit and a DP / DM fast charging protocol detection unit; The CC fast charging protocol detection unit includes at least two first comparison units, a first enable switch K11, a first enable switch K12, a pull-up resistor, and a transceiver switching switch; The first input terminal of the first comparison unit is electrically connected to the CC terminal of the Type-C interface through the first enable switch K11, and the enable terminal of the first enable switch K11 is electrically connected to the FPGA main control unit through the level conversion unit; the CC terminal of the Type-C interface is electrically connected to one end of the pull-up resistor through the first enable switch K12, the other end of the pull-up resistor is electrically connected to the 3.3V power supply, and the enable terminal of the first enable switch K12 is electrically connected to the FPGA main control unit through the level conversion unit; the CC terminal of the Type-C interface is also electrically connected to the transceiver switching switch, and the control terminal of the transceiver switching switch is electrically connected to the FPGA main control unit; the second input terminal of the first comparison unit inputs a reference voltage, and the output terminal of the first comparison unit is electrically connected to the FPGA main control unit through the level conversion unit; The DP / DM fast charging protocol detection unit includes eight second comparison units, a second enable switch K21, a second enable switch K22, a second enable switch K23, a second enable switch K24, a second enable switch K25, and an NMOS transistor Q20; The first input terminals of four second comparison units are electrically connected to the DP terminal of the Type-C interface through the second enable switch K21, the first input terminals of the other four second comparison units are electrically connected to the DM terminal of the Type-C interface through the second enable switch K22, the second input terminals of the eight second comparison units respectively input reference voltages, the output terminals of the eight second comparison units are electrically connected to the FPGA main control unit through the level conversion unit, and the enable terminals of the second enable switch K21 and the second enable switch K22 are electrically connected to the FPGA main control unit through the level conversion unit; The DP terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q20, the DM terminal of the Type-C interface is electrically connected to the source of the NMOS transistor Q20, the gate of the NMOS transistor Q20 is electrically connected to an NMOS transistor driving circuit, and the control terminal of the NMOS transistor driving circuit is electrically connected to the FPGA main control unit; The DP terminal of the Type-C interface is electrically connected to the second enable switch K23. The input terminal and the enable terminal of the second enable switch K23 are electrically connected to the FPGA main control unit through the level conversion unit; the DP terminal of the Type-C interface is electrically connected to the 2.75V power supply through the second enable switch K24, and the enable terminal of the second enable switch K24 is electrically connected to the FPGA main control unit; the DP terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q201. The source of the NMOS transistor Q201 is grounded through the resistor R13. The gate of the NMOS transistor Q201 is electrically connected to both the FPGA main control unit and one end of the resistor R14, and the other end of the resistor R14 is grounded; The DM terminal of the Type-C interface is electrically connected to the second enable switch K25. The input terminal and the enable terminal of the second enable switch K25 are electrically connected to the FPGA main control unit through the level conversion unit; the DM terminal of the Type-C interface is electrically connected to the drain of the NMOS transistor Q202. The source of the NMOS transistor Q202 is grounded through the resistor R26. The gate of the NMOS transistor Q202 is electrically connected to both the FPGA main control unit and one end of the resistor R28, and the other end of the resistor R28 is grounded; the DM terminal of the Type-C interface is electrically connected to the 1.2V power supply through the second enable switch K26, and the enable terminal of the second enable switch K26 is electrically connected to the FPGA main control unit.

6. The verification device for the multi-protocol charging chip according to claim 5, wherein It further includes a PMU power management unit, which is configured to perform power management, including providing a reference voltage.

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