A new industrial communication bus controller

Abstract

The application relates to a novel industrial communication bus controller which mainly comprises a PLL, a CLKDIV clock frequency division module, a configuration management module, an interface management unit, a sending controller, a bit stream processor, a data check unit, a transceiving FIFO, an error management and transceiving state management module. When the product is applied, the MCU gives data to the bus controller, the bus controller performs check on the data and participates in bus competition, and automatically completes data sending. The controller automatically receives bus data and performs check, and the MCU reads the data and applies the same, so that a field bus system which is compatible with RS-485 and has real-time communication can be developed by users in a short period, and therefore the bus controller is particularly suitable for RS-485 product technology upgrading and helps to obviously improve communication and control performance.

Description

TECHNICAL FIELD

[0001] The present application relates to a new type of industrial communication bus controller, belonging to the field of industrial control. By using the controller, the processor can hand over the task of data communication to the controller, and the new field bus system can increase the real-time communication capability on the basis of preserving the traditional RS-485 long frame communication, significantly improve the flexibility of the bus system construction, the real-time performance of the system and the comprehensive cost. BACKGROUND

[0002] At present, the field bus commonly used in the industrial automation industry mainly includes CAN-bus and RS-485. The RS-485 bus has the advantages of low hardware cost, many nodes, simple use, unlimited single frame data length and long transmission distance.

[0003] RS-485 is a half-duplex bus, and the receiving and transmitting control of data in the communication process completely depends on the MCU. In the RS-485 bus system, a master-slave network structure is mainly used, each station is assigned an address, and the master station sends a command to poll and read the data of each station one by one. Another function of polling is to ensure that at any time, only one station in the network sends data to the bus. If multiple stations send data to the bus at the same time, the result will be that all stations cannot normally receive due to signal interference, and the system cannot normally communicate.

[0004] The RS-485 bus is widely used in industrial control occasions, and the main products include PLC, frequency converter, remote I / O module, sensor, etc. The most commonly used communication protocol based on the RS-485 bus is the Modbus RTU protocol.

[0005] When there are many slave stations in the RS-485 bus system, this one-master multi-slave communication mode will cause the communication efficiency of the system to be significantly reduced, because the time overhead required for polling all slave stations for one round is extremely large. If the existence of the situation that some slave stations have response timeout is considered, the time required for one round of polling will be further lengthened. The polling cycle is lengthened, and the real-time performance of the slave station data update is significantly deteriorated.

[0006] Compared with RS-485, CAN-bus has obvious advantages in communication real-time and aspect. CAN-bus bus system allows the existence of multiple master and slave, the station can actively send data, single frame data length is short, communication real-time is high. In CAN2.0A / B, it is stipulated that the length of a frame of data is at most 8 bytes, especially suitable for real-time control occasions. If a large amount of data needs to be sent through CAN-bus, then the data needs to be sent by unpacking, and the target station splices the data after receiving, which will lead to the increase of software development difficulty. In addition, CAN-bus has hard real-time, when the bus length is long, it is easy to cause response timeout error, leading to data transmission failure. CAN-bus has high requirements for the professional skills of users, and does not support long frame communication, which needs to invent a kind of field bus technology which has the advantages of CAN-bus and RS-485 and is reliable and easy to use. SUMMARY

[0007] The present application relates to a new type of industrial communication bus controller, the bus developed by using the controller can be compatible with traditional RS-485 bus, and through the introduction of bus competition, bus arbitration, data verification and other functions, the disadvantages of poor communication real-time of traditional RS-485 bus are overcome.

[0008] The bus controller block diagram described in the patent is shown in Figure 1 It is composed of PLL circuit (1), clock division circuit CLKDIV unit (2), configuration / mode management unit (3), interface management unit (4), receiving FIFO (5), bit stream processor (6), sending FIFO (7), sending controller (8), data verification unit (9) and state management unit (10).

[0009] Further, the PLL is connected with the external clock signal through the CLK pin, provides the clock multiplication for the controller, and the multiplication coefficient can be set. The clock signal after multiplication enters the CLKDIV unit, and the CLKDIV is used for clock division, and the clock after division provides data receiving trigger detection for the bit stream processor.

[0010] Further, the bus controller needs to be used with MCU. The MCU accesses the bus controller configuration operation parameters through the interface management unit, starts the bus controller, writes the sending data, receives the data and monitors the controller running state. All operations are completed by reading and writing internal registers.

[0011] Further, the configuration / mode management unit provides the controller with running configuration parameters, and the controller only allows configuration running parameters in the configuration mode. These configuration parameters include frequency multiplication coefficient, baud rate, transmission bit sequence, sampling point, check function, interruption, etc. The parameter configuration must be performed before the controller is enabled, and the configuration is completed, and the controller exits the configuration mode and enters the working mode by setting the mode register.

[0012] Further, the controller can perform data transmission and reception in the working mode. When data is transmitted, the data is written into the transmission FIFO through the controller interface, and a transmission request is performed. After the transmission request is executed, the controller locks the data in the transmission FIFO and calculates the checksum. If the current bus is in the idle state, the data will be immediately transmitted. If the bus is busy, the controller will participate in the bus competition after the bus is idle for the 11th bit, and the data will be sent out. At the same time, the controller continues to monitor RX and takes the value from RX at the preset sampling position. If the logical value of the sample is inconsistent with the transmission value, the controller will immediately stop transmission and participate in the next bus competition until the data transmission is completed.

[0013] Specifically, each frame of data transmitted or received is composed of consecutive n bytes (n is not greater than 255), based on SCI format transmission, including 1 start bit, 8 data bits and 1 stop bit, and there is no extra idle bit between bytes. The data transmission bit sequence can be adjusted, and can be set to MSB first transmission or LSB first transmission. In the scenario that needs to be compatible with RS-485 communication, the LSB first transmission should be set.

[0014] Further, the bus controller determines that the state of the bus is idle when it monitors 11 consecutive implicit bits.

[0015] Further, the bus controller triggers the start of the bit stream processor (6) to receive bus data bit by bit and automatically splice into bytes when it monitors a burst of falling edges. If the start bit is abnormal or the stop bit is abnormal, the bit stream processor will stop data reception and report an error. After the data reception is completed and the reception is correct, the data is stored in the idle reception FIFO, and if all the reception FIFOs are unavailable, a data overflow error is generated. After the data is successfully stored, the state register changes, and the data reception can be performed through interruption or state query.

[0016] Further, the bus controller of the present patent performs transmission and reception check on data in the form of summation. The data check function can be turned on or off by configuration. Only when the bus controller turns on the check function, the data transmission and reception perform data check. In the case of turning off the check function, the data transmission and reception do not perform check.

[0017] Further, to avoid the receiving error caused by the clock bias between the sender and the receiver, the receiving controller completes the data receiving synchronization through the data start bit.

[0018] Further, the bus controller of the present patent supports error identification, including bus clamp timeout error, frame interval error, bit error, and receiving check error.

[0019] Further, the bus controller of the present patent supports single transmission and automatic retransmission mode.

[0020] Further, the data receiving completion, data sending completion, and bus error interrupt output are supported.

[0021] By using the bus controller of the present patent, the user can easily construct a multi-master multi-slave fieldbus system, while the traditional RS-485 can only construct a single-master multi-slave system. In the bus system developed based on the controller of the present patent, the data receiving and sending process control is mainly completed by the bus controller, and each station can freely send data, and the entire network is no longer dependent on the polling mode communication. The data request is greatly reduced, the bus occupancy rate is reduced, and the communication real-time performance is significantly enhanced. The larger the size of the station, the more obvious the real-time performance advantage.

[0022] At the same time, the controller of the present patent can send up to 255 bytes in a single frame, which is compatible with the RS-485 bus. In this way, for the stations without real-time requirements, RS-485 communication can continue to be used, and communication is realized through polling mode. For stations with real-time requirements, the controller of the present patent is used. Such a hybrid mode can maximize the balance between economy and practicality.

[0023] In addition, the controller of the present patent does not support bus filtering and ACK response, so the application configuration is simpler and easier to use than CAN-bus.

[0024] The multi-station bus system based on the present patent is shown in the schematic diagram Figure 4 . BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The communication controller block diagram

[0026] Figure 2 The transceiver circuit diagram

[0027] Figure 3 The controller application schematic diagram

[0028] Figure 4 The bus network schematic diagram

[0029] In the figure: 1, PLL circuit, 2, clock frequency division circuit, 3, configuration / mode management module, 4, interface management unit, 5, receive FIFO, 6, bit stream processor, 7, send FIFO, 8, send controller, 9, data check unit, 10, state management unit. DETAILED DESCRIPTION

[0030] The present application relates to a new type of industrial communication bus controller, the communication controller system block diagram as shown in Figure 1 It is composed of PLL circuit (1), clock frequency division circuit CLKDIV unit (2), configuration / mode management unit (3), interface management unit (4), receive FIFO (5), bit stream processor (6), send FIFO (7), send controller (8), data check unit (9) and state management unit (10).

[0031] In order to facilitate the development and application of the controller, the necessary communication and control interface is defined in the application for the controller, which is used to realize the MCU configuration and data reading of the controller. The controller pin definition is shown in table 1.

[0032] Table 1 controller pin definition

[0033]

[0034] When the bus controller is applied, it must be matched with the bus transceiver circuit. The recommended transceiver circuit in the patent is shown in Figure 2 It is compatible with RS-485 transceiver. The transceiver converts the TTL signal output by the bus controller into bus differential signal, and converts the bus differential signal into TTL output to the bus controller. The differential signal has better interference suppression ability in the transmission process, longer transmission distance and higher reliability. The truth table of the transceiver circuit is shown in table 2.

[0035] Table 2 transceiver truth table

[0036]

[0037] In the implicit state, the voltage of DH and DL is maintained by resistance pull-up and pull-down. In the explicit state, DH is directly connected with the ground through the transistor, and DL is connected with + 5V, so that the bus is clamped instantaneously, only showing the explicit state. This is the basis for the bus controller in the application to realize communication bit arbitration. When multiple transceivers are connected to the bus, the bus after superposition (logic &) of different signals is shown in table 3.

[0038] Table 3 line and relationship table

[0039] Transmit signal 1 Transmit signal 2 Logical relationship Result Dominant Dominant & Dominant Dominant Recessive & Dominant Recessive Recessive & Recessive

[0040] The complete communication site is shown inFigure 3 As shown, by MCU, bus controller, transceiver and actuator. Transceiver is directly connected with bus. DH and DL represent bus data high and bus data low respectively, MCU communicates with other stations of network through controller and processes received data, and performs corresponding control action. The bus system schematic diagram composed of multiple stations based on the controller developed by the patent is shown in Figure 4 As shown, the new bus network also allows RS-485 devices to access, but RS-485 devices can still only work in polling mode in the new bus network.

[0041] Before the bus controller works, the MCU must configure it as necessary. Including the configuration of PLL frequency multiplication, baud rate, sampling point, verification, transmission bit sequence, transmission mode, and interrupt. After the configuration is completed, the MCU sets the mode register inside the bus controller to exit the configuration mode and enter the working mode.

[0042] The controller sends the FIFO depth of 255 bytes, so the single transmission data length must not exceed 255 bytes. Before starting transmission, the MCU writes the data to be sent to the controller's transmit FIFO. After the data is ready, execute data transmission by setting the transmit request bit inside the controller.

[0043] After the data transmission request is executed, if data verification is enabled, the controller will automatically complete data verification and calculation before data is sent. At the same time, the bus controller will determine the timing of data transmission according to the current bus state. When the controller detects that the current bus is in an idle state, the data will be sent immediately. If the current bus is being occupied, it will participate in bus competition and try to send data after the bus is idle for the 11th bit. If the competition fails during transmission, the controller will determine whether to resend the next time the bus is idle according to the configured transmission mode.

[0044] The controller verification algorithm is as follows:

[0045] Sum is an 8-bit unsigned number, the initial value is 0.

[0046] Sum = data1 + data2 +... + dataN

[0047] Sum = ~sum + 1

[0048] During transmission, the controller will sample the bus at the preset sampling position through RX after each data bit is sent, and compare the sampling value with the current transmission value. If the transmission is a recessive bit, but RX sampling is a dominant bit, indicating arbitration failure, the controller will immediately stop this round of transmission. If a dominant bit is sent and a recessive bit is monitored, a bit error will occur. Similarly, the controller will also produce a bit error when it stops monitoring a dominant bit.

[0049] The bus data receiving is completed by the bus controller bit stream processor, which detects the bus data by a data start bit and starts receiving, and continuously converts the serial bit stream into byte data. During the receiving process, if the controller opens the check function, the controller performs the check on the received data, and when the frame data receiving is completed, if the check result is correct, the data will be transferred to the receiving FIFO and the MCU is informed by the state or interrupt that the new data receiving is completed.

[0050] The bus controller is internally provided with three receiving FIFOs, and the depth of each FIFO is 255 bytes. After receiving new data, if the receiving FIFOs are all not empty, a receiving overflow error will be generated, and the overflow data is automatically discarded.

[0051] The controller running state, bus error state, FIFO state, data sending state and various states can be inquired through the state register of the bus controller. If the corresponding interrupt is opened, when the state is set, the interrupt will be triggered to inform the MCU to process the corresponding event, so that the working efficiency of the MCU can be improved.

[0052] At present, the bus controller has been developed and verified on the FPGA through Verilog, and practical application tests have been carried out, and the main functions meet the design expectation.

[0053] The above is the description of the specific embodiments of the present application, but not the limitation of the present application, and the person skilled in the art can make various transformations and changes without departing from the spirit and scope of the present application, so that the corresponding equivalent technical solutions can be obtained, therefore all equivalent technical solutions should be included in the protection scope of the present application.

Claims

1. A new type of industrial communication bus controller, characterized in that The bus controller is composed of a PLL circuit (1), a clock dividing circuit CLKDIV unit (2), a configuration / mode management unit (3), an interface management unit (4), a receiving FIFO (5), a bit stream processor (6), a sending FIFO (7), a sending controller (8), a data check unit (9) and a state management unit (10); The new type industrial communication bus controller has a communication bit arbitration function, each station can send data at the same time; during data sending, when the bus sampling value is different from the sending value, the controller stops data sending; In the implicit state, the voltage of DH and DL is maintained by resistance pull-up and pull-down, in the explicit state, DH is directly connected with the ground through a transistor, and DL is connected with the positive pole of the transceiver power supply, so that the bus is clamped instantaneously, and only the explicit state is reflected; During sending, the controller samples the bus at a preset sampling position through RX after sending each data bit, and compares the sampling value with the current sending value, if a implicit bit is sent, but the RX sampling is an explicit bit, which indicates that the arbitration fails, and the controller immediately stops the current sending; The transceiver converts the TTL signal sent by the bus controller into a bus differential signal, and converts the bus differential signal into a TTL output to the bus controller; The PLL is connected with an external clock signal through a CLK pin, provides clock frequency multiplication for the controller, and the frequency multiplication coefficient can be set; the clock signal after frequency multiplication enters the CLKDIV unit, and CLKDIV is used for clock division; the clock after frequency division provides data receiving trigger detection for the bit stream processor; The bus controller needs to be used in cooperation with an MCU; the MCU accesses the bus controller configuration operation parameters through the interface management unit, starts the bus controller, writes sending data, receives data and monitors the controller running state; all operations are completed through reading and writing internal registers; The configuration / mode management unit provides running configuration parameters for the controller, and the controller only allows configuration running parameters in the configuration mode; the configuration parameters include frequency multiplication coefficient, baud rate, sending bit sequence, sampling point, check function and interruption; the controller must be configured with parameters before being started, and after the configuration is completed, the configuration mode is exited and the working mode is entered by setting a mode register; The controller can execute data sending and receiving in the working mode; during data sending, the data is written into the sending FIFO through the controller interface, and a sending request is executed; After the sending request is executed, the controller locks the data in the sending FIFO and calculates the check sum; if the current bus is in an idle state, the data will be immediately sent; if the bus is busy, the controller will participate in bus competition at the 11th bit after the bus is idle, and the data is sent out; at the same time, the controller continuously monitors RX, and takes the value from RX at a preset sampling position; if the sampled logic value is inconsistent with the sending value, the controller will immediately stop sending, and participate in the next bus competition until the data sending is completed; The transceiver converts the TTL signal sent by the bus controller into a bus differential signal, and converts the bus differential signal into a TTL output to the bus controller; Each frame of data sent or received consists of n consecutive bytes, where n is not greater than 255, based on SCI format transmission, including 1 start bit, 8 data bits and 1 stop bit, no extra idle bit between bytes; the bit sequence of data transmission can be adjusted, which can be set to MSB first or LSB first; in the scenario that needs to be compatible with RS-485 communication, the LSB first should be set; The bus controller determines that the state of the bus is idle when 11 consecutive recessive bits are monitored; The bus controller will trigger the start of the bit stream processor to receive the bus data bit by bit and automatically splice it into bytes when a sudden falling edge is monitored; if the start bit is abnormal or the stop bit is abnormal, the bit stream processor will stop data reception and report an error; after the data reception is completed and accepted correctly, it is stored in the idle receiving FIFO, and if all receiving FIFOs are unavailable, a data overflow error will be generated; After the data is successfully stored, the state register changes, and data reception can be performed through interruption or state query; The bus controller performs transmit-receive check on the data in the sum mode; In order to avoid receiving errors caused by clock deviation between the sender and the receiver, the controller completes data reception synchronization through the data start bit during reception.

2. A new type of industrial communication bus controller according to claim 1, characterized in that The data check function can be turned on or off through configuration.

3. A new type of industrial communication bus controller according to claim 1, characterized in that It has bus error identification, including bus clamping timeout error, sending bit error, and receiving check error.

4. A new type of industrial communication bus controller according to claim 1, characterized in that Supports single transmission and automatic retransmission mode.

5. A new type of industrial communication bus controller according to claim 1, characterized in that Supports data reception completion, data transmission completion and bus error interruption output.

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