A method, system, storage medium and device for reading multi-channel multi-linked list addresses

Abstract

The present invention provides a method, system, storage medium and device for reading multi-channel multi-linked list addresses, the method comprising: configuring a header pointer parameter of each channel data in the multi-channel; calculating the header pointer address of the current channel corresponding to the current data according to the header pointer parameter; reading the starting data page pointer address of the current channel in the initial address cache according to the header pointer address of the current channel; calculating the relative position of the position of the current data and the starting data page pointer address of the current channel; and finding the data page pointer address corresponding to the current data according to the relative position and reading it, and then outputting the data page pointer address. The method, system, storage medium and device for reading multi-channel multi-linked list addresses according to the present invention can highly utilize the amount of data accessed by the bus in the process of reading multi-channel multi-linked list addresses, reduce the number of DDR reads, and improve the overall performance of the system.

Description

Technical Field

[0001] The present invention relates to the field of computer storage technology, in particular to the field of multi-channel multi-linked list address reading technology, and specifically to a method, system, storage medium and device for multi-channel multi-linked list address reading. Background Art

[0002] In computer science, linked lists are a basic data structure that can be used to generate other types of data structures. A linked list usually consists of a series of nodes, each of which contains arbitrary instance data (data fields) and one or two links ("links") that point to the location of the previous / next node. The most obvious benefit of a linked list is that the way a regular array arranges associated items may be different from the order in which these items are in memory or on disk, and data access often requires conversion between different arrangements. A linked list is a self-referential data type because it contains a pointer (link) to another data of the same type.

[0003] In the field of data transmission and data storage, the storage of massive data requires extensive use of linked lists for access, and the linked list format and size are defined according to the needs of the system or product itself.

[0004] Fig.11 Figure 2 shows a traditional multi-linked list data page addressing process. Fig.11 It can be seen that if the addressing method is used in the traditional way, steps 3, 4 and 6 will be accessed repeatedly. The number of DDR accesses increases dramatically, which has a great impact on system performance. In addition, the data access is large and frequent, and this problem becomes a serious bottleneck. Summary of the invention

[0005] In view of this, the purpose of the present invention is to propose an improved multi-channel multi-linked list address reading method, system, storage medium and device to highly utilize the amount of data accessed by the bus, reduce the number of DDR reads, and improve the overall performance of the system.

[0006] Based on the above purpose, on the one hand, the present invention provides a method for reading addresses of multiple channels and multiple linked lists, wherein the method comprises the following steps:

[0007] Configure the header pointer parameters of each channel data in multiple channels;

[0008] Calculate the header pointer address of the current channel corresponding to the current data according to the header pointer parameter;

[0009] Reading a starting data page pointer address of the current channel in an initial address cache according to a header pointer address of the current channel;

[0010] Calculating the relative position of the current data position and the starting data page pointer address of the current channel; and

[0011] The data page pointer address corresponding to the current data is found according to the relative position and read, and then the data page pointer address is output.

[0012] In some embodiments of the method for reading addresses of multiple channels and multiple linked lists according to the present invention, finding the data page pointer address corresponding to the current data according to the relative position includes:

[0013] Determine whether the current data position spans across pages; and

[0014] When the position of the current data does not cross pages, the data page pointer address corresponding to the current data is obtained; or, when the position of the current data crosses pages, the linked list address corresponding to the position of the current data is obtained and the data page pointer address corresponding to the current data is obtained based on the corresponding linked list address.

[0015] In some embodiments of the method for reading addresses of multiple channels and multiple linked lists according to the present invention, obtaining the data page pointer address corresponding to the current data refers to reading a data page address cache.

[0016] In some embodiments of the method for reading multi-channel multi-linked lists addresses according to the present invention, when reading the data page address cache, N data page addresses are compiled into a cache group, so that when reading a cache group, another subsequent cache group is pre-fetched in advance according to the read state, where N is an integer greater than 1.

[0017] In some embodiments of the method for reading multi-channel multi-linked list addresses according to the present invention, obtaining the linked list address corresponding to the position of the current data refers to reading a linked list address cache.

[0018] Another aspect of the present invention further provides a system for multi-channel multi-linked list address reading, comprising:

[0019] A general process control module, the general process control module is configured to configure a header pointer parameter of each channel data in the multi-channel, calculate a header pointer address of a current channel corresponding to the current data according to the header pointer parameter, read a starting data page pointer address of the current channel, calculate a relative position between a position of the current data and a starting data page pointer address of the current channel, and read and output a data page pointer address corresponding to the current data;

[0020] a starting position control module, the starting position control module being configured to cache a starting data page pointer address of each channel data in the multiple channels for reading by the overall process control module; and

[0021] A data page address control module, wherein the data page address control module is configured to obtain a data page pointer address corresponding to the current data for reading and outputting by the overall process control module.

[0022] In some embodiments of the system for multi-channel multi-linked list address reading according to the present invention, the data page address control module obtains the data page pointer address corresponding to the current data by reading a data page address cache.

[0023] In some embodiments of the multi-channel multi-linked list address reading system according to the present invention, the data page address control module compiles N data page addresses into a cache group when reading the data page address cache, so that when a cache group is currently read, another subsequent cache group is pre-fetched in advance according to the current state, where N is an integer greater than 1.

[0024] In some embodiments of the system for multi-channel multi-linked list address reading according to the present invention, the system further comprises:

[0025] A linked list address control module is configured to read a linked list address cache when the position of the current data crosses pages to obtain a linked list address corresponding to the position of the current data.

[0026] In yet another aspect of the present invention, a computer-readable storage medium is provided, storing computer program instructions, which, when executed, implement any of the above-mentioned methods for reading multi-channel multi-linked lists addresses according to the present invention.

[0027] In another aspect of the present invention, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any one of the multi-channel multi-linked list address reading methods according to the present invention is executed.

[0028] The present invention has at least the following beneficial technical effects: The present invention proposes a method for reading multi-channel multi-linked list addresses, which greatly reduces the number of times the system reads external DDR (a memory, i.e., double rate synchronous dynamic random access memory), optimizes the bandwidth efficiency of reading DDR, and improves the system timeliness of the data page addressing hardware solution of the traditional multi-linked list. Through the local cache mechanism and solution, the number of times the system reads external DDR is greatly reduced, the bandwidth efficiency of reading DDR is optimized, and the system timeliness of the data page addressing hardware solution of the traditional multi-linked list is improved. In addition, the present invention invents a ping-pong cache mechanism when reading multiple data, and then pre-fetches operations as much as possible when executing data, which makes up for the bandwidth efficiency problem and execution efficiency problem of one-to-one reading, and improves the overall performance of the system. . BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0030] In the figure:

[0031] Figure 1 is a schematic diagram showing a method for reading addresses of multiple channels and multiple linked lists according to the present invention;

[0032] Figure 2 is a schematic diagram showing an example of allocating prior data to each channel in the method for reading addresses of multiple channels and multiple linked lists according to the present invention;

[0033] FIG. 3( a) is a schematic diagram showing an example of a start address cache mechanism in a method for reading addresses in multiple channels and multiple linked lists according to the present invention; FIG. 3( b) is a flow diagram showing an example of a start address cache reading process in a method for reading addresses in multiple channels and multiple linked lists according to the present invention;

[0034] FIG. 4( a) is a schematic diagram showing an example of a linked list address cache mechanism in a method for reading addresses in multiple channels and multiple linked lists according to the present invention; FIG. 4( b) is a flow diagram showing an example of a linked list address cache reading process in a method for reading addresses in multiple channels and multiple linked lists according to the present invention;

[0035] FIG. 5( a) is a schematic diagram showing an example of a data page address cache mechanism in a method for multi-channel multi-linked list address reading according to the present invention; FIG. 5( b) is a flow diagram showing an example of a data page address cache reading process in a method for multi-channel multi-linked list address reading according to the present invention;

[0036] Figure 6 is a schematic block diagram showing an embodiment of a system for multi-channel multi-linked list address reading according to the present invention;

[0037] Figure 7 is a schematic block diagram showing a preferred embodiment of a system for multi-channel multi-linked list address reading according to the present invention;

[0038] Figure 8 A schematic diagram showing an embodiment of a computer-readable storage medium for implementing a method for reading multi-channel multi-linked list addresses according to the present invention;

[0039] Fig. 9 A schematic diagram showing the hardware structure of an embodiment of a computer device for implementing a method for reading multi-channel multi-linked lists addresses according to the present invention;

[0040] Fig.10 is a schematic diagram showing a typical multi-linked list address access for storage product definition;

[0041] Fig.11 It is a schematic diagram showing the data page addressing process of a traditional multi-linked list. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0043] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product or device that includes a series of steps or units.

[0044] Fig.10 A definition of typical multi-linked list address access for storage products. Usually, users will use multiple channels to access together. Each channel corresponds to a different table header pointer. The size of the data page is generally the smallest particle for data storage, and the data page pointer is stored in a multi-linked list. Usually, the number of single data page pointers for each table is a fixed value, and the amount of data accessed by a single channel at a time will also be split into a quantitative value by the task. In a specific example, for example, the data page size is set to 4KB, the size of a single data page pointer is set to 1024 (including 1023 data page pointers, 1 table pointer and at the last position of the table), and the maximum data access amount allocated to a single channel at a time is set to 4MB. The actual maximum amount of data for each table is much larger than 4MB. Please note that the examples here are for illustrative purposes only and are not intended to limit the present invention. Those skilled in the art can arbitrarily set the above values ​​as needed.

[0045] In actual application, the configuration stores the starting position of each channel header pointer and the amount of data in the current channel. The previous data to be processed enters in an interlaced manner in each channel. If you want to obtain the current data to be processed, you must passively follow the order of the previous data and find the corresponding data page address of the current data through the multi-linked list mode to calculate it. Under normal circumstances, the hardware execution will follow Fig.11The traditional multi-linked list data page addressing process is executed. In the above example, since the maximum value of the single-channel data volume is 4MB and the data page granularity is 4KB, the maximum number of data page pointers to be searched in a single channel is 1024. If the traditional addressing method is used, steps 3, 4, and 6 will be repeatedly accessed many times. The number of DDR accesses has increased dramatically, which has a great impact on system performance. In addition, the data access is large and frequent, and this problem has become a serious bottleneck.

[0046] Aiming at the shortcomings of the traditional multi-linked list data page addressing process, the present invention starts from the various differences in memory access and invents an improved method based on multi-channel multi-linked list address reading. By using local cache and marking, the common access part of the channel only accesses the DDR once, without repeatedly accessing the DDR multiple times. The bus access data volume can be highly utilized and processed quickly in advance. This solution improves the operation of multiple DDR reads in the traditional solution as a whole and improves the performance of the system.

[0047] Therefore, according to the first aspect of the present invention, a method 100 for reading addresses of multiple channels and multiple linked lists is provided. Figure 1 A schematic block diagram of an embodiment of a method for reading addresses of multiple channels and multiple linked lists according to the present invention is shown. Figure 1 In the illustrated embodiment, the method includes:

[0048] Step S110: configuring the table header pointer parameters of each channel data in the multi-channel;

[0049] Step S120: Calculate the header pointer address of the current channel corresponding to the current data according to the header pointer parameter;

[0050] Step S130: reading the starting data page pointer address of the current channel in the initial address cache according to the header pointer address of the current channel;

[0051] Step S140: Calculate the relative position of the current data position and the start data page pointer address of the current channel;

[0052] Step S150: Find the data page pointer address corresponding to the current data according to the relative position and read it, and then output the data page pointer address.

[0053] Figure 2 1 is a schematic diagram showing an example of allocating prior data to each channel in the method for reading addresses of multiple channels and multiple linked lists according to the present invention. Figure 2As shown in the figure, each channel data needs to be sent after the configuration is started before the next configuration can be performed, but the initial address of each configuration will not change before the current sending. Therefore, the initial address of each channel is stored in the starting address cache. Then, when the channel data enters staggered, each data transmission only needs to be read from the DDR once when the first data of the channel arrives, and then stored in the starting address cache. The starting address can be obtained by reading the starting address cache subsequently.

[0054] The multi-channel multi-linked list address reading method 100 according to the first aspect of the present invention is to Fig.11 The steps 3 and 4 of the traditional multi-linked list data page addressing process that requires multiple accesses to the DDR are improved, and the repeatedly used data is cached locally (i.e., stored in the initial address cache) for independent management, while the overall process is only responsible for requesting to read data and waiting for the result to be returned.

[0055] The initial address cache stores the starting address. Fig.11 The result of step 4 in step 4 is the address of the starting data page pointer of the current channel. Each time the data configured by the channel is sent to the completion, there is only one address of the starting data page pointer, so the value only needs to be read from the DDR once. FIG. 3(a) is a schematic diagram showing an example of the starting address cache mechanism in the method for reading addresses of multiple channels and multiple linked lists according to the present invention. As shown in FIG. 3(a), the initial address cache contains a channel enable flag and starting address data, and the enable flag is set to valid when the first data of the channel is processed, and is set to invalid when all the data of the configuration of the channel are completed.

[0056] Fig. 3(b) is a flow chart showing an example of the start address cache reading process in the method for reading multi-channel multi-linked list addresses according to the present invention. The specific process of "reading the start data page pointer address of the current channel in the initial address cache" is shown in Fig. 3(b). It is in an idle state at the beginning. When reading the initial address cache according to the header pointer address of the current channel, if the valid bit of the current cache corresponding to the channel is valid, it means that the initial address of the current channel has been updated, and it can be read directly; if the valid bit is invalid, the initial address corresponding to the channel is read from the DDR (there may be multiple linked list reading operations), and after the reading is completed, it is updated to the cache, the valid position is set to valid, and the data is output.

[0057] According to a preferred embodiment of the method for reading multi-channel multi-linked list addresses of the present invention, finding the data page pointer address corresponding to the current data according to the relative position includes: determining whether the position of the current data crosses pages; and when the position of the current data does not cross pages, obtaining the data page pointer address corresponding to the current data; or, when the position of the current data crosses pages, obtaining the linked list address corresponding to the position of the current data and obtaining the data page pointer address corresponding to the current data according to the corresponding linked list address. Further preferably, obtaining the linked list address corresponding to the position of the current data refers to reading the linked list address cache.

[0058] As described above, only when a certain channel involves a cross-page from the start to the end of a single data transmission will the linked list address corresponding to the location of the current data be obtained, otherwise the data page pointer address corresponding to the current data is directly obtained. For example, in the above example, since the maximum data volume of each channel is 4MB, it is possible that each channel needs to obtain a maximum of 1024 data page pointers in a single configuration. However, each data page pointer page contains 1023 data page pointers and 1 table pointer. In extreme cases, it is necessary to read the linked list twice to find all the data page pointers to obtain 1024 data page pointers. Therefore, it is necessary to store the corresponding linked list pointer of each channel in the linked list address cache. Figure 4 (a) is a schematic diagram showing an example of a linked list address cache mechanism in a method for reading addresses of multiple channels and multiple linked lists according to the present invention, and specifically shows the storage form of the two linked lists.

[0059] FIG4( b ) is a flow chart showing an example of a linked list address cache reading process in a multi-channel multi-linked list address reading method according to the present invention, and several situations of the linked list address cache reading are discussed. The situations are described as follows:

[0060] Case 1: Read linked list 0 or linked list 1, and the target exists in the cache. After reading the data in the corresponding cache, it is completed.

[0061] Case 2: Read linked list 0, and the target does not exist in the cache. After reading DDR, update linked list 0 cache and mark, complete.

[0062] Case 3: Read linked list 1, and linked list 0 exists in the cache, but linked list 1 does not exist in the cache. First read the data in the corresponding cache, then read the DDR, then update the cache and mark in linked list 1, and complete.

[0063] Case 4: Read linked list 1, and neither linked list 0 nor linked list 1 exists in the cache. Read DDR to obtain the value of linked list 0, update the cache mark, read DDR again to obtain the value of linked list 1, update the cache mark, and complete.

[0064] Note that the case where the linked list address cache is not read will be automatically skipped in the overall flow control.

[0065] According to a preferred embodiment of the method for reading addresses of multiple channels and multiple linked lists of the present invention, obtaining the data page pointer address corresponding to the current data refers to reading the data page address cache. Further preferably, when reading the data page address cache, N data page addresses are compiled into a cache group, so that when reading a cache group, another subsequent cache group can be pre-fetched in advance according to the read state. Wherein N is an integer greater than 1.

[0066] In practical applications, the ultimate goal is to obtain the data page address of the current data of each channel according to the previous data. However, the conventional reading method faces the problems of multiple data pages in each channel at a time and frequent switching of multiple channels. The inventors consider that a fixed storage number is not preferred due to the large number of data page pointers in the end, and optimize it by using the principle of ping-pong cache as described above.

[0067] FIG5(a) is a schematic diagram showing an example of a data page address cache mechanism in a method for reading addresses of multiple channels and multiple linked lists according to the present invention. In this example, as shown in FIG5(a), a single cache group may contain 4 data page addresses. According to the current execution data volume of 4KB per data page, 4 data page pointers are sequentially read from the DDR each time, that is, 16KB of data volume, that is, the amount of data read once by the DDR is more than that of the reading method of the traditional technology, which improves the utilization rate of reading the DDR and reduces the number of reads. Similarly, by using the principle of ping-pong cache, when one of the cache groups is currently being read, the 4 data page addresses in the next cache group can be pre-fetched in advance according to the state to improve the operation efficiency. Please note that the example here sets N to 4 for illustrative purposes only, but is not intended to limit the present invention. Those skilled in the art can set N to any integer greater than 1 as needed.

[0068] FIG5( b) is a flow chart showing an example of a data page address cache reading process in a multi-channel multi-linked list address reading method according to the present invention. The specific process of "reading data page address cache" according to the above further preferred embodiment is shown in FIG5( b), which is generally divided into the following situations:

[0069] Case 1: Matching is successful. The overall process initiates a read operation, the corresponding channel is not locked, and the corresponding enable and sequence number match is successful. After the hit data in the read cache is found, it is determined whether another cache group needs to be updated.

[0070] Case 2: The match has not been successful yet and you need to wait. Wait until the lock is released and then match again. If successful, the process is the same as case 1. If not, the process is the same as case 3.

[0071] Case 3: Matching failed. The data must be read from the DDR completely and the reading must be completed.

[0072] In summary, the method 100 for multi-channel multi-linked list address reading according to the first aspect of the present invention and its preferred embodiment introduces an internal cache mechanism (initial address cache, linked list address cache and / or data page address cache) to reduce the number of multiple external DDR accesses, thereby greatly improving the execution speed of the system. In addition, a ping-pong cache mechanism is designed when multiple data are read, so that the operation is pre-fetched as much as possible during data execution, which makes up for the bandwidth efficiency and execution efficiency problems of one-to-one reading and improves the overall performance of the system.

[0073] The second aspect of the present invention further provides a multi-channel multi-linked list address reading system 200. Figure 6 FIG. 2 is a schematic block diagram of an embodiment of a system 200 for reading addresses of multiple channels and multiple linked lists according to the present invention. Figure 6 As shown, the system includes:

[0074] A general process control module 210, wherein the general process control module 210 is configured to configure a header pointer parameter of each channel data in the multi-channel, calculate a header pointer address of a current channel corresponding to the current data according to the header pointer parameter, read a starting data page pointer address of the current channel, calculate a relative position between a position of the current data and a starting data page pointer address of the current channel, and read and output a data page pointer address corresponding to the current data;

[0075] A starting position control module 220, wherein the starting position control module 220 is configured to cache a starting data page pointer address of each channel data in the multiple channels for reading by the overall process control module; and

[0076] The data page address control module 230 is configured to obtain the data page pointer address corresponding to the current data for the overall process control module to read and output.

[0077] In some embodiments of the system 200 for multi-channel multi-linked list address reading according to the present invention, the data page address control module 230 is further configured to obtain the data page pointer address corresponding to the current data by reading the data page address cache.

[0078] In some embodiments of the multi-channel multi-linked list address reading system 200 according to the present invention, the data page address control module 210 is further configured to compile N data page addresses into a cache group when reading the data page address cache, so as to pre-fetch another subsequent cache group in advance according to the current state when reading a cache group currently. Wherein, N is an integer greater than 1.

[0079] Figure 7A preferred embodiment of a multi-channel multi-linked list address reading system according to the present invention is shown, namely, system 200', which further includes: a linked list address control module 240, wherein the linked list address control module 240 is configured to read the linked list address cache when the position of the current data crosses pages to obtain the linked list address corresponding to the position of the current data.

[0080] In summary, the multi-channel multi-linked list address reading system 200 and its preferred embodiment system 200' according to the second aspect of the present invention introduce an internal cache mechanism (initial address cache, linked list address cache and / or data page address cache) to reduce the number of multiple external DDR accesses, thereby greatly improving the execution speed of the system. In addition, a ping-pong cache mechanism is designed when multiple data are read, so that pre-fetch operations are performed as much as possible when data is executed, which makes up for the bandwidth efficiency and execution efficiency problems of one-to-one reading and improves the overall performance of the system.

[0081] A third aspect of the embodiments of the present invention further provides a computer-readable storage medium. Figure 8 A schematic diagram of a computer-readable storage medium for a method of reading addresses of multiple channels and multiple linked lists provided in accordance with an embodiment of the present invention is shown. Figure 8 As shown, the computer-readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. When the computer program instructions 310 are executed, the method of any of the above embodiments is implemented.

[0082] It should be understood that, without conflicting with each other, all the embodiments, features and advantages described above for the method of multi-channel multi-linked list address reading according to the present invention are also applicable to the system and storage medium for multi-channel multi-linked list address reading according to the present invention.

[0083] According to a fourth aspect of the embodiments of the present invention, a computer device 400 is provided, including a memory 420 and a processor 410, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0084] like Fig. 9 FIG. 1 is a schematic diagram of the hardware structure of a computer device for executing a method for reading addresses of multiple channels and multiple linked lists provided by the present invention. Fig. 9 The computer device 400 shown in FIG. 1 is taken as an example, and the computer device includes a processor 410 and a memory 420, and may also include: an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430 and the output device 440 may be connected via a bus or other means. Fig. 9The bus connection is taken as an example. The input device 430 can receive input digital or character information, and generate signal input related to the reading of multi-channel multi-link table addresses. The output device 440 can include display devices such as display screens.

[0085] The memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the resource monitoring method in the embodiment of the present application. The memory 420 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of the resource monitoring method, etc. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 420 may optionally include a memory remotely arranged relative to the processor 410, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0086] The processor 410 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 420, that is, implements the resource monitoring method of the above method embodiment.

[0087] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the invention constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0088] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be a volatile memory or a nonvolatile memory, or may include both a volatile memory and a nonvolatile memory. As an example and not by way of limitation, a nonvolatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. A volatile memory may include a random access memory (RAM), which may act as an external cache memory. As an example and not by way of limitation, RAM may be obtained in a variety of forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0089] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using the following components invented to perform the functions herein: a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0090] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0091] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0092] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for reading addresses of multiple channels and multiple linked lists, characterized in that: The following steps are involved: Configure the header pointer parameters of each channel data in multiple channels; Calculate the header pointer address of the current channel corresponding to the current data according to the header pointer parameter; Reading a starting data page pointer address of the current channel in an initial address cache according to a header pointer address of the current channel, wherein the initial address cache is a local cache; Calculating the relative position of the current data position and the starting data page pointer address of the current channel; as well as Find the data page pointer address corresponding to the current data according to the relative position and read it, and then output the data page pointer address; Reading the starting data page pointer address of the current channel in the initial address cache according to the header pointer address of the current channel includes: reading the channel enable flag and the starting address data of the current channel in the initial address cache according to the header pointer address, and determining whether the channel enable flag is set to be valid; If it is set to be valid, the starting address data is used as the starting data page pointer address; The step of finding the data page pointer address corresponding to the current data according to the relative position comprises: Determine whether the current data position spans across pages; and When the position of the current data does not cross pages, the data page pointer address corresponding to the current data is obtained; or, when the position of the current data crosses pages, the linked list address corresponding to the position of the current data is obtained and the data page pointer address corresponding to the current data is obtained based on the corresponding linked list address.

2. The method according to claim 1, characterized in that The obtaining of the data page pointer address corresponding to the current data refers to reading a data page address cache.

3. The method according to claim 2, characterized in that When reading the data page address cache, N data page addresses are compiled into a cache group, so that when reading a cache group, another subsequent cache group is pre-fetched in advance according to the read state, Wherein, N is an integer greater than 1.

4. The method according to claim 1, characterized in that: The obtaining of the linked list address corresponding to the position of the current data refers to reading the linked list address cache.

5. A multi-channel multi-linked list address reading system, characterized in that: include: A general process control module, the general process control module is configured to configure a header pointer parameter of each channel data in the multi-channel, calculate a header pointer address of a current channel corresponding to the current data according to the header pointer parameter, read a starting data page pointer address of the current channel, calculate a relative position between a position of the current data and a starting data page pointer address of the current channel, and read and output a data page pointer address corresponding to the current data; A starting position control module, the starting position control module is configured to cache the starting data page pointer address of each channel data in the multiple channels for reading by the overall process control module; as well as A data page address control module, wherein the data page address control module is configured to obtain a data page pointer address corresponding to the current data for reading and outputting by the overall process control module.

6. The system according to claim 5, characterized in that The data page address control module obtains the data page pointer address corresponding to the current data by reading the data page address cache.

7. The system according to claim 6, characterized in that When reading the data page address cache, the data page address control module compiles N data page addresses into a cache group, so that when a cache group is currently read, another subsequent cache group is pre-fetched in advance according to the current state. Wherein, N is an integer greater than 1.

8. A computer-readable storage medium, characterized in that: Computer program instructions are stored, and when the computer program instructions are executed, the method for reading multi-channel multi-linked list addresses as described in any one of claims 1 to 4 is implemented.

9. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, and when the computer program is executed by the processor, the method for reading multi-channel multi-linked lists addresses as described in any one of claims 1 to 4 is performed.

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