A defense mechanism for avoiding the triggering of instruction sequence-triggered hardware Trojans

Abstract

The present invention discloses a defense mechanism for avoiding the triggering of instruction sequence-triggered hardware Trojans, which is applied to the field of processor hardware security. Aiming at the problems that the existing mechanism of instruction obfuscation at the software level is easily bypassed by attackers and the deficiencies of the existing mechanism of instruction obfuscation at the hardware level; during the operation of the processor program, the established instruction stream input from the instruction cache to the IF first passes through an instruction fine-grained encryption module for encryption; when the encrypted established instruction is input from the IF to the newly added pipeline IO, a decryption operation is first performed; then, according to the control information 1 given by the newly added pipeline IO, the dynamic random module is driven to generate control information 2, and several custom OPCode instructions are randomly selected from the obfuscation instruction library composed of custom OPCode instructions and inserted between the established instructions of the processor; finally, the obfuscated instruction stream is input to the ID, so as to achieve that the processor avoids the triggering of instruction sequence-triggered hardware Trojans.

Description

Technical Field

[0001] The present invention belongs to the fields of processor hardware security and large-scale digital integrated circuits, and particularly relates to a defense technology against hardware Trojan activation. Background Art

[0002] Instruction sequence-triggered hardware Trojans refer to special modules and circuits deliberately implanted into the hardware design of a processor by a third party, or malicious modules and circuits intentionally left by the designer, and the attacker can activate the hardware Trojan through the processor instruction sequence. The inserted instruction sequence-triggered hardware Trojan may cause the leakage of critical information of the processor and the tampering of the content of critical components, thereby changing the operation result and purpose of the processor. The implantation of this type of hardware Trojan usually occurs in untrusted links in the design and manufacturing of the processor, such as untrusted EDA tools, untrusted third-party IP suppliers, untrusted design companies, and untrusted foundries. In a processor, in order to achieve the concealment and controllability of the implanted hardware Trojan, the attacker generally selects the processor instruction sequence as its trigger condition.

[0003] Currently, there are mainly three defense technologies against instruction sequence-triggered hardware Trojans implanted in a processor: (1) detecting the hardware Trojan by collecting the bypass physical information (power consumption, timing, electromagnetic) of the processor chip; (2) obtaining the gate-level netlist of the processor chip through reverse engineering and detecting the hardware Trojan by analyzing the gate-level netlist; (3) starting from the triggering method of the hardware Trojan, reducing the triggering probability of the hardware Trojan implanted in the processor.

[0004] Technology (1) is a non-destructive detection of the processor chip, and its main disadvantages are: (1) process deviation has a relatively serious impact on the bypass physical information of the processor chip, which will cause deviation in the detection of the hardware Trojan; (2) for a hardware Trojan with extremely small area consumption implanted in the processor chip, this method has a large detection deviation.

[0005] Technology (2) is a destructive detection of the processor chip, and its main disadvantage is that the processor chip will be damaged once reverse engineered and cannot be used again.

[0006] Technique (3) is a defense measure starting from the triggering conditions of hardware Trojans. Currently, existing techniques mainly start from the software and hardware levels and disrupt the established instruction order in the processor compiler stage through instruction obfuscation methods. Its main disadvantages are as follows: (1) The mechanism of instruction obfuscation at the software level is easily bypassed by attackers; (2) The means of instruction obfuscation at the hardware level usually obfuscates instructions between the instruction fetch stage and the decoding stage of the processor. Therefore, it cannot address the security issue of hardware Trojans triggered by instruction sequences in the processor fetch stage; (3) When the current technique uses obfuscated instructions or equivalent instructions to replace the established instructions of the processor, most instructions do not perform replacement of the instruction operation code (OperationCode, OPCode). Therefore, it cannot effectively deal with hardware Trojans triggered by the OPCode sequence of instructions; (4) The current technique can only reduce the triggering probability of instruction sequence-triggered hardware Trojans and cannot completely avoid the triggering of this type of hardware Trojan; (5) The current technique will result in a fixed mapping relationship between the established instructions of the processor and the obfuscated instructions or equivalent instructions. Therefore, the instruction obfuscation or instruction equivalence of the current technique is not random, and attackers can easily analyze this mapping relationship based on a large amount of test data. Summary of the Invention

[0007] To solve the above technical problems, the present invention proposes a defense mechanism to avoid the triggering of instruction sequence-triggered hardware Trojans, and ensures that the mechanism proposed by the present invention cannot be bypassed by attackers through a pure hardware implementation method.

[0008] The technical solution adopted by the present invention is: a defense mechanism to avoid the triggering of instruction sequence-triggered hardware Trojans, including: an instruction fine-grained encryption module, an instruction fine-grained decryption module, a dynamic random module, an obfuscated instruction library composed of custom OPCode instructions, and a newly added pipeline instruction obfuscation (Instruction Obfuscate, IO) stage;

[0009] The instruction fine-grained encryption module encrypts the established instruction stream output from the instruction cache to the fetch stage; the encrypted established instruction stream output from the instruction cache to the fetch stage is decrypted by the instruction fine-grained decryption module and then output to the newly added pipeline IO;

[0010] According to the control information 1 given by the newly added pipeline IO stage, the dynamic random module is driven to generate control information 2 and randomly select several custom OPCode instructions from the obfuscated instruction library composed of custom OPCode instructions and insert them between the established instructions of the processor;

[0011] The processor inputs the obfuscated instruction stream obtained in the newly added pipeline IO stage to the decoding stage.

[0012] Advantages of the present invention: The present invention has the following advantages:

[0013] (1) The present invention ensures that the mechanism proposed by the present invention cannot be bypassed by attackers through a pure hardware implementation method;

[0014] (2) Through the instruction fine-grained encryption / decryption module in the mechanism proposed by the present invention, the present invention avoids the triggering of instruction sequence-triggered hardware trojans that may exist in the IF stage;

[0015] (3) Through the dynamic random module, the mechanism proposed by the present invention has a certain degree of randomness when obfuscating the established instructions of the processor, so that attackers cannot analyze the mapping rule between the established instructions of the processor and the obfuscated instructions;

[0016] (4) Through the obfuscation instruction library composed of custom OPCode instructions and the newly added pipeline IO in the mechanism proposed by the present invention, it is ensured that the obfuscation instructions inserted after the valid established instructions of the processor are unique compared to the legal instructions of the compilation tool chain, so that the mechanism proposed by the present invention can completely avoid the triggering of instruction sequence-triggered hardware trojans implanted in the processor. At the same time, due to the existence of custom OPCode, it can also completely avoid the triggering of hardware trojans triggered by OPCode sequences;

[0017] (5) The present invention is simple and efficient, does not require too much hardware resources, only needs to make minor modifications to the processor core and can be easily deployed in the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the functional structure block diagram of the mechanism proposed by the present invention.

[0019] Figure 2 is the structural schematic diagram of the dynamic random module in the mechanism proposed by the present invention.

[0020] Figure 3 is the structural schematic diagram of the self-feedback RO chain used by the true random number generator in the mechanism proposed by the present invention.

[0021] Figure 4 is the instruction sequence-triggered hardware trojan designed to verify the effectiveness of the mechanism proposed by the present invention;

[0022] Figure 5 is for implanting the hardware trojan as shown in Figure 4 in a RISC-V processor without deploying the mechanism proposed by the present invention, and the test result of executing the test code containing the trigger sequence.

[0023] Figure 6 is for implanting the hardware trojan as shown in Figure 4The shown hardware trojan and the test results of executing test code containing a trigger sequence. Detailed implementation manners

[0024] To facilitate those skilled in the art to understand the technical content of the present invention, the content of the present invention will be further explained below in conjunction with the drawings.

[0025] Embodiment 1

[0026] This embodiment combines with the attached Figure 1 to illustrate the working principle of the present invention:

[0027] As Figure 1 shown, the object of the present invention is achieved through the following technical solutions: A defense mechanism for avoiding the triggering of instruction sequence-triggered hardware trojans, including an instruction fine-grained encryption module, an instruction fine-grained decryption module, a dynamic random module, an obfuscation instruction library composed of custom OPCode instructions, and a newly added pipelined IO. During the operation of the processor program, the established instruction stream output from the instruction cache to the Instruction Fetch (IF) stage needs to be encrypted by the instruction fine-grained encryption module first to ensure that the instruction sequence-triggered hardware trojans that may exist in the IF stage are not triggered; the established instructions with fine-grained encryption need to be subjected to fine-grained decryption operations when output from the IF stage to the newly added pipelined Instruction Obfuscate (IO) stage; then, according to the control information 1 given by the newly added pipelined IO, the dynamic random module is driven to generate control information 2, and several custom OPCode instructions are randomly selected from the obfuscation instruction library composed of custom OPCode instructions and inserted between the established instruction streams that are input to the newly added pipelined IO after the fine-grained decryption operation, so as to completely disrupt the order of the processor's established instruction stream; finally, the processor outputs the obfuscated instruction stream obtained in the newly added pipelined IO stage to the Instruction Decode (ID) stage, thereby realizing that the processor avoids the triggering of instruction sequence-triggered hardware trojans and ensuring the security and reliability of the processor at the hardware level.

[0028] Embodiment 2

[0029] The instruction fine-grained encryption / decryption module performs an exclusive OR operation on the instructions according to the key provided by the dynamic random module.

[0030] Embodiment 3

[0031] This embodiment combines with the attached Figures 2-3 to illustrate the working process of the dynamic random module:

[0032] As Figure 2As shown, the dynamic random module consists of a True Random Number Generator (TRNG) and a Pseudo Random Number Generator (PRNG), and can generate random numbers with a relatively high entropy per bit in each clock cycle. Its working steps are as follows:

[0033] First, when the processor is reset, it drives the Seek control logic to generate the TRNG enable signal TRNG_EN, and drives the TRNG to generate the initial random seed Seek required by the PRNG, the key required by the instruction fine-grained encryption / decryption module, and a 6-bit true random number.

[0034] Second, the Seek control logic obtains the Seek value from the TRNG and temporarily stores it in the register Seek_R, and at the same time generates a valid signal for this value;

[0035] Then, the PRNG starts running by obtaining the random seed value Seek_R and valid from the Seek control logic module, and realizes generating random numbers with a relatively high entropy per bit in each clock cycle;

[0036] Finally, the Seek control logic module generates the TRNG enable signal TRNG_EN according to the indication signal that the PRNG cycle is about to end generated by the PRNG, and drives the TRNG to regenerate the random seed Seek and the 6-bit true random number required by the PRNG. Ensure that the Seek value and the characteristic feedback polynomial of the PRNG can be updated by the true random number generator every 127 cycles.

[0037] As Figure 2 shown, the pseudo random number generator consists of a 7-bit Fibonacci Linear Feedback Shift Register (LFSR), and its characteristic feedback polynomial is where g(m) is equal to 1 or 0, which is determined by the 6-bit true random number given by the true random number generator; the seek value of the pseudo random number is given by the true random number generator; the seek value and g(m) are updated by the true random number generator every 127 cycles.

[0038] As Figure 3 shown, Figure 2The core part of the true random number generator (TRNG) shown is composed of a self-feedback ring oscillator (RO) chain consisting of an inverter latch and a shift register. Its working principle is as follows: The inverter latch is reset to zero when the reset signal enable_i = 1'b0. When enable_i = 1'b1, enable_i is input to the n-bit shift register, and the inverter latches are individually activated in sequence, causing the RO to start oscillating and the TRNG to start working.

[0039] Embodiment 4

[0040] The instructions in the obfuscation instruction library composed of the described custom OPCode instructions are all combined from custom OPCode (Operation Code, OPCode) and single-cycle type instructions that can operate on target registers; the implementation process is as follows:

[0041] Select single-cycle instructions in the processor instruction encoding that can operate on target registers, and always set the target register (rd) to x0, so that the fabricated obfuscation instructions can use the processor's arithmetic resources and read the values of general-purpose registers for actual operations, but the target register x0 is always 0 and will not affect the normal operation of the processor; at the same time, replace the instruction opcode OPCode of the obfuscation instruction with custom OPCode (OPCode[1:0] == 2'b10), and modify the logic in the processor decoding stage so that the processor decoder can correctly identify the custom OPCode. This ensures that the instructions in the obfuscation instruction library are different from the legal instructions of the compilation tool chain and are a special and unique existence.

[0042] Embodiment 5

[0043] The newly added pipelined IO mainly realizes inserting several custom OPCode instructions randomly selected from the obfuscation instruction library after each valid established instruction, and its specific logic is as follows:

[0044] Detect whether the instruction output from the IF stage to the IO stage is a valid instruction. If so: while the processor transmits the newly added pipelined IO stage instruction to the ID stage, the IO stage logic obtains a 2-bit random number from the dynamic random module and randomly reads x custom OPCode instructions (x = [1, 3]) from the obfuscated instruction library, and selects a custom OPCode instruction from the obfuscated instruction library with a 5-bit random number. At the same time, pull down the upward handshake signal io_ready of the IO stage to pause the pipeline of the processor's IF stage; read x custom OPCode instructions from the obfuscation library according to the 5-bit random number, and at the same time pull up the downward handshake signal io_valid of the IO stage. The processor transmits the obfuscated instruction stream to the ID stage for execution; after the inserted custom OPCode instruction is executed, pull up the upward handshake signal io_ready of the IO stage to resume the pipeline of the processor's IF stage, transmit the instruction of the IF stage to the IO stage, and then transmit it to the ID stage by the IO stage. Otherwise, the mechanism proposed by the present invention does not perform instruction obfuscation work, and only needs to latch the signal output from the processor's IF stage to the newly added pipelined IO stage.

[0045] Example 6

[0046] The control information 1 is the valid signal of the established instruction input by the processor from the IF stage to the newly added pipelined IO stage.

[0047] Example 7

[0048] The control information 2 is a 7-bit random number obtained by the logic of the newly added pipelined IO stage from the dynamic random module, where the high 2 bits control the newly added pipeline to read x instructions from the obfuscated instruction library, and the low 5 bits control the newly added pipeline to randomly select an instruction from the obfuscated instruction library.

[0049] Example 8

[0050] This embodiment combines the appendix Figures 4-6 to illustrate the technical effects of the present invention:

[0051] The present invention will use the open-source RISC-V processor PULPino as a verification experiment platform, and analyze the security of the mechanism proposed by the present invention from the perspective of attack examples to prove the security and effectiveness of the mechanism proposed by the present invention.

[0052] The present invention designs a hardware trojan triggered by an instruction sequence as Figure 5 shown. The instruction sequence that triggers the hardware trojan is: addi, jarl, nop, lw. The function of the instruction sequence-triggered hardware trojan is to modify the processor address space to hijack the processor control flow.

[0053] In a RISC-V processor without the mechanism proposed by the present invention, a hardware trojan as shown in the figure is implanted, and test code containing a trigger sequence is executed. The running result is as Figure 5 shown: After the hardware trojan is triggered, the data address 0x00107fec accessed by the lw instruction to the DTCM is modified to 0x1a105018, causing the lw instruction to instead read the value 0x434 of the ht_pc_addr_reg, so as to replace the return address 0x500 after the execution of the jump of func1 with 0x434 (the entry address of the function func2), thereby completing the hijacking of the processor control flow and making it execute the content of the function func2.

[0054] In a RISC-V processor with the mechanism proposed by the present invention, a hardware trojan as shown in the figure is implanted, and test code containing a trigger sequence is executed. The running result is as Figure 6 shown: A number of obfuscation instructions are inserted between the established instructions addi, jarl, nop, and lw of the processor, so that the instruction sequence type hardware trojan is not triggered.

[0055] In summary, the present invention proposes a defense mechanism to avoid the triggering of instruction sequence triggered hardware trojans. By means of a pure hardware implementation method, it is ensured that the mechanism proposed by the present invention cannot be bypassed by attackers; through the instruction fine-grained encryption / decryption module in the mechanism proposed by the present invention, the triggering of instruction sequence triggered hardware trojans that may exist in the IF stage is avoided; through the dynamic random module, the mechanism proposed by the present invention has a certain randomness when obfuscating the established instructions of the processor, so that attackers cannot analyze the mapping rule between the established instructions and the obfuscation instructions of the processor; through the obfuscation instruction library composed of custom OPCode instructions and the newly added pipeline IO in the mechanism proposed by the present invention, it is ensured that the obfuscation instructions inserted after the valid established instructions of the processor are unique compared with the legal instructions of the compilation tool chain, so that the mechanism proposed by the present invention can completely avoid the triggering of instruction sequence triggered hardware trojans implanted in the processor. At the same time, due to the existence of custom OPCode, the triggering of hardware trojans with OPCode sequence as the trigger condition can also be completely avoided; the present invention is simple and efficient, does not require too much hardware resources, only needs to make minor modifications to the processor core and can be easily deployed in the processor.

[0056] Those of ordinary skill in the art will realize that the embodiments described herein are for helping readers understand the principles of the present invention and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A defense mechanism for preventing the triggering of instruction sequence-triggered hardware Trojans, characterized in that, Including: An instruction fine-grained encryption module, an instruction fine-grained decryption module, a dynamic random module, a confusion instruction library composed of custom OPCode instructions, and a newly added pipeline instruction confusion stage; The instruction fine-grained encryption module encrypts the established instruction stream output from the instruction cache to the fetch stage; the encrypted established instruction stream output from the instruction cache to the fetch stage is decrypted by the instruction fine-grained decryption module and then output to the newly added pipeline confusion stage; The newly added pipeline instruction confusion stage inserts several custom OPCode instructions randomly selected from the confusion instruction library after each valid established instruction; The processor sends the confused instruction stream obtained in the newly added pipeline instruction confusion stage to the decoding stage.

2. The defense mechanism for avoiding the triggering of instruction sequence-triggered hardware Trojans according to claim 1, characterized in that, The said instruction fine-grained encryption / decryption module performs exclusive OR processing on the instructions according to the key provided by the dynamic random module.

3. A defense mechanism for preventing the triggering of instruction sequence-triggered hardware Trojans according to claim 1, characterized in that, The implementation process of the confusion instruction library composed of the said custom OPCode instructions is as follows: Select single-cycle instructions in the processor instruction encoding that have operable target registers, and always set the target register to x0; at the same time, replace the instruction operation code OPCode of the confusion instruction with the custom OPCode, and modify the logic in the processor decoding stage so that the processor decoder can correctly identify the custom OPCode.

4. A defense mechanism for avoiding the triggering of instruction sequence-triggered hardware Trojans according to claim 1, characterized in that, According to the control information 1 given by the newly added pipeline IO, drive the dynamic random module to generate control information 2 to randomly select several custom OPCode instructions from the confusion instruction library composed of custom OPCode instructions and insert them between the established instruction streams output to the newly added pipeline IO after fine-grained decryption operation.

5. A defense mechanism for preventing the triggering of instruction sequence-triggered hardware Trojans according to claim 1, characterized in that, Randomly select several custom OPCode instructions from the confusion instruction library composed of custom OPCode instructions and insert them between the established instruction streams input to the newly added pipeline IO after fine-grained decryption operation. The implementation process is as follows: If the instruction input from the fetch stage to the confusion stage is a valid instruction, while the processor transmits the instructions in the newly added pipeline instruction confusion stage to the decoding stage, the instruction confusion stage logic obtains a 2-bit random number from the dynamic random module to randomly read x custom OPCode instructions from the confusion instruction library, and a 5-bit random number to select one custom OPCode instruction from the confusion instruction library. At the same time, pull down the upward handshake signal io_ready of the instruction confusion stage to pause the pipeline of the processor fetch stage; read x custom OPCode instructions from the confusion instruction library according to the 5-bit random number, and at the same time, pull up the downward handshake signal io_valid of the instruction confusion stage. The processor transmits the confused instruction stream to the decoding stage for execution; after the inserted custom OPCode instructions are executed, pull up the upward handshake signal io_ready of the instruction confusion stage to resume the pipeline of the processor fetch stage, transmit the instructions in the fetch stage to the instruction confusion stage, and then transmit them to the decoding stage by the instruction confusion stage.

6. A defense mechanism for preventing the triggering of instruction sequence-triggered hardware Trojans according to claim 5, characterized in that, If the instruction input from the fetch stage to the instruction confusion stage is an invalid instruction, then latch the signal output from the processor fetch stage to the newly added pipeline instruction confusion stage.

7. A defense mechanism for preventing the triggering of instruction sequence-triggered hardware Trojans according to claim 4, characterized in that, The control information 1 is a valid signal of an established instruction input by the processor from the instruction fetch stage to the newly added pipelined instruction obfuscation stage.

8. A defense mechanism for preventing the triggering of instruction sequence-triggered hardware Trojans according to claim 4, characterized in that, The control information 2 is a 7-bit random number obtained by the logic of the newly added pipelined instruction obfuscation stage from the dynamic random module, where the high 2 bits control the newly added pipeline to read x instructions from the obfuscated instruction library, and the low 5 bits control the newly added pipeline to randomly select an instruction from the obfuscated instruction library.

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