Unified identification method and system for analog bad data and switch topology errors

Abstract

The present invention belongs to the technical field of power system operation and control, and provides a unified identification method and system for analog quantity bad data and switch topology errors, including: obtaining a set of voltage state variables of all physical nodes on both sides of the switch, and dividing them into independent variables and dependent variables; according to a weighted least squares estimation model, using an iterative method to correct the independent variables until the correction amount is less than a set threshold, and taking the final corrected independent variables as the estimated values ​​of the independent variables; based on the estimated values ​​of the independent variables, calculating the analog quantity measurement residuals and the estimated values ​​of the dependent variables; based on the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables, calculating the Lagrange multiplier; based on the Lagrange multiplier and the analog quantity measurement residuals, judging whether there are analog quantity bad data and switch topology errors. By decoupling the state variables, the identification speed of analog quantity bad data and switch topology errors is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power system operation and control, and in particular relates to a unified identification method and system for bad analog data and switch topology errors. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Switch topology analysis is the basis of power system state estimation, and the correctness of its results affects whether the estimation algorithm can converge correctly. The generalized state estimation proposed in 1998 included the switch state and the parameters of the transmission elements into the state variables, but because the nodes analyzed are the real physical connection points between the zero-impedance elements and the impedance elements, there are problems such as too many estimation nodes, large iteration matrix dimensions, and slow calculation speed. Summary of the invention

[0004] In order to solve the technical problems existing in the above-mentioned background technology, the present invention provides a unified identification method and system for bad analog data and switch topology errors. On the basis of a generalized state estimation model, the number of generalized state estimation nodes is feature extracted and the state variables are decoupled, thereby improving the identification speed of bad analog data and switch topology errors.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A first aspect of the present invention provides a unified identification method for analog bad data and switch topology errors, comprising:

[0007] Obtain the voltage state variable set of all physical nodes on both sides of the switch and divide it into independent variables and dependent variables;

[0008] According to the weighted least squares estimation model, the independent variable is corrected by an iterative method until the correction amount is less than a set threshold value, and the final corrected independent variable is used as the estimated value of the independent variable;

[0009] Calculating simulated quantity measurement residuals and estimated values ​​of the dependent variables based on the estimated values ​​of the independent variables;

[0010] calculating Lagrange multipliers based on the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables;

[0011] Based on the Lagrange multiplier and the analog quantity measurement residual, it is determined whether there is bad analog quantity data and switch topology error.

[0012] Furthermore, the method for dividing the independent variables and the dependent variables is:

[0013] Based on the connection relationship between the switch and the physical node and the switch status, a topological analysis is performed to obtain all topological nodes. Each topological node corresponds to a group of physical nodes connected by a closed switch.

[0014] The voltage state variables of all topological nodes are combined into independent variables;

[0015] The voltage state variables of physical nodes except topological nodes are composed of dependent variables.

[0016] Furthermore, the simulated variable measurement residual is the difference between the variable measurement and the measurement value calculated from the estimated value of the independent variable.

[0017] Furthermore, the Lagrange multiplier is calculated as follows:

[0018] Concatenating the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables to obtain estimated values ​​of the state variables of all physical nodes;

[0019] Based on the estimated values ​​of the state variables of all physical nodes, the expanded measurement Jacobian matrix is ​​calculated;

[0020] Based on the extended measurement Jacobian matrix, measurement residual and constraint matrix, the Lagrange multiplier is obtained.

[0021] Furthermore, the specific method for determining whether there is bad analog data and switch topology error is:

[0022] Calculating the covariance matrix of the Lagrange multiplier and the simulated quantity measurement residual;

[0023] Calculating the standardized residual and the standardized multiplier based on the covariance matrix, the Lagrange multiplier and the simulated measurement residual;

[0024] If the maximum standard residual is greater than the set value, it means there is bad analog data; if the maximum standardized multiplier is greater than the set value, it means there is a switch topology error.

[0025] A second aspect of the present invention provides a unified identification system for analog bad data and switch topology errors, comprising:

[0026] A variable partitioning module is configured to: obtain a set of voltage state variables of all physical nodes on both sides of the switch, and partition the set into independent variables and dependent variables;

[0027] An independent variable estimation module is configured to: according to a weighted least squares estimation model, use an iterative method to correct the independent variable until the correction amount is less than a set threshold, and use the final corrected independent variable as an estimated value of the independent variable;

[0028] A dependent variable estimation module, configured to: calculate a simulated quantity measurement residual and an estimated value of the dependent variable based on an estimated value of the independent variable;

[0029] A Lagrange multiplier calculation module, configured to: calculate Lagrange multipliers based on the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables;

[0030] The topology error judgment module is configured to judge whether there is bad analog quantity data and switch topology error based on the Lagrange multiplier and the analog quantity measurement residual.

[0031] Furthermore, the variable partitioning module is specifically configured as follows:

[0032] Based on the connection relationship between the switch and the physical node and the switch status, a topological analysis is performed to obtain all topological nodes. Each topological node corresponds to a group of physical nodes connected by a closed switch.

[0033] The voltage state variables of all topological nodes are combined into independent variables;

[0034] The voltage state variables of physical nodes except topological nodes are composed of dependent variables.

[0035] Furthermore, the simulated variable measurement residual is the difference between the variable measurement and the measurement value calculated from the estimated value of the independent variable.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention provides a unified identification method for bad analog data and switch topology errors, which can make full use of the results of traditional state estimation, accurately identify switch and analog measurement errors, and specifically identify the switch status of suspicious plants or suspicious buses.

[0038] The present invention provides a unified identification method for analog bad data and switch topology errors. The order reduction processing in the iterative solution process reduces the dimension of the measurement Jacobian matrix, which can reduce the amount of calculation, improve the calculation speed, and reduce the memory requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0040] Figure 1 is a schematic diagram of a method according to a first embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of electrical wiring of a physical node according to the first embodiment of the present invention;

[0042] Figure 3 It is a schematic diagram of node topology analysis of the first embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0044] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0045] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0046] Embodiment 1

[0047] This embodiment provides a unified identification method for bad analog data and switch topology errors, sets the voltages of all physical nodes on both sides of the switch as state variables, generates a constraint matrix based on the condition that the voltages at both ends of the closed switch in the power system are equal; obtains a set of voltage state variables of all physical nodes on both sides of the switch, and divides all voltage state variables into independent variables and dependent variables; based on the independent variables, uses an iterative method to correct the independent variables according to the weighted least squares estimation model until the correction amount is less than the set threshold, and uses the final corrected independent variable as the estimated value of the independent variable; based on the estimated value of the independent variable, calculates the analog measurement residual and the estimated value of the dependent variable; calculates the Lagrange multiplier corresponding to the constraint equation based on the estimated value of the voltage state variable of each node in the system (the estimated value of the independent variable and the estimated value of the dependent variable are concatenated); based on the multiplier and the analog measurement residual, determines whether there is bad analog data and switch topology errors. Specifically including:

[0048] Step 1: Topological analysis, that is, based on the connection relationship between the switch and the physical node and the switch state (open or closed), a topological analysis is performed to obtain all topological nodes. Each topological node corresponds to a group of physical nodes connected by the closed switch. Specifically, the two nodes on both sides of the switch with the switch state in the closed position are divided into the same connected piece (connecting each closed switch element or other busbar), and a physical node is selected in each connected piece as a topological node; the power system is estimated by weighted least squares, and the topological node is obtained by equations (6) and (8).

[0049] Estimated value of the voltage state variable of the node (topological node) after the flutter analysis And the simulated measurement residual r.

[0050] Step 101: Assume that there are n nodes in the system. After topological analysis, N connected slices are obtained. The number of physical nodes connected to each connected slice is n1, n2, ..., n. N , the voltages of all physical nodes in each connected piece are equal, where each connected piece takes the state variable of its corresponding topological node, the voltage state variables of all topological nodes constitute the independent variable x1, and the voltage state variables of physical nodes other than the topological nodes constitute the dependent variable x2; set the initial value of the voltage state variable of each topological node in the power system, and perform iterative correction to obtain the corrected voltage state variable (the estimated value of the voltage state variable );

[0051] The known power system analog measurement equation is:

[0052] z=h1(x1)+v (1)

[0053] Among them, x1 is the voltage state variable (independent variable) of the node after the system topology analysis, h1(x1) is the measurement function, z is the quantity measurement (this quantity is measured, so it is actually independent of the variable), which is directly obtained by the measurement system. Its data can be node voltage, injected power and branch flow, v is the measurement random error of the quantity measurement, which obeys the normal distribution with a mean of 0, and the covariance matrix of the error is R. The following example illustrates the quantity measurement z, the measurement function h(x), and the residual: the power flowing through the resistor R=2 is P, which is measured by 2 instruments and is 5 and 4.9 respectively. The voltage u at both ends is the state quantity, then:

[0054] Quantity measurement z = [5, 4.9] T ;

[0055] The measurement function is

[0056]

[0057] After estimation (assuming that the accuracy of the two tables is the same, the simplest estimation method is to take the average value, or the least squares method can be used. For this example, the results are consistent), the estimated value of the state variable u is

[0058]

[0059] Then the residuals of the measurements z1 and z2 are

[0060]

[0061]

[0062] Usually, the model of power system state estimation adopts weighted least squares method, and its objective function, that is, weighted least squares estimation model, is as follows:

[0063] J(x1)=(z-h1(x1)) T R -1 (z-h1(x1)) (2)

[0064] Where R represents the covariance matrix of the error corresponding to a given quantity measurement. If there are m quantity measurements in the power system and the voltage vectors of N topological nodes are to be calculated, then

[0065] z=[z1 z2 ... z m ] T (3)

[0066] x1=[x1 x2 ... x N ] T (4)

[0067] Among them, z1,z2,…,z m with x1,x2,…,x N are the elements in z and x1 respectively, i In polar coordinates it can be defined as

[0068] x i =[θ i v i ] T i=1,....,N (5)

[0069] Among them, θ i With v i Represent the phase angle and amplitude of the voltage respectively. The optimal estimate of formula (2) can be solved by Newton's method, and its iterative correction equation is as follows:

[0070]

[0071] Where k is the number of iterations, The Jacobian matrix of the independent variable corresponding to the measurement function h1(x1):

[0072]

[0073] The specific steps of solving formula (6), i.e. iterative correction, are as follows:

[0074] (1) Assigning initial value The voltage amplitude is set to 1 and the phase angle is set to 0, that is, v i =1.0,θ i =0, set k=0;

[0075] (2) Based on Calculate H1 using formula (7).

[0076] (3) According to formula (6), the correction value is obtained Modify the independent variable:

[0077] (4) Let k = k + 1.

[0078] (5) If The maximum value of each element in is less than the threshold 10 -4 Then the final modified independent variable is the estimated value of the state variable Otherwise, go to (2).

[0079] Step 102: Estimated values ​​of voltage state variables at each node in the power system Calculate the simulated measurement residual r.

[0080] The estimated values ​​of the voltage state variables at each node in the power system are obtained After that, the simulated measurement residual r is the difference between the measurement z and the measurement value calculated from the estimated value of the independent variable The difference, that is, the estimated residual is:

[0081]

[0082] Step 2: Determine the dependent variables based on the estimated values ​​of the voltage state variables in step 1 This gives the voltages of all physical points And construct the constraint matrix A of the closed switch.

[0083] Step 201: Calculate the voltage of the physical node and construct a constraint matrix A.

[0084] Based on the physical connection diagram, each topological node is a connected piece consisting of one or more closed switches. If the voltage of each physical node is a state variable to be determined, then

[0085] x=[x1 ... x N x n+1 .... x nn ] (9)

[0086] Obviously, nn>>N, x contains x1=[x1 x2 ... x N ].

[0087] by Figure 2 As an example, the electrical wiring diagram after topology is as follows: Figure 3As shown, node 3' is connected by switches 6-7, 5-8, 7-8, 7-10, and 8-9, and its physical nodes include 5, 6, 7, 8, 9, and 10. The state variables x of each physical node in the connected slice = [...x5 x6 x7 x8 x9 x 10 ...] T .

[0088] x 3' is the state variable corresponding to node 3' after topological analysis, Figure 2 The wiring diagram shown is easy to understand

[0089] x 3' =x5=x6=x7=x8=x9=x 10 (10)

[0090] That is, the voltage of all physical nodes in the system can be estimated by step 1 get.

[0091] The state of each physical node constitutes the full state x, and the state of one node in each connected piece constitutes x1. It is easy to see that this x1 is exactly the same as x1 in step 1.

[0092] by Figure 2 For example, take

[0093] x1=[x1 x 12 x7] T =[x 1' x 2' x 3' ] T (11)

[0094] Except for x1, the states of all physical nodes in the system are x2, that is,

[0095]

[0096] by Figure 2 For example, there are

[0097] x2=[x2 x3 x4 x 11 x 13 x5 x6 x8 x9 x 10 ] (13)

[0098] The closed switch constraint equation of the connected patch corresponding to node 3', that is, equation (10), can be transformed into the following form:

[0099]

[0100] The five equations of formula (14) can respectively represent whether the switches 5-8, 6-7, 7-8, 8-9, and 7-10 are connected in the connecting piece, that is, whether the switch is in a closed state.

[0101] Formula (14) is written in matrix form as follows

[0102]

[0103] Without loss of generality, the constraint equations for all nodes in the system can be written as follows:

[0104]

[0105] in,

[0106]

[0107] Where A2 is a negative unit matrix, without loss of generality:

[0108]

[0109] Among them, I 2×2 is a 2×2 dimensional unit matrix, whose elements correspond to the phase angle and amplitude of the x1 state variable, n N ×n N dimensional unit matrix.

[0110] Obviously, after the estimation in step 1, the estimated value of x1 is The x2 estimate is:

[0111]

[0112] The estimated values ​​of the independent variables and the dependent variables are concatenated to obtain the estimated values ​​of the state variables of all physical nodes, that is, the estimated value of the state of the whole system.

[0113] Step 202: Obtain augmented H and λ.

[0114] The quantity measured is characterized by the state variable x:

[0115] z=h(x)+v=h1(x1)+v (19)

[0116] According to the estimated values ​​of the state variables of all physical nodes in step 201 Find the expanded measurement Jacobian matrix H.

[0117]

[0118] Based on the extended measurement Jacobian matrix, measurement residual (measurement value of measurement z and state variable estimation value of all physical nodes) The difference between the switch constraints and the constraint matrix are used to find the Lagrange multiplier λ corresponding to the switch constraints:

[0119]

[0120] If there are n k switch constraint equations (the number of connected pieces is the number of topological nodes, each connected piece has a number of switches, and each switch is an equation, that is, n k is the number of switches), it is easy to know that the number of rows in A is n k ,λ is n k dimensional column vector, whose element value is λ i The multiplier value corresponding to the i-th switch constraint.

[0121] Step 3: Obtain the standardized multiplier λ N,i and the standard residual r N,i , through λ N,i and r N,i Whether the threshold value is exceeded, the simulated bad data and the error of the switch element status are uniformly identified.

[0122] Step 301, calculate the Lagrange multiplier and the covariance matrix of the measurement residual:

[0123] First, according to formula (22), we can find the matrices C1 and C2.

[0124]

[0125] From the state estimation theory, we know that when the measurement random error v obeys the normal distribution and satisfies the white noise condition, the multiplier and residual also obey the normal distribution and satisfy the white noise condition, and the corresponding covariance matrix is ​​V λ 、V r .

[0126] The following relationship holds, namely

[0127]

[0128] V r =R-HC2H T (twenty four)

[0129] Step 302: Standardize the residuals and multipliers and identify bad data.

[0130] Based on the covariance matrix V r 、V λ , Lagrange multiplier λ and simulated measurement residual r, calculate the standard residual and standardized multiplier. According to the concept of standardized residual, the standard residual r N,iand the normalization multiplier λ N,i The definition is as follows:

[0131]

[0132]

[0133] In the formula, r i ,λ i are the i-th element in the matrix r, λ, and v r,ii , v λ,ii The matrices V r 、V λ The element at (i,i) on the diagonal matrix.

[0134] Any element of the multiplier λ vector is associated with the measurement equation of the corresponding switching element, and has the consistency and correlation with the residual distribution of the analog quantity, thereby having the function of identifying error information.

[0135] According to the knowledge of probability theory, the standard residual and the standardized multiplier should be less than 2.81. If the maximum standard residual is greater than the set value of 2.81, it means that there is bad analog data; if the maximum standardized multiplier is greater than 2.81, it means that there is a switch topology error. Therefore, the maximum standard residual is used to detect and identify bad analog data, and the maximum standardized multiplier is used to identify the switch component information error.

[0136] like Figure 1 As shown, the theoretical basis of the present invention is as follows: the constraint equations in the generalized state estimation model are re-described, the global state variables are decoupled according to the characteristics of the constraint equations, and the decoupled state variables are divided into independent variables and dependent variables; independent state variables are used to represent the measurement equations, and the measurement Jacobian matrix structure is analyzed accordingly, and the global solution is divided into two steps when the objective function remains unchanged; finally, the bad analog data and the errors of the switch element state are uniformly identified through Lagrange multipliers and measurement residuals. Specifically:

[0137] Usually, the topological grid nodes are connected pieces composed of zero-impedance elements (switches, circuit breakers, etc.), and the physical nodes refer to the real connection nodes with impedance elements and zero-impedance elements. Physical nodes have more real connection nodes with zero-impedance elements than grid nodes.

[0138] Define the state variable corresponding to the physical node as x, and the measurement equation is

[0139] z=h(x)+v (27)

[0140] Where x is the voltage state variable corresponding to the physical node of the system, h(x) is the measurement function, and z is the quantity measurement, which is the same as in formula (1).

[0141] The generalized state estimation model considering the closed switch state is as follows:

[0142] J(x)=(zh(x)) T R -1 (zh(x))

[0143] st. Ax=0 (28)

[0144] The constraint equation is used to describe that the voltage state variables at both ends of the closed switch are equal, so each row of the matrix A has two non-zero element values, namely 1 and -1.

[0145] Formula (28) is a nonlinear optimization problem with equality constraints, and its corresponding Lagrangian function is:

[0146]

[0147] The optimal solution of formula (29) is:

[0148]

[0149] in

[0150]

[0151] Solving equation (30) yields the estimated value of the state variable x: The estimated residual is The multiplier λ can be expressed as:

[0152]

[0153] Where S = (AA T ) -1 AH T R -1 is the sensitivity matrix of the multiplier λ and the residual r. The above formula shows that in the process of solving equation (30), although the multiplier λ participates in the iterative calculation, its final value can be directly obtained from the estimated residual. And each element value in λ corresponds to a constraint equation in Ax=0.

[0154] According to the generalized state estimation theory, if the measurement error v obeys the normal distribution, then the multiplier λ also obeys the normal distribution. Therefore, the correctness of the corresponding switch state can be determined by checking whether the value of each element of λ is abnormal. If its value exceeds the threshold, the corresponding switch state may be wrong.

[0155] The above is the basic theory of generalized state estimation.

[0156] The present invention optimizes the high-dimensional matrix calculation in the process of solving the above formula (30), reduces the matrix dimension, and thus improves the calculation speed.

[0157] If the n physical nodes in a connected sheet (connecting closed switch elements or other buses) in a power plant are defined as state variables, the node voltages in the connected sheet are equal, which can be written as follows:

[0158] x1=x2=…=x n (33)

[0159] Equation (33) can be written as follows:

[0160]

[0161] The above n state variables correspond to a connected piece, that is, a node after topological analysis.

[0162] Without loss of generality, formula (34) is abbreviated as follows:

[0163] [1 n |-I n×n ]x=0 n (35)

[0164] In the formula, x is the state variable of each physical node in the system, 1 n is an n-dimensional column vector whose elements are all 1, I n×n is an n-dimensional unit matrix, 0 n is an n-dimensional zero matrix.

[0165] If the system has N connected slices, the number of physical nodes connected to each connected slice is n1, n2, ..., n respectively. N , where each connected piece takes a state variable to form x1 (this x1 is x1 in step 101), and the remaining state variables are defined as x2. The system state variables can be expressed as:

[0166]

[0167] By sorting the state variables, the closed switch state constraint equation can be written as follows:

[0168]

[0169] Formula (37) can be written as

[0170]

[0171] Among them, I 2×2 is a 2×2 dimensional unit matrix, whose elements correspond to the phase angle and amplitude of the x1 state variable, n N ×n N dimensional unit matrix.

[0172] Formula (37) is an expression of the switch constraint equation Ax=0.

[0173] Since x2 is consistent with x1 through the equality constraint equation, x1 represents the minimum set of system state variables and is the independent variable of the system, while x2 is the dependent variable.

[0174] The measurement equation represented by the state variable x can always be expressed through x1 as:

[0175] z=h(x)+v=h(x1,x2)+v=h1(x1)+v (39)

[0176] Where v is the random error of the measurement.

[0177] Correspondingly, the augmented H equivalent transformation is:

[0178]

[0179] Formula (30) can be solved by the following iterative equation:

[0180]

[0181] Where k is the number of iterations, Δz k is the correction amount of z for the kth iteration, and R represents the covariance matrix of the error corresponding to the given quantity measurement.

[0182] Formula (41) shows that when the measurement equation is expressed by the state variable x1, the final estimate of the model is and The solution is consistent with the solution of the generalized state estimation; during the iteration process, x2 always remains consistent with x1. Since λ is 0 at this time, this value does not affect the correction of x1, that is, the solution of x1 can be completely solved by the first sub-formula. Since the Jacobian matrix H1 only takes partial derivatives of x1, its dimension is much lower than the dimension of H in the generalized state estimation. The order reduction process in the iterative solution process can reduce the amount of calculation and reduce the memory requirement.

[0183] After iterative solution of factor (41), λ is always zero, and the switch topology error cannot be determined. and λ can be found Then, it can be directly obtained by equation (18) and equation (32).

[0184] by Figure 2 Take the following as an example to illustrate the details of each step of the present invention:

[0185] (1) Figure 2 After topological analysis, the nodes (connected pieces) are 1', 2', 3', such as Figure 3 As shown,

[0186] x1=[x 1' x 2' x 3' ] T (42)

[0187] Among them, topological node 1' corresponds to physical nodes 1, 2, 3, and 4, topological node 2' corresponds to physical nodes 11, 12, and 13, and topological node 3' corresponds to physical nodes 5, 6, 7, 8, 9, and 10.

[0188] (2) By Figure 2 As shown, A1 represents a generator, A2 represents a switch in closed position, and A3 represents a switch in open position. The nodes connected by the closed switches form a connected piece, nodes 1, 2, 3, and 4 form a connected piece 1', nodes 5, 6, 7, 8, 9, and 10 form a connected piece 3', and nodes 11, 12, and 13 form a connected piece 2'. The voltages of the physical nodes in each connected piece are equal.

[0189] definition:

[0190] x=[x1 x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 ] T (43)

[0191] x1=[x1 x 12 x7] T

[0192] x2=[x2 x3 x4 x5 x6 x8 x9 x 10 x 11 x 13 ] T (44)

[0193] The corresponding A matrix form is as follows:

[0194]

[0195]

[0196]

[0197] The measurement function in formula (19) is Figure 2 For example, the power measurement z of branch 3-6 is expressed by x1, and its variable is the same as x 1' ,x 3' Related, the form is as follows:

[0198] z=h(x 1' ,x3' )+v (48)

[0199] If the measurement is expressed in x, it has the following form:

[0200] z=h(x3,x6)+v (49)

[0201] Although its value remains unchanged, and x3 = x 1' ,x6=x 3' However, due to the change of variable names, the dimensions and structures of H1 and H change accordingly.

[0202] (3) According to the structure of A, the corresponding relationship between λ and the switch in step (3) is shown in Table 1.

[0203] Table 1. Correspondence between multipliers and switches

[0204] Multiplier Corresponding switch <![CDATA[λ1]]> 1-2 <![CDATA[λ2]]> 1-3 <![CDATA[λ3]]> 1-4 <![CDATA[λ4]]> 5-8 <![CDATA[λ5]]> 8-9 <![CDATA[λ6]]> 6-7 <![CDATA[λ7]]> 7-8 <![CDATA[λ8]]> 7-10 <![CDATA[λ9]]> 11-12 <![CDATA[λ 10 ]]> 13-12

[0205] Embodiment 2

[0206] This embodiment provides a unified identification system for analog bad data and switch topology errors, which specifically includes the following modules:

[0207] A variable partitioning module is configured to: obtain a set of voltage state variables of all physical nodes on both sides of the switch, and partition the set into independent variables and dependent variables;

[0208] An independent variable estimation module is configured to: according to a weighted least squares estimation model, use an iterative method to correct the independent variable until the correction amount is less than a set threshold, and use the final corrected independent variable as an estimated value of the independent variable;

[0209] A dependent variable estimation module, configured to: calculate a simulated quantity measurement residual and an estimated value of the dependent variable based on an estimated value of the independent variable;

[0210] A Lagrange multiplier calculation module, configured to: calculate Lagrange multipliers based on the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables;

[0211] The topology error judgment module is configured to judge whether there is bad analog quantity data and switch topology error based on the Lagrange multiplier and the analog quantity measurement residual.

[0212] The variable partitioning module is specifically configured as follows:

[0213] Based on the connection relationship between the switch and the physical node and the switch status, a topological analysis is performed to obtain all topological nodes. Each topological node corresponds to a group of physical nodes connected by a closed switch.

[0214] The voltage state variables of all topological nodes are combined into independent variables;

[0215] The voltage state variables of physical nodes except topological nodes are composed of dependent variables.

[0216] The simulated variable measurement residual is the difference between the measured variable and the measured value calculated from the estimated value of the independent variable.

[0217] It should be noted here that each module in this embodiment corresponds to each step in Example 1 one by one, and the specific implementation process is the same, which will not be repeated here.

[0218] Embodiment 3

[0219] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the method for uniformly identifying bad analog data and switch topology errors as described in the first embodiment are implemented.

[0220] Embodiment 4

[0221] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the unified identification method for analog bad data and switch topology errors as described in the first embodiment are implemented.

[0222] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0223] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0224] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0225] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0226] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0227] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A unified identification method for bad analog data and switch topology errors, characterized in that: include: Obtain the voltage state variable set of all physical nodes on both sides of the switch and divide it into independent variables and dependent variables; The method of dividing the independent variables and the dependent variables is: Based on the connection relationship between the switch and the physical node and the switch status, a topological analysis is performed to obtain all topological nodes. Each topological node corresponds to a group of physical nodes connected by a closed switch. The voltage state variables of all topological nodes are combined into independent variables; The voltage state variables of the physical nodes except the topological nodes are formed into dependent variables; According to the weighted least squares estimation model, the independent variable is corrected by an iterative method until the correction amount is less than a set threshold value, and the final corrected independent variable is used as the estimated value of the independent variable; Calculating simulated quantity measurement residuals and estimated values ​​of the dependent variables based on the estimated values ​​of the independent variables; calculating Lagrange multipliers based on the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables; The calculation method of the Lagrange multiplier is: Concatenating the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables to obtain estimated values ​​of the state variables of all physical nodes; Based on the estimated values ​​of the state variables of all physical nodes, the expanded measurement Jacobian matrix is ​​calculated; Based on the extended measurement Jacobian matrix, measurement residual and constraint matrix, the Lagrange multiplier is obtained; Optimize high-dimensional matrix calculations during the solution process; The order reduction process in the iterative solution process reduces the dimension of the measurement Jacobian matrix; Based on the Lagrange multiplier and the analog quantity measurement residual, it is determined whether there is bad analog quantity data and switch topology error.

2. The method for uniformly identifying bad analog data and switch topology errors according to claim 1, characterized in that: The simulated variable measurement residual is the difference between the variable measurement and the value of the variable calculated from the estimated value of the independent variable.

3. The method for uniformly identifying bad analog data and switch topology errors according to claim 1, characterized in that: The specific method for determining whether there is bad analog data and switch topology error is as follows: Calculating the covariance matrix of the Lagrange multiplier and the simulated quantity measurement residual; Calculating the standardized residual and the standardized multiplier based on the covariance matrix, the Lagrange multiplier and the simulated measurement residual; If the maximum standard residual is greater than the set value, it means there is bad analog data; if the maximum standardized multiplier is greater than the set value, it means there is a switch topology error.

4. Unified identification system for bad analog data and switch topology errors, characterized by: include: A variable partitioning module is configured to: obtain a set of voltage state variables of all physical nodes on both sides of the switch, and partition the set into independent variables and dependent variables; The method of dividing the independent variables and the dependent variables is: Based on the connection relationship between the switch and the physical node and the switch status, a topological analysis is performed to obtain all topological nodes. Each topological node corresponds to a group of physical nodes connected by a closed switch. The voltage state variables of all topological nodes are combined into independent variables; The voltage state variables of the physical nodes except the topological nodes are formed into dependent variables; An independent variable estimation module is configured to: according to a weighted least squares estimation model, use an iterative method to correct the independent variable until the correction amount is less than a set threshold, and use the final corrected independent variable as an estimated value of the independent variable; A dependent variable estimation module, configured to: calculate a simulated quantity measurement residual and an estimated value of the dependent variable based on an estimated value of the independent variable; A Lagrange multiplier calculation module, configured to: calculate Lagrange multipliers based on the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables; The calculation method of the Lagrange multiplier is: Concatenating the estimated values ​​of the independent variables and the estimated values ​​of the dependent variables to obtain estimated values ​​of the state variables of all physical nodes; Based on the estimated values ​​of the state variables of all physical nodes, the expanded measurement Jacobian matrix is ​​calculated; Based on the extended measurement Jacobian matrix, measurement residual and constraint matrix, the Lagrange multiplier is obtained; Optimize high-dimensional matrix calculations during the solution process; The order reduction process in the iterative solution process reduces the dimension of the measurement Jacobian matrix; The topology error judgment module is configured to judge whether there is bad analog quantity data and switch topology error based on the Lagrange multiplier and the analog quantity measurement residual.

5. The unified identification system for analog bad data and switch topology errors according to claim 4, characterized in that: The simulated variable measurement residual is the difference between the variable measurement and the value of the variable calculated from the estimated value of the independent variable.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the unified identification method for analog bad data and switch topology errors as described in any one of claims 1 to 3 are implemented.

7. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the unified identification method for analog bad data and switch topology errors according to any one of claims 1 to 3 are implemented.

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