A hybrid-size cell circuit design method using a two-step modular iteration approach

Abstract

The present invention provides a method for designing a mixed-size cell circuit using a two-step modulus iteration method. First, the multi-row high-standard cells are preprocessed into single-row height sub-cells. Then, a network flow is established for all cells and diffused to avoid local congestion. Next, the legalization problem is equivalent to a convex quadratic programming problem, and the quadratic programming problem is equivalently transformed into a linear complementarity problem, which is solved using a two-step modulus system matrix splitting iteration method. Finally, the multi-row high-standard cells are restored and placed in the available positions in the row, and the remaining illegal cells are processed. Compared with the prior art, the present invention can accelerate the convergence rate of the iteration process, quickly obtain a high-quality neighborhood solution to the legalization problem, reduce the number of iterations and running time in the process of solving the linear complementarity problem, and further improve the design efficiency in the layout stage through a forward scanning and backward scanning technique by selecting two pairs of appropriate splitting matrices M1, N1, M2, N2.

Description

Technical Field

[0001] The invention relates to the field of physical design automation of very large scale integrated circuits, and in particular to a mixed-size unit circuit design method using a two-step module iteration method, which can be used for the legalization process of mixed-size standard unit circuits. Background Art

[0002] For many years, single row height standard cell layout has been dominant. However, as the complexity of advanced technology node design requirements increases, mixed size standard cell circuit layout is gradually introduced into VLSI design. Usually, simple cells such as inverters are designed as single row height, while complex cells such as flip-flops are designed as multiple row heights; in physical design synthesis, the goal of the layout stage is to determine the location and orientation of each cell in the layout.

[0003] The layout problem is an NP-hard problem, and the huge amount of standard cell data in each circuit design causes the solution space to explode, making an accurate solution almost impossible. Therefore, some approximate methods are usually used to obtain an approximate optimal solution to avoid the computational time complexity of direct solution. However, how to quickly and efficiently approximate the optimal solution is a problem that needs to be solved urgently.

[0004] In order to simplify the design complexity of the layout stage, this stage is usually decomposed into three sub-stages, namely global layout, legalization, and detailed layout stages. In the global layout stage, the overlap between cells is temporarily ignored, with the goal of minimizing the line length; legalization eliminates the cell overlap generated in the previous stage and aligns the cells to the available positions in the row; the detailed layout stage further refines the layout results of the previous stage through operations such as cell exchange; due to the heterogeneous structure of standard cells, the legalization problem becomes more and more complicated; the existing legalization algorithms mainly include heuristic algorithms and analytical algorithms; heuristic algorithms have the advantage of fast solution speed, but are prone to fall into local optimal solutions; analytical algorithms can analyze the problem model from a global perspective and are more likely to produce high-quality neighborhood solutions; Chen Jianli et al. (CN 106971042 A) proposed to transform the quadratic programming problem in the legalization problem into a linear complementarity problem, and apply the modular matrix splitting iteration method to solve the linear complementarity problem; from a global perspective, the convergence speed of solving the linear complementarity problem is further improved, but the number of iterations and running time are relatively long, and the design efficiency of the layout stage is low. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to solve the deficiencies in the prior art. The present invention provides a mixed-size unit circuit design method using a two-step modular iteration method. The method consists of a forward scan and a backward scan, which can reduce the number of iterations and running time in the process of solving the linear complementarity problem, and further improve the design efficiency in the layout stage.

[0006] In order to achieve the above objectives, the present invention provides a mixed-size unit circuit design method using a two-step modular iteration method, which is used in the legalization process of mixed-size standard unit circuits, and includes the following steps:

[0007] S1: pre-processing the standard unit, dividing the multiple-row-height standard unit into multiple single-row-height standard sub-units;

[0008] S2: diffuse the standard unit;

[0009] S3: Formulate the mixed-size standard unit legalization problem as a quadratic programming mathematical model;

[0010] S4: Convert the quadratic programming model into a linear complementarity problem;

[0011] S5: Solve the linear complementarity problem using a two-step modular matrix splitting iteration method;

[0012] S6: unify the x coordinates of the sub-units divided from the standard unit of multiple row heights, and align them to the available positions in the row;

[0013] S7: Legalize the remaining illegal units.

[0014] Furthermore, the specific implementation of step S1 includes: given a layout rectangular area of ​​a chip, (0,0) and (W,H) are used to represent the coordinates of its lower left corner and upper right corner respectively; W represents the width of the layout area, and H represents the height of the layout area; the standard cell set to be laid out is C = (c 1 ,c 2 ,…c n ), where unit c i The initial lower left corner coordinates obtained from the global stage are The width and height of the unit are w i ,h i , the coordinates after the legalization stage are (x i ,y i ); align all standard cells to the nearest row that matches their power line; for standard cells with multiple row heights, represent them as multiple sub-cells, using (c i1 ,c i2 ,…c it ), where t means the height of the standard cell is t times the row height.

[0015] Furthermore, in step S2, in order to avoid overcrowding of standard cells in subsequent processing, the network flow algorithm is used to diffuse the cells to ensure that the cell width in each row does not exceed the width of the row; we divide the layout area into grids evenly in the horizontal and vertical directions, and each grid constitutes a node in the network flow graph; in addition, two additional nodes are created, namely the super source node (N B ) and super sink nodes (N E );Calculate the sum of the areas of the cells in each grid s C , and compare it with the grid area s G Compare; if s C >s G , then the grid is called the overflow grid and the overflow area s is recorded o ; if s C ≤s G , then the grid is called an idle grid and the remaining idle area s is recorded f For the overflow grid, set it to the source node N in the network flow s , and establish a line from N B To N s The arc, the capacity and cost on the arc are set to s o and zero; for an idle grid, set it to the target node N t , and establish a line from N t To N E The arc, the capacity and cost on the arc are set to s f and 0; and for the overflow grid, find the free grid adjacent to it and establish s To N t The capacity and cost on the arc are set to infinity and the displacement of the unit moving between the two grids respectively; the established network flow graph is solved to obtain the strategy of unit movement in the grid, and the unit is moved according to the strategy. The unit after movement c i The coordinates of

[0016] Furthermore, in step S3, the legalization process is to eliminate the overlap between cells and minimize the total displacement of the standard cell as the optimization goal. In the previous step, the cell has been moved minimally in the vertical direction, that is, aligned with the matching power rail, so the displacement in the vertical direction can be ignored. The legalization problem is described as the following model (1):

[0017]

[0018] The above model is rewritten as the standard form of convex quadratic programming problem, namely:

[0019]

[0020] Where B is an identity matrix, is a column vector consisting of the initial horizontal coordinates of the elements; any adjacent pair of standard elements should satisfy the inequality x j -x i ≥w i (x j ≥x i ), the inequality is established between all adjacent cells, which can be written in matrix form Wx≥d, where W is a matrix containing only two elements -1 and 1 in each row, representing cell c respectively. i and c j The horizontal coordinate x j ,x i , d is a column vector, where the corresponding component represents the left unit c i The width w i ; Then the number of rows of W and d is the number of constraints, and the number of columns of W is the total number of standard cells, that is, the sum of the number of single-row-height cells and the number of sub-cells into which multiple-row-height standard cells are split; R is also a matrix consisting of -1 and 1 in each row, where -1 represents multiple-row-height standard cells c i Subunit c i1 , 1 means c i Subunit c i2 , and so on. i2 -x i1 =0 guarantee c i The horizontal coordinates of the sub-units are equal, so the constraint matrix Rx = 0 can be obtained; a mixed-size standard unit layout, the matrix W, R and vector d constructed according to this position are as follows:

[0021] R=(0 -1 1 0), d=(w 1 w 2 );

[0022] Using the Lagrange multiplier method, the equality constraints in the quadratic programming are added to the objective function, and (2) can be expressed as:

[0023]

[0024] Here, λ is the Lagrange multiplier.

[0025] Furthermore, in step S4, using the Karush-Kuhn-Tucker (KKT) condition, model (3) can be written as a KKT equation system with the following conditions:

[0026]

[0027] Rewrite equation (4) into the following form:

[0028]

[0029] make The problem then evolves into finding a pair of non-negative and orthogonal solution vectors (w, z) that satisfy the following conditions:

[0030] w=Az+q≥0,z≥0and w T z ≥ 0.(6)

[0031] Problem (6) is a linear complementarity problem.

[0032] Furthermore, the specific implementation of step S5 is as follows: A=M 1 -N 1 =M 2 -N 2 For the two splits of A, it can be transformed into the following equivalent absolute value equation:

[0033]

[0034] Given an arbitrary initial vector v (0) ∈R n×1 , calculate v by iteratively solving the linear system (k+1) The value of the absolute residual vector RES(z (k) ):=||min(Az (k) +q,z (k) )|| 2 Less than or equal to a given constant, then it can be considered an iterative sequence Convergence, the solution process can be described as:

[0035]

[0036] and

[0037]

[0038] For formula (8), direct methods such as Cholesky decomposition or LU decomposition can be used to solve it, and the conjugate gradient method can also be used for approximate solution; take Ω = ωI, and select M 1 ,N 1 ,M 2 ,N 2 As shown below:

[0039]

[0040]

[0041] Among them, β, θ are positive constants, F = tridiag(W(B+λR T R) -1 W T ) is the Schur complement matrix W(B+λR T R) -1 W T Since matrix inversion takes a lot of time, the Sherman-Morrison formula is used to simplify the inversion calculation; because RR T is a diagonal matrix whose diagonal elements are all 2, and B is the identity matrix, then (B+λR T R) -1 It can be expressed by the following equation:

[0042]

[0043] therefore, Furthermore, in step S6, the x-coordinates of all subunits of each multiple-row-height standard unit are sorted in ascending order, and the median is the desired x-coordinate of the multiple-row-height standard unit, and then the unit is placed at the nearest available position to the desired x-coordinate.

[0044] Furthermore, in step S7, for a few standard cells that still overlap or exceed the right boundary of the layout area, the standard cells are traversed from the upper right corner of the layout area in the order from right to left and from top to bottom. i If it exceeds the right boundary, its coordinates are set to Ww i , if unit c i With c i-1 If they overlap, then c i-1 Set the coordinate to x i -w i-1 Since the movement of multiple row height standard cells may cause the cells of adjacent rows to overlap, the multiple row height standard cells that have been moved in the previous row will not be moved in the next row; then, the standard cells are traversed again from left to right and from bottom to top according to the same rule. After this step, all cell overlaps can be eliminated.

[0045] The above technical scheme of the present invention has the following advantages over the prior art: a mixed-size unit circuit design method using a two-step modular iteration method, first pre-processing multiple row height standard units into single row height sub-units, then establishing a network flow for all units, diffusing them to avoid local congestion, then equivalently converting the legalization problem into a convex quadratic programming, and equivalently converting the quadratic programming problem into a linear complementary problem, solving it using a two-step modular matrix splitting iteration method, finally restoring the multiple row height standard units and placing them on the available positions in the row, and processing the remaining illegal units; compared with the prior art, the present invention adopts a forward scanning and backward scanning technology, by selecting two pairs of appropriate splitting matrices M 1 ,N 1 ,M 2 ,N 2 , which can accelerate the convergence speed of the iterative process, quickly obtain high-quality neighborhood solutions to the legalization problem, reduce the number of iterations and running time in the process of solving the linear complementarity problem, and further improve the design efficiency in the layout stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flow chart for legalization of mixed-size standard unit circuits;

[0047] Figure 2 is a sample diagram of the layout of mixed-size standard cells;

[0048] Figure 3 This is a diagram of the solution steps of the two-step modular matrix splitting iteration method. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0050] like Figure 1 A mixed-size unit circuit design method using a two-step module iteration method is shown, and the specific steps are as follows:

[0051] S1: pre-processing the standard unit, dividing the multiple-row-height standard unit into multiple single-row-height standard sub-units;

[0052] The specific implementation method includes: given a chip layout rectangular area, use (0,0) and (W,H) to represent its lower left corner coordinates and upper right corner coordinates respectively; W represents the width of the layout area, and H represents the height of the layout area. The standard cell set to be laid out is C = (c 1 ,c 2,…c n ), where unit c i The initial lower left corner coordinates obtained from the global stage are The width and height of the unit are w i ,h i , the coordinates after the legalization stage are (x i ,y i ); align all standard cells to the nearest row that matches their power line. For standard cells with multiple row heights, represent them as multiple sub-cells, using (c i1 ,c i2 ,…c it ), where t means the height of the standard cell is t times the row height.

[0053] S2: diffuse the standard unit;

[0054] To avoid overcrowding of standard cells in subsequent processing, the network flow algorithm is used to diffuse the cells to ensure that the cell width in each row does not exceed the width of the row; we divide the layout area into grids evenly in the horizontal and vertical directions, and each grid constitutes a node in the network flow graph; in addition, two additional nodes are created, namely the super source node (N B ) and super sink nodes (N E );Calculate the sum of the areas of the cells in each grid s C , and compare it with the grid area s G Compare; if s C >s G , then the grid is called the overflow grid and the overflow area s is recorded o ; if s C ≤s G , then the grid is called an idle grid and the remaining idle area s is recorded f ; For the overflow grid, set it to the source node N in the network flow s , and establish a line from N B To N s The arc, the capacity and cost on the arc are set to s o and zero; for an idle grid, set it to the target node N t , and establish a line from N t To N E The arc, the capacity and cost on the arc are set to s f and 0; and for the overflow grid, find the free grid adjacent to it and establish s To N tThe capacity and cost on the arc are set to infinity and the displacement of the unit moving between the two grids respectively; the established network flow graph is solved to obtain the strategy of unit movement in the grid, and the unit is moved according to the strategy. The unit after movement c i The coordinates of

[0055] S3: Formulate the mixed-size standard unit legalization problem as a quadratic programming mathematical model;

[0056] The legalization process is to eliminate the overlap between cells and minimize the total displacement of the standard cell as the optimization goal. In the previous steps, the cell has made the minimum vertical movement, that is, aligned with the matching power rail, so the displacement in the vertical direction can be ignored. The legalization problem is described as the following model (1):

[0057]

[0058] The above model is rewritten as the standard form of convex quadratic programming problem, namely:

[0059]

[0060] Where B is an identity matrix, is a column vector consisting of the initial horizontal coordinates of the elements; any adjacent pair of standard elements should satisfy the inequality x j -x i ≥w i (x j ≥x i ), the inequality is established between all adjacent cells, which can be written in matrix form Wx≥d, where W is a matrix containing only two elements -1 and 1 in each row, representing cell c respectively. i and c j The horizontal coordinate x j ,x i , d is a column vector, where the corresponding component represents the left unit c i The width w i ; Then the number of rows of W and d is the number of constraints, and the number of columns of W is the total number of standard cells, that is, the sum of the number of single-row-height cells and the number of sub-cells into which multiple-row-height standard cells are split; R is also a matrix consisting of -1 and 1 in each row, where -1 represents multiple-row-height standard cells c i Subunit c i1 , 1 means c i Subunit c i2 , and then classify; x i2 -x i1 =0 guarantee c i The horizontal coordinates of the sub-units are equal, so the constraint matrix Rx=0 can be obtained; Figure 2 This is a simple example diagram of a mixed-size standard cell layout. The matrices W, R, and vector d constructed based on this position are shown below:

[0061] R=(0 -1 1 0), d=(w 1 w 2 ).

[0062] Using the Lagrange multiplier method, the equality constraints in the quadratic programming are added to the objective function, and (2) can be expressed as:

[0063]

[0064] Here, λ is the Lagrange multiplier.

[0065] S4: Convert the quadratic programming model into a linear complementarity problem;

[0066] Using the Karush-Kuhn-Tucker (KKT) conditions, model (3) can be written as the following KKT equations:

[0067]

[0068] Rewrite equation (4) into the following form:

[0069]

[0070] make The problem then evolves into finding a pair of non-negative and orthogonal solution vectors (w, z) that satisfy the following conditions:

[0071] w=Az+q≥0,z≥0and w T z ≥ 0.(6)

[0072] Problem (6) is a linear complementarity problem.

[0073] S5: Solve the linear complementarity problem using a two-step modular matrix splitting iteration method;

[0074] Furthermore, the specific implementation of step S5 is: A=M 1 -N 1 =M 2 -N 2 For the two splits of A, it can be transformed into the following equivalent absolute value equation:

[0075]

[0076] Given an arbitrary initial vector v (0) ∈R n×1, calculate v by iteratively solving the linear system (k+1) The value of the absolute residual vector RES(z (k) ):=||min(Az (k) +q,z (k) )|| 2 Less than or equal to a given constant, then it can be considered an iterative sequence Convergence, the solution process can be described as:

[0077]

[0078] and

[0079]

[0080] Formula (8) can be solved by direct methods such as Cholesky decomposition or LU decomposition, or by conjugate gradient method for approximate solution. In the present invention, Ω = ωI is taken, and M is selected. 1 ,N 1 ,M 2 ,N 2 As shown below:

[0081]

[0082] Among them, β, θ are positive constants, F = tridiag(W(B+λR T R) -1 W T ) is the Schur complement matrix W(B+λR T R) -1 W T Since matrix inversion requires a lot of time, the present invention uses the Sherman-Morrison formula to simplify the inversion calculation; because RR T is a diagonal matrix whose diagonal elements are all 2, and B is the identity matrix, then (B+λR T R) -1 It can be expressed by the following equation:

[0083]

[0084] therefore, The specific solution process is as follows Figure 3 shown.

[0085] S6: unify the x coordinates of the sub-units divided from the standard unit of multiple row heights, and align them to the available positions in the row;

[0086] Sort the x-coordinates of all sub-units of each multiple-row-height standard unit in ascending order, and the median is the desired x-coordinate of the multiple-row-height standard unit. Then place the unit at the nearest available position to the desired x-coordinate.

[0087] S7: Legalize the remaining illegal units;

[0088] For a few standard cells that still overlap or exceed the right boundary of the layout area, start from the upper right corner of the layout area and traverse the standard cells from right to left and from top to bottom. i If it exceeds the right boundary, its coordinates are set to Ww i , if unit c i With c i-1 If they overlap, then c i-1 Set the coordinate to x i -w i-1 ; Since the movement of multiple row height standard cells may cause the cells of adjacent rows to overlap, the multiple row height standard cells that have been moved in the previous row will not be moved in the next row. Then, the standard cells are traversed again from left to right and from bottom to top according to the same rule. After this step, all cell overlaps can be eliminated.

[0089] The above description is only an exemplary embodiment of the present invention, and does not limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present invention.

Claims

1. A mixed-size unit circuit design method using a two-step modular iteration method, the method is used for the legalization process of mixed-size standard unit circuits, characterized in that: The steps include: S1: pre-processing the standard unit, dividing the multiple-row-height standard unit into multiple single-row-height standard sub-units; S2: diffuse the standard unit; S3: Formulate the mixed-size standard unit legalization problem as a quadratic programming mathematical model; In step S3, the legalization process is to eliminate the overlap between cells and minimize the total displacement of the standard cell as the optimization goal. In the previous step, the cell has been moved minimally in the vertical direction, that is, aligned with the matching power rail, so the displacement in the vertical direction can be ignored. The legalization problem is described as the following model (1): The above model is rewritten as the standard form of convex quadratic programming problem, namely: Where B is an identity matrix, is a column vector consisting of the initial horizontal coordinates of the elements; any adjacent pair of standard elements should satisfy the inequality x j -x i ≥w i (x j ≥x i ), establish this inequality between all adjacent cells, and write it in matrix form Wx≥d, where W is a matrix with only two elements -1 and 1 in each row, representing cell c i and c j The horizontal coordinate x j ,x i , d is a column vector, where the corresponding component represents the left unit c i The width w i ; Then the number of rows of W and d is the number of constraints, and the number of columns of W is the total number of standard cells, that is, the sum of the number of single-row-height cells and the number of sub-cells into which multiple-row-height standard cells are split; R is also a matrix consisting of -1 and 1 in each row, where -1 represents multiple-row-height standard cells c i Subunit c i1 , 1 means c i Subunit c i2 , and then classify; x i2 -x i1 =0 guarantee c i The horizontal coordinates of the subunits are equal, so the constraint matrix Rx = 0 can be obtained; the constructed matrices W, R and vector d are as follows: Using the Lagrange multiplier method, the equality constraints in the quadratic programming are added to the objective function, and (2) can be expressed as: Among them, λ is the Lagrange multiplier; S4: Convert the quadratic programming model into a linear complementarity problem; S5: Solve the linear complementarity problem using a two-step modular matrix splitting iteration method; S6: unify the x coordinates of the sub-units divided from the standard unit of multiple row heights, and align them to the available positions in the row; S7: Legalize the remaining illegal units.

2. A mixed-size unit circuit design method using a two-step modular iteration method according to claim 1, characterized in that: The specific implementation of step S1 includes: given a layout rectangular area of ​​a chip, (0,0) and (W,H) are used to represent the coordinates of its lower left corner and upper right corner respectively; W represents the width of the layout area, and H represents the height of the layout area; the standard cell set to be laid out is C = (c1, c2, ... c n ), where unit c i The initial lower left corner coordinates obtained from the global stage are The unit width and height are w i ,h i , the coordinates after the legalization stage are (x i ,y i ); align all standard cells to the nearest row that matches their power line; for standard cells with multiple row heights, represent them as multiple sub-cells, using (c i1 ,c i2 ,…c it ), where t means the height of the standard cell is t times the row height.

3. A mixed-size unit circuit design method using a two-step modular iteration method according to claim 1, characterized in that: In step S2, in order to avoid overcrowding of standard cells in subsequent processing, the network flow algorithm is used to diffuse the cells to ensure that the cell width in each row does not exceed the width of the row; we divide the layout area into grids evenly in the horizontal and vertical directions, and each grid constitutes a node in the network flow graph; in addition, two additional nodes are created, namely the super source node (N B ) and super sink nodes (N E );Calculate the sum of the areas of the cells in each grid s C , and compare it with the grid area s G Compare; if s C >s G , then the grid is called the overflow grid and the overflow area s is recorded o ; if s C ≤s G , then the grid is called an idle grid and the remaining idle area s is recorded f ; For the overflow grid, set it to the source node N in the network flow s , and establish a line from N B To N s The arc, the capacity and cost on the arc are set to s o and zero; for an idle grid, set it to the target node N t , and establish a line from N t To N E The arc, the capacity and cost on the arc are set to s f and 0; and for the overflow grid, find the free grid adjacent to it and establish s To N t The capacity and cost on the arc are set to infinity and the displacement of the unit moving between the two grids respectively; the established network flow graph is solved to obtain the strategy of unit movement in the grid, and the unit is moved according to the strategy. The unit after movement c i The coordinates of 4. A mixed-size unit circuit design method using a two-step modular iteration method according to claim 1, characterized in that: In step S4, using the Karush-Kuhn-Tucker (KKT) condition, model (3) can be written as the following KKT equations: The KKT equations (4) are reformulated as follows: make The problem then evolves into finding a pair of non-negative and orthogonal solution vectors (w, z) that satisfy the following conditions: w=Az+q≥0,z≥0 and w T z≥0(6) Problem (6) is a linear complementarity problem.

5. A mixed-size unit circuit design method using a two-step modular iteration method according to claim 1, characterized in that: Furthermore, the specific implementation of step S5 is: A=M1-N1=M2-N2 are two splits of A, which can be converted into the following equivalent absolute value equation: Given an arbitrary initial vector v (0) ∈R n×1 , calculate v by iteratively solving the linear system (k+1) The value of the absolute residual vector RES(z (k) ):=||min(Az (k) +q,z (k) )||2 is less than or equal to a given constant, then it can be considered an iterative sequence Convergence, the solution process can be described as: and For formula (8), Cholesky decomposition or LU decomposition is used for direct solution, and conjugate gradient method is also used for approximate solution; Ω = ωI, and M1, N1, M2, N2 are selected as follows: Among them, β, θ are positive constants, F = tridiag(W(B+λR T R) -1 W T ) is the Schur complement matrix W(B+λR T R) -1 W T The tridiagonal matrix of , since the matrix inversion takes a lot of time, the Sherman-Morrison formula is used to simplify the inversion calculation; because RR T is a diagonal matrix whose diagonal elements are all 2, and B is the identity matrix, then (B+λR T R) -1 It can be expressed by the following equation: therefore, 6. A mixed-size unit circuit design method using a two-step modular iteration method according to claim 1, characterized in that: In step S6, the x coordinates of all subunits of each multiple row height standard unit are sorted in ascending order, and the median is the desired x coordinate of the multiple row height standard unit, and then the unit is placed at the nearest available position to the desired x coordinate.

7. A mixed-size unit circuit design method using a two-step modular iteration method according to claim 1, characterized in that: In step S7, for a few standard cells that still overlap or exceed the right boundary of the layout area, the standard cells are traversed from the upper right corner of the layout area in the order from right to left and from top to bottom. i If it exceeds the right boundary, its coordinates are set to Ww i , if unit c i With c i-1 If they overlap, then c i-1 Set the coordinate to x i -w i-1 ; Since the movement of multiple row height standard cells may cause the cells of adjacent rows to overlap, the multiple row height standard cells that have been moved in the previous row will not be moved in the next row; then, the standard cells are traversed again from left to right and from bottom to top according to the same rules. After this step, all cell overlaps can be eliminated.

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