Output circuit, data driver, and display device

Abstract

An object of the present application is to provide an output circuit, a data driver, and a display device which are simple in structure and can achieve area saving. The output circuit includes: a first switch which outputs a positive voltage signal from an output terminal in an on state when the positive voltage signal is received via a first node; a second switch which outputs a negative voltage signal from an output terminal in an on state when the negative voltage signal is received via a second node; a third switch and a fourth switch which set the first node and the second node to a reference power supply voltage in an on state; a first follower circuit which follows a voltage signal of the first node by a source follower operation and generates a voltage signal in phase as a gate voltage and supplies the gate voltage to a gate of the first switch; and a second follower circuit which follows a voltage signal of the second node by a source follower operation and generates a voltage signal in phase as a gate voltage and supplies the gate voltage to a gate of the second switch.

Description

TECHNICAL FIELD

[0001] The present application relates to an output circuit that selectively outputs one of a positive voltage and a negative voltage, a data driver that drives a display panel, and a display device. BACKGROUND

[0002] Currently, as a main display device, there is a liquid crystal display device in which a liquid crystal panel using an active matrix driving method is used as a display device.

[0003] In the liquid crystal panel, a plurality of data lines and a plurality of gate lines are cross-arranged, the plurality of data lines respectively extend in a vertical direction of a two-dimensional picture, and the plurality of gate lines respectively extend in a horizontal direction of the two-dimensional picture. Further, a pixel portion connected to the data line and the gate line is formed at each intersection of the plurality of data lines and the plurality of gate lines.

[0004] The liquid crystal display device includes a data driver along with the liquid crystal panel, the data driver supplies a gray scale data signal having an analog voltage value corresponding to a luminance level of each pixel to the data line with a data pulse of a horizontal scanning period.

[0005] In order to prevent deterioration of the liquid crystal panel, the data driver performs polarity inversion driving, that is, a positive gray scale data signal and a negative gray scale data signal are alternately supplied to the liquid crystal panel every predetermined frame period.

[0006] As an output circuit that performs such polarity inversion driving, there is proposed an output circuit provided with a switch group that receives a positive driving voltage and a negative driving voltage corresponding to a gray scale data signal, and alternately selects one of the two to be output to a liquid crystal panel (for example, refer to SW1 to SW12 of Figures 8-10 of Patent Document 1).

[0007] In the output circuit described in the Patent Document 1, by using the switches SW1 to SW12, a state in which the positive driving voltage (5V) is output from the output pad OUT1 (a state of Figure 8 of the document) is switched to a state in which the negative driving voltage (-5V) is output from the output pad OUT1 (a state of Figure 10 of the document).

[0008] Further, in performing such polarity switching, in the output circuit described in the Patent Document 1, after a state in which one end of each switch is temporarily set to 0V (a state of Figure 9 of the document), it is switched to a state shown in Figure 10 of the document. Thereby, the voltage resistance of each switch can be constituted with a low voltage resistance element of one half of a liquid crystal driving voltage range.

[0009] [Patent Literature]

[0010] [Patent Literature]

[0011] [Patent Literature 1] Japanese Patent Laid-Open No. 2008-102211 SUMMARY

[0012] [Problems to be Solved by the Invention]

[0013] In Patent Literature 1 (the literature's Figures 8-10 ), the output selection switches (SW5 to SW8) connected to OUT1 and OUT2 can be provided as low-voltage elements whose voltage resistance at both ends is one-half of the range of the liquid crystal drive voltage.

[0014] However, in the case where the switches are configured with low-voltage transistor switches of one-half of the range of the liquid crystal drive voltage, a complementary switch in which a positive channel (P-channel) type and a negative channel (N-channel) type are combined is not suitable for use for the following reasons, and it is more desirable to configure the switches with a single conduction type transistor switch.

[0015] For example, the range of the voltage value of the drive voltage of the positive polarity is set to VGND (0 V) to VDDH (5 V), and the range of the voltage value of the drive voltage of the negative polarity is set to VDDL (-5 V) to VGND (0 V). Here, a case where the output selection switch SW5 that outputs the drive voltage of the positive polarity shown in Patent Literature 1 (the literature's Figures 8-10 ) is configured with an N-channel transistor switch is considered. The N-channel transistor switch SW5 outputs the drive voltage of the positive polarity supplied to the first terminal, and thus the control terminal thereof is supplied with the positive power supply voltage VDDH at the maximum. Here, when the output terminal OUT1 connected to the second terminal of the N-channel transistor switch SW5 is driven toward the reference power supply voltage VGND due to the polarity inversion from the negative polarity to the positive polarity, if the output terminal OUT1 does not sufficiently approach the reference power supply voltage VGND from the drive voltage of the negative polarity, there is a risk that the voltage difference between the control terminal of the N-channel transistor switch SW5 and the output terminal OUT1 connected to the second terminal exceeds the voltage resistance. In order to avoid the risk, it is necessary to sufficiently ensure the drive time of the reference power supply voltage VGND to the output terminal OUT1 at the time of polarity inversion, but it is difficult to achieve high-speed drive under the operation condition of a short output period.

[0016] In addition, in the case where the voltage value of the drive voltage of the positive polarity is close to the positive power supply voltage VDDH, in the N-channel transistor switch SW5, even if the positive power supply voltage VDDH is supplied to the control terminal thereof, it is not possible to output the voltage range from the positive power supply voltage VDDH to the threshold voltage of the N-channel transistor.

[0017] On the other hand, consider the case where the output selection switch SW5 is configured as a P-channel transistor switch. The P-channel transistor switch SW5 outputs a drive voltage of positive polarity supplied to the first terminal, and thus is controlled in such a manner that a voltage within the withstand voltage of the low voltage side with respect to the drive voltage of positive polarity is supplied to the control terminal thereof. In this case, there is no risk that the voltage difference between the control terminal of the P-channel transistor switch SW5 and the output terminal OUT1 connected to the second terminal exceeds the withstand voltage. In addition, as long as the supply voltage to the control terminal of the P-channel transistor switch SW5 is appropriately controlled with respect to the drive voltage of positive polarity, any drive voltage of positive polarity can be outputted through the P-channel transistor switch SW5.

[0018] Thus, the output selection switch that outputs a drive voltage of positive polarity is most suitable to be configured solely as a P-channel transistor switch. Similarly, the output selection switch that outputs a drive voltage of negative polarity is most suitable to be configured solely as an N-channel transistor switch.

[0019] In addition, in the structure where the output selection switch is configured as a single-conductivity-type transistor switch, when outputting a drive voltage of positive polarity in the vicinity of the reference power supply voltage VGND, cross-polarity control is required, that is, at least a voltage of negative polarity is supplied to the control terminal of the P-channel transistor switch that outputs a drive voltage of positive polarity. Similarly, cross-polarity control is also required for the control terminal of the N-channel transistor that outputs a drive voltage of negative polarity.

[0020] However, such cross-polarity control, that is, control that switches the polarity of the voltage supplied to the control terminal of the transistor switch, has been difficult in the past.

[0021] Therefore, an object of the present application is to provide an output circuit that is simple in structure and can achieve area saving, and a data driver and a display device that use the output circuit.

[0022] [Means for Solving the Problem]

[0023] The output circuit of the present application includes: a positive voltage signal supply circuit that supplies a positive voltage signal, which is a high voltage compared to a reference power supply voltage, to a first node or cuts off supply of the positive voltage signal to the first node; a negative voltage signal supply circuit that supplies a negative voltage signal, which is a low voltage compared to the reference power supply voltage, to a second node or cuts off supply of the negative voltage signal to the second node; a first output terminal; a first switch composed of a P-channel transistor having a source connected to the first node and a drain connected to the first output terminal, which connects the first output terminal and the first node in an on state and cuts off connection between the first output terminal and the first node in an off state; a second switch composed of an N-channel transistor having a source connected to the second node and a drain connected to the first output terminal, which connects the first output terminal and the second node in an on state and cuts off connection between the first output terminal and the second node in an off state; a third switch that applies the reference power supply voltage to the first node in an on state and stops application of the reference power supply voltage to the first node in an off state; a fourth switch that applies the reference power supply voltage to the second node in an on state and stops application of the reference power supply voltage to the second node in an off state; a first control section that sets the first switch to the off state when activated; a second control section that sets the second switch to the off state when activated; a first follower circuit connected to the first node and a gate of the first switch, which includes a first N-channel source follower transistor that performs a source follower operation by receiving a voltage signal of the first node at its own gate, generates a first gate voltage corresponding to a voltage of a source of the first N-channel source follower transistor and in phase with the voltage signal of the first node, and supplies the first gate voltage to the gate of the first switch; and a second follower circuit connected to the second node and a gate of the second switch, which includes a first P-channel source follower transistor that performs a source follower operation by receiving a voltage signal of the second node at its own gate, generates a second gate voltage corresponding to a voltage of a source of the first P-channel source follower transistor and in phase with the voltage signal of the second node, and supplies the second gate voltage to the gate of the second switch.

[0024] In addition, the data driver of the present application includes a plurality of the output circuits, and outputs a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity for driving a plurality of data lines of a liquid crystal display panel from the plurality of output circuits.

[0025] In addition, the display device of the present application includes a plurality of the output circuits, and outputs a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity from the plurality of output circuits.

[0026] [Effects of the Invention]

[0027] In the output circuit of the present application, the first switch (P-channel transistor) outputs a positive polarity voltage signal from the output terminal in an on state when receiving a voltage signal of a positive polarity higher than a reference power supply voltage via the first node. Further, the second switch (N-channel transistor) outputs a negative polarity voltage signal from the output terminal in an on state when receiving a voltage signal of a negative polarity lower than the reference power supply voltage via the second node. Here, the first and second follower circuits control the first and second switches in the following manner. That is, the first follower circuit follows the voltage signal of the first node by a source follower action and generates a voltage signal of the same phase as a gate voltage and supplies it to the gate of the first switch. The second follower circuit follows the voltage signal of the second node by a source follower action and generates a voltage signal of the same phase as a gate voltage and supplies it to the gate of the second switch. Further, the output circuit is provided with third and fourth switches which set the first and second nodes to the reference power supply voltage in an on state, respectively, and first and second control means which set the first and second switches to an off state in an effective state, respectively, set the second switch to an off state and the second node to the reference power supply voltage when outputting the positive polarity voltage signal from the output terminal, and set the first switch to an off state and the first node to the reference power supply voltage when outputting the negative polarity voltage signal from the output terminal.

[0028] According to such a structure, when processing a positive polarity voltage signal higher than a reference power supply voltage and a negative polarity voltage signal lower than the reference power supply voltage, a transistor of a withstand voltage of about one-half of a voltage range from a minimum voltage of the negative polarity voltage signal to a maximum voltage of the positive polarity voltage signal can be used as each switch. Further, the first and second switches as output selection switches are controlled across polarity by the simple source follower circuits of the first and second follower circuits.

[0029] Therefore, according to the present application, an output circuit capable of selectively outputting one of a positive polarity voltage and a negative polarity voltage, a data driver including the output circuit, and a display device can be implemented in a simple structure and with a reduced area. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A circuit diagram showing an example of the structure of the output circuit 100.

[0031] Figure 2A A waveform chart showing a waveform of the voltage signal Vgl 1 generated by the follower circuit 50 following the positive polarity voltage signal Vp (Vl l).

[0032] Figure 2B A time chart showing a waveform of a voltage signal Vgl l generated by the follow-up circuit 50 following the positive voltage signal Vp (Vl l).

[0033] Figure 3 A circuit diagram showing a follow-up circuit 50A as an example of a specific circuit of the follow-up circuit 50.

[0034] Figure 4 A circuit diagram showing a follow-up circuit 60A as an example of a specific circuit of the follow-up circuit 60.

[0035] Figure 5 A circuit diagram showing a follow-up circuit 50B as another example of a specific circuit of the follow-up circuit 50.

[0036] Figure 6 A circuit diagram showing a follow-up circuit 60B as another example of a specific circuit of the follow-up circuit 60.

[0037] Figure 7A A waveform chart showing a waveform of a voltage signal Vgl l generated by the follow-up circuit 50B following the positive voltage signal Vp (Vl l).

[0038] Figure 7B A time chart showing a waveform of a voltage signal Vgl l generated by the follow-up circuit 60B following the negative voltage signal Vn (V21).

[0039] Figure 8 A circuit diagram showing a follow-up circuit 50C as still another example of a specific circuit of the follow-up circuit 50.

[0040] Figure 9 A time chart showing an example of internal operation of the output circuit 100.

[0041] Figure 10 A circuit diagram showing a structure of an output circuit 200 as another example of the output circuit of the present application.

[0042] Figure 11 A block diagram showing a structure of a display device 400 having a data driver 73 including the output circuit of the present application.

[0043] Figure 12 A block diagram showing an internal structure of the data driver 73.

[0044] [Explanation of symbols]

[0045] 10A: positive voltage signal supply circuit

[0046] 11, 21: output selection switch

[0047] 12, 13, 22, 23: switch

[0048] 20A: negative voltage signal supply circuit

[0049] 50, 60: follower circuit

[0050] 73: data driver

[0051] 100, 200: output circuit

[0052] 400: display device DETAILED DESCRIPTION

[0053] [Example 1]

[0054] Figure 1 A circuit diagram showing the structure of the output circuit 100 as an example of the output circuit of the present application.

[0055] First, the power supply voltages supplied to the output circuit 100 will be described.

[0056] The power supply voltages supplied to the output circuit 100 are composed of five power supply voltages, that is, a reference power supply voltage VGND, a high-order power supply voltage VDD2H, a low-order power supply voltage VDD1H, a high-order power supply voltage VDD2L, and a low-order power supply voltage VDD1L. The high-order power supply voltage VDD2H is composed of two positive power supply voltages on the high potential side with respect to the reference power supply voltage VGND, and the high-order power supply voltage VDD2L is composed of two negative power supply voltages on the low potential side with respect to the reference power supply voltage VGND. The potential relationship of these five power supply voltages is (VDD2H > VDD1H > VGND > VDD1L > VDD2L). In addition, the potential difference between the low-order power supply voltages VDD1H and VDD1L of the positive and negative sides is set to a value smaller than each of the potential differences between the high-order power supply voltages VDD2H and VDD2L and the reference power supply voltage VGND. Further, the power supply structure formed by the five power supply voltages is used in each of the following embodiments.

[0057] The output circuit 100 receives a signal having a potential of the reference power supply voltage VGND or higher as a positive polarity voltage signal, and receives a signal having a potential of the reference power supply voltage VGND or lower as a negative polarity voltage signal, and switches these positive polarity voltage signal and negative polarity voltage signal at a prescribed timing to output to a capacitive load (for example, a data line of a liquid crystal display device), thereby driving the capacitive load (performing polarity inversion driving).

[0058] The output circuit 100 includes a positive voltage signal supply circuit 10A, an output selection switch 11, a switch 12, a switch 13, a negative voltage signal supply circuit 20A, an output selection switch 21, a switch 22, a switch 23, a follower circuit 50 and a follower circuit 60, and a control section 101. Further, the output circuit 100 includes a node Nsll, a node Ns21, and an output terminal DLl connected to one capacitive load.

[0059] The positive voltage signal supply circuit 10A includes an amplification circuit 10 and a switch 14. The amplification circuit 10 receives an input voltage signal Vpi having a potential in a range of a reference power supply voltage VGND to a positive high power supply voltage VDD2H, and outputs a positive voltage signal Vp amplified thereby. The switch 14 controls supply and cut-off of the positive voltage signal Vp to the node Nsll. Further, in order to pass the positive voltage signal Vp of a wide voltage range, the switch 14 is constituted by a complementary switch of a double conduction type including a P-channel and an N-channel. The both ends of the switch 14 are terminals of the same positive voltage range, and the switch 14 can be simply used as a complementary switch. In addition, the amplification circuit 10 can be configured to include a function of the switch 14 in the inside, and in this case, an output node of the amplification circuit 10 becomes the node Nsll. In addition, as the amplification circuit 10, it is not limited to a voltage follower which amplifies and outputs the same potential positive voltage signal Vp as the input voltage signal Vpi, but can be an amplification circuit which amplifies and outputs a positive voltage signal Vp having a different potential with respect to the potential of the input voltage signal Vpi. In this specification, a voltage signal supplied from the positive voltage signal supply circuit 10A to the node Nsll is described as Vll or Vp.

[0060] With the above-described configuration, the positive voltage signal supply circuit 10A generates the positive voltage signal Vp having a potential in a range of the reference power supply voltage VGND to the positive high power supply voltage VDD2H, and supplies it to the node Nsll or cuts off the supply.

[0061] The negative voltage signal supply circuit 20A includes an amplification circuit 20 and a switch 24. The amplification circuit 20 receives an input voltage signal Vni having a potential within a range of the negative high-level power supply voltage VDD2L to the reference power supply voltage VGND, and outputs a negative voltage signal Vn amplified thereby. The switch 24 controls supply and cutoff of the negative voltage signal Vn to the node Ns21. Further, in order to pass the negative voltage signal Vn of a wide voltage range, the switch 24 is configured of a complementary switch of a double conduction type including a P-channel and an N-channel. The both ends of the switch 24 are terminals of the same negative voltage range, and the switch 24 can be simply used as a complementary switch. In addition, the amplification circuit 20 can be configured to include a function of the switch 24 therein, and in this case, an output node of the amplification circuit 20 becomes the node Ns21. In addition, as the amplification circuit 20, it is not limited to a voltage follower which amplifies and outputs the negative voltage signal Vn of the same potential as the input voltage signal Vni, but can be an amplification circuit which amplifies and outputs the negative voltage signal Vn having a different potential with respect to the potential of the input voltage signal Vni. In this specification, a voltage signal supplied from the negative voltage signal supply circuit 20A to the node Ns21 is described as V21 or Vn.

[0062] With the above-described configuration, the negative voltage signal supply circuit 20A generates the negative voltage signal Vn having a potential within a range of the negative high-level power supply voltage VDD2L to the reference power supply voltage VGND, and supplies the same to the node Ns21 or performs cutoff of the supply.

[0063] The output selection switch 11 is configured of a P-channel transistor, and a first terminal (hereinafter referred to as a source) thereof is connected to the node Ns11, and a second terminal (hereinafter referred to as a drain) thereof is connected to the output terminal DL1. Further, a follow-up circuit 50 is connected to a control terminal (hereinafter referred to as a gate Ng11) of the output selection switch 11. With this configuration, the output selection switch 11 outputs the voltage signal V11 of the node Ns11 to the output terminal DL1 in an on state.

[0064] The output selection switch 21 is configured of an N-channel transistor, and a source thereof is connected to the node Ns21, and a drain thereof is connected to the output terminal DL1. Further, a follow-up circuit 60 is connected to a gate Ng21 which is a control terminal of the output selection switch 21. With this configuration, the output selection switch 21 outputs the voltage signal V21 of the node Ns21 to the output terminal DL1 in an on state.

[0065] The switch 12 is composed of, for example, an N-channel transistor connected between the node Nsll and a reference power supply terminal supplied with a reference power supply voltage VGND. The switch 12 is controlled to be in an on state or an off state in accordance with a control signal S12 supplied from the control section 101. The switch 12 applies the reference power supply voltage VGND to the node Nsll when in the on state.

[0066] The switch 13 is composed of, for example, a P-channel transistor connected between the gate Ngll of the output selection switch 11 and the reference power supply terminal. The switch 13 is controlled to be in an on state or an off state in accordance with a control signal S13 supplied from the control section 101. The switch 13 controls the output selection switch 11 to be in the off state when controlled to be in the on state together with the switch 12. Further, the switch 13 can be replaced by a switch connected between the gate Ngll of the output selection switch 11 and the node Nsll.

[0067] The switch 22 is composed of, for example, a P-channel transistor connected between the node Ns21 and the reference power supply terminal. The switch 22 is controlled to be in an on state or an off state in accordance with a control signal S22 supplied from the control section 101. The switch 22 applies the reference power supply voltage VGND to the node Ns21 when in the on state.

[0068] The switch 23 is composed of, for example, an N-channel transistor connected between the gate Ng21 of the output selection switch (N-channel transistor) 21 and the reference power supply terminal. The switch 23 is controlled to be in an on state or an off state in accordance with a control signal S23 supplied from the control section 101. The switch 23 controls the output selection switch 21 to be in the off state when controlled to be in the on state together with the switch 22. Further, the switch 23 can be replaced by a switch connected between the gate Ng21 of the output selection switch 21 and the node Ns21.

[0069] Thus, in the operation of outputting the positive or negative voltage signal (Vp or Vn) to the output terminal DLl, the switch 12, the switch 13, the switch 22, and the switch 23 control at least one of the output selection switch 11 and the output selection switch 21 to be in the off state when the other is controlled to be in the on state.

[0070] The follower circuit 50 is connected between the node Nsll connected to the source of the output selection switch 11 and the gate Ngll.

[0071] The follower circuit 50 receives at least a positive power supply voltage higher than the reference power supply voltage VGND and a negative power supply voltage lower than the reference power supply voltage VGND, and includes an N-channel transistor 51 and a load element 52 connected in series between these two different power supply voltages. A voltage signal Vll of a node Nsl l is supplied to a gate of the N-channel transistor 51, and the positive power supply voltage is applied to a drain. The negative power supply voltage is applied to one end of the load element 52, and the other end is connected to a source of the N-channel transistor 51.

[0072] The follower circuit 50 performs a source follower operation, that is, follows the voltage signal Vll of the node Nsl l from the connection point of the source of the N-channel transistor 51 and the load element 52 and outputs a voltage signal in phase on the low voltage side compared to the voltage signal Vll. The follower circuit 50 supplies the output voltage signal as a gate voltage Vgl l to the gate Ngll of the output selection switch 11.

[0073] With this configuration, the follower circuit 50 controls the gate-source voltage difference (absolute value) of the output selection switch 11 to be a voltage difference higher than the threshold voltage (absolute value) that maintains the on state within the element withstand voltage VDD2T, based on the voltage signal Vll of the node Nsl l. Therefore, according to the operation of the follower circuit 50, the output selection switch 11 can reliably output a positive voltage signal Vll having a potential in the range of the reference power supply voltage VGND to the positive high power supply voltage VDD2H to the output terminal DLl.

[0074] The follower circuit 60 is connected between a node Ns21 connected to a source of the output selection switch 21 and a gate Ng21.

[0075] The follower circuit 60 receives at least a positive power supply voltage higher than the reference power supply voltage VGND and a negative power supply voltage lower than the reference power supply voltage VGND, and includes a P-channel transistor 61 and a load element 62 connected in series between these two different power supply voltages. A voltage signal V21 of a node Ns21 is supplied to a gate of the P-channel transistor 61, and the negative power supply voltage is applied to a drain. The positive power supply voltage is applied to one end of the load element 62, and the other end is connected to a source of the P-channel transistor 61.

[0076] The follower circuit 60 performs a source follower operation, that is, follows the voltage signal V21 of the node Ns21 from the connection point of the source of the P-channel transistor 61 and the load element 62 and outputs a voltage signal in phase on the high voltage side compared to the voltage signal V21. The follower circuit 60 supplies the output voltage signal as a gate voltage Vg21 to the gate Ng21 of the output selection switch 21.

[0077] With such a configuration, the follower circuit 60 controls the gate-source voltage difference of the output selection switch 21 to a voltage difference higher than the threshold voltage (absolute value) that maintains the on state within the element withstand voltage VDD2T, based on the voltage signal V21 of the node Ns21. Therefore, according to the operation of the follower circuit 60, the output selection switch 21 can reliably output the voltage signal V21 of the negative polarity having a potential within the range of the negative high-level power supply voltage VDD2L to the reference power supply voltage VGND to the output terminal DL1.

[0078] Further, the load elements 52 and 62 of the follower circuit 50 and the follower circuit 60 can be configured by a constant current source, a resistive element, or a circuit that controls a constant current or a resistance value.

[0079] The on and off of each of the switches 12 to 14 and the switches 22 to 24 are controlled by the control signals S12 to S14 and the control signals S22 to S24 output from the control section 101, respectively.

[0080] Next, the element withstand voltage VDD2T of the output circuit 100 shown in FIG. 1 will be described. Figure 1

[0081] Further, each element of the output circuit 100 is configured by a low-voltage element of the element withstand voltage VDD2T that is smaller than the output voltage range (VDD2H to VDD2L) of the output terminal DL1, and the minimum withstand voltage is about one-half of the output voltage range, that is, a degree larger than each potential difference between the high-level power supply voltage VDD2H and the high-level power supply voltage VDD2L and the reference power supply voltage VGND. Then, the potential difference between the low-level power supply voltages VDD1H and VDD1L is set to be smaller than the low voltage of the element withstand voltage VDD2T.

[0082] Specifically, in the section between the positive voltage signal supply circuit 10A and the node Ns11, the voltage is maintained within the range of the reference power supply voltage VGND to the positive high-level power supply voltage VDD2H, and therefore the amplification circuit 10 and the switch 14 can be configured by a transistor of the element withstand voltage VDD2T. Similarly, in the section between the negative voltage signal supply circuit 20A and the node Ns21, the voltage is maintained within the range of the reference power supply voltage VGND to the negative high-level power supply voltage VDD2L, and therefore the amplification circuit 20 and the switch 24 can be configured by a transistor of the element withstand voltage VDD2T.

[0083] ​In the case where the positive voltage signal Vp is output to the output terminal DL1, the output selection switch 11 is controlled by the follower circuit 50 to be in the on state. Thus, each voltage of the source and drain of the output selection switch 11 becomes within the positive voltage range of VGND to VDD2H. Further, the gate-source voltage difference of the output selection switch 11 is controlled by the follower circuit 50 to be within the element withstand voltage VDD2T. On the other hand, in the case where the negative voltage signal Vn is output to the output terminal DL1, the output selection switch 11 is controlled to be in the off state by the fact that the reference power supply voltage VGND is supplied to the gate and source of the output selection switch 11 due to the switches 12 and 13. Thus, even if the output terminal DL1 to which the drain of the output selection switch 11 is connected is the negative voltage signal Vn, each voltage between the terminals of the source, drain, and gate of the output selection switch 11 is controlled to be within the element withstand voltage VDD2T. Furthermore, in the case where the output terminal DL1 is switched from the positive voltage signal Vp to the negative voltage signal Vn, for example, the switch 12 is controlled to be in the off state while the switch 13 is controlled to be in the on state, and then the follower circuit 50 is operated, whereby the output terminal DL1 is temporarily driven from the positive voltage to the reference power supply voltage VGND. Thereafter, the output operation is switched to the negative voltage signal Vn. Thus, each voltage difference between the terminals of the output selection switch 11 can be kept within the low element withstand voltage VDD2T.

[0084] In the case where the positive voltage signal Vp is output to the output terminal DL1, the output selection switch 11 is controlled by the follower circuit 50 to be in the on state. Thus, each voltage of the source and drain of the output selection switch 11 becomes within the positive voltage range of VGND to VDD2H. Further, the gate-source voltage difference of the output selection switch 11 is controlled by the follower circuit 50 to be within the element withstand voltage VDD2T. On the other hand, in the case where the negative voltage signal Vn is output to the output terminal DL1, the output selection switch 11 is controlled to be in the off state by the fact that the reference power supply voltage VGND is supplied to the gate and source of the output selection switch 11 due to the switches 12 and 13. Thus, even if the output terminal DL1 to which the drain of the output selection switch 11 is connected is the negative voltage signal Vn, each voltage between the terminals of the source, drain, and gate of the output selection switch 11 is controlled to be within the element withstand voltage VDD2T. Furthermore, in the case where the output terminal DL1 is switched from the positive voltage signal Vp to the negative voltage signal Vn, for example, the switch 12 is controlled to be in the off state while the switch 13 is controlled to be in the on state, and then the follower circuit 50 is operated, whereby the output terminal DL1 is temporarily driven from the positive voltage to the reference power supply voltage VGND. Thereafter, the output operation is switched to the negative voltage signal Vn. Thus, each voltage difference between the terminals of the output selection switch 11 can be kept within the low element withstand voltage VDD2T.

[0085] As described above, Figure 1The output circuit 100 shown can be constructed using transistors with a component withstand voltage of VDD2T, including the output selection switch 11 and the output selection switch 21.

[0086] Next, refer to Figure 2A and Figure 2B The functions of follower circuit 50 and follower circuit 60 will be explained.

[0087] Figure 2A The waveforms of the voltage signal V11 supplied to the source of the output selection switch 11 and the gate voltage Vg11 of the output selection switch 11 controlled by the follower circuit 50 are shown when the positive voltage signal Vp is continuously output.

[0088] exist Figure 2A In one example shown, the voltage signal V11 has the following waveform: at time t1, it changes from the positive voltage of the biased reference power supply voltage VGND to the positive voltage of the biased high-level power supply voltage VDD2H, and at time t2, it changes again to the positive voltage of the biased reference power supply voltage VGND.

[0089] The gate voltage Vg11 of the output selection switch 11 follows the voltage changes within the voltage range between the reference power supply voltage VGND and the positive high-level power supply voltage VDD2H relative to the voltage signal V11. Specifically, when the voltage signal V11 is at the positive high-level power supply voltage VDD2H side, the gate voltage Vg11 is controlled within the positive voltage range below the positive low-level power supply voltage VDD1H. When the voltage signal V11 is at the reference power supply voltage VGND side, the gate voltage Vg11 is controlled within the negative voltage range above the negative low-level power supply voltage VDD1L. Therefore, the voltage difference between the voltage signal V11 and the gate voltage Vg11 is above the threshold voltage (absolute value) of the output selection switch 11 and is controlled within the device withstand voltage VDD2T.

[0090] Figure 2B The waveforms of the voltage signal V21 supplied to the source of the output selection switch 21 and the gate voltage Vg21 of the output selection switch 21 controlled by the follower circuit 60 are shown when the negative voltage signal Vn is continuously output during multiple periods.

[0091] exist Figure 2B In one example shown, the voltage signal V21 has the following waveform: at time t1, it changes from the negative terminal voltage of the biased reference power supply voltage VGND to the negative terminal voltage of the biased high-level power supply voltage VDD2L, and at time t2, it changes again to the negative terminal voltage of the biased reference power supply voltage VGND.

[0092] The gate voltage Vg21 of the output selection switch 21 varies in phase with the voltage in the voltage range between the positive low-level power supply voltage VDD1H and the negative low-level power supply voltage VDD1L with respect to the voltage of the voltage signal V21 with reference to the reference power supply voltage VGND and the negative high-level power supply voltage VDD2L. Specifically, when the voltage signal V21 is on the negative high-level power supply voltage VDD2L side, the gate voltage Vg21 is controlled to be in the negative voltage range above the negative low-level power supply voltage VDD1L, and when the voltage signal V21 is on the reference power supply voltage VGND side, the gate voltage Vg21 is controlled to be in the positive voltage range below the positive low-level power supply voltage VDD1H. Thus, the voltage difference between the voltage signal V21 and the gate voltage Vg21 is above the threshold voltage of the output selection switch 21, and is controlled to be within the element withstand voltage VDD2T.

[0093] Further, in the following description, the phrase that the waveforms of signals are in phase with each other is used in the sense that the change of one voltage signal is accompanied by the change of the other voltage signal. That is, even if there is a temporary delay in the change of the other voltage signal with respect to the change of one voltage signal, or a slight difference in the amount of voltage change, it is regarded as being in phase.

[0094] Further, in the following description, the phrase that the waveforms of signals are in phase with each other is used in the sense that the change of one voltage signal is accompanied by the change of the other voltage signal. That is, even if there is a temporary delay in the change of the other voltage signal with respect to the change of one voltage signal, or a slight difference in the amount of voltage change, it is regarded as being in phase. Figure 2A Similarly, the gate voltage Vg21 is controlled in the voltage range between the power supply voltage VDD1L and the power supply voltage VDD1H, but as long as it is a follow-up action in phase with the voltage signal V21 and is a structure that satisfies within the element withstand voltage VDD2T, it can also be controlled in the voltage range between the power supply voltage VGND and the power supply voltage VDD1H, and the power supply voltage VGND and the power supply voltage VDD2H.

[0095] Figure 2B Similarly, the gate voltage Vg21 is controlled in the voltage range between the power supply voltage VDD1L and the power supply voltage VDD1H, but as long as it is a follow-up action in phase with the voltage signal V21 and is a structure that satisfies within the element withstand voltage VDD2T, it can also be controlled in the voltage range between the power supply voltage VGND and the power supply voltage VDD1H, and the power supply voltage VGND and the power supply voltage VDD2H.

[0096] As described in detail above, the follow-up circuit 50 and the follow-up circuit 60 respectively control the gate voltage of the output selection switch 11 and the output selection switch 21 by the source follow-up action of following up the voltage of the source of the output selection switch 11 and the output selection switch 21. That is, in the output circuit 100, the control of the output selection switches (11, 21) across the voltage polarity is performed by a simple circuit such as a source follow-up circuit (50, 60). Furthermore, the follow-up circuit 50 and the follow-up circuit 60 are constituted by elements within the low element withstand voltage VDD2T, Figure 1 ​The entire output circuit 100 can also be composed of elements within the element withstand voltage VDD2T, and thus the area of the circuit can be reduced (cost reduction).

[0097] In the output circuit 100, the output selection switch 11 as the first switch receives the positive voltage signal V11 higher than the reference power supply voltage VGND via the node Ns11 and outputs the voltage signal V11 from the output terminal DL1 in the on state. Further, the output selection switch 21 as the second switch receives the negative voltage signal V21 lower than the reference power supply voltage VGND via the node Ns21 and outputs the voltage signal V21 from the output terminal DL1 in the on state. At this time, the follower circuit 50 and the follower circuit 60 control the output selection switch 11 and the output selection switch 21 in the following manner. That is, the follower circuit 50 follows the voltage signal of the node Ns11 by source follower action and generates a voltage signal in phase as the gate voltage Vgl 1 and supplies it to the gate Ng11 of the output selection switch 11. The follower circuit 60 follows the voltage signal of the node Ns21 by source follower action and generates a voltage signal in phase as the gate voltage Vg21 and supplies it to the gate Ng21 of the output selection switch 21. Further, the output circuit 100 is provided with the switch 12 as the third switch that sets the node Ns11 to the reference power supply voltage VGND in the on state, the switch 22 as the fourth switch that sets the node Ns21 to the reference power supply voltage VGND in the on state, the switch 13 as the first control means that sets the output selection switch 11 to the off state in the on state, and the switch 23 as the second control means that sets the output selection switch 21 to the off state in the on state. Thus, when the positive voltage signal V11 is output from the output terminal DL1, the output selection switch 21 is set to off and the node Ns21 is set to the reference power supply voltage, and when the negative voltage signal V21 is output from the output terminal DL1, the output selection switch 11 is set to off and the node Ns11 is set to the reference power supply voltage.

[0098] According to such a configuration, when processing a positive polarity voltage signal (Vp, V11) higher than the reference power supply voltage VGND and a negative polarity voltage signal (Vn, V21) lower than the reference power supply voltage VGND, a transistor having a withstand voltage of about half of a voltage range from a minimum voltage (VDD2L) of the negative polarity voltage signal to a maximum voltage (VDD2H) of the positive polarity voltage signal can be used as each switch (11, 12, 14, 51). Further, a gate voltage of the output selection switch 11 and the output selection switch 21 as output selection switches is controlled across polarity by the simple source follower circuits of the follower circuit 50 and the follower circuit 60.

[0099] Accordingly, according to Figure 1 the output circuit 100 illustrated in FIG. 1, an output circuit capable of selectively outputting one of a positive polarity voltage and a negative polarity voltage can be implemented with a simple configuration and a reduced area.

[0100] Further, Figure 1 The output circuit 100 and each of the following embodiments can also be constituted by a P-channel and N-channel Metal Oxide Semiconductor (MOS) transistor circuit formed on a semiconductor substrate such as a silicon substrate, or a P-channel and N-channel thin film transistor circuit formed on an insulating substrate such as glass or plastic. In addition, in the case of being constituted by a MOS transistor, the back gate can also be set in a manner such that a voltage difference from each of the terminals of the gate, the drain, and the source is within the low element withstand voltage VDD2T.

[0101] [Embodiment 2]

[0102] Figure 3 and Figure 4 is a circuit diagram of the follower circuit 50A and the follower circuit 60A as an example of a specific circuit of the follower circuit 50 and the follower circuit 60 of the output circuit 100. Further, in the follower circuit 50A and the follower circuit 60A, the same operations as those of the follower circuit 50 and the follower circuit 60 are respectively performed on the N-channel transistor 51 and the current source 52. Figure 1 Figure 2A and Figure 2B

[0103] Figure 3 The follower circuit 50A illustrated in FIG. 5A includes the N-channel transistor 51 and the current source 52 connected in series between the positive low-level power supply voltage VDD1H and the negative low-level power supply voltage VDD1L.

[0104] ​​The positive low power supply voltage VDD1H is applied to the drain of the N-channel transistor 51, and the voltage signal V11 is applied to the gate. The negative low power supply voltage VDD1L is applied to one terminal of the current source 52, and the other terminal is connected to the source of the N-channel transistor 51.

[0105] The follower circuit 50A performs a source follower operation, that is, follows the voltage signal V11 of the node Ns11 from the connection point of the source of the N-channel transistor 51 and the current source 52 and outputs a voltage signal in phase on the low voltage side compared to the voltage signal V11. The follower circuit 50A supplies the output voltage signal as the gate voltage Vg11 to the gate Ng11 of the output selection switch 11. Further, the voltage difference between the voltage signal V11 and the gate voltage Vg11 is set by the current value of the current source 52 and is controlled to be a voltage difference slightly higher than the threshold voltage of the N-channel transistor 51. Thus, both the N-channel transistor 51 and the current source 52 can operate within the element withstand voltage VDD2T.

[0106] Figure 4 The illustrated follower circuit 60A includes the current source 62 and the P-channel transistor 61 connected in series between the positive low power supply voltage VDD1H and the negative low power supply voltage VDD1L.

[0107] The negative low power supply voltage VDD1L is applied to the drain of the P-channel transistor 61, and the voltage signal V21 is applied to the gate. The positive low power supply voltage VDD1H is applied to one terminal of the current source 62, and the other terminal is connected to the source of the P-channel transistor 61.

[0108] The follower circuit 60A performs a source follower operation, that is, follows the voltage signal V21 of the node Ns21 from the connection point of the source of the P-channel transistor 61 and the current source 62 and outputs a voltage signal in phase on the high voltage side compared to the voltage signal V21. The follower circuit 60A supplies the output voltage signal as the gate voltage Vg21 to the gate Ng21 of the output selection switch 21. Further, the voltage difference between the voltage signal V21 and the gate voltage Vg21 is set by the current value of the current source 62 and is controlled to be a voltage difference slightly higher than the threshold voltage (absolute value) of the P-channel transistor 61. Thus, both the P-channel transistor 61 and the current source 62 can operate within the element withstand voltage VDD2T.

[0109] [Embodiment 3]

[0110] Figure 5 and Figure 6 to indicate as Figure 1Another example of the specific circuit of the follower circuit 50 and the follower circuit 60 in the output circuit 100 shown in FIG. 1 is a circuit diagram of a follower circuit 50B and a follower circuit 60B. Also in the follower circuit 50B and the follower circuit 60B, the same operations as those of the follower circuit 50 and the follower circuit 60 are respectively performed Figure 2A and Figure 2B .

[0111] Figure 5 The follower circuit 50B shown in FIG. 2 is composed of a sub-follower circuit 58B and a sub-follower circuit 59B.

[0112] The sub-follower circuit 58B includes an N-channel transistor 51, a current source 52, and a clamping element 55 connected in series between a positive high-level power supply voltage VDD2H and a reference power supply voltage VGND.

[0113] The positive high-level power supply voltage VDD2H is applied to the drain of the N-channel transistor 51 via the clamping element 55, and a voltage signal V11 is applied to the gate. The reference power supply voltage VGND is applied to one end of the current source 52, and the other end is connected to the source of the N-channel transistor 51.

[0114] The sub-follower circuit 58B performs a source follower operation, that is, follows the voltage signal V11 from the connection point of the source of the N-channel transistor 51 and the current source 52 to a node Ns11 and outputs a voltage signal in phase on the low voltage side compared to the voltage signal V11 as a voltage signal Vg53.

[0115] The sub-follower circuit 59B includes an N-channel transistor 53 and a current source 54 connected in series between a positive low-level power supply voltage VDD1H and a negative low-level power supply voltage VDD1L.

[0116] The positive low-level power supply voltage VDD1H is applied to the drain of the N-channel transistor 53, and the voltage signal Vg53 output from the sub-follower circuit 58B is applied to the gate. The negative low-level power supply voltage VDD1L is applied to one end of the current source 54, and the other end is connected to the source of the N-channel transistor 53.

[0117] The sub-follower circuit 59B performs a source follower operation, that is, follows the voltage signal Vg53 from the connection point of the source of the N-channel transistor 53 and the current source 54 and outputs a voltage signal in phase on the low voltage side compared to the voltage signal Vg53 as a gate voltage Vg11. The sub-follower circuit 59B supplies the output gate voltage Vg11 to the gate Ng11 of the output selection switch 11.

[0118] That is, the secondary follower circuit 58B outputs a voltage signal Vg53 by controlling the source follower operation of the N-channel transistor 51 that follows the voltage signal V11, and the secondary follower circuit 59B outputs a gate voltage Vg11 by controlling the source follower operation of the N-channel transistor 53 that follows the voltage signal Vg53. Therefore, the gate voltage Vg11 follows the voltage signal V11 and is controlled to be a low-voltage-side in-phase signal relative to the voltage signal V11. Furthermore, the voltage difference between the voltage signal V11 and the voltage signal Vg53 is set by the current value of the current source 52 and is controlled to be slightly higher than the threshold voltage of the N-channel transistor 51. Additionally, the voltage difference between the voltage signal Vg53 and the gate voltage Vg11 is set by the current value of the current source 54 and is controlled to be slightly higher than the threshold voltage of the N-channel transistor 53.

[0119] in addition, Figure 5 The sub-follower circuit 58B shown includes a clamping element 55. This clamping element 55 clamps the upper limit of the voltage signal Vg53 so that the gate-source voltage difference of the N-channel transistor 53 in the sub-follower circuit 59B is less than the device withstand voltage VDD2T. The clamping element 55 is constructed from a structure consisting of N-stage (N≧1) diodes connected in series or parallel, or from a resistive element, and is connected between the positive high-level power supply voltage VDD2H and the drain of the N-channel transistor 51. Therefore, both the sub-follower circuits 58B and 59B can operate within the device withstand voltage VDD2T. Furthermore, if the sub-follower circuit 59B is configured to satisfy the device withstand voltage VDD2T, the supplied power supply voltage can be set to VGND and VDD1L or VGND and VDD2L instead of VDD1H and VDD1L.

[0120] In addition, Figure 5 In one example shown, the follower circuit 50B is composed of two secondary follower circuits 58B and 59B, but it can also be constructed by connecting three or more secondary follower circuits. Thus, by constructing the follower circuit 50B with multiple stages of secondary follower circuits, and... Figure 3 Compared to the follower circuit 50A, this increases the gate-source voltage difference of the output selection switch 11. As a result, the on-resistance of the output selection switch 11 decreases, and the driving capability of the positive voltage signal Vp is improved.

[0121] Figure 6 The follower circuit 60B shown is composed of a secondary follower circuit 68B and a secondary follower circuit 69B.

[0122] The secondary follower circuit 68B includes a current source 52, a P-channel transistor 61, and a clamping element 65, which are cascaded between the reference power supply voltage VGND and the negative high-level power supply voltage VDD2L.

[0123] The negative high power supply voltage VDD2L is applied to the drain of the P-channel transistor 61 via the clamping element 65, and the voltage signal V21 is applied to the gate. The reference power supply voltage VGND is applied to one end of the current source 52, and the other end thereof is connected to the source of the P-channel transistor 61.

[0124] The sub follower circuit 68B performs a source follower operation of following the voltage signal V21 of the node Ns21 from the connection point of the source of the P-channel transistor 61 and the current source 52 and outputting a voltage signal on the high voltage side as compared with the voltage signal V21 as the voltage signal Vg63.

[0125] The sub follower circuit 69B includes the P-channel transistor 63 and the current source 64 connected in series between the negative low power supply voltage VDD1Land the positive low power supply voltage VDD1H. The sub follower circuit 69B performs a source follower operation of following the voltage signal Vg63 from the connection point of the source of the P-channel transistor 63 and the current source 64 and outputting a voltage signal on the high voltage side in phase as compared with the voltage signal Vg63 as the gate voltage Vg21. The sub follower circuit 69B supplies the output gate voltage Vg21 to the gate Ng21 of the output selection switch 21.

[0126] That is, the sub follower circuit 68B outputs the voltage signal Vg63 by the source follower operation of the P-channel transistor 61 following the voltage signal V21, and the sub follower circuit 69B outputs the gate voltage Vg21 by the source follower operation of the P-channel transistor 63 following the voltage signal Vg63. Thus, the gate voltage Vg21 is controlled to be a same phase signal following the high voltage side of the voltage signal V21. Further, the voltage difference between the voltage signal V21 and the voltage signal Vg63 is set by the current value of the current source 62 and is controlled to be a voltage difference slightly higher than the threshold voltage (absolute value) of the P-channel transistor 61. In addition, the voltage difference between the voltage signal Vg63 and the gate voltage Vg21 is set by the current value of the current source 64 and is controlled to be a voltage difference slightly higher than the threshold voltage (absolute value) of the P-channel transistor 63.

[0127] Further, Figure 6In the sub-follower circuit 68B, a clamping element 65 is provided, which clamps the lower limit value of the voltage signal Vg63 so that the gate-source voltage difference of the P-channel transistor 63 of the sub-follower circuit 69B does not exceed the element withstand voltage VDD2T. The clamping element 65 is composed of a structure of transistors connected in series or in parallel in a diode connection of N stages (N > 1) or a resistance element, and is connected between the negative high potential power supply voltage VDD2Land the drain of the P-channel transistor 61. Thus, both the sub-follower circuit 68B and the sub-follower circuit 69B can operate within the element withstand voltage VDD2T. Further, the sub-follower circuit 69B can be configured so as to satisfy the element withstand voltage VDD2T, and the supply power voltage can be set to VGND and VDD1H or VGND and VDD2H instead of VDD1Hand VDD1L.

[0128] Further, in Figure 6 In the example shown in FIG. 6, the follower circuit 60B is composed of two sub-follower circuits 68B and 69B, but can be composed of three or more sub-follower circuits. In this case, the follower circuit 60B is composed of a multistage sub-follower circuit, and the gate-source voltage difference of the output selection switch 21 is larger than that of the follower circuit 60A of FIG. 5. Figure 4 As a result, the on-resistance of the output selection switch 21 decreases, and the driving ability of the negative voltage signal Vn improves.

[0129] Next, the operation of the follower circuit 50B and the follower circuit 60B will be described with reference to the signal waveforms shown in FIG. 7. Figure 7A Figure 7B Figure 5 Figure 6 The follower circuit 50B and the follower circuit 60B are composed of a multistage sub-follower circuit, and the gate-source voltage difference of the output selection switch 21 is larger than that of the follower circuit 50A of FIG. 4.

[0130] Figure 7A The signal waveforms of the voltage signal V11, the voltage signal Vg53, and the gate voltage Vg11 in the follower circuit 50B shown in FIG. 7 are shown in FIG. 8. The voltage signal V11 and the gate voltage Vg11 are the same as those shown in FIG. 7. The voltage signal Vg53 is obtained by converting the voltage signal V11 into a voltage signal in the voltage range between the reference power supply voltage VGND and the voltage Vcpl by the sub-follower circuit 58B of the follower circuit 50B. The voltage Vcpl is set by the clamping element 55 of the follower circuit 50B. That is, the follower circuit 50B shown in FIG. 7 converts the voltage signal V11 into a low voltage side voltage signal (the gate voltage Vg11) in two stages. Figure 5 Figure 2A Figure 5 Further, the voltage signal V11 and the gate voltage Vg11 are shown in the same waveforms for the sake of simplicity, but the follower circuit 50B is composed of a multistage sub-follower circuit.

[0131] Further, the voltage signal V11 and the gate voltage Vg11 are shown in the same waveforms for the sake of simplicity, but the follower circuit 50B is composed of a multistage sub-follower circuit. Figure 2A Figure 7A Further, the voltage signal V11 and the gate voltage Vg11 are shown in the same waveforms for the sake of simplicity, but the follower circuit 50B is composed of a multistage sub-follower circuit.​​​​​​Figure 5 The structure of the follower circuit 50B can further enlarge the voltage difference between the voltage signal Vll and the gate voltage Vgl l.

[0132] Figure 7B The signal waveforms of the voltage signal V21, the voltage signal Vg63, and the gate voltage Vg21 in the follower circuit 60B are shown. Figure 6 The voltage signal V21 and the gate voltage Vg21 are the same as those in the follower circuit 50B. The voltage signal Vg63 is a voltage signal obtained by converting the voltage signal V21 into a voltage range between the reference power supply voltage VGND and a voltage Vcp2 by the sub-follower circuit 68B of the follower circuit 60B. The voltage Vcp2 is set by the clamping element 65 of the follower circuit 60B. That is, the voltage signal Vg63 is a voltage signal obtained by converting the voltage signal V21 into a voltage range between the reference power supply voltage VGND and the voltage Vcp2. Figure 2B The follower circuit 60B of the output circuit 100 shown in FIG. 8 converts the voltage signal V21 into the voltage signal on the high voltage side (the gate voltage Vg21) in two stages. Figure 6

[0133] Further, in the follower circuit 60B, the voltage signal V21 and the gate voltage Vg21 are represented in the same waveforms for the sake of illustration of the action, but the follower circuit 60B is configured by a plurality of sub-follower circuits. Figure 2B The structure of the follower circuit 60B can further enlarge the voltage difference between the voltage signal V21 and the gate voltage Vg21. Figure 7B Figure 6 [Embodiment 4]

[0134] [Embodiment 4]

[0135] Figure 8 FIG. 10 is a circuit diagram of a follower circuit 50C which is an example of another specific circuit of the follower circuit 50 shown in FIG. 1. Further, in the follower circuit 50C, the same actions as those of the follower circuit 50B shown in FIG. 5 are performed. Figure 1 The structure of the follower circuit 50C can further enlarge the voltage difference between the voltage signal Vll and the gate voltage Vgl l. Figure 5 Figure 7A

[0136] Figure 8 The follower circuit 50C shown in FIG. 10 is configured by a sub-follower circuit 58C and a sub-follower circuit 59C.

[0137] The sub-follower circuit 58C is configured by replacing the clamping element 55 of the sub-follower circuit 58B shown in FIG. 7 by a current source 56 and adding a clamping element 57 between the source of the N-channel transistor 51 and the reference power supply voltage VGND. The sub-follower circuit 59C is the same structure as the sub-follower circuit 59B shown in FIG. 7. Figure 5 Figure 5

[0138] ​​​​​​The current value of the current source 56 of the sub-following circuit 58C is set to be equal to the current value of the current source 52. Thus, the voltage signal Vg53 also rapidly follows the change in the voltage signal V11. The clamping element 57 is configured by a structure of transistors connected in series or in parallel in an N-stage (N > 1) diode connection or a resistance element or the like. The clamping element 57 clamps the upper limit value of the output voltage signal Vg53 of the sub-following circuit 58C in such a manner that the gate-source voltage difference of the N-channel transistor 53 of the sub-following circuit 59C does not exceed the element withstand voltage VDD2T. Further, the operation of the following circuit 50C other than the above is the same as that of the following circuit 50B shown in FIG. 6. Thus, both the sub-following circuit 58C and the sub-following circuit 59C can operate within the element withstand voltage VDD2T. Figure 5 The sub-following circuit 58C and the sub-following circuit 59C can operate within the element withstand voltage VDD2T.

[0139] Further, in the following circuit 50C shown in FIG. 7, as in the following circuit 50B shown in FIG. 6, by being configured with a multi-stage sub-following circuit, the output selection switch 11 can be operated with a low on-resistance and the driving capability of the positive voltage signal Vp can be improved. Figure 8 Figure 5 Further, in the following circuit 50C shown in FIG. 7, as in the following circuit 50B shown in FIG. 6, by being configured with a multi-stage sub-following circuit, the output selection switch 11 can be operated with a low on-resistance and the driving capability of the positive voltage signal Vp can be improved.

[0140] Further, in the following circuit 60 shown in FIG. 8, the same changes as those of the following circuit 50 shown in FIG. 6 can be applied to the following circuit 60. Figure 1 Figures 5 to 8 Further, in the following circuit 60 shown in FIG. 8, the same changes as those of the following circuit 50 shown in FIG. 6 can be applied to the following circuit 60.

[0141] [Embodiment 5]

[0142] Figure 9 In order to show the case where the output circuit 100 performs the so-called polarity inversion driving in which the positive voltage signal Vp and the negative voltage signal Vn are periodically and alternately switched, FIG. 10 shows an example of the time chart of the control signals S12 to S14 and the control signals S22 to S24 generated by the control section 101. Figure 1 Further, FIG. 11 shows the voltage waveforms of the voltage signal V11 of the node Ns11, the voltage signal V21 of the node Ns21, and the output voltage VDL1 of the output terminal DL1 generated by the on-off control of the switches 12 to 14 and the switches 22 to 24 based on the control signals S12 to S14 and the control signals S22 to S24. Figure 9

[0143] ​​​Furthermore, switches 12 and 23, which receive control signals S12 and S23 respectively, are configured using N-channel transistors, and switches 13 and 22, which receive control signals S13 and S22 respectively, are configured using P-channel transistors. Additionally, switches 14 and 24, which receive control signals S14 and S24 respectively, are complementary transistor switches, with the gate of the N-channel transistor receiving the control signals S14 and S24. The control signals S12, S13, S14, S22, S23, and S24 controlling each switch are supplied with a power supply voltage corresponding to the voltage polarity of the switch they control.

[0144] Control unit 101 performs the following operations during each of the following periods: positive drive period T2 for outputting positive voltage signal Vp, negative drive period T4 for outputting negative voltage signal Vn, switching period T1, and switching period T3. Figure 9 The diagram illustrates the on / off control of switches 12-14 and 22-24 based on control signals S12-S14 and S22-S24. Thus, as... Figure 9 As shown, during the switching period T1, switching period T3, positive drive period T2, and negative drive period T4, voltage signal V11 is generated at node Ns11, and voltage signal V21 is generated at node Ns21. Furthermore, output voltage VDL1 is output via output terminal DL1. Moreover, the positive voltage signal Vp and the negative voltage signal Vn can be single or multiple step signals within their respective polarity voltage ranges. Alternatively, the positive drive period T2 and the negative drive period T4 can each be divided into multiple periods that sequentially output multiple voltage signals of the same polarity.

[0145] Here, as Figure 9 As shown, to prevent the switches from exceeding their withstand voltage, a switching period T1 and a switching period T3 are provided between the positive drive period T2 and the negative drive period T4, during which the output terminal DL1 is temporarily driven at the reference power supply voltage VGND. Furthermore, the state immediately preceding the switching period T1 (the initial state) is set to the state in which the negative voltage signal Vn generated in the negative voltage signal supply circuit 20A is supplied to the output terminal DL1 via the output selection switch 21, i.e., the operating state during the negative drive period T4.

[0146] Figure 9In the middle, first, during the switching period Tl, the voltage signals from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A to the nodes Nsl l and Ns21 are cut off by setting both the switch 14 and the switch 24 to the off state by the control signal S14 and the control signal S24. Further, the reference power supply voltage VGND is supplied to the gate and the source (the node Nsl l) of the output selection switch (P-channel transistor) 11 by setting both the switch 12 and the switch 13 to the on state by the control signal S12 and the control signal S13. Thus, the voltage signal Vl l of the node Nsl l becomes the reference power supply voltage VGND, and the follow-up circuit 50 becomes the inactive state, so the output selection switch 11 becomes the off state. Further, the reference power supply voltage VGND is supplied to the gate and the source (the node Ns21) of the output selection switch (N-channel transistor) 21 by setting the switch 22 to the on state by the control signal S22.

[0147] Further, during the switching period Tl, the control signal S23 causes the switch 23 to become the off state, so the output selection switch 21 is set to the on state by the follow-up circuit 60. Thus, the voltage signal V21 of the node Ns21 is pulled up to the reference power supply voltage VGND, and the output voltage VDLl of the output terminal DLl is also pulled up to the reference power supply voltage VGND via the output selection switch 21.

[0148] Next, during the positive electrode drive period T2, the reference power supply voltage VGND is supplied to the gate and the source (the node Ns21) of the output selection switch (N-channel transistor) 21 by setting both the switch 22 and the switch 23 to the on state by the control signal S22 and the control signal S23. Thus, the voltage signal V21 of the node Ns21 becomes the reference power supply voltage VGND, and the follow-up circuit 60 becomes the inactive state, so the output selection switch 21 becomes the off state. Further, the switch 12 and the switch 13 are set to the off state by the control signal S12 and the control signal S13, and the output selection switch 11 is set to the on state by the follow-up circuit 50.

[0149] Further, during the positive electrode driving period T2, the switch 24 is set to the off state by the control signal S24, and the supply of the voltage signal from the negative electrode voltage signal supply circuit 20A continues to be cut off. On the other hand, the switch 14 is set to the on state by the control signal S14, and the positive electrode voltage signal Vp (V11) is supplied from the positive electrode voltage signal supply circuit 10A to the node Nsll. Then, the output voltage VDLl of the output terminal DLl is pulled up to the positive electrode voltage signal Vp via the output selection switch 11 in the on state. Further, during the positive electrode driving period T2, even if the voltage of the positive electrode voltage signal Vp output from the positive electrode voltage signal supply circuit 10A changes, the on state of the output selection switch 11 is maintained by the follow-up circuit 50. Therefore, the output voltage VDLl also changes in accordance with the voltage of the positive electrode voltage signal Vp.

[0150] Next, during the switching period T3, the switches 14 and 24 are both set to the off state by the control signals S14 and S24, and the supply of the voltage signals from the positive electrode voltage signal supply circuit 10A and the negative electrode voltage signal supply circuit 20A is cut off. In addition, the control signals S22 and S23 cause the switches 22 and 23 to both continue to be in the on state, and therefore the voltage signal V21 of the node Ns21 is maintained at the reference power supply voltage VGND, and the follow-up circuit 60 also maintains the inactive state. Thus, the output selection switch 21 continues to be in the off state.

[0151] Further, during the switching period T3, the control signal S12 causes the switch 12 to be in the on state, and the reference power supply voltage VGND is supplied to the source (node Nsll) of the output selection switch (P-channel transistor) 11. In addition, the control signal S13 causes the switch 13 to continue to be in the off state, and the follow-up circuit 50 causes the output selection switch 11 to maintain the on state. Thus, the voltage signal V11 of the node Nsll is pulled down to the reference power supply voltage VGND, and the output voltage VDLl of the output terminal DLl is also pulled down to the reference power supply voltage VGND via the output selection switch 11.

[0152] Next, during the negative electrode driving period T4, the switches 12 and 13 are both set to the on state by the control signals S12 and S13, and the reference power supply voltage VGND is supplied to the gate and the source (node Nsll) of the output selection switch (P-channel transistor) 11. Thus, the voltage signal V11 of the node Nsll becomes the reference power supply voltage VGND. In addition, the switches 22 and 23 are both set to the off state by the control signals S22 and S23, and the output selection switch 21 is set to the on state by the follow-up circuit 60.

[0153] Furthermore, during the negative drive period T4, switch 14 is set to the open state via control signal S14, and the supply of voltage signal from positive voltage signal supply circuit 10A continues to be cut off. On the other hand, switch 24 is set to the open state via control signal S24, and negative voltage signal Vn (V21) is supplied from negative voltage signal supply circuit 20A to node Ns21. As a result, the output voltage VDL1 of output terminal DL1 is pulled down to the negative voltage signal Vn via the open output selection switch 21. Moreover, during the negative drive period T4, even if the voltage of the negative voltage signal output from negative voltage signal supply circuit 20A changes, the open state of output selection switch 21 is maintained by follower circuit 60. Therefore, the output voltage VDL1 also changes with the voltage of negative voltage signal Vn.

[0154] Furthermore, during the switching period T1 and the switching period T3, one of the follower circuits 50 and 60 becomes in a failure state. Therefore, the follower circuits 50 and 60 can also be configured with a switch that temporarily cuts off the current source when it becomes in a failure state.

[0155] Furthermore, in the described embodiment, as follows Figure 9 The operation of the control during the alternating switching between positive and negative drive periods is explained using the example shown. When the power is on and off, control is performed corresponding to the rise and fall of the power supply voltage. For example, during the rise and fall of the power supply voltage, in order to drive the capacitive load connected to the output terminal DL1 to the reference power supply voltage, the supply of voltage signals from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A is cut off. That is, the control unit 101 controls the operation by setting switches 14 and 24 to the off state, switches 12 and 22 to the on state, and switches 13 and 23 to the off state. Furthermore, control can also be performed by setting both the follower circuit 50 and the follower circuit 60 to the active state, thereby turning both the output selection switch 11 and the output selection switch 21 to the on state.

[0156] [Example 6]

[0157] Figure 10 A circuit diagram illustrating the structure of an output circuit 200, which is another example of the output circuit of the present invention.

[0158] Output circuit 100 alternately outputs positive and negative voltage signals to the load of a system. In contrast, Figure 10 The output circuit 200 shown outputs a negative voltage signal to the other load while outputting a positive voltage signal to one of the two system loads, and alternately switches the polarity of the two loads in a polarity reversal drive.

[0159] Furthermore, in Figure 10 In the output circuit 200 shown, a positive voltage signal supply circuit 10B is used instead. Figure 1 The positive voltage signal supply circuit 10A shown is replaced by a negative voltage signal supply circuit 20B, and the control unit 101 is replaced by a control unit 201. Furthermore, in... Figure 10 The output circuit 200 shown includes newly added output terminals DL2, switches 32, 33, 34, 42, 43, and 44, output selection switches 31 and 41, follower circuits 50A and 60A. Other structures are the same as those shown. Figure 1 The same as shown.

[0160] Figure 10 In the circuit, the positive voltage signal supply circuit 10B controls the supply and disconnection of the positive voltage signal Vp (VGND < Vp < VDD2H) to node Ns11 or node Ns31 of the two systems. The negative voltage signal supply circuit 20B controls the supply and disconnection of the negative voltage signal Vn (VGND > Vn > VDD2L) to node Ns21 or node Ns41 of the two systems.

[0161] Output selection switch 31 is composed of a P-channel transistor whose source is connected to node Ns31 and whose drain is connected to output terminal DL2. Output selection switch 41 is composed of an N-channel transistor whose source is connected to node Ns41 and whose drain is connected to output terminal DL2.

[0162] Follower circuit 50A is connected between the gate and source of output selection switch (P-channel transistor) 31, and performs the same function as follower circuit 50. Follower circuit 60A is connected between the gate and source of output selection switch (N-channel transistor) 41, and performs the same function as follower circuit 60.

[0163] Switch 32 is composed of an N-channel transistor connected to node Ns31 and the reference power supply terminal supplying the reference power supply voltage VGND. Switch 42 is composed of a P-channel transistor connected to node Ns41 and the reference power supply terminal. Switch 33 is composed of a P-channel transistor connected between the gate of the output selection switch (P-channel transistor) 31 and the reference power supply terminal. Switch 43 is composed of an N-channel transistor connected between the gate of the output selection switch (N-channel transistor) 41 and the reference power supply terminal. Furthermore, switch 33 can be replaced with a switch connected between the gate of the output selection switch 31 and node Ns31, and switch 43 can be replaced with a switch connected between the gate of the output selection switch 41 and node Ns41.

[0164] like Figure 10As shown, circuit 202, which is configured between nodes Ns11 and Ns21 and output terminal DL1, and circuit 203, which is configured between nodes Ns31 and Ns41 and output terminal DL2, have the same function: when one outputs a positive voltage signal, the other outputs a negative voltage signal.

[0165] Figure 10 The positive voltage signal supply circuit 10B shown is for... Figure 1 The positive voltage signal supply circuit 10A shown is formed by adding a switch 34, which controls the supply and cutoff of the positive voltage signal Vp to node Ns31. To allow the positive voltage signal Vp to pass through a wide voltage range, switch 34 is also a complementary switch, similar to switch 14. Furthermore, the amplifier circuit 10 included in the positive voltage signal supply circuit 10B can also be configured to internally incorporate the functions of switches 14 and 34.

[0166] The negative voltage signal supply circuit 20B is... Figure 1 The negative voltage signal supply circuit 20A shown is formed by adding a switch 44, which controls the supply and cutoff of the negative voltage signal Vn to node Ns41. To allow the negative voltage signal Vn to pass through a wide voltage range, switch 44 is also a complementary switch, similar to switch 24. Furthermore, the amplifier circuit 20 included in the negative voltage signal supply circuit 20B can also be configured to internally incorporate the functions of switches 24 and 44.

[0167] exist Figure 10 In the output circuit 200 shown, when a positive voltage signal Vp is output to the output terminal DL1, the control unit 201... Figure 9 During the positive drive period T2 (including the switching periods before and after), the control unit 201 controls the on / off states of switches 12-14 and 22-24, which control the output to the output terminal DL1, in the same manner as the control during that period. Furthermore, at this time, the control unit 201... Figure 9 During the negative drive period T4 (including the switching periods before and after), the switches 12 to 14 and 22 to 24 are controlled to turn on and off in the same way as the switches 32 to 34 and 42 to 44 that control the output to the output terminal DL2, thereby outputting a negative voltage signal Vn to the output terminal DL2.

[0168] On the other hand, when outputting a negative voltage signal Vn to the output terminal DL1, the control unit 201... Figure 9The control of each of the switches 12 to 14, 22 to 24 that controls the output to the output terminal DL1 is conducted in the same manner as the control during the negative electrode drive period T4 (including the periods before and after the switching) shown in FIG. 6. Further, at this time, the control section 201 conducts the on / off control of each of the switches 32 to 34, 42 to 44 that controls the output to the output terminal DL2 in the same manner as the control during the positive electrode drive period T2 (including the periods before and after the switching) shown in FIG. 6, whereby the positive electrode voltage signal Vp is output to the output terminal DL2. Figure 9 The control of each of the switches 12 to 14, 22 to 24 that controls the output to the output terminal DL1 is conducted in the same manner as the control during the negative electrode drive period T4 (including the periods before and after the switching) shown in FIG. 6. Further, at this time, the control section 201 conducts the on / off control of each of the switches 32 to 34, 42 to 44 that controls the output to the output terminal DL2 in the same manner as the control during the positive electrode drive period T2 (including the periods before and after the switching) shown in FIG. 6, whereby the positive electrode voltage signal Vp is output to the output terminal DL2.

[0169] That is, the control section 201 generates the control signals S32 to S34, S42 to S44 that control the switches 32 to 34, 42 to 44 in the same manner as the control section 101 shown in FIG. 5, together with the control signals Sll to S13, S22 to S24 at the timings shown in FIG. 6. Further, in the case where each of the switches 14, 24, 34, and 44 is composed of a complementary type switch, the complementary signals supplied to these switches 14, 24, 34, and 44 are also generated in the control section 201. Figure 1 Figure 9 That is, the control section 201 generates the control signals S32 to S34, S42 to S44 that control the switches 32 to 34, 42 to 44 in the same manner as the control section 101 shown in FIG. 5, together with the control signals Sll to S13, S22 to S24 at the timings shown in FIG. 6. Further, in the case where each of the switches 14, 24, 34, and 44 is composed of a complementary type switch, the complementary signals supplied to these switches 14, 24, 34, and 44 are also generated in the control section 201.

[0170] As described in detail above, in the output circuit 200 shown in FIG. 6, the drive control shown in FIG. 7 is also conducted in the same manner as the output circuit 100. Figure 10 Figure 9 As described in detail above, in the output circuit 200 shown in FIG. 6, the drive control shown in FIG. 7 is also conducted in the same manner as the output circuit 100. Figure 10 As described in detail above, in the output circuit 200 shown in FIG. 6, the drive control shown in FIG. 7 is also conducted in the same manner as the output circuit 100.

[0171] [Example 7]

[0172] Figure 11 A block diagram showing the schematic structure of a liquid crystal display device 400 including a data driver 73 having the output circuit of the present application.

[0173] Figure 11 ​​In the active matrix type display panel 71 including a liquid crystal display device per pixel unit, m (m is an integer of 2 or more) horizontal scan lines S1 to Sm extending in the horizontal direction of a two-dimensional picture and n (n is an integer of 2 or more) data lines D1 to Dn extending in the vertical direction of the two-dimensional picture are formed. A display cell that assumes a pixel is formed at each intersection of the horizontal scan lines and the data lines. The display cell includes at least a switching element and a pixel electrode, and when the switching element becomes in an on state according to a scan pulse of the horizontal scan line, a gray scale voltage signal of the data line is applied to the pixel electrode via the switching element, and the brightness of each pixel is controlled according to the gray scale voltage applied to the pixel electrode. Further, Figure 11 The structure of the specific display cell is omitted from the description.

[0174] The drive control section 74 receives an image signal VD in which a control signal and the like are integrated, and generates a timing signal based on a horizontal synchronization signal from the image signal VD and supplies it to the scan driver 72. In addition, the drive control section 74 generates various control signal groups and a sequence of pixel data PD that indicates the brightness level of each pixel in, for example, 8-bit luminance gray scale from the image signal VD and supplies it to the data driver 73.

[0175] The scan driver 72 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S1 to Sm of the display panel 71 according to the timing signal supplied from the drive control section 74.

[0176] The data driver 73 is formed on, for example, a semiconductor device such as a Large Scale Integrated Circuit (LSI). The data driver 73 converts the pixel data PD supplied from the drive control section 74 into gray scale voltage signals G1 to Gn having a gray scale voltage corresponding to each pixel data PD for each of n horizontal scan lines. Then, the data driver 73 applies the gray scale voltage signals G1 to Gn to the data lines D1 to Dn of the display panel 71.

[0177] Further, the scan driver 72 or the data driver 73 can be formed integrally with the display panel 71 as part or all of the circuit. In addition, the data driver 73 can be constituted by a plurality of LSIs.

[0178] Figure 12 A block diagram showing the internal structure of the data driver 73.

[0179] As Figure 12As shown, the data driver 73 includes a shift register 600, a data register latch circuit 700, a level shift circuit 800, a level voltage generation circuit 500, a decoder circuit 900, and an output amplification circuit 2000.

[0180] Further, the data driver 73 also includes an interface circuit (not shown) that receives a control signal and an image digital signal supplied from the drive control section 74, generates a clock signal and a control signal required inside the driver, and outputs various signal groups in synchronization with the image digital signal. Figure 11 As shown, the drive control section 74 supplies a control signal and an image digital signal to the data driver 73, and generates a clock signal and a control signal required inside the driver, and outputs various signal groups in synchronization with the image digital signal. Figure 12 In the drawing, details of the interface circuit are omitted for convenience of explanation.

[0181] Further, the shift register 600 and the data register latch circuit 700 are supplied with at least a reference power supply voltage VGND and a positive low-side power supply voltage VDD1H as power supply voltages, and the block that generates a negative-side signal is also supplied with a negative low-side power supply voltage VDD1L.

[0182] The level shift circuit 800, the level voltage generation circuit 500, and the decoder circuit 900 are supplied with at least the reference power supply voltage VGND, a positive high-side power supply voltage VDD2H, and a negative high-side power supply voltage VDD2L as power supply voltages. The output amplification circuit 2000 is supplied with the reference power supply voltage VGND, the positive low-side power supply voltage VDD1H, the negative low-side power supply voltage VDD1L, the positive high-side power supply voltage VDD2H, and the negative high-side power supply voltage VDD2L as power supply voltages.

[0183] The shift register 600 generates a plurality of latch timing signals for selection that are latched in synchronization with a clock signal CLK in accordance with a start pulse, and supplies the signals to the data register latch circuit 700.

[0184] The data register latch circuit 700 receives an image digital signal, a polarity inversion signal POL, a timing control signal, and the like, and imports the image digital signal by every predetermined number in accordance with each latch timing signal supplied from the shift register 600, and supplies the predetermined number of image digital signals at a latch timing to the level shift circuit 800.

[0185] Further, the data register latch circuit 700 selects an output of the image digital signal to the level shifter 80P or the level shifter 80N corresponding to the positive or the negative in accordance with the polarity inversion signal POL.

[0186] The level shift circuit 800 includes a positive level shifter 80P and a negative level shifter 80N. The positive level shifter 80P converts the positive image digital signal of low amplitude (VGND ~ VDD1H) into a positive image digital signal of analog voltage amplitude (VGND ~ VDD2H). The negative level shifter 80N converts the negative image digital signal of low amplitude (VDD1L ~ VGND) into a negative image digital signal of analog voltage amplitude (VDD2L ~ VGND). The prescribed image digital data signals supplied from the data register latch circuit 700 are sent to the positive level shifter 80P or the negative level shifter 80N in accordance with the polarity inversion signal POL, are widened to the analog voltage amplitude corresponding to each polarity, and are sent to the positive decoder 90P or the negative decoder 90N.

[0187] The decoder circuit 900 has a structure in which a pair of decoders composed of the positive decoder 90P and the negative decoder 90N is provided for every 2 outputs. Further, the arrangement order of the decoders 90P, 90N of each polarity within the decoder circuit 900 can be changed as appropriate.

[0188] The level voltage generation circuit 500 generates a plurality of level voltages for the positive and a plurality of level voltages for the negative, which have mutually different voltage values, supplies the plurality of level voltages for the positive to the positive decoder 90P, and supplies the plurality of level voltages for the negative to the negative decoder 90N.

[0189] The decoder circuit 900 selects the level voltage corresponding to the image digital signal after the level shift processing for each polarity from among the plurality of level voltages for every 2 outputs of the pair of the positive decoder 90P and the negative decoder 90N, and supplies each level voltage to the output amplification circuit 2000.

[0190] The output amplification circuit 2000 is composed of, for example, an output circuit 200 of Figure 10 The output amplification circuit 2000 receives the polarity inversion signal POL and the switch control signal group, and performs operational amplification on the level voltage of each polarity selected by the decoder circuit 900, respectively. Then, the output amplification circuit 2000 outputs the positive voltage signal Vp to one of the 2 output terminals of the data driver 73 and outputs the negative voltage signal Vn to the other of the 2 output terminals in accordance with the polarity inversion signal POL. Further, in the output amplification circuit 2000, the positive voltage signal Vp and the negative voltage signal Vn are output in accordance with the polarity inversion signal POL, for example, by Figure 10The control signals S12 to S14, the control signals S22 to S24, the control signals S32 to S34, and the control signals S42 to S44 of the output circuit 200 are controlled to control the on and off of the switches 12 to 14, the switches 22 to 24, the switches 32 to 34, and the switches 42 to 44. Further, Figure 10 The control section 201 (not shown) that generates each control signal can also be built into the output amplification circuit 2000 and provided in common for a plurality of output circuits 200 of the output amplification circuit 2000.

[0191] Further, in the data driver shown in FIG. 8, Figure 12 In the block diagram of the data driver shown in FIG. 8, the blocks having a voltage range of the analog voltage amplitude are the level shift circuit 800, the decoder circuit 900, the output amplification circuit 2000, and the level voltage generation circuit 500.

[0192] The level voltage generation circuit 500 can be composed of a circuit block that generates a plurality of level voltages in the positive analog voltage range (VGND to VDD2H) and a circuit block that generates a plurality of level voltages in the negative analog voltage range (VDD2L to VGND). The output amplification circuit 2000 can also be composed of elements having a withstand voltage in the positive analog voltage range (VGND to VDD2H) and elements having a withstand voltage in the negative analog voltage range (VDD2L to VGND).

[0193] Thus, Figure 12 In the data driver shown in FIG. 8, the liquid crystal drive voltage signals in the voltage range of VDD2L to VDD2H based on the negative voltage signal and the positive voltage signal are output from the output terminal, but the elements that constitute the data driver can be composed of elements having a low element withstand voltage VDD2T that can operate in the positive analog voltage range (VGND to VDD2H) or the negative analog voltage range (VDD2L to VGND) of about one-half of the liquid crystal drive voltage range. In the case of a transistor having a low element withstand voltage VDD2T, for example, the gate insulating film can be thinned, and the output circuit composed of the transistor can be realized in a manner that saves area. Further, since the withstand voltage is lowered, the element spacing can also be narrowed. Thus, Figure 12 The data driver of the present embodiment can be composed in a manner that saves area, and thus can be realized at a low cost.

Claims

1. An output circuit characterized by comprising: comprises: a positive voltage signal supply circuit that supplies a positive voltage signal, which is a high voltage compared to a reference power supply voltage, to a first node, or cuts off supply of the positive voltage signal to the first node; a negative voltage signal supply circuit that supplies a negative voltage signal, which is a low voltage compared to the reference power supply voltage, to a second node, or cuts off supply of the negative voltage signal to the second node; a first output terminal; a first switch that comprises a positive channel transistor with a source connected to the first node and a drain connected to the first output terminal, connects the first output terminal and the first node in an on state, and cuts off connection between the first output terminal and the first node in an off state; a second switch that comprises a negative channel transistor with a source connected to the second node and a drain connected to the first output terminal, connects the first output terminal and the second node in an on state, and cuts off connection between the first output terminal and the second node in an off state; a third switch that applies the reference power supply voltage to the first node in an on state, and stops application of the reference power supply voltage to the first node in an off state; a fourth switch that applies the reference power supply voltage to the second node in an on state, and stops application of the reference power supply voltage to the second node in an off state; a first control unit that sets the first switch to the off state when effective; a second control unit that sets the second switch to the off state when effective; a first follower circuit that is connected to the first node and a gate of the first switch, and comprises a first negative channel source follower transistor that performs a source follower operation by receiving a voltage signal of the first node at a gate thereof, and generates a first gate voltage corresponding to a voltage of a source of the first negative channel source follower transistor, which is in phase with the voltage signal of the first node, and supplies the first gate voltage to the gate of the first switch; and a second follower circuit that is connected to the second node and a gate of the second switch, and comprises a first positive channel source follower transistor that performs a source follower operation by receiving a voltage signal of the second node at a gate thereof, and generates a second gate voltage corresponding to a voltage of a source of the first positive channel source follower transistor, which is in phase with the voltage signal of the second node, and supplies the second gate voltage to the gate of the second switch, the positive voltage signal supply circuit, the negative voltage signal supply circuit, the first switch, the second switch, the third switch, the fourth switch, the first control unit, the second control unit, the first follower circuit, and the second follower circuit are each configured with a low voltage element having a lower withstand voltage than an output voltage range of the first output terminal.

2. The output circuit according to claim 1, wherein ​ The first follower circuit has a structure in which the first negative channel type source follower transistor and a first load element are connected in series between terminals of mutually different power supply voltages, and generates a voltage at a connection point of the source of the first negative channel type source follower transistor and the first load element as the first gate voltage, The second follower circuit has a structure in which the first positive channel type source follower transistor and a second load element are connected in series between terminals of mutually different power supply voltages, and generates a voltage at a connection point of the source of the first positive channel type source follower transistor and the second load element as the second gate voltage.

3. The output circuit according to claim 1, wherein The first follower circuit has a plurality of positive channel type sub follower circuits connected in series, Each of the plurality of positive channel type sub follower circuits includes a negative channel type source follower transistor and a load element connected in series between different power supply voltage terminals, and is configured to have the gate of the negative channel type source follower transistor as an input terminal and to have a connection point of the source of the negative channel type source follower transistor and the load element as an output terminal, The first node is connected to the input terminal of the first stage positive channel type sub follower circuit among the plurality of positive channel type sub follower circuits, and the gate of the first switch is connected to the output terminal of the last stage positive channel type sub follower circuit, Each of the positive channel type sub follower circuits other than the first stage and the last stage positive channel type sub follower circuits among the plurality of positive channel type sub follower circuits has the output terminal of the preceding stage positive channel type sub follower circuit connected to the input terminal thereof and has the input terminal of the succeeding stage positive channel type sub follower circuit connected to the output terminal thereof, The second follower circuit has a plurality of negative channel type sub follower circuits connected in series, Each of the plurality of negative channel type sub follower circuits includes a positive channel type source follower transistor and a load element connected in series between different power supply voltage terminals, and is configured to have the gate of the positive channel type source follower transistor as an input terminal and to have a connection point of the source of the positive channel type source follower transistor and the load element as an output terminal, The second node is connected to the input terminal of the first stage negative channel type sub follower circuit among the plurality of negative channel type sub follower circuits, and the gate of the second switch is connected to the output terminal of the last stage negative channel type sub follower circuit, Each of the negative channel type sub follower circuits other than the first stage and the last stage negative channel type sub follower circuits among the plurality of negative channel type sub follower circuits has the output terminal of the preceding stage negative channel type sub follower circuit connected to the input terminal thereof and has the input terminal of the succeeding stage negative channel type sub follower circuit connected to the output terminal thereof.

4. The output circuit according to claim 1, wherein The first follower circuit includes a first positive channel type sub follower circuit and a second positive channel type sub follower circuit, The first positive electrode sub-following circuit and the second positive electrode sub-following circuit each include a negative channel type source follower transistor and a load element connected in series between different power supply voltage terminals, and are configured to have a gate of the negative channel type source follower transistor as an input terminal and a connection point of a source of the negative channel type source follower transistor and the load element as an output terminal, The first positive electrode sub-following circuit has the first node connected to the input terminal thereof and has an input terminal of the second positive electrode sub-following circuit connected to the output terminal thereof, and the second positive electrode sub-following circuit has the gate of the second switch connected to the output terminal thereof, The second following circuit includes a first negative electrode sub-following circuit and a second negative electrode sub-following circuit, The first negative electrode sub-following circuit and the second negative electrode sub-following circuit each include a positive channel type source follower transistor and a load element connected in series between different power supply voltage terminals, and are configured to have a gate of the positive channel type source follower transistor as an input terminal and a connection point of a source of the positive channel type source follower transistor and the load element as an output terminal, The first negative electrode sub-following circuit has the second node connected to the input terminal thereof and has an input terminal of the second negative electrode sub-following circuit connected to the output terminal thereof, and the second negative electrode sub-following circuit has the gate of the second switch connected to the output terminal thereof.

5. The output circuit according to any one of claims 1 to 4, wherein a control section controls the third switch, the fourth switch, the first control means, the second control means, the positive voltage signal supply circuit, and the negative voltage signal supply circuit in such a manner as to switch the positive voltage signal and the negative voltage signal at a prescribed timing to output from the first output terminal.

6. The output circuit according to claim 5, wherein the control section, in a case where the positive voltage signal is to be output from the first output terminal, controls the third switch to be in an off state, controls the fourth switch to be in an on state, controls the first control means to be in an inactive state, controls the second control means to be in an active state, controls the positive voltage signal supply circuit in such a manner as to supply the positive voltage signal to the first node, and controls the negative voltage signal supply circuit in such a manner as to cut off supply of the negative voltage signal to the second node, in a case where the negative voltage signal is to be output from the first output terminal, controls the third switch to be in an on state, controls the fourth switch to be in an off state, controls the first control means to be in an active state, controls the second control means to be in an inactive state, controls the negative voltage signal supply circuit in such a manner as to supply the negative voltage signal to the second node, and controls the positive voltage signal supply circuit in such a manner as to cut off supply of the positive voltage signal to the first node.

7. The output circuit according to claim 5 or 6, wherein The control section sets a first period, a second period, a third period, and a fourth period as control periods, the first period is for preparing to switch the output from the negative voltage signal to the positive voltage signal, the second period is for outputting the positive voltage signal from the first output terminal, the third period is for preparing to switch the output from the positive voltage signal to the negative voltage signal, and the fourth period is for outputting the negative voltage signal from the first output terminal, In the first and third periods, the supply of the positive voltage signal by the positive voltage signal supply circuit and the supply of the negative voltage signal by the negative voltage signal supply circuit are cut off, and the third switch and the fourth switch are controlled to be in the on state, at least one of the first switch and the second switch is controlled to be in the on state by the first control means and the second control means, whereby the first output terminal, the first node, and the second node are set to the state of the reference power supply voltage, In the second period, the supply of the negative voltage signal by the negative voltage signal supply circuit is cut off, and the positive voltage signal is supplied to the first node by the positive voltage signal supply circuit, and the third switch is controlled to be in the off state, the fourth switch is controlled to be in the on state, the first control means is controlled to be in the inactive state, and the second control means is controlled to be in the active state, whereby the positive voltage signal is supplied to the first output terminal via the first switch, In the fourth period, the supply of the positive voltage signal by the positive voltage signal supply circuit is cut off, and the negative voltage signal is supplied to the second node by the negative voltage signal supply circuit, and the third switch is controlled to be in the on state, the fourth switch is controlled to be in the off state, the first control means is controlled to be in the active state, and the second control means is controlled to be in the inactive state, whereby the negative voltage signal is supplied to the first output terminal via the second switch.

8. The output circuit according to any one of claims 5 to 7, characterized by, Further comprising: a second output terminal; a third node and a fourth node; a fifth switch including a positive channel transistor having a source connected to the third node and a drain connected to the second output terminal, which connects the second output terminal and the third node in the on state and cuts off the connection between the second output terminal and the third node in the off state; a sixth switch including a negative channel transistor having a source connected to the fourth node and a drain connected to the second output terminal, which connects the second output terminal and the fourth node in the on state and cuts off the connection between the second output terminal and the fourth node in the off state; a seventh switch which applies the reference power supply voltage to the third node in the on state and stops the application of the reference power supply voltage to the third node in the off state; an eighth switch which applies the reference power supply voltage to the fourth node in the on state and stops the application of the reference power supply voltage to the fourth node in the off state; a third control means which, when active, sets the fifth switch to an open state; a fourth control means which, when active, sets the sixth switch to an open state; a third follower circuit connected to the third node and the gate of the fifth switch, including a second negative channel type source follower transistor which performs a source follower operation with its own gate receiving a voltage signal of the third node, and generates a third gate voltage corresponding to the voltage of the source of the second negative channel type source follower transistor, which is in phase with the voltage signal of the third node, and supplies the gate of the fifth switch; and a fourth follower circuit connected to the fourth node and the gate of the sixth switch, including a second positive channel type source follower transistor which performs a source follower operation with its own gate receiving a voltage signal of the fourth node, and generates a fourth gate voltage corresponding to the voltage of the source of the second positive channel type source follower transistor, which is in phase with the voltage signal of the fourth node, and supplies the gate of the sixth switch, the positive voltage signal supply circuit controls the supply or cutoff of the positive voltage signal to the first node or the third node, the negative voltage signal supply circuit controls the supply or cutoff of the negative voltage signal to the second node or the fourth node, the positive voltage signal supply circuit, the negative voltage signal supply circuit, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the third control means, the fourth control means, the third follower circuit, and the fourth follower circuit are each composed of a low voltage element having a lower withstand voltage than the output voltage range of the second output terminal.

9. The output circuit according to claim 8, wherein in a case where the positive voltage signal is to be output from the second output terminal, the control portion controls the seventh switch to an open state, the eighth switch to a conductive state, the third control means to an inactive state, the fourth control means to an active state, and controls the positive voltage signal supply circuit in such a manner that the positive voltage signal is supplied to the third node, and controls the negative voltage signal supply circuit in such a manner that the supply of the negative voltage signal to the fourth node is cut off, in a case where the negative voltage signal is to be output from the second output terminal, the control portion controls the seventh switch to a conductive state, the eighth switch to an open state, the third control means to an active state, the fourth control means to an inactive state, and controls the negative voltage signal supply circuit in such a manner that the negative voltage signal is supplied to the fourth node, and controls the positive voltage signal supply circuit in such a manner that the supply of the positive voltage signal to the third node is cut off.

10. A data driver, comprising: a plurality of output circuits each of which is as claimed in any one of claims 1 to 9, and outputs a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity for driving a plurality of data lines of a liquid crystal display panel from the plurality of output circuits.

11. A display device, characterized by comprising: comprising: A data driver including a plurality of output circuits as claimed in any one of claims 1 to 9, outputs a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity from a plurality of the output circuits; and A liquid crystal display panel having a plurality of data lines that receive the plurality of gray scale voltage signals.

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