memory array

Abstract

The present invention discloses a memory array comprising at least one band region comprising a plurality of source line bands and a plurality of word line bands; at least two sub-arrays comprising a plurality of interleaved active magnetic storage elements, wherein the at least two sub-arrays are separated by the band region; and a plurality of interleaved dummy magnetic storage elements arranged within the band region.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element, and in particular to a high-density magnetoresistive random access memory (MRAM) array. Background Art

[0002] The magnetoresistance (MR) effect is known to occur when a material's electrical resistance changes with an applied magnetic field. Its physical quantity is defined as the difference in resistance in the presence and absence of a magnetic field divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive production and holds significant commercial value. Furthermore, by leveraging the characteristic of giant magnetoresistive (GMR) materials, which exhibit varying resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can be fabricated, offering the advantage of retaining stored data even when power is off.

[0003] The magnetoresistance effect is also used in the field of magnetic field sensing. For example, the electronic compass components used in mobile phones with global positioning systems (GPS) are used to provide information such as the user's movement direction. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistance (AMR) sensing elements, GMR sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned existing technologies generally include: larger chip area, more expensive manufacturing process, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, etc., and further improvement is necessary. Summary of the Invention

[0004] The main purpose of the present invention is to provide a high-density magnetoresistive random access memory (MRAM) array to address the above-mentioned deficiencies and shortcomings of the prior art.

[0005] In one aspect, the present invention provides a memory array comprising at least one band region comprising a plurality of source line bands and a plurality of word line bands; at least two sub-arrays comprising a plurality of interleaved active magnetic storage elements, wherein the at least two sub-arrays are separated by the band region; and a plurality of interleaved dummy magnetic storage elements disposed within the band region.

[0006] According to an embodiment of the present invention, the plurality of interleaved active magnetic storage elements and the plurality of interleaved dummy magnetic storage elements are evenly distributed across the at least two sub-arrays and the strip area.

[0007] According to an embodiment of the present invention, the plurality of interleaved dummy magnetic storage elements include dummy magnetic tunneling junction (MTJ) elements.

[0008] According to an embodiment of the present invention, the bottom electrode of the dummy MTJ element is not electrically connected to the plurality of source line straps or the plurality of word line straps.

[0009] According to an embodiment of the present invention, the plurality of source line strips include a plurality of first source line strips extending along a first direction and a plurality of second source line strips extending along the first direction.

[0010] According to an embodiment of the present invention, the plurality of first source line strips extending along the first direction and the plurality of second source line strips extending along the first direction sandwich the plurality of word line strips extending along the first direction.

[0011] According to an embodiment of the present invention, each of the plurality of first source line strips is connected to a common source line extending along a second direction.

[0012] According to an embodiment of the present invention, the first direction is orthogonal to the second direction.

[0013] According to an embodiment of the present invention, the memory array further includes a first dummy diffusion region extending along the first direction and directly below the plurality of first source line straps.

[0014] According to an embodiment of the present invention, the memory array further includes a second dummy diffusion region extending along the first direction and directly below the plurality of second source line straps.

[0015] According to an embodiment of the present invention, no diffusion region is provided between the first dummy diffusion region and the second dummy diffusion region.

[0016] According to an embodiment of the present invention, each of the plurality of interleaved active magnetic storage elements is electrically connected to a storage node pad via a tungsten via.

[0017] According to an embodiment of the present invention, no tungsten vias are arranged in the strip area.

[0018] According to an embodiment of the present invention, the memory array further includes a plurality of gate lines extending along the second direction.

[0019] According to an embodiment of the present invention, the plurality of staggered active magnetic storage elements include a plurality of first active magnetic storage elements arranged in a first column and a plurality of second active magnetic storage elements arranged in a second column, wherein the plurality of first active magnetic storage elements arranged in the first column and the plurality of second active magnetic storage elements arranged in the second column are respectively aligned with the plurality of gate lines extending along the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a memory array according to an embodiment of the present invention, mainly showing an active region, polysilicon gate lines, a common source line located in the M1 metal layer, a source line strap, and a word line strap;

[0021] Figure 2 A schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the locations of conductive vias, storage node pads, and tungsten vias;

[0022] Figure 3 A schematic diagram of a memory array according to an embodiment of the present invention, mainly showing the positions of magnetic storage elements;

[0023] Figure 4 A schematic diagram of a memory array according to an embodiment of the present invention, mainly showing the location of the V2 conductive via in the band area;

[0024] Figure 5 A schematic diagram of a memory array according to an embodiment of the present invention is shown, which mainly shows the locations of pads located on the M3 metal layer in the band area;

[0025] Figure 6 To follow Figure 5 A schematic cross-sectional view shown along the median tangent line II';

[0026] Figure 7 A schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the V3 conductive vias;

[0027] Figure 8 A schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the M4 metal layer;

[0028] Figure 9 A schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the V4 conductive vias;

[0029] Figure 10 A schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the M5 metal layer;

[0030] Figure 11A schematic three-dimensional diagram of a portion of the structure of a sub-array of a memory array according to an embodiment of the present invention;

[0031] Figure 12 FIG2 is a schematic three-dimensional diagram of a portion of the structure of a sub-array and a band area of ​​a memory array according to an embodiment of the present invention.

[0032] Description of main component symbols

[0033] 1 Memory array

[0034] 100 semiconductor substrate

[0035] 140 Tungsten Via

[0036] 210~260 dielectric layer

[0037] AA Active Area

[0038] AAd1 first dummy diffusion area

[0039] AAd2 Second dummy diffusion area

[0040] BE bottom electrode

[0041] BL bit line

[0042] C D Drain contact plug

[0043] C P contact plug

[0044] C S Source contact differential plug

[0045] CSL Common Source Line

[0046] D1 First direction

[0047] D2 Second direction

[0048] DD drain region

[0049] GL Polysilicon Gate Line

[0050] M1~M5 metal layers

[0051] M A Active magnetic storage elements

[0052] M A1 First active magnetic storage element

[0053] M A2 Second active magnetic storage element

[0054] M D Dummy magnetic storage element

[0055] MAS subarray

[0056] P1 pad

[0057] P2 storage node pads

[0058] P S1 、P S2 、P W pads

[0059] P VS1 、P VS2 、P VW pads

[0060] P DS41 、P DS42 、P DW4 pads

[0061] SD source region

[0062] SL Source Line

[0063] SLS Source Line Strap

[0064] SLS1 first source line strap

[0065] SLS2 Second source line strap

[0066] SR band area

[0067] STI shallow trench isolation

[0068] T transistor

[0069] TE top electrode

[0070] V1~V4 conductive vias

[0071] V A1 、V A3 Conductive vias

[0072] V S1 、V S2 、V W Conductive vias

[0073] V PS1 、V PS2 、V PW Conductive vias

[0074] V DS31 、V DS32 、V DW3 Conductive vias

[0075] V DS41 、V DS42 、VDW4 Conductive vias

[0076] WL word line

[0077] WLS Word Line Strip DETAILED DESCRIPTION

[0078] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable a person skilled in the art to implement them.

[0079] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0080] The present invention discloses a high-density memory layout, particularly a high-density magnetoresistive random access memory (MRAM) array. A specific technical feature of the high-density memory layout is that a plurality of staggered dummy magnetic storage elements are arranged in a strap region between two sub-arrays, so that the active magnetic storage elements and dummy magnetic storage elements of the memory array are evenly distributed in a staggered arrangement across the two sub-arrays and the strap region, thereby achieving a high-density memory layout.

[0081] In the detailed description below, Mn represents different metal layers in the metal interconnect structure, where n is a positive integer. For example, M1 represents the first metal layer in the metal interconnect structure, M2 represents the second metal layer in the metal interconnect structure, and so on. Vn represents different conductive vias in the metal interconnect structure. For example, V1 represents the conductive via connecting M1 to M2, V2 represents the conductive via connecting M2 to M3, and so on.

[0082] See also Figure 1 , which is a schematic diagram of a memory array according to an embodiment of the present invention, mainly showing the active region, polysilicon gate line, common source line located in the M1 metal layer, source line strap, and word line strap. Figure 1As shown, the memory array 1 includes at least two sub-arrays MAS and at least one strip region SR. According to an embodiment of the present invention, the strip region SR is a strip-shaped region extending along a first direction D1, and the two sub-arrays MAS are separated by the strip region SR. According to an embodiment of the present invention, the memory array 1 further includes a plurality of polysilicon gate lines GL extending along a second direction D2 and a plurality of active areas AA formed in a semiconductor substrate 100 and extending along the first direction D1. According to an embodiment of the present invention, the first direction D1 is orthogonal to the second direction D2. According to an embodiment of the present invention, the active areas AA are isolated from each other by shallow trench isolation regions STI.

[0083] According to an embodiment of the present invention, the polysilicon gate line GL passes through the two sub-arrays MAS and the band region SR, and forms a transistor T at the intersection of the sub-array MAS and the active region AA. According to an embodiment of the present invention, the transistor T includes a source region SD and a drain region DD, for example, N + According to an embodiment of the present invention, two first dummy diffusion regions AAd1 and second dummy diffusion regions AAd2 extending along a first direction D1 are further provided within the strip region SR, adjacent to the two sub-arrays MAS, respectively. According to an embodiment of the present invention, the first dummy diffusion regions AAd1 and the second dummy diffusion regions AAd2 can help improve the yield of memory cells located at the edges of the sub-arrays MAS.

[0084] According to an embodiment of the present invention, multiple source line straps SLS and multiple word line straps WLS are further provided within the strap region SR and are located in the M1 metal layer. The multiple source line straps SLS include multiple first source line straps SLS1 extending along a first direction D1 and multiple second source line straps SLS2 extending along the first direction D1. According to an embodiment of the present invention, the multiple first source line straps SLS1 are substantially aligned with the first dummy diffusion area AAd1, and the multiple second source line straps SLS2 are substantially aligned with the second dummy diffusion area AAd2. According to an embodiment of the present invention, no diffusion region is provided between the first dummy diffusion area AAd1 and the second dummy diffusion area AAd2.

[0085] According to an embodiment of the present invention, multiple word line straps WLS are also provided within the strap region SR and are also located in M1. According to an embodiment of the present invention, multiple first source line straps SLS1 extending along the first direction D1 and multiple second source line straps SLS2 extending along the first direction D1 sandwich the multiple word line straps WLS extending along the first direction D1. According to an embodiment of the present invention, the word line straps WLS, the first source line straps SLS1, and the second source line straps SLS2 are arranged in a staggered manner. According to an embodiment of the present invention, each word line strap WLS is connected to the first source line straps WLS via two contact plugs C. P They are electrically connected to two adjacent polysilicon gate lines GL respectively.

[0086] According to an embodiment of the present invention, the first source line strips SLS1 are respectively connected to the common source lines CSL extending along the second direction D2. According to an embodiment of the present invention, the common source lines CSL are connected to the common source lines CSL via the source contact plugs C S The memory array 1 further includes a plurality of pads P1 located on the drain region DD of the transistor T and electrically connected to the source region SD of the transistor T. D Electrically connected to the drain region DD of the transistor T.

[0087] See also Figure 2 , which is a schematic diagram of a memory array according to an embodiment of the present invention, mainly showing the locations of conductive vias, storage node pads and tungsten vias. Figure 2 As shown, the memory array 1 further includes a plurality of V1 conductive vias, including conductive vias V disposed on each pad P1 in the sub-array MAS. A1 , conductive vias V provided on each first source line strap SLS1 in the strap region SR S1 , conductive vias V on each second source line strap SLS2 S2 and conductive vias V on each word line strap WLS W According to an embodiment of the present invention, the conductive via V S1 and conductive vias V W The width in the first direction D1 is greater than the conductive through hole V A1 The width in the first direction D1.

[0088] According to an embodiment of the present invention, the memory array 1 further includes a plurality of sub-arrays MAS electrically connected to the conductive vias V A1 The storage node pad P2 located in the M2 metal layer is electrically connected to the conductive via V in the band region SR. S1 Pad P S1 , electrically connected to the conductive via V in the strip region SR S2 Pad P S2 , and electrically connected to the conductive via V in the strip region SR W Pad P W According to an embodiment of the present invention, the storage node pad P2 may have a rectangular outline, the long side of which is parallel to the first direction D1 and partially overlaps with the polysilicon gate line GL below. According to an embodiment of the present invention, the memory array 1 further includes a plurality of tungsten through-holes 140 in the sub-array MAS, each electrically connected to the corresponding storage node pad P2. According to an embodiment of the present invention, the plurality of tungsten through-holes 140 are staggered and substantially aligned with the polysilicon gate line GL below. According to an embodiment of the present invention, the pad P2 in the band region SR S1 , pad P S2 and pad P WNo tungsten vias are arranged on it.

[0089] See also Figure 3 , which is a schematic diagram of a memory array according to an embodiment of the present invention, mainly showing the position of the magnetic storage element. Figure 3 As shown, the sub-array MAS of the memory array 1 includes a plurality of staggered active magnetic storage elements M A The band region SR includes a plurality of interleaved dummy magnetic storage elements M D According to an embodiment of the present invention, in the sub-array MAS, the active magnetic storage element M A Set on the corresponding tungsten through hole 140, that is, the active magnetic storage element M A The active magnetic memory element M is substantially aligned with the tungsten through hole 140 below, and therefore, is also substantially aligned with the polysilicon gate line GL below. A The tungsten via 140 is electrically connected to the storage node pad P2 below.

[0090] According to an embodiment of the present invention, the active magnetic storage element M A The first active magnetic storage element M is arranged in a first column. A1 and a plurality of second active magnetic storage elements M arranged in a second column A2 , wherein the first active magnetic storage element M arranged in the first column A1 and the second active magnetic storage element M arranged in the second column A2 They are respectively aligned with corresponding gate lines GL extending along the second direction D2.

[0091] According to an embodiment of the present invention, the active magnetic storage element M A and a dummy magnetic storage element M D Contains a magnetic tunneling junction (MTJ) element. According to an embodiment of the present invention, the MTJ element may include a multi-layer structure, for example, a bottom electrode, a top electrode, and a magnetic tunneling junction structure located between the bottom electrode and the top electrode, including, but not limited to, a reference layer, a channel layer, a free layer, and a cap layer. According to an embodiment of the present invention, the dummy magnetic storage element M D The bottom electrode of the MTJ element (dummy MTJ element) is not electrically connected to the source line strap or the word line strap.

[0092] According to an embodiment of the present invention, the dummy magnetic storage element M D The pads P are arranged in a staggered manner in the tape region SR. S1 , pad P S2 and pad P W Because the pad P in the band area SR S1 , pad P S2 and pad P WNo tungsten through-holes are arranged on the dummy magnetic storage element M. D The bottom electrode is not directly electrically connected to the pad P in the band region SR. S1 , pad P S2 and pad P W According to an embodiment of the present invention, the dummy magnetic storage element M D With pad P S1 Between, the virtual magnetic storage element M D With pad P S2 Between, the virtual magnetic storage element M D With pad P W There is only a dielectric layer in between.

[0093] According to an embodiment of the present invention, the staggered arrangement of active magnetic storage elements M A and staggered arrangement of dummy magnetic storage elements M D The magnetic storage elements are evenly distributed on the two sub-arrays MAS and the band region SR. Such a uniform and repeated arrangement of magnetic storage elements can realize a high-density memory layout.

[0094] See also Figure 4 , which is a schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the location of the V2 conductive via in the band region SR. Figure 4 As shown, the memory array 1 is further provided with staggered conductive vias V in the band region SR. PS1 , conductive via V PW and conductive vias V PS2 , where the conductive via V PS1 , conductive via V PW and conductive vias V PS2 Connect to the pads P below S1 , pad P W and pad P S2 Electrical connection.

[0095] See also Figure 5 , which is a schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the position of the pads located in the M3 metal layer in the band region SR. Figure 5 As shown, the memory array 1 is further provided with a pad P located in the M3 metal layer in the band region SR. VS1 , pad P VW and pad P VS2 , where pad P VS1 , pad P VW and pad P VS2 The size and position of are substantially the same as the first source line strap SLS1, word line strap WLS and second source line strap SLS2 below.

[0096] According to an embodiment of the present invention, the pad P VS1 Covering conductive via V PS1 and the adjacent dummy magnetic storage element M D , and set the dummy magnetic storage element M D The upper electrode is electrically connected to the conductive via V PS1 According to an embodiment of the present invention, the pad P VS2 Covering conductive via V PS2 and the adjacent dummy magnetic storage element M D , and set the dummy magnetic storage element M D The upper electrode is electrically connected to the conductive via V PS2 According to an embodiment of the present invention, the pad P VW Covering conductive via V PW and the adjacent dummy magnetic storage element M D , and set the dummy magnetic storage element M D The upper electrode is electrically connected to the conductive via V PW .

[0097] See also Figure 6 , which is along Figure 5 The cross-sectional view shown by the midline II', wherein the same regions, layers or components are still represented by the same symbols. Figure 6 As shown, there may be multiple dielectric layers on the semiconductor substrate 100, for example, dielectric layers 210 to 260. As mentioned above, in the dummy magnetic storage element M D The lower electrode BE and the pad P below S2 There is only a dielectric layer 230 between them, so the dummy magnetic storage element M D The lower electrode BE is not directly connected to the pad P below S2 According to an embodiment of the present invention, the conductive via V PS2 It can penetrate the dielectric layers 230-250 and be electrically connected to the pad P below. S2 . Pad P VS2 Covering conductive via V PS2 and a dummy magnetic storage element M D , and set the dummy magnetic storage element M D The upper electrode TE is electrically connected to the conductive via V PS2 .

[0098] See also Figure 7 , which is a schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the V3 conductive via. Figure 7 As shown, the memory array 1 further comprises a plurality of staggered conductive vias V in the sub-array MAS. A3 , which is substantially aligned with the corresponding active magnetic storage element M A, that is, in the sub-array MAS, each conductive via V A3 Directly electrically connected to each active magnetic storage element M A According to an embodiment of the present invention, a plurality of staggered conductive through holes V are provided in the strip region SR. DS31 , conductive via V DW3 and conductive vias V DS32 , are electrically connected to pads P VS1 , pad P VW and pad P VS2 According to an embodiment of the present invention, the conductive via V DS31 , conductive via V DW3 and conductive vias V DS32 It has a rectangular outline, the long side of which is parallel to the first direction D1, and each conductive through hole V DS31 , conductive via V DW3 and conductive vias V DS32 The area of ​​each conductive via V A3 .

[0099] See also Figure 8 , which is a schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the M4 metal layer. Figure 8 As shown, the memory array 1 further includes a plurality of bit lines BL located in the M4 metal layer in the sub-array MAS, which are electrically connected to corresponding conductive vias V on the same row in the first direction D1. A3 According to an embodiment of the present invention, in the strip region SR, corresponding to the conductive via V DS31 , conductive via V DW3 and conductive vias V DS32 There are multiple staggered pads P DS41 , pad P DW4 and pad P DS42 .

[0100] See also Figure 9 , which is a schematic diagram of a memory array according to an embodiment of the present invention, mainly showing the layout of the V4 conductive via. Figure 9 As shown, the memory array 1 is in the band region SR, corresponding to the pad P DS41 , pad P DW4 and pad P DS42 There are multiple staggered conductive through holes V DS41 , conductive via V DW4 and conductive vias V DS42 .

[0101] See also Figure 10, which is a schematic diagram of a memory array according to an embodiment of the present invention, which mainly shows the layout of the M5 metal layer. Figure 10 As shown, the memory array 1 further includes a plurality of word lines WL and source lines SL located in the M5 metal layer. The word lines WL and the source lines SL are parallel to each other and extend along the second direction D2. The word lines WL are electrically connected to the corresponding conductive vias V DW4 , the source line SL is electrically connected to the corresponding conductive through hole V DS41 and conductive vias V DS42 .

[0102] See also Figure 11 , which is a schematic diagram of a partial structure of a sub-array of a memory array according to an embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. For the convenience of explanation, the dielectric layer has been omitted in the figure. Figure 11 As shown, the drain region DD of the transistor T is connected to the drain contact plug C via the drain contact plug C. D Electrically connected to the corresponding pad P1, and then through the conductive through hole V A1 The active magnetic storage element M is electrically connected to the corresponding storage node pad P2, wherein the storage node pad P2 extends in the first direction D1 toward the common source line. A tungsten through hole 140 is provided on the storage node pad P2, wherein the tungsten through hole 140 is approximately aligned with the gate line GL below. A is directly disposed above the tungsten via 140, and the conductive via V A3 Directly set on the active magnetic storage element M A Directly above the conductive via V A3 The bit lines BL are electrically connected to the bit lines BL extending along the first direction D1 . Above the bit lines BL are word lines WL and source lines SL extending along the second direction D2 .

[0103] See also Figure 12 , which is a schematic diagram of a portion of the structure of the sub-array MAS and the band region SR of the memory array according to an embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figure 12 As shown, the active magnetic storage element M A and a dummy magnetic storage element M D The storage node pads P2 in the sub-array MAS and the pads P in the band region SR are evenly distributed in a staggered arrangement to achieve a high-density memory layout. S1 , pad P S2 and pad P W In the second direction D1, the pads P are not aligned in a straight line, but are staggered. S1 , pad P S2and pad P W No tungsten through-holes are arranged on the dummy magnetic storage element M. D The bottom electrode is not directly electrically connected to the pad P in the band region SR. W . Conductive via V PS2 Electrically connected to the pad P below S2 . Pad P VS2 Covering conductive via V PS2 and a dummy magnetic storage element M D , and set the dummy magnetic storage element M D The upper electrode is electrically connected to the conductive via V PS2 .from Figure 1 It can be clearly seen that the common source line CSL located in the M1 metal layer is electrically connected to the source line SL located in M5 via the second source line strap SLS2 and the connection paths formed in V1, M2, V2, M3, V3, M4 and V4.

[0104] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A memory array, characterized in that: Include: at least one strip region comprising a plurality of discontinuous source line strips and a plurality of discontinuous word line strips; at least two subarrays comprising a plurality of interleaved active magnetic storage elements, wherein the at least two subarrays are separated by the at least one stripe region, one of the at least two subarrays is disposed above the at least one stripe region, and another of the at least two subarrays is disposed below the at least one stripe region; a plurality of common source lines extending along a second direction within the at least two sub-arrays, wherein one of the plurality of common source lines extending from the one of the at least two sub-arrays above the at least one strip area is disconnected from one of the plurality of common source lines extending from the other of the at least two sub-arrays below the at least one strip area and is electrically connected to one of the plurality of discontinuous source line strips; and A plurality of staggered dummy magnetic storage elements are disposed within the at least one zone.

2. The memory array according to claim 1, wherein: The plurality of interleaved active magnetic storage elements and the plurality of interleaved dummy magnetic storage elements are evenly distributed across the at least two sub-arrays and the at least one stripe area.

3. The memory array according to claim 1 , wherein: The plurality of interleaved dummy magnetic storage elements include dummy magnetic tunneling junction elements.

4. The memory array according to claim 3, wherein: A bottom electrode of the dummy magnetic tunneling junction element is not electrically connected to the plurality of discontinuous source line straps or the plurality of discontinuous word line straps.

5. The memory array according to claim 1, wherein The plurality of discontinuous source line strips include a plurality of first source line strips extending along a first direction and a plurality of second source line strips extending along the first direction.

6. The memory array according to claim 5, wherein: The plurality of first source line straps extending along the first direction and the plurality of second source line straps extending along the first direction sandwich the plurality of word line straps extending along the first direction.

7. The memory array according to claim 5, wherein: Each of the plurality of first source line straps is connected to each of the plurality of common source lines extending along the second direction.

8. The memory array according to claim 7, wherein: The first direction is orthogonal to the second direction.

9. The memory array according to claim 5, wherein: The memory array further includes a first dummy diffusion region extending along the first direction and directly below the plurality of first source line straps.

10. The memory array according to claim 9, wherein: The memory array further includes a second dummy diffusion region extending along the first direction and directly below the plurality of second source line straps.

11. The memory array according to claim 10, wherein: No diffusion region is provided between the first dummy diffusion region and the second dummy diffusion region.

12. The memory array according to claim 1, wherein: Each of the plurality of interleaved active magnetic storage elements is electrically connected to a storage node pad through a tungsten via.

13. The memory array according to claim 1, wherein: No tungsten vias are arranged in the at least one zone area.

14. The memory array according to claim 7, wherein: The memory array further includes a plurality of gate lines extending along the second direction.

15. The memory array of claim 14, wherein: The plurality of staggered active magnetic memory elements include a plurality of first active magnetic memory elements arranged in a first column and a plurality of second active magnetic memory elements arranged in a second column, wherein the plurality of first active magnetic memory elements arranged in the first column and the plurality of second active magnetic memory elements arranged in the second column are respectively aligned with the plurality of gate lines extending along the second direction.

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