Semiconductor integrated circuit and control method of semiconductor integrated circuit

Abstract

An embodiment of the present application provides a semiconductor integrated circuit and a control method of the semiconductor integrated circuit capable of suppressing power consumption without increasing chip area. The semiconductor integrated circuit of an embodiment includes a first signal line having a first portion and a second portion, a second signal line having a third portion and a fourth portion, a first inverter disposed between the first portion and the second portion of the first signal line, a second inverter disposed between the third portion and the fourth portion of the second signal line, and a control circuit. In a first period, a first signal is input to the first portion of the first signal line in response to a first clock signal. In a second period after the first period, a second signal is input to the third portion of the second signal line in response to a second clock signal. The first inverter outputs a first inverted signal obtained by logically inverting the first signal to the second portion. The second inverter outputs a second inverted signal obtained by logically inverting the second signal to the fourth portion. The control circuit makes the second signal line in a floating state in the first period and makes the first signal line in a floating state in the second period.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-25415 (filed on February 19, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The embodiments of the present invention relate to a semiconductor integrated circuit and a control method for the semiconductor integrated circuit. Background Technology

[0004] In semiconductor integrated circuits, when signals are transmitted through signal lines, the capacitive coupling between the signal lines increases power consumption. Increasing the spacing between signal lines reduces the coupling capacitance, thus suppressing the increase in power consumption, but this increases the chip area. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor integrated circuit that can suppress power consumption without increasing the chip area, and a method for controlling the semiconductor integrated circuit.

[0006] One embodiment of a semiconductor integrated circuit includes: a first signal line having a first portion and a second portion; a second signal line having a third portion and a fourth portion; a first inverter disposed between the first portion and the second portion of the first signal line; a second inverter disposed between the third portion and the fourth portion of the second signal line; and control circuitry. During a first period, a first signal is input to the first portion of the first signal line in response to a first clock signal. During a second period following the first period, a second signal is input to the third portion of the second signal line in response to a second clock signal. The first inverter outputs a first inverted signal, obtained by logically inverting the first signal, to the second portion. The second inverter outputs a second inverted signal, obtained by logically inverting the second signal, to the fourth portion. The control circuitry keeps the second signal line in a floating state during the first period and keeps the first signal line in a floating state during the second period. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a memory system that includes a non-volatile memory comprising a semiconductor integrated circuit having an embodiment.

[0008] Figure 2 This is a block diagram illustrating the configuration of a non-volatile memory in an implementation method.

[0009] Figure 3A This is an example of a sequence of instructions that indicates a read operation from non-volatile memory.

[0010] Figure 3BThis is an example of a sequence of instructions related to the data read operation of non-volatile memory.

[0011] Figure 4 This is a block diagram illustrating the partial configuration of the non-volatile memory in an implementation method.

[0012] Figure 5 This is a circuit diagram illustrating the first example of an invert repeater circuit according to an implementation method.

[0013] Figure 6 yes Figure 5 The timing diagram shows an example of the circuit's operation.

[0014] Figure 7 This is a circuit diagram for generating EQ and / EQ signals.

[0015] Figure 8 This is a circuit diagram illustrating a second example of an inverted repeater circuit according to an implementation method.

[0016] Figure 9 yes Figure 8 The timing diagram shows an example of the circuit's operation.

[0017] Figure 10 This is a schematic diagram of the repeater circuit of the first comparative example.

[0018] Figure 11 yes Figure 10 The timing diagram shows an example of the circuit's operation.

[0019] Figure 12 This is a schematic diagram showing the configuration of the signal lines in the first comparative example.

[0020] Figure 13 This is a schematic diagram illustrating the configuration of the signal lines of the data bus in an implementation method.

[0021] Figure 14 This is a schematic diagram showing the configuration of the signal lines in the second comparative example.

[0022] Figure 15 This is a table that compares the current of the power supply.

[0023] Figure 16 This is a schematic diagram used to illustrate the change in the potential of a signal line (period 01).

[0024] Figure 17 This is a schematic diagram used to illustrate the change in the potential of a signal line (period 02).

[0025] Figure 18 This is a schematic diagram (cycle 1) used to illustrate the potential changes of the signal lines generated by the equalizer circuit.

[0026] Figure 19 This is a schematic diagram (cycle 2) used to illustrate the potential changes of the signal lines generated by the equalizer circuit.

[0027] Figure 20 This is a schematic diagram (cycle 3) used to illustrate the potential changes of the signal lines generated by the equalizer circuit.

[0028] Figure 21 This is a schematic diagram illustrating the operation of a semiconductor integrated circuit, used to explain variations of the implementation method. Detailed Implementation

[0029] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the drawings, the same symbols are used to refer to the same parts and the descriptions are omitted.

[0030] The semiconductor integrated circuit of the embodiments of the present invention is, for example, Figure 1 The memory system shown includes non-volatile memory 2. Non-volatile memory 2 is a semiconductor memory capable of non-volatilely storing data. Non-volatile memory 2 may include, for example, NAND (Not And) flash memory. Memory controller 1 controls the operation of non-volatile memory 2. The host device may be, for example, a personal computer, a mobile terminal, or other electronic device.

[0031] First of all, Figure 1 The memory system shown will be described below. Furthermore, in the following description, signals DQ<7:0> refer to the set of signals DQ<0>, DQ<1>, ..., DQ<7>, each a 1-bit signal. Signals DQ<7:0> are 8-bit signals.

[0032] The memory controller 1 receives commands from the host and controls the non-volatile memory 2 based on the received commands. Specifically, the memory controller 1 writes data instructed by the host to be written to the non-volatile memory 2, reads data instructed by the host to be read from the non-volatile memory 2, and sends it to the host. The non-volatile memory cell to which the write is to is specified by the memory controller 1. Hereinafter, the non-volatile memory cell of the non-volatile memory 2 will also be referred to as a "memory cell".

[0033] The memory controller 1 and the non-volatile memory 2 transmit and receive signals conforming to the interface standard of the memory controller 1 and the non-volatile memory 2 via individual signal lines. The signals transmitted and received between the memory controller 1 and the non-volatile memory 2 are / CE, / RB, CLE, ALE, / WE, / RE, RE, / WP, DQ<7:0>, DQS, / DQS, etc.

[0034] The / CE signal is the chip enable signal used to enable non-volatile memory 2. The / RB signal is the ready-to-work signal indicating whether non-volatile memory 2 is in a ready state (receiving commands from external sources) or a busy state (not receiving commands from external sources). The CLE signal is the instruction latch enable signal sent to non-volatile memory 2 when the CLE signal is at a high level (H), indicating that the DQ<7:0> signal represents an instruction. The ALE signal is the address latch enable signal sent to non-volatile memory 2 when the ALE signal is at a high level (H), indicating that the DQ<7:0> signal represents an address.

[0035] The signal / WE is a write enable signal indicating that the signal DQ<7:0> sent to non-volatile memory 2 will be stored in non-volatile memory 2. In Single Data Rate (SDR) mode, the signal DQ<7:0>, representing an instruction, address, or data, sent to non-volatile memory 2 at the rising edge of the signal / WE is stored. Similarly, in Double Data Rate (DDR) mode, the signal DQ<7:0>, representing an instruction or address, sent to non-volatile memory 2 at the rising edge of the signal / WE is stored. The signal / WE is activated whenever an instruction, address, or data is received from non-volatile memory 2 via memory controller 1.

[0036] The / RE signal is a read enable signal that instructs the memory controller 1 to read the signal DQ<7:0> from the non-volatile memory 2. The RE signal is the complementary signal to the / RE signal. For example, the / RE and RE signals are used to control the timing of the operation of the non-volatile memory 2 when the output signal DQ<7:0> is displayed. More specifically, in single data rate mode, the signal DQ<7:0> is output as data to the non-volatile memory 2 at the falling edge of the / RE signal. Furthermore, in double data rate mode, the signal DQ<7:0> is output as data to the non-volatile memory 2 at both the falling and rising edges of the / RE signal.

[0037] The / WP signal is a write protection signal that instructs non-volatile memory 2 to disable data writing. Signals DQ<7:0> are data entities transmitted and received between non-volatile memory 2 and memory controller 1, including instructions (CMD), addresses (ADD), and data (DAT). Data DAT contains both write and read data.

[0038] The signal DQS is a data strobe signal used to control the timing of the operation of the non-volatile memory 2 related to the signal DQ<7:0>. The signal / DQS is the complementary signal to signal DQS. Signals DQS and / DQS are generated, for example, based on signals RE and / RE. More specifically, in double data rate mode, the signal DQ<7:0>, which indicates that data will be stored in the non-volatile memory 2 at the falling and rising edges of signal DQS, is used as input. Additionally, in double data rate mode, signal DQS is generated based on the falling and rising edges of signal / RE and is output from the non-volatile memory 2 along with the data signal DQ<7:0>.

[0039] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected by a bus 16.

[0040] RAM11 temporarily stores data received from the host before storing it in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 before sending it to the host. RAM11 is, for example, a general-purpose semiconductor memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0041] Processor 12 controls the operation of the entire memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. Processor 12, for example, responds to a data read command received from the host and issues the read command to non-volatile memory 2. This operation is performed similarly during data writes. Processor 12 determines the storage area (storage region) of non-volatile memory 2 for the data accumulated in RAM 11. Furthermore, processor 12 has the function of performing various operations on the read data from non-volatile memory 2.

[0042] Host interface 13 connects to the host and performs processing that conforms to the interface standard between the host and the host. For example, host interface 13 transmits commands and data received from the host to processor 12. In addition, host interface 13 sends data read from non-volatile memory 2, responses from processor 12, etc., to the host.

[0043] ECC circuit 14 encodes the data stored in RAM 11 to generate codewords. In addition, ECC circuit 14 decodes the codewords read from non-volatile memory 2.

[0044] The memory interface 15 is connected to the non-volatile memory 2 via a bus, performing communication with the non-volatile memory 2. According to the instructions of the processor 12, the memory interface 15 sends the instruction CMD, address ADD, and write data to the non-volatile memory 2. Additionally, the memory interface 15 receives read data from the non-volatile memory 2.

[0045] Figure 1 The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0046] When a write command is received from the host, the memory system operates as follows: Processor 12 temporarily stores the data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword to memory interface 15. Memory interface 15 writes the input codeword to non-volatile memory 2.

[0047] When a read command is received from the host, the memory system operates as follows: The memory interface 15 inputs the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in RAM 11. The processor 12 sends the data stored in RAM 11 to the host via the host interface 13.

[0048] Figure 2 This is a block diagram illustrating an example configuration of non-volatile memory 2. Non-volatile memory 2 includes a memory cell array 21, input / output circuitry 22, logic control circuitry 24, registers 26, a sequencer 27, voltage generation circuitry 28, a line decoder 30, a sense amplifier 31, and an inverting repeater circuit 40. Non-volatile memory 2 also includes input / output pads 32, logic control pads 34, and power input terminals 35.

[0049] The memory cell array 21 contains multiple memory cells (not shown) that correspond to word lines and bit lines.

[0050] Input / output circuit 22 transmits and receives signals DQ<7:0>, DQS, and / DQS with memory controller 1. Input / output circuit 22 transfers the instruction CMD and address ADD within signal DQ<7:0> to register 26. Additionally, input / output circuit 22 transmits and receives write and read data with sense amplifier 31.

[0051] The logic control circuit 24 receives signals / CE, CLE, ALE, / WE, / RE, RE, / WP, and / RB from the memory controller 1. Additionally, the logic control circuit 24 transmits signal / RB to the memory controller 1, notifying the external system of the state of the non-volatile memory 2.

[0052] Register 26 stores the instruction CMD and the address ADD. Register 26 transmits the address ADD to the line decoder 30 and the sense amplifier 31, and transmits the instruction CMD to the sequencer 27.

[0053] Sequencer 27 receives instruction CMD and controls the entire non-volatile memory 2 according to the sequence of received instruction CMD.

[0054] The voltage generation circuit 28 generates the voltages required for data writing, data reading, and data erasure based on instructions from the sequencer 27. Various voltages are supplied from the voltage generation circuit 28 to the line decoder 30, the sense amplifier 31, and the memory cell array 21 based on the address from the register 26.

[0055] The line decoder 30 receives the block address and line address from the address ADD in register 26. The line decoder 30 selects the block based on the block address and selects the word line based on the line address.

[0056] When reading data, the sensing amplifier 31 senses the read data read from the memory cell to the bit line and transmits the sensed read data to the input / output circuit 22. When writing data, the sensing amplifier 31 transmits the written data to the memory cell via the bit line.

[0057] Data transfer between the sensing amplifier 31 and the input / output circuit 22 is performed via the data bus YIO. Data written to and read from the non-volatile memory 2 is transmitted via the data bus YIO.

[0058] The reverse repeater circuit 40 is positioned near the center of the data bus YIO. The reverse repeater circuit 40 can suppress the increase in power supply current flowing through the data bus YIO, as detailed below.

[0059] The input / output pad group 32 includes multiple terminals (pads) corresponding to signals DQ<7:0> and DQS, / DQS, used to transmit and receive signals containing data between the non-volatile memory 2 and the memory controller 1.

[0060] The logic control pad group 34 includes multiple terminals (pads) corresponding to signals / CE, CLE, ALE, / WE, / RE, RE, / WP, and / RB, used to send and receive signals between the non-volatile memory 2 and the memory controller 1.

[0061] The power input terminal group 35 includes multiple terminals for receiving power supply voltages Vcc, VccQ, and ground voltage Vss, used to supply various operating power sources to the non-volatile memory 2 from the outside. The power supply voltage Vcc is the circuit power supply voltage typically supplied externally as the operating power source. For example, the power supply voltage Vcc is 2.5V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. For example, the power supply voltage VccQ is 1.2V.

[0062] Figure 3A This represents an example of an instruction sequence that instructs a read operation of non-volatile memory 2. Figure 3B This represents an example of a sequence of instructions related to the action of reading data from non-volatile memory 2.

[0063] like Figure 3A As shown, during the read operation, memory controller 1 toggles the / WE signal and simultaneously issues the read instruction "00h", five consecutive cycles of address ADD, and the instruction "30h", sending them to non-volatile memory 2. The read instruction "00h" commands data to be read from the memory cell array 21 of non-volatile memory 2. The instruction "30h" commands the start of the read operation. When non-volatile memory 2 receives the instruction "30h", it begins reading data from the memory cell array 21, notifying memory controller 1 that the signal / RB is at level L and that non-volatile memory 2 is in a busy state. After the data reading from the memory cell array 21 is completed, non-volatile memory 2 notifies memory controller 1 that the signal / RB is at level H and that non-volatile memory 2 is in a ready state.

[0064] After confirming that the non-volatile memory 2 is ready, memory controller 1, such as Figure 3BAs shown, the switching signals / RE and RE are used. The non-volatile memory 2 synchronously transmits the read data as the signal DQ<7:0> to the memory controller 1 along with the signals / RE and RE. Additionally, the non-volatile memory 2 synchronously switches the signals DQS and / DQS along with the signal DQ<7:0> and transmits it to the memory controller 1.

[0065] Figure 4 This is a block diagram showing the components of a non-volatile memory 2, including an input / output circuit 22, a sense amplifier 31, an inverting repeater circuit 40, and a data bus YIO. The input / output circuit 22 transmits and receives data between itself and the sense amplifier 31 via the data bus YIO. The data bus YIO includes multiple signal lines D. For example, the data bus YIO includes 128 signal lines D.

[0066] The sense amplifier 31 includes a sense amplifier assembly 31A connected to bit lines BL0-BLm, a data register 31B connected to the sense amplifier assembly 31A, and a data multiplexer 31C connected to the data register 31B. The number of bit lines is, for example, approximately 130,000. The sense amplifier assembly 31A senses and reads the read data to the bit lines and transmits the write data to the memory cell via the bit lines. The data register 31B stores the read data or the write data. The data multiplexer 31C selects the data transmitted on the signal line D constituting the data bus YIO from the data transmitted on the bit lines BL0-BLm.

[0067] The input / output circuit 22 may also include a bus width conversion circuit 221. For example, the conversion circuit 221 converts the bus width of a data bus YIO containing 128 signal lines to a bus width containing 8 signal lines for transmitting signals DQ<7:0> respectively. The conversion circuit 221 may also be a FIFO (First In First Out) circuit. The sense amplifier 31 operates with a power supply voltage Vcc (e.g., 2.5V) to the conversion circuit 221. The conversion circuit 221 operates with a power supply voltage VccQ (e.g., 1.2V) to the memory controller 1.

[0068] The reverse repeater circuit 40 is controlled by the control circuit 50. Figure 4 In this diagram, the control circuit 50 is shown as a circuit block distinct from the input / output circuit 22 and the logic control circuit 24. However, the control circuit 50 may also be configured as part of the input / output circuit 22 and / or the logic control circuit 24.

[0069] Figure 5 The diagram shows an example of the configuration of the reverse repeater circuit 40. Figure 5The reverse repeater circuit 40 shown is connected to the first signal line D1 and the second signal line D2. At least a portion of the first signal line D1 and at least a portion of the second signal line D2 extend in the same direction and are adjacent to each other. For example, the first signal line D1 and the second signal line D2 are adjacent signal lines D among a plurality of signal lines D constituting the data bus YIO. The first signal line D1 and the second signal line D2 are capacitively coupled to each other. Furthermore, it is not limited to the first signal line D1 being entirely adjacent to the second signal line D2. Even when at least a portion of the first signal line D1 is adjacent to at least a portion of the second signal line D2, capacitive coupling will still exist between them.

[0070] Hereinafter, signal line D1 and signal line D2 will also be referred to as "signal line D". Signal line D1 includes part D1a and part D1b. Similarly, signal line D2 includes part D2a and part D2b. Here, to simplify the explanation, the operation of the reverse repeater circuit 40 with two signal lines will be illustrated by example. In addition, the capacitance between signal lines generated by capacitive coupling will also be referred to as "coupling capacitance".

[0071] Furthermore, the following explanation uses a read operation as an example. That is, the memory controller 1 switches signals / RE and RE, and the non-volatile memory 2 synchronously transmits the read data as a signal DQ<7:0> to the memory controller 1 in accordance with signals / RE and RE. This operation will be explained using this example. In addition, in the following explanation, a signal level of H is defined as "signal on", and a signal level of L is defined as "signal off".

[0072] The reverse repeater circuit 40 operates in response to a first clock signal CLKA and a second clock signal CLKB. The first clock signal CLKA transitions between a first level (e.g., H level) and a second level (e.g., L level), which is different from the first level. The second clock signal CLKB transitions between a third level (e.g., H level) and a fourth level (e.g., L level), which is different from the third level. For example, the first level is higher than the second level, and the third level is higher than the fourth level. Alternatively, the first level may be lower than the second level, and the third level may be lower than the fourth level.

[0073] When the first clock signal CLKA is turned on, the first signal DataA is input to the first part D1a of the first signal line D1. The inverting repeater circuit 40 outputs the signal obtained by logically inverting the first signal DataA (hereinafter referred to as the "inverted signal") to the second part D1b of the first signal line D1. The first receiving circuit 61 connected to the first signal line D1 receives the inverted signal of the first signal DataA.

[0074] When the second clock signal CLKB is turned on, the second signal DataB is input to the third part D2a of the second signal line D2. The inverting repeater circuit 40 outputs the inverted signal of the second signal DataB to the fourth part D2b of the second signal line D2. The second receiving circuit 62 connected to the second signal line D2 receives the inverted signal of the second signal DataB.

[0075] The reverse repeater circuit 40 is connected to the first receiving circuit 61 and the second receiving circuit 62. Figure 5 An example is shown where the first receiving circuit 61 and the second receiving circuit 62 are flip-flops (FF). In this case, if the first clock signal CLKA is turned on, then the first receiving circuit 61 stores the inverted signal of the first signal DataA (the first inverted signal). If the second clock signal CLKB is turned on, then the second receiving circuit 62 stores the inverted signal of the second signal DataB (the second inverted signal).

[0076] Figure 6 The timing diagram shows an example of the operation of the reverse repeater circuit 40. Figure 6 In this diagram, V_CLK is the potential of the reference clock signal CLK, which serves as the operating reference for the non-volatile memory 2. V_CLKA is the potential of the first clock signal CLKA, and V_CLKB is the potential of the second clock signal CLKB. Additionally, V_DataA is the potential of the first signal line D1 (more specifically, the potential of the first portion D1a of the first signal line D1), and V_DataB is the potential of the second signal line D2 (more specifically, the potential of the third portion D2a of the second signal line D2). V_EQ is the potential of the EQ signal. Hereinafter, the signal names in the timing diagram will be the same as described above.

[0077] like Figure 6 As shown, the period of the first clock signal CLKA and the period of the second clock signal CLKB are the same as the period of the reference clock signal CLK.

[0078] However, the duration of the on-time of the first clock signal CLKA and the second clock signal CLKB is half the duration of the on-time of the reference clock signal CLK. Furthermore, the on-time of the first clock signal CLKA is offset from the on-time of the second clock signal CLKB by an amount equivalent to half a cycle of the reference clock signal CLK.

[0079] like Figure 6As shown, the period from when the first clock signal CLKA is turned on until the second clock signal CLKB is turned on after the first clock signal CLKA is turned off is called "the first cycle C1". Similarly, the period from when the second clock signal CLKB is turned on until the first clock signal CLKA is turned on after the second clock signal CLKB is turned off is called "the second cycle C2". The first clock signal CLKA is turned off during the second cycle C2. The second clock signal CLKB is turned off during the first cycle C1. Hereinafter, both the first cycle C1 and the second cycle C2 will be referred to as a "cycle". The first cycle C1 and the second cycle C2 repeat alternately.

[0080] In cycle 1 (C1), the first signal DataA is input to signal line D1 in response to the first clock signal CLKA. In cycle 2 (C2), the second signal DataB is input to signal line D2 in response to the second clock signal CLKB. In other words, in cycle 1 (C1), the first signal DataA is input to the first portion (D1a) of signal line D1 in response to the first clock signal CLKA. In cycle 2 (C2), the second signal DataB is input to the third portion (D2a) of signal line D2 in response to the second clock signal CLKB.

[0081] The inverter repeater circuit 40 includes a first inverter repeater 411 disposed on the first signal line D1 and a second inverter repeater 412 disposed on the second signal line D2. In other words, the first inverter repeater 411 is disposed between the first portion D1a and the second portion D1b of the first signal line D1, and the second inverter repeater 412 is disposed between the third portion D2a and the fourth portion D2b of the second signal line D2. Hereinafter, both the first inverter repeater 411 and the second inverter repeater 412 will be referred to as "inverter repeater 41" or simply "inverter 41".

[0082] The first inverter 411 (first inverter 411) outputs the inverted signal of the signal received at the input terminal from the output terminal when the first clock signal CLKA is at level H. Conversely, when the first clock signal CLKA is at level L, the first inverter 411 does not output a signal from the output terminal regardless of the potential level of the signal received at the input terminal. The first signal DataA, input to the first signal line D1, is input to the first inverter 411 in response to the falling edge of the first clock signal CLKA. The first inverter 411 outputs the inverted signal of the first signal DataA to the first signal line D1, and the first receiving circuit 61 receives the inverted signal of the first signal DataA. In other words, the first inverter 411 outputs the inverted signal of the first signal DataA, which is input to the first part D1a of the first signal line D1, to the second part D1b of the first signal line D1.

[0083] The second inverter 412 (second inverter 412) outputs the inverted signal of the signal received at the input terminal from the output terminal when the second clock signal CLKB is at level H. Conversely, when the second clock signal CLKB is at level L, the second inverter 412 does not output a signal from the output terminal regardless of the potential level of the signal received at the input terminal. The second signal DataB, input to the second signal line D2, is input to the second inverter 412 in response to the falling edge of the second clock signal CLKB. The second inverter 412 outputs the inverted signal of the second signal DataB to the second signal line D2, and the second receiving circuit 62 receives the inverted signal of the second signal DataB. In other words, the second inverter 412 outputs the inverted signal of the second signal DataB, which is input to the third part D2a of the second signal line D2, to the fourth part D2b of the second signal line D2. The timing at which the second receiving circuit 62 receives the inverted signal of the second signal DataB is offset from the timing at which the first receiving circuit 61 receives the inverted signal of the first signal DataA by an amount equivalent to half a cycle of the reference clock signal CLK.

[0084] In non-volatile memory 2, Figure 4 The control circuit 50 shown generates a reference clock signal CLK based on the signal / RE and signal RE received from the memory controller 1, and generates a first clock signal CLKA and a second clock signal CLKB based on the generation of the reference clock signal CLK. For example, the pulse generated from the rising edge of the reference clock signal CLK is set as the first clock signal CLKA, and the pulse generated from the falling edge of the reference clock signal CLK is set as the second clock signal CLKB. In this case, the control circuit 50 functions, for example, as a frequency divider circuit that divides the reference clock signal CLK.

[0085] The non-volatile memory 2 transmits data with the memory controller 1 synchronously with the signals / RE and RE. Therefore, the control circuit 50 can also use the signals / RE and RE to generate the first clock signal CLKA and the second clock signal CLKB.

[0086] In the first cycle (first period) C1, control circuit 50 makes the second signal line D2 float, and in the second cycle (second period) C2, it makes the first signal line D1 float. Additionally, during the period after the first clock signal CLKA is disconnected in the first cycle C1, and during the period after the second clock signal CLKB is disconnected in the second cycle C2, control circuit 50 makes both the first signal line D1 and the second signal line D2 float.

[0087] That is, during the period when the first clock signal CLKA is at level H in the first cycle C1 (the third cycle C1a), the second signal line D2 is in a floating state. During the period when the first clock signal CLKA is at level L in the first cycle C1 (the fourth cycle C1b), both the first signal line D1 and the second signal line D2 are in a floating state.

[0088] Furthermore, during the period when the second clock signal CLKB is at level H in the second cycle C2 (the fifth cycle) C2a, the first signal line D1 is in a floating state. During the period when the second clock signal CLKB is at level L in the second cycle C2 (the sixth cycle) C2b, both the first signal line D1 and the second signal line D2 are in a floating state.

[0089] The reverse repeater circuit 40 includes an equalizer circuit 42. The equalizer circuit 42 averages the potentials of the first reverse repeater 411 (floating state) on the first signal line D1 and the second reverse repeater 412 (floating state) on the second signal line D2. This potential averaging is referred to as "level adjustment." The equalizer circuit 42 performs this level adjustment when both the first signal line D1 and the second signal line D2 are in a floating state. Furthermore, regarding the potentials of the first reverse repeater 411 and the second reverse repeater 412, "front potential" refers to the potential of the signal line D on the input side of the reverse repeater 41, and "back potential" refers to the potential of the signal line D on the output side of the reverse repeater 41 (the same applies below).

[0090] Generally speaking, the potential of a floating signal line is easily affected by capacitive coupling with adjacent signal lines. That is, the potential of the first floating signal line D1 is influenced by the potential of the second floating signal line D2. Furthermore, the potential of the second floating signal line D2 is influenced by the potential of the first floating signal line D1.

[0091] The floating signal line D is affected by other signal lines D through capacitive coupling, which may lead to an increase in power supply current and increased power consumption of the circuit. The equalizer circuit 42 can suppress this increase in power consumption by adjusting the level, as detailed below. First, the structure and operation of the equalizer circuit 42 will be explained below.

[0092] As explained above, in response to the first clock signal CLKA, the first signal DataA is input to the first signal line D1. The first clock signal CLKA is turned on in the first half of the first cycle C1 and turned off in the second half of the first cycle C1. Therefore, the first signal DataA is input to the first signal line D1 in the first half of the first cycle C1. The control circuit 50 keeps the first signal line D1 in a floating state in the second half of the first cycle C1. Moreover, the equalizer circuit 42 adjusts the level of the first signal line D1 in the second half of the first cycle C1.

[0093] Additionally, in response to the second clock signal CLKB, the second signal DataB is input to the second signal line D2. The second clock signal CLKB is turned on in the first half of the second cycle C2 and turned off in the second half of the second cycle C2. Therefore, the second signal DataB is input to the second signal line D2 in the first half of the second cycle C2. The control circuit 50 keeps the second signal line D2 in a floating state in the second half of the second cycle C2. Moreover, the equalizer circuit 42 adjusts the level of the second signal line D2 in the second half of the second cycle C2.

[0094] In other words, during the period C1b of the first clock signal CLKA in the first cycle C1 (the fourth period), when both the first signal line D1 and the second signal line D2 are in a floating state, the equalizer circuit 42 electrically connects the first part D1a and the second part D1b of the first signal line D1, and electrically connects the third part D2a and the fourth part D2b of the second signal line D2. Similarly, during the period C2b of the second cycle C2 (the sixth period), when both the first signal line D1 and the second signal line D2 are in a floating state, the equalizer circuit 42 electrically connects the first part D1a and the second part D1b of the first signal line D1, and electrically connects the third part D2a and the fourth part D2b of the second signal line D2.

[0095] Through level adjustment by equalizer circuit 42, the potentials before and after the first reverse repeater 411 are made consistent, and the potentials before and after the second reverse repeater 412 are made consistent. In each cycle, equalizer circuit 42 performs level adjustment to make the potentials before and after the reverse repeater 41 of signal line D in floating state consistent.

[0096] like Figure 5 As shown, the equalizer circuit 42 has a first equalizer 421 and a second equalizer 422. The first equalizer 421 electrically connects the first inverted repeater 411 of the first signal line D1 during level adjustment by the equalizer circuit 42. The second equalizer 422 electrically connects the second inverted repeater 412 of the second signal line D2 during level adjustment by the equalizer circuit 42. Both the first equalizer 421 and the second equalizer 422 are referred to as "equalizer 420".

[0097] The first equalizer 421 and the first reverse repeater 411 are connected in parallel to the first signal line D1. When the first equalizer 421 is on, the first and second ends of the first reverse repeater 411 in the first signal line D1 are electrically connected. Therefore, by turning on the first equalizer 421, charge moves between the first and second ends of the first reverse repeater 411. Through this charge movement, the charge stored on the input side and the charge stored on the output side of the first reverse repeater 411 in the first signal line D1 are neutralized. As a result, the first signal line D1 is short-circuited across the first reverse repeater 411 via the first equalizer 421, thereby aligning the potential of the first signal line D1 across the first reverse repeater 411.

[0098] The second equalizer 422 and the second reverse repeater 412 are connected in parallel to the second signal line D2. When the second equalizer 422 is on, the front and rear ends of the second reverse repeater 412 in the second signal line D2 are electrically connected. Therefore, by turning on the second equalizer 422, charge moves between the front and rear ends of the second reverse repeater 412. Through this charge movement, the charge stored on the input side and the charge stored on the output side of the second reverse repeater 412 in the second signal line D2 are neutralized. As a result, the second signal line D2 is short-circuited before and after the second reverse repeater 412 via the second equalizer 422, thereby making the potential of the second signal line D2 consistent before and after the second reverse repeater 412.

[0099] The control circuit 50 controls the on / off operation of the equalizer 420 based on the EQ signal and the / EQ signal obtained by inverting the EQ signal. When the EQ signal is on and the / EQ signal is off, the first equalizer 421 and the second equalizer 422 are turned on, and the first inverting repeater 411 in the first signal line D1 is short-circuited before and after, and the second inverting repeater 412 in the second signal line D2 is short-circuited before and after. Figure 6 As shown, when both the first clock signal CLKA and the second clock signal CLKB are disconnected, the EQ signal is turned on, and at this time, the / EQ signal is disconnected.

[0100] also, Figure 6 In the diagram, the thick solid lines representing potentials V_DataA and V_DataB indicate the potential of signal line D when an input signal is received. The dashed lines representing potentials V_DataA and V_DataB indicate the potential of signal line D in a floating state affected by capacitive coupling. The arrows representing potentials V_DataA and V_DataB indicate the potential changes of signal line D caused by level adjustments. Figure 6 In the diagram, potential Vd10 is the potential V_DataA after level adjustment, and potential Vd20 is the potential V_DataB after level adjustment.

[0101] As described above, the equalizer circuit 42 can electrically connect the first part D1a and the second part D1b in the first signal line D1, and can electrically connect the third part D2a and the fourth part D2b in the second signal line D2. The equalizer 420 is, for example, a transfer gate composed of an n-type MOS (Metal Oxide Semiconductor) transistor and a p-type MOS transistor. Alternatively, the equalizer 420 can be composed of a single transistor.

[0102] EQ signals and / EQ signals can also use, for example, the first clock signal CLKA and the second clock signal CLKB, through Figure 7 The exclusive OR circuit 51 shown is generated by connecting it in series with the inverter 52. That is, the control circuit 50 can also generate an EQ signal as the XOR of the first clock signal CLKA and the second clock signal CLKB, inverting the logic value of the EQ signal to generate the / EQ signal. Both the EQ signal and the / EQ signal are referred to as the first control signal. In this way, the control circuit 50 can also use the first clock signal CLKA and the second clock signal CLKB to generate the first control signal, and use the first control signal to control the equalizer circuit 42.

[0103] The reverse repeater circuit 40 keeps one of the two adjacent signal lines D in a floating state while driving one of them. Therefore, it reduces the impact of capacitive coupling on the other adjacent signal lines D. Furthermore, the reverse repeater circuit 40 suppresses increased power consumption through level adjustment by the equalizer circuit 42.

[0104] The following explains how power consumption can be suppressed by adjusting the level of the equalizer circuit 42. The above explanation addressed the case where there are two signal lines D connected to the reverse repeater 41. However, the number of signal lines D connected to the reverse repeater 41 is arbitrary. The following explanation addresses the case where there are three signal lines D connected to the reverse repeater 41. Figure 8 Explain the operation of the reverse repeater circuit 40.

[0105] Figure 8 This is a circuit diagram illustrating the reverse repeater circuit 40 of the embodiment. The reverse repeater circuit 40 of the embodiment is connected to at least a first signal line D1, a second signal line D2, and a third signal line D3 arranged in a specific configuration. The first signal line D1 and the second signal line D2 are capacitively coupled to each other, and the second signal line D2 and the third signal line D3 are capacitively coupled to each other.

[0106] Figure 8 The reverse repeater circuit 40 shown is in Figure 5The configuration obtained by adding a third signal line D3, a third reverse repeater 413, a third equalizer 423, and a third receiving circuit 63 to the reverse repeater circuit 40 shown.

[0107] When the first clock signal CLKA is turned on, the third signal DataC is input to the third signal line D3. The third inverting repeater 413, configured along the third signal line D3, outputs the inverted signal obtained by logically inverting the third signal DataC to the third signal line D3. The third equalizer 423 electrically connects the front and rear ends of the third inverting repeater 413 on the third signal line D3 through level adjustment. The third receiving circuit 63 receives the inverted signal of the third signal DataC when the first clock signal CLKA is at level H.

[0108] In response to the first clock signal CLKA, signals are transmitted on the first signal line D1 and the third signal line D3. Additionally, in response to the second clock signal CLKB, signals are transmitted on the second signal line D2.

[0109] Figure 9 This represents the potential of the clock signal, the potential of signal line D, and the potential of the EQ signal. Figure 9 In this context, V_DataC is the potential of signal line D3 (the third signal line). Potential Vd30 is the level-adjusted potential V_DataC.

[0110] Figure 5 Signal line D1 (first signal) and signal line D2 (second signal) are shown. In contrast, Figure 8 Signal lines D1, D2, and D3 are shown. The relationship between signal line D1 and signal line D2 is equivalent to the relationship between signal line D3 and signal line D2. Figure 8 In the configuration shown where the first signal line D1 and the third signal line D3 are arranged with the second signal line D2 separated by the third signal line D2, the potential of the central second signal line D2 is affected by the potential changes of the adjacent two signal lines D.

[0111] Figure 10 This represents the repeater circuit of the first comparative example that does not have the reverse repeater circuit 40. Hereinafter, it will be... Figure 8 The operation of the reverse repeater circuit 40 in the illustrated embodiment is similar to... Figure 10 The operation of the repeater circuit in the first comparative example shown is compared.

[0112] Figure 10The diagram shows a first signal line D1 to which the first signal DataA is input, and a second signal line D2 to which the second signal DataB is input. The first signal DataA is received by a first receiving circuit 61, and the second signal DataB is received by a second receiving circuit 62. In the first comparative example, a general-purpose buffer 71 is used to relay the signals on signal line D. A "general-purpose buffer" is a buffer circuit that does not invert the logic value of the signal.

[0113] Figure 11 express Figure 10 The timing diagram shows an example of the circuit's operation. Figure 11 In this diagram, V_CLK is the potential of the reference clock signal CLK, V_DataA is the potential of signal line D1 (number 1), and V_DataB is the potential of signal line D2 (number 2). In response to the rising edge of the reference clock signal CLK, signal line D1 (number 1) is input to signal line D1. Similarly, in response to the rising edge of the reference clock signal CLK, signal line D2 (number 2) is input to signal line D2. That is, the timing of transmitting signal line D1 (number 1) and signal line D2 (number 2) is the same.

[0114] Figure 12 This indicates the configuration of signal line D in the first comparative example. The distance between the first signal line D1 and the second signal line D2 is S, and the coupling capacitance between the first signal line D1 and the second signal line D2 is C. The distance S can also be, for example, the minimum spacing d specified by circuit design rules.

[0115] Figure 13 Indicates connection to Figure 8 The signal lines D of the reverse repeater circuit 40 in the illustrated embodiment are configured as follows: The interval between the first signal line D1 and the second signal line D2 is S, and the coupling capacitance between the first signal line D1 and the second signal line D2 is C. Similarly, the interval between the second signal line D2 and the third signal line D3 is S, and the coupling capacitance between the second signal line D2 and the third signal line D3 is C. The first signal DataA is input to the first signal line D1, and the third signal DataC is input to the third signal line D3. The second signal line D2 is in a floating state.

[0116] in addition, Figure 14 This illustrates the configuration of signal line D in the second comparative example. The configuration shown in the second comparative example is based on the first comparative example, but the spacing between the first signal line D1 and the second signal line D2 is increased to 2 × S. The coupling capacitance between the first signal line D1 and the second signal line D2 is 0.5 × C.

[0117] Figure 15 express Figure 12 The example shown is of the power supply current in the configuration of signal line D in the first comparative example. Figure 13Examples of power supply current in the configuration of signal line D in the illustrated embodiment, and Figure 14 The example shown is an example of the power supply current in the configuration of signal line D in the second comparative example. Figure 15 The examples are divided into four cases, namely Example 1 to Example 4, based on the potential change of the signal line D. The values ​​of the power current Ivcc flowing in the power line with power supply voltage Vcc and the power current Ivss flowing in the power line with ground voltage Vss are shown. However, the magnitudes of the power currents shown in the first comparative example, the embodiment, and the second comparative example are relative.

[0118] Example 1 illustrates an example where the potentials of the two closest signal lines in a data transmission signal line change in opposite directions. That is, regarding Example 1, in the first and second comparative examples, the potential V_DataA of the first signal line D1 changes from H level to L level, and the potential V_DataB of the second signal line D2 changes from L level to H level. In the implementation, potential V_DataA changes from H level to L level, and potential V_DataC changes from L level to H level. In Example 1, the potential V_DataB of the second signal line D2 in the floating state of the implementation does not change. Figure 15 In the diagram, the potential V_DataB of the second signal line D2 in the floating state is represented by a dashed line (the same applies to Examples 2-4).

[0119] Example 2 illustrates an example where the potentials of the two closest signal lines in a data transmission signal line change in the same direction. That is, regarding Example 2, in the first and second comparative examples, potentials V_DataA and V_DataB change from high (H) level to low (L) level. In the implementation, potentials V_DataA and V_DataC change from high (H) level to low (L) level. In Example 2, in the implementation, the potential V_DataB of the second signal line D2 changes from high (H) level to low (L) level.

[0120] Example 3 illustrates an example where, among the two closest signal lines in a data transmission signal line configuration, the potential of one of the two signal lines changes, causing the two signal lines to reach the same potential. That is, regarding Example 3, in the first and second comparative examples, the potential V_DataA changes from H level to L level, while the potential V_DataB remains fixed at L level. In the implementation, the potential V_DataA changes from H level to L level, while the potential V_DataC remains fixed at L level. In Example 3, the potential V_DataB of the second signal line D2 in the implementation changes from H level to L level. However, the change in potential V_DataB in the implementation is less than the change in potential of the other signal lines D. This is because the effect of capacitive coupling between the signal lines D is reduced by using the equalizer circuit 42 for level adjustment. Details of reducing the effect of capacitive coupling through level adjustment will be described below.

[0121] Example 4 illustrates an example where, among the two closest signal lines in a data transmission signal line configuration, the potential of one of the two signal lines changes, resulting in different potentials between the two signal lines. Regarding Example 4, in the first and second comparative examples, potential V_DataA changes from H level to L level, while potential V_DataB remains fixed at H level. In the implementation, potential V_DataA changes from H level to L level, while potential V_DataC remains fixed at H level. In Example 4, in the implementation, potential V_DataB changes from H level to L level. However, by using the equalizer circuit 42 for level adjustment, the change in potential V_DataB is smaller.

[0122] If Figure 15 Comparing the first comparative example with the implementation, in Example 1, the power supply current Ivcc and power supply current Ivss are "2", while in the implementation, they are "1". Furthermore, in Examples 3 and 4, the power supply current Ivcc and power supply current Ivss are "1" in the first comparative example, while in the implementation, they are "0.5". Thus, the power supply current in the implementation is smaller than in the first comparative example. This is because, in the implementation, the effect of capacitive coupling is approximately half that of the first comparative example. When using the reverse repeater circuit 40 of the implementation, the effect of capacitive coupling between signal lines D is smaller because the second signal line D2, disposed between the first signal line D1 and the third signal line D3, is in a floating state.

[0123] Even when using the configuration of the second comparative example, the power supply current can be reduced compared to the configuration of the first comparative example. For example... Figure 15As shown, in Example 1, the power supply currents Ivcc and Ivss are "2" in the first comparative example, and "1" in the second comparative example. Similarly, in Examples 3 and 4, the power supply currents Ivcc and Ivss are "1" in the first comparative example, and "0.5" in the second comparative example. The capacitive coupling between signal lines D is less significant in the second comparative example because the spacing between the first signal line D1 and the second signal line D2 is larger than that in the first comparative example. However, in the configuration of the second comparative example, the circuit area increases due to the increased spacing between signal lines D. On the other hand, in the configuration of the embodiment, the spacing between signal lines D is half that of the second comparative example, and the power supply current is the same. Therefore, the reverse repeater circuit 40 according to the embodiment can suppress the increase in circuit area and reduce the power supply current.

[0124] Furthermore, the potential of the floating signal line D is easily affected by capacitive coupling with adjacent signal lines D. For example, the potential of the floating second signal line D2 is affected by the potential changes of the first signal line D1 and the third signal line D3.

[0125] The potential of signal line D is then determined from... Figure 16 The state changes of period 01 shown are as follows Figure 17 The state of period 02 shown is studied. Figure 16 and Figure 17 In this diagram, the signal line D with a change in potential is represented as "on," and the signal line D in the floating state is represented as "off." Additionally, Figure 16 and Figure 17 The arrows indicate the direction of potential change on signal line D. That is, a downward arrow in the diagram represents a change in potential from H level to L level, and an upward arrow represents a change in potential from L level to H level. This representation is also used in the following diagrams.

[0126] In cycle 01, when the potentials of the first signal line D1 and the third signal line D3 change from H level to L level, the potential of the floating second signal line D2 decreases due to capacitive coupling. Here, regarding the potential of the floating second signal line D2, the case where it is not affected by the surrounding signal lines D is set to "0", and the case where it decreases due to capacitive coupling is set to "-1". In cycle 01, by setting the second signal line D2 to a floating state, the power supply current can be reduced as described above.

[0127] In cycle 02, which immediately follows cycle 01, signal lines D1 and D3 are set to a floating state, and the potential of signal line D2 is set to level H ("1"). If the potential of signal line D2 was "0" in cycle 01, then simply raising its potential by "1" is sufficient. However, if the potential of signal line D2 has decreased to "-1" in cycle 01, then its potential must be raised by "2" to achieve a potential of "1". In other words, by keeping signal line D2 floating in cycle 01, the power supply current can be suppressed in cycle 01, but the power supply current will increase in cycle 02.

[0128] As described above, if the potential of the signal line D, whose potential changes in the floating state, is set to H level or L level in the next cycle, the power consumption may increase depending on the initial state of the signal line D, that is, based on the operation of the previous cycle.

[0129] To address this, the reverse repeater circuit 40 with equalizer circuit 42 initializes the potential change generated via capacitive coupling during the period when signal line D is in a floating state. Therefore, the reverse repeater circuit 40 can suppress the increase in power supply current in the next cycle. Referring hereafter... Figures 18-20 The operation of equalizer circuit 42 is explained.

[0130] exist Figure 18 In cycle 1, the potentials of signal lines D1 and D3 change from H level to L level. At this time, the potential of signal line D2 decreases from "0" to "-1" on the input side of the second reverse repeater 412, and increases from "1" to "2" on the output side of the second reverse repeater 412. During cycle 1, equalizers 421, 422, and 423 are in the off state.

[0131] Next, in Figure 19 In cycle 2 shown, signal lines D1, D2, and D3 are set to a floating state, and the level is adjusted using equalizer circuit 42. That is, equalizers 421, 422, and 423 are turned on. By turning on equalizer 422, the potential of signal line D2 is consistent before and after the second reverse repeater 412, which is "0.5".

[0132] Then, in Figure 20In cycle 3 shown, signal lines D1 and D3 remain floating, while the potential of signal line D2 is set to H level. At this time, the potential of signal line D2 rises from "0.5" to "1" on the input side of the second inverting repeater 412, and decreases from "0.5" to "0" on the output side of the second inverting repeater 412. In this way, in the circuit with equalizer circuit 42, the changing potential of signal line D2 can be suppressed.

[0133] Furthermore, after cycle 3, level adjustment is still performed using equalizer circuit 42. Specifically, the first equalizer 421 connected to the first signal line D1 and the third equalizer 423 connected to the third signal line D3 are turned on. As a result, the potential of the first signal line D1 before and after the first reverse repeater 411 is consistent, and the potential of the third signal line D3 before and after the third reverse repeater 413 is consistent. Therefore, the potential fluctuations of the first signal line D1 and the third signal line D3 caused by the potential change of the second signal line D2 can be reduced. As a result, the magnitude of the potential changes of the first signal line D1 and the third signal line D3 can be suppressed.

[0134] As described above, charge is balanced by using equalizer circuit 42 for level adjustment. The charge is stored in the signal lines D in the first and second halves of the reverse repeater 41 due to capacitive coupling with other signal lines D. As a result, the increase in power supply current in the next cycle caused by the charge stored during the floating period of signal lines D (the previous cycle) can be suppressed.

[0135] As explained above, the reverse repeater circuit 40 reduces the effects of capacitive coupling by making one of the two adjacent signal lines D float. As a result, power supply current can be suppressed without increasing the area of ​​the semiconductor integrated circuit.

[0136] Furthermore, the equalizer circuit 42, through level adjustment, averages the potential before and after the input signal for the floating signal line D. Therefore, in each cycle, the positive and negative charges accumulated in the floating signal line D are canceled out. By canceling out the charges, the effect of potential fluctuations generated in the floating signal line D on the signal line D in the next cycle of the input signal is suppressed. As a result, the increase in power supply current can be suppressed.

[0137] As explained above, the semiconductor integrated circuit according to the embodiment can suppress the increase of power supply current in all cycles and reduce the power consumption of the semiconductor integrated circuit without increasing the area of ​​the semiconductor integrated circuit.

[0138] In addition, such as Figure 6As shown, the period of the EQ signal controlling the operation of the equalizer 420 is half the period of the reference clock signal CLK. However, the operating speed of the input / output circuit 22 is set slower than the operating speed of the sensing amplifier 31 (the transmission speed of the control signal in the control signal line of the sensing amplifier 31) which reads data from the memory cell array 21 of the non-volatile memory 2. The operating period of the input / output circuit 22 is, for example, about 100MHz. Therefore, even though the period of the EQ signal is half the period of the reference clock signal CLK, the reverse repeater circuit 40 can operate stably. In this way, the reverse repeater circuit 40 can be configured in the signal lines of the semiconductor integrated circuit where the signal transmission speed is relatively slow.

[0139] Furthermore, the closer the magnitude of the parasitic capacitance of signal line D is to the input and output sides of the reverse repeater 41, the more easily the potential of the floating signal line D before and after the reverse repeater 41 can be made consistent through level adjustment. That is, preferably, the magnitude of the parasitic capacitance of the first signal line D1 is equal before and after the first reverse repeater 411, and the magnitude of the parasitic capacitance of the second signal line D2 is equal before and after the second reverse repeater 412. In other words, assuming that the parasitic capacitance per unit length in the wiring is approximately fixed, it is preferable that the wiring length of the first portion D1a of the first signal line D1 is equal to the wiring length of the second portion D1b. Additionally, it is preferable that the wiring length of the third portion D2a of the second signal line D2 is equal to the wiring length of the fourth portion D2b. For example, if the magnitude of the parasitic capacitance of signal line D is approximately fixed throughout the entire length of signal line D, the reverse repeater 41 can be positioned near the center of the entire length of signal line D.

[0140] <Example of Variation>

[0141] exist Figure 8 In the illustrated embodiment of the reverse repeater circuit 40, the signal is shown to be transmitted in one direction along the signal line D. However, the reverse repeater circuit 40 can also be configured in the signal line D where the signal is transmitted bidirectionally. With the reverse repeater circuit 40, even in the case of the signal line D where the signal is transmitted bidirectionally, the increase in power supply current can be suppressed, reducing the power consumption of the semiconductor integrated circuit.

[0142] For example, when the signal is transmitted bidirectionally in the data bus YIO of the non-volatile memory 2, the increase in power supply current can be suppressed by the reverse repeater circuit 40. Hereinafter, the case where the signal is transmitted from the input / output circuit 22 to the sensing amplifier 31 is referred to as "data input". On the other hand, the case where the signal is transmitted from the sensing amplifier 31 to the input / output circuit 22 is referred to as "data output".

[0143] Figure 21The circuit configurations of the reverse repeater circuits 40A and 40B in the variations of the implementation are shown. In the variations, the reverse repeater circuits 40A and 40B transmit signals bidirectionally in the signal line D. Figure 21 In this diagram, the direction from left to right on the paper is designated as "Direction 1 R1", and the direction from right to left is designated as "Direction 2 R2". For example, Direction 1 R1 is the direction of signal travel when data is input, and Direction 2 R2 is the direction of signal travel when data is output.

[0144] exist Figure 21 In the variation shown, signal DataA1 travels in the first direction R1 along the first signal line D1, and signal DataA2 travels in the second direction R2 along the first signal line D1. Signal DataB1 travels in the first direction R1 along the second signal line D2, and signal DataB2 travels in the second direction R2 along the second signal line D2.

[0145] In a variation, an inverting repeater circuit 40 is configured in the first signal line D1 and the second signal line D2. The inverting repeater circuit 40 is configured by connecting the first circuit 401, the second circuit 402 and the third circuit 403 in series. Figure 21 In the diagram, the reverse repeater circuit 40 configured on the first signal line D1 is shown as the first reverse repeater circuit 40A, and the reverse repeater circuit 40 configured on the second signal line D2 is shown as the second reverse repeater circuit 40B.

[0146] The first circuit 401 has a configuration in which a general-purpose buffer N11 for transmitting signals along the first direction R1 and a general-purpose buffer N12 for transmitting signals along the second direction R2 are connected in reverse parallel. The second circuit 402 has a configuration in which an inverting repeater 4111 for transmitting signals along the first direction R1, an inverting repeater 4112 for transmitting signals along the second direction R2, and an equalizer 4201 are connected in parallel. The third circuit 403 has a configuration in which a general-purpose buffer N31 for transmitting signals along the first direction R1 and a general-purpose buffer N32 for transmitting signals along the second direction R2 are connected in reverse parallel.

[0147] In response to the clock signal CLKA_DIN transmitted in the first clock line CA1, signal DataA1 is moved in the first direction R1 in the first inverting repeater circuit 40A. Similarly, in response to the clock signal CLKA_DOUT transmitted in the second clock line CA2, signal DataA2 is moved in the second direction R2 in the first inverting repeater circuit 40A. On the other hand, in response to the clock signal CLKB_DIN transmitted in the third clock line CB1, signal DataB1 is moved in the first direction R1 in the second inverting repeater circuit 40B. Furthermore, in response to the clock signal CLKB_DOUT transmitted in the fourth clock line CB2, signal DataB2 is moved in the second direction R2 in the second inverting repeater circuit 40B.

[0148] The clock signal CLKA_DIN, as the logical product of the first clock signal CLKA and the signal DIN, is generated by the first AND circuit 81. The clock signal CLKA_DOUT, as the logical product of the first clock signal CLKA and the signal DOUT, is generated by the second AND circuit 82. Conversely, the clock signal CLKB_DIN, as the logical product of the second clock signal CLKB and the signal DIN, is generated by the third AND circuit 83. The clock signal CLKB_DOUT, as the logical product of the second clock signal CLKB and the signal DOUT, is generated by the fourth AND circuit 84.

[0149] When the signal transmitted in signal line D travels in the first direction R1, the control circuit 50 sets signal DIN to level H and signal DOUT to level L. When the signal travels in the second direction R2 in signal line D, the control circuit 50 sets signal DIN to level L and signal DOUT to level H. Thus, in the variant configuration, the signal is transmitted bidirectionally in signal line D. Furthermore, the timing of the first clock signal CLKA being turned on is offset from the timing of the second clock signal CLKB being turned on by an amount equivalent to half the period of the reference clock signal CLK. Therefore, the timing of the potential change of the first signal line D1 can be offset from the timing of the potential change of the second signal line D2 by an amount equivalent to half the period of the reference clock signal CLK.

[0150] As described above, when data is transmitted, the control circuit 50 can also use the signals / RE and RE to generate control signals for the reverse repeater circuit 40. On the other hand, when data is received, the control circuit 50 can also generate the signals DIN and DOUT as control signals for the reverse repeater circuit 40 based on the signals DQS and / DQS.

[0151] (Other implementation methods)

[0152] The above description assumes that the non-volatile memory 2 is a NAND flash memory, but the non-volatile memory 2 can also be other types of memory devices. Furthermore, embodiments of the present invention can also be semiconductor integrated circuits other than non-volatile memory.

[0153] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, as well as in the invention described in the claims and its equivalents.

[0154] [Explanation of Symbols]

[0155] 1. Memory controller

[0156] 2. Non-volatile memory

[0157] 21-cell memory array

[0158] 22 Input / Output Circuit

[0159] 24 Logic Control Circuit

[0160] 31 Sensing Amplifier

[0161] 40. Reverse Repeater Circuit

[0162] 42 Equalizer Circuit

[0163] 50 Control Circuit

[0164] 411 First Reverse Repeater

[0165] 412 Second Reverse Repeater

[0166] 413 Third Reverse Repeater

[0167] 421 First Equalizer

[0168] 422 Second Equalizer

[0169] 423 Third Equalizer

[0170] D1 Signal Line 1

[0171] D2 Signal Line 2

[0172] D3 is the third signal line.

Claims

1. A semiconductor integrated circuit, comprising: The first signal line has a first part and a second part that are input with a first signal in response to a first clock signal during a first period; The second signal line has a third portion and a fourth portion that are input as a second signal in response to a second clock signal during a second period following the first period; The first inverter, disposed between the first portion and the second portion of the first signal line, outputs the first inverted signal, obtained by logically inverting the first signal, to the second portion; The second inverter, disposed between the third and fourth portions of the second signal line, outputs the second inverted signal, obtained by logically inverting the second signal, to the fourth portion; and The control circuit, during the first period, keeps the second signal line in a floating state, and during the second period, keeps the first signal line in a floating state; and The first clock signal transitions between a first level and a second level different from the first level. The second clock signal transitions between a third level and a fourth level, which is different from the third level. During the third period, which is part of the first period, the first clock signal is at the first level, and the second clock signal is at the fourth level. During a fourth period, which is another part of the first period, the first clock signal is the second level, and the second clock signal is the fourth level. During the fifth period, which is part of the second period, the first clock signal is at the second level, and the second clock signal is at the third level. During the sixth period, which is another part of the second period, the first clock signal is the second level, and the second clock signal is the fourth level.

2. The semiconductor integrated circuit according to claim 1, wherein The first level is higher than the second level. The third level is higher than the fourth level.

3. The semiconductor integrated circuit according to claim 1, wherein the control circuit generates the first clock signal and the second clock signal from a reference clock signal.

4. The semiconductor integrated circuit according to claim 3 further comprises an equalizer circuit, the equalizer circuit being capable of electrically connecting the first portion of the first signal line to the second portion, and being capable of electrically connecting the third portion of the second signal line to the fourth portion.

5. The semiconductor integrated circuit according to claim 4, wherein the equalizer circuit comprises: The first equalizer electrically connects the first part to the second part; and The second equalizer electrically connects the third part to the fourth part.

6. The semiconductor integrated circuit according to claim 5, wherein the first equalizer and the second equalizer are transmission gates composed of n-type MOS transistors and p-type MOS transistors.

7. The semiconductor integrated circuit according to claim 4, wherein During the third period, The control circuit makes the second signal line float. The first signal is input to the first signal line; During the fourth period, The control circuit enables the first signal line and the second signal line to be in a floating state. The equalizer circuit electrically connects the first part of the first signal line to the second part, and electrically connects the third part of the second signal line to the fourth part; During the fifth period, The control circuit makes the first signal line float. The second signal is input to the second signal line; and During the sixth period, The control circuit enables the first signal line and the second signal line to be in a floating state. The equalizer circuit electrically connects the first part of the first signal line to the second part, and electrically connects the third part of the second signal line to the fourth part.

8. The semiconductor integrated circuit according to claim 7, wherein The wiring length of the first portion of the first signal line is equal to the wiring length of the second portion. The wiring length of the third part of the second signal line is equal to the wiring length of the fourth part.

9. The semiconductor integrated circuit according to claim 4, wherein The control circuit uses the first clock signal and the second clock signal to generate a first control signal, and uses the first control signal to control the equalizer circuit.

10. The semiconductor integrated circuit according to claim 9, further comprising: Non-volatile memory, capable of storing data; The sensing amplifier reads data from the non-volatile memory; and A data bus, connected to the sensing amplifier, is provided for transmitting the data read from the non-volatile memory; The data bus includes the first signal line and the second signal line.

11. The semiconductor integrated circuit of claim 10, wherein the non-volatile memory is a NAND flash memory.

12. The semiconductor integrated circuit according to claim 1, wherein At least a portion of the first signal line and at least a portion of the second signal line extend in the same direction and are adjacent to each other.

13. The semiconductor integrated circuit according to claim 1, wherein The sum of the lengths of the third and fourth periods is the same as the length of the first period, and the sum of the lengths of the fifth and sixth periods is the same as the length of the second period.

14. The semiconductor integrated circuit according to claim 13, wherein The length of the first period is the same as the length of the second period. The length of the third period is the same as the length of the fifth period.

15. The semiconductor integrated circuit according to claim 1, wherein the first signal line and the second signal line are signal lines for bidirectional signal transmission.

16. A control method for a semiconductor integrated circuit, During the first period, in response to the first clock signal, a first signal is input to the first part of the first signal line having the first part and the second part. During the second period following the first period, in response to the second clock signal, a second signal is input to the third portion of the second signal line having the third and fourth portions. In the first inverter configured between the first portion and the second portion of the first signal line, a first inverted signal obtained by logically inverting the first signal is output to the second portion. In the second inverter configured between the third and fourth portions of the second signal line, a second inverted signal, obtained by logically inverting the second signal, is output to the fourth portion. During the first period, the second signal line is made to float, and during the second period, the first signal line is made to float. The first clock signal is switched between a first level and a second level different from the first level. The second clock signal is switched between a third level and a fourth level, which is different from the third level. During a third period, which is part of the first period, the first clock signal is set to the first level, and the second clock signal is set to the fourth level. In a fourth period, which is another part of the first period, the first clock signal is set to the second level, and the second clock signal is set to the fourth level. During a fifth period, which is part of the second period, the first clock signal is set to the second level, and the second clock signal is set to the third level. During the sixth period, which is another part of the second period, the first clock signal is set to the second level, and the second clock signal is set to the fourth level.

17. The control method for a semiconductor integrated circuit according to claim 16, wherein... During the third period, Make the second signal line float. The first signal is input to the first signal line; During the fourth period, The first signal line and the second signal line are made to float. Electrically connect the first portion of the first signal line to the second portion, and electrically connect the third portion of the second signal line to the fourth portion; During the fifth period, Make the first signal line float. The second signal is input to the second signal line; and During the sixth period, The first signal line and the second signal line are made to float. Electrically connect the first portion of the first signal line to the second portion, and electrically connect the third portion of the second signal line to the fourth portion.

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