Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes a plurality of string groups respectively connected to a corresponding source select line among a plurality of source select lines. The peripheral circuit is configured to perform a program operation to store data within the memory block. The control logic controls the program operation of the peripheral circuit. The plurality of source select lines are grouped into a plurality of source select line groups. The control logic controls the peripheral circuit to increase a voltage of a first source select line group among the plurality of source select line groups to a first level, the first source select line group including a source select line connected to a selected string group.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0025923, filed on February 25, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to semiconductor memory devices and methods of operating the semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be formed in a two-dimensional structure (where strings are arranged horizontally on a semiconductor substrate) or a three-dimensional structure (where strings are stacked vertically on a semiconductor substrate). Three-dimensional memory devices are memory devices designed to address the integration limitations of two-dimensional semiconductor memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0005] According to one embodiment of this disclosure, a semiconductor memory device may include a memory block, peripheral circuitry, and control logic. The memory block may include multiple serial groups, each connected to a corresponding source select line among multiple source select lines. The peripheral circuitry may be configured to perform programming operations to store data within the memory block. The control logic may control the programming operations of the peripheral circuitry. The multiple source select lines may be grouped into multiple source select line groups. The control logic may control the peripheral circuitry to increase the voltage of a first source select line group among the multiple source select line groups to a first level, the first source select line group including source select lines connected to a selected serial group.

[0006] According to another embodiment of this disclosure, a method of operating a semiconductor memory device can perform programming operations on a memory block, which may include first to Nth (N is a natural number greater than or equal to 3) string groups. The programming operation may include multiple programming cycles. Each programming cycle may include a pre-charge phase and a verification phase. The verification phase may include: increasing the voltage of a first source select line and a second source select line to a first level, the first source select line being connected to a first string group selected as the programming target among the first to Nth string groups, and the second source select line being connected to a second string group. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is a diagram. Figure 1 A diagram of one embodiment of a memory cell array.

[0009] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0010] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0011] Figure 5 This is a diagram illustrating an example of a serial group of configured memory blocks.

[0012] Figure 6A It is a diagram. Figure 5 The circuit diagram of the first string group in the string group shown.

[0013] Figure 6B This is a circuit diagram illustrating a portion of the unit strings included in the first and second string groups.

[0014] Figure 7 This is a circuit diagram illustrating a page buffer PB1 included in a semiconductor memory device 100 according to one embodiment.

[0015] Figure 8 This is a diagram illustrating another example of a serial group of configured memory blocks.

[0016] Figure 9 This is a circuit diagram showing a portion of the unit strings included in the first to fourth string groups.

[0017] Figure 10 This is a diagram illustrating the programming operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 11 This is a flowchart according to an embodiment of the present disclosure, illustrating an embodiment of the verification phase during programming operations of a semiconductor memory device.

[0019] Figure 12 This is a flowchart according to an embodiment of the present disclosure, illustrating an embodiment of the pre-charge phase during programming operations of a semiconductor memory device.

[0020] Figure 13 The diagram is based on Figure 11 and Figure 12 Timing diagram of an embodiment.

[0021] Figure 14This is a flowchart according to another embodiment of the present disclosure, illustrating one embodiment of the verification phase during programming operations of a semiconductor memory device.

[0022] Figure 15 This is a flowchart according to another embodiment of the present disclosure, illustrating one embodiment of a pre-charge phase during programming operations of a semiconductor memory device.

[0023] Figure 16 The diagram is based on Figure 14 and Figure 15 Timing diagram of an embodiment.

[0024] Figure 17 The illustration includes Figure 1 A block diagram of an embodiment of a memory system for a semiconductor memory device.

[0025] Figure 18 It is a diagram. Figure 17 A block diagram of an application example of a memory system.

[0026] Figure 19 The illustration includes references. Figure 18 A block diagram of the computing system describing the memory system. Detailed Implementation

[0027] The specific structural or functional descriptions of the embodiments disclosed in this specification or application are provided for the purpose of describing embodiments according to this disclosure. Embodiments according to this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0028] In the description of this disclosure, the terms "first" and "second" may be used to describe various components, but the components are not limited by these terms. These terms may be used to distinguish one component from another. For example, a first component may be referred to as a second component and a second component may be referred to as a first component, without departing from the scope of this disclosure.

[0029] Embodiments of this disclosure provide a semiconductor memory device capable of reducing programming disturbances, and a method for operating the semiconductor memory device.

[0030] In one embodiment, the control logic can control the peripheral circuitry to reduce the voltage of the first source select line group to a second level after applying a verification voltage to a selected word line among the word lines connected to the memory block and applying a verification pass voltage to an unselected word line.

[0031] In one embodiment, the control logic can control the peripheral circuitry to maintain the voltage of a second source select line group that is different from the first source select line group while increasing the voltage of the first source select line group to a first level, applying a verification voltage to the selected word line among the word lines connected to the memory block, applying a verification pass voltage to the unselected word line, and decreasing the voltage of the first source select line group to a second level.

[0032] In one embodiment, the voltage of the second source selection line group can be maintained at the second level.

[0033] In one embodiment, the first level may be a voltage used to turn on a source selection transistor connected to the first source selection line group, and the second level may be a ground voltage.

[0034] In one embodiment, the control logic can control the peripheral circuitry to apply a precharge voltage to a common source line connected to the memory block and to increase the voltage of the first source select line group to a first level.

[0035] In one embodiment, the control logic can control the peripheral circuitry to decrease the voltage of the first source select line group to a second level after increasing the voltage of the first source select line group to a first level.

[0036] In one embodiment, the control logic can control the peripheral circuitry to maintain the voltage of a second source select line group that is different from the first source select line group while applying a precharge voltage to a common source line connected to the memory block, increasing the voltage of the first source select line group to a first level, and decreasing the voltage of the first source select line group to a second level.

[0037] In one embodiment, the memory block may include first to fourth string groups, the selected string group may correspond to the first string group, the first source select line group may include first and second source select lines respectively connected to the first and second string groups, and the second source select line group may include third and fourth source select lines respectively connected to the third and fourth string groups.

[0038] In one embodiment, the control logic can control the peripheral circuitry to apply a precharge voltage to a common source line connected to the memory block after applying a verification voltage to a selected word line among the word lines connected to the memory block and applying a verification pass voltage to an unselected word line.

[0039] In one embodiment, the control logic can control the peripheral circuitry to reduce the voltage of the first source select line group to a second level after a pre-charge voltage is applied to the common source line.

[0040] In one embodiment, the source select lines belonging to the first source select line group can be electrically connected to each other.

[0041] In one embodiment, the source select lines belonging to the second source select line group can be electrically connected to each other.

[0042] In one embodiment, the verification step may further include reducing the voltage of the first and second source select lines to a second level.

[0043] In one embodiment, the first level may be a voltage that enables the source select transistors included in the first and second string groups to conduct, the second level may be a ground voltage, and during the verification phase, the voltages of the third and fourth source select lines may be maintained at the second level, the third source select line being connected to the third string group among the first to the Nth string groups, and the fourth source select line being connected to the fourth string group among the first to the Nth string groups.

[0044] In one embodiment, the precharge phase may include: applying a precharge voltage to a common source line connected to the memory block; and increasing the voltages of the first and second source select lines to a first level.

[0045] In one embodiment, during the pre-charge phase, the voltages of the third and fourth source selection lines can be maintained at the second level.

[0046] In one embodiment, the precharge phase may include: applying a precharge voltage to a common source line connected to the memory block; and reducing the voltages of the first and second source select lines to a second level.

[0047] In one embodiment, the first source select line and the second source select line can be electrically connected to each other, and the third source select line and the fourth source select line can be electrically connected to each other.

[0048] This technology can provide a semiconductor memory device that can reduce programming disturbances, and a method for operating the semiconductor memory device.

[0049] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0050] refer to Figure 1 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, read and write circuitry 130, control logic 140, and a voltage generator 150. The control logic 140 can be implemented in hardware, software, or a combination of both. For example, the control logic 140 can be control logic circuitry operating according to an algorithm, and / or a processor executing control logic code.

[0051] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to read and write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz includes multiple memory cells. As one embodiment, the multiple memory cells are non-volatile memory cells and can be configured using non-volatile memory cells with a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array. According to one embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array. Furthermore, each memory cell among the multiple memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 can be a multi-level cell (MLC) storing two bits of data. In another embodiment, each memory cell in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each memory cell in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to one embodiment, the memory cell array 110 may include a plurality of memory cells, each storing five or more bits of data.

[0052] Address decoder 120, read and write circuitry 130, control logic 140, and voltage generator 150 operate as peripheral circuitry driving memory cell array 110. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control of control logic 140. Address decoder 120 receives addresses through input / output buffers (not shown) within semiconductor memory device 100.

[0053] Address decoder 120 is configured to decode block addresses among received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during a read voltage application operation, address decoder 120 applies a read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines. Similarly, during a program verification operation, address decoder 120 applies a verification voltage generated in voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines.

[0054] Address decoder 120 is configured to decode the column address in the received address. Address decoder 120 transmits the decoded column address to read and write circuitry 130.

[0055] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or program operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read and write circuitry 130.

[0056] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0057] The read and write circuit 130 includes multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, while continuously supplying sensing current to the corresponding bit line connected to the memory cell, the multiple page buffers PB1 to PBm sense changes in the amount of current flowing according to the programming state of the corresponding memory cell through sensing nodes, and latch the sensed changes as sensed data. The read and write circuit 130 operates in response to a page buffer control signal output from control logic 140.

[0058] During a read operation, the read and write circuit 130 senses data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. As an example, in addition to a page buffer (or page register), the read and write circuit 130 may also include column select circuitry, etc.

[0059] Control logic 140 is connected to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals to adjust the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110.

[0060] In response to a control signal output from control logic 140, voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and in response to control by control logic 140, generate multiple voltages by selectively activating these multiple pump capacitors.

[0061] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on control logic 140.

[0062] Figure 2 It is a diagram. Figure 1 A diagram of one embodiment of a memory cell array.

[0063] refer to Figure 2 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Reference) Figure 3 and Figure 4 The structure of each memory block will be described in more detail.

[0064] Figure 3 It is a diagram. Figure 2The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0065] refer to Figure 3 The memory block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a 'U' shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 3 In this diagram, two unit strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0066] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0067] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As one embodiment, a pillar for providing the channel layer may be provided in each cell string. As one embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film.

[0068] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0069] As one embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. Figure 3 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0070] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0071] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0072] The first memory cells MC1 to the nth memory cell MCn can be divided into: the first memory cells MC1 to the pth memory cells MCp, and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other through the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0073] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0074] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0075] The cell string arranged in the column direction is connected to the bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0076] A page is configured for memory cells connected to the same word line within a cell string arranged in the row direction. For example, memory cells in cell strings CS11 to CS1m in the first row, connected to the first word line WL1, are configured as one page. Memory cells in cell strings CS21 to CS2m in the second row, connected to the first word line WL1, are configured as another page. A cell string arranged in a row direction can be selected by selecting either drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0077] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0078] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. With more dummy memory cells provided, the reliability of operation for memory block BLKa increases; however, the size of memory block BLKa increases. With fewer dummy memory cells provided, the size of memory block BLKa can be reduced; however, the reliability of operation for memory block BLKa may decrease.

[0079] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0080] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0081] refer to Figure 4 The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes, stacked on a substrate (not shown) beneath the memory block BLKb: at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0082] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a single source select line.

[0083] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0084] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0085] Therefore, in addition to excluding the pipe transistor PT from each cell string, Figure 4 The memory block BLKb has the same Figure 3 The equivalent circuit of the memory block BLKa is similar to the equivalent circuit.

[0086] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0087] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the reliability of operation for memory block BLKb increases; however, the size of memory block BLKb increases. With fewer dummy memory cells provided, the size of memory block BLKb can be reduced; however, the reliability of operation for memory block BLKb may decrease.

[0088] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0089] Figure 5 This is a diagram illustrating an example of a serial group of configured memory blocks.

[0090] refer to Figure 5 , Figure 3 and Figure 4 The string groups STRING GROUP 1 and STRING GROUP 2 included in the memory blocks BLKa and BLKb shown are illustrated. See also, for example, a reference. Figure 3 The string groups included in a memory block BLKa can be defined as cell strings sharing a drain select line or a source select line. For example, in Figure 3 In this configuration, the unit strings CS11 to CS1m that share the first drain selection line DSL1 and the first source selection line SSL1 can be configured as the first string group STRING GROUP 1. Simultaneously, the unit strings CS21 to CS2m that share the second drain selection line DSL2 and the second source selection line SSL2 can be configured as the second string group STRING GROUP 2.

[0091] As another example, in Figure 4In this memory block, cell strings CS11' to CS1m' sharing the first drain select line DSL1 and the first source select line SSL1 can be configured as a first string group STRING GROUP 1. Simultaneously, cell strings CS21' to CS2m' sharing the second drain select line DSL2 and the second source select line SSL2 can be configured as a second string group STRING GROUP 2. The memory block comprises two string groups, STRING GROUP 1 and STRING GROUP 2, arranged in the +Y direction. Each string group in STRING GROUP 1 and STRING GROUP 2 comprises cell strings arranged in the row direction (i.e., the +X direction). Simultaneously, each string group in STRING GROUP 1 and STRING GROUP 2 comprises pages arranged in the string direction (i.e., the +Z direction). References will follow. Figure 6A and Figure 6B Describe the configuration for each string group.

[0092] Figure 6A It is a diagram. Figure 5 The circuit diagram of the first string group is shown. Since the second string group can be configured in the same way as the first, its detailed circuit diagram is omitted.

[0093] refer to Figure 6A The first string group 1 includes unit strings CS11 to CS1m that share a first drain select line DSL1 and a first source select line SSL1. That is, the unit strings CS11 to CS1m included in the first string group 1 are collectively connected to the first drain select line DSL1 and the first source select line SSL1. In the first string group 1, the unit strings CS11 to CS1m are arranged in the +X direction. The unit strings CS11 to CS1m are respectively connected to the corresponding bit lines BL1 to BLm.

[0094] Meanwhile, the first STRING GROUP 1 includes pages PAGE11 to PAGE1n arranged in the +Z direction. Each page in PAGE11 to PAGE1n can be a collection of memory cells connected to corresponding word lines WL1 to WLn.

[0095] Although not in Figure 6A As shown, the second string group 2 may also include unit strings CS21 to CS2m arranged in the +X direction. Simultaneously, the second string group 2 may include pages PAGE21 to PAGE2n arranged in the +Z direction.

[0096] Figure 6BThis is a circuit diagram illustrating a portion of the unit strings included in the first and second string groups.

[0097] refer to Figure 6B The unit string CS11 included in the first string group STRING GROUP 1 and the unit string CS21 included in the second string group STRING GROUP 2 are shown. Figure 6B It can be illustrated in the +X direction. Figure 5 The circuit diagram of the memory block is shown in the image. Therefore, in Figure 6B In the diagram, the unit strings CS12 to CS1m included in the first string group STRING GROUP 1 and the unit strings CS22 to CS2m included in the second string group STRING GROUP 2 are not shown.

[0098] The first string group STRING GROUP 1's cell string CS11 includes memory cells MC11 to MC1n, which are connected between the first drain select transistor DST1 and the first source select transistor SST1. The second string group STRING GROUP 2's cell string CS21 includes memory cells MC21 to MC2n, which are connected between the second drain select transistor DST2 and the second source select transistor SST2.

[0099] The cell string CS11 included in the first string group STRING GROUP 1 and the cell string CS21 included in the second string group STRING GROUP 2 are both connected to bit line BL1. Simultaneously, the page buffer PB1 is also connected to bit line BL1. That is, the cell string CS11 included in the first string group STRING GROUP 1 and the cell string CS21 included in the second string group STRING GROUP 2 can share page buffer PB1.

[0100] Figure 7 This is a circuit diagram illustrating a page buffer PB1 included in a semiconductor memory device 100 according to one embodiment. Figure 7 The page buffer shown can be Figure 1 The read and write circuit 130 includes any one of the page buffers PB1 to PBm. Since the multiple page buffers PB1 to PBm included in the read and write circuit 130 can be configured similarly to each other, any one of the page buffers is described as an example.

[0101] The page buffer can operate in response to signals output from control logic 140. The signals PB_SENSE, SA_PRECH_N, SA_SENSE, SA_CSOC, SA_DISCH, and PRECHSO_N described below can be included in the control signal CTRPB output from control logic 140. Page buffer PB1 is specifically described below.

[0102] refer to Figure 7 Page buffer PB1 can be connected to the memory cell via bit line BL1, and can perform bit line pre-charge operation by charging the charge supplied from the power supply voltage VCORE through the first NMOS transistor N1 to the fifth NMOS transistor N5 and the first PMOS transistor P1 to the third PMOS transistor P3. Furthermore, page buffer PB1 can discharge the charge charged to bit line BL1 to ground voltage through the first NMOS transistor N1, the fourth NMOS transistor N4, and the fifth NMOS transistor N5.

[0103] The first NMOS transistor N1 is connected between bit line BL1 and the common node CSO. The first PMOS transistor P1 is connected between the power supply voltage VCORE and the sense amplifier node SAN. The second NMOS transistor N2 is connected between the common node CSO and the sense amplifier node SAN. The second PMOS transistor P2 is connected between the sense amplifier node SAN and the sense node SO. The third NMOS transistor N3 is connected between the sense node SO and the common node CSO. The third PMOS transistor P3 is connected between the power supply voltage VCORE and the sense node SO. The fourth NMOS transistor N4 and the fifth NMOS transistor N5 are connected in series between the common node CSO and ground.

[0104] The first NMOS transistor N1 is controlled by the page buffer sensing signal PB_SENSE, the second NMOS transistor N2 is controlled by the current sensing signal SA_CSOC, and the third NMOS transistor N3 is controlled by the sense amplifier sensing signal SA_SENSE. Furthermore, the fourth NMOS transistor N4 is controlled by the sense amplifier discharge signal SA_DISCH, and the fifth NMOS transistor N5 and the first PMOS transistor P1 are controlled by the voltage at node QS of the sense latch circuit LATS. The second PMOS transistor P2 is controlled by the sense amplifier precharge signal SA_PRECH_N, and the third PMOS transistor P3 is controlled by the sense node precharge signal PRECHSO_N. That is, the page buffer sensing signal PB_SENSE is applied to the gate of the first NMOS transistor N1, the current sensing signal SA_CSOC is applied to the gate of the second NMOS transistor N2, and the sense amplifier sensing signal SA_SENSE is applied to the gate of the third NMOS transistor N3. Furthermore, the sense amplifier discharge signal SA_DISCH is applied to the gate of the fourth NMOS transistor N4, and the voltage of node QS of the sense latch circuit LATS is applied to the gate of the fifth NMOS transistor N5 and the gate of the first PMOS transistor P1. The sense amplifier precharge signal SA_PRECH_N is applied to the gate of the second PMOS transistor P2, and the sense node precharge signal PRECHSO_N is applied to the gate of the third PMOS transistor P3.

[0105] The sense latch circuit LATS may include a latch configured by two inverters (not shown) connected to node QS, and may include a reset transistor (not shown) and a set transistor (not shown) for controlling the voltage of node QS.

[0106] Figure 8 This is another example diagram illustrating a serial group of memory blocks. Meanwhile, Figure 9 This is a circuit diagram showing a portion of the unit strings included in the first to fourth string groups.

[0107] refer to Figure 8 The memory block can include four string groups: STRING GROUP 1 through STRING GROUP 4. (See reference above.) Figure 4 As described, the string groups included in the memory block can be defined as cell strings sharing a drain select line or a source select line. Figure 5 The memory block shown may include two string groups, but as Figure 8 As shown, the memory block can be configured to include four string groups.

[0108] refer to Figure 9The diagram shows the unit string CS11 included in the first string group STRING GROUP 1, the unit string CS21 included in the second string group STRING GROUP 2, the unit string CS31 included in the third string group STRING GROUP 3, and the unit string CS41 included in the fourth string group STRING GROUP 4. Figure 9 It can be illustrated in the +X direction. Figure 8 The circuit diagram of the memory block shown is shown.

[0109] The first string group STRING GROUP 1, string CS11, includes memory cells MC11 to MC1n, which are connected between the first drain select transistor DST1 and the first source select transistor SST1. The second string group STRING GROUP 2, string CS21, includes memory cells MC21 to MC2n, which are connected between the second drain select transistor DST2 and the second source select transistor SST2. The third string group STRING GROUP 3, string CS31, includes memory cells MC31 to MC3n, which are connected between the third drain select transistor DST3 and the third source select transistor SST3. The fourth string group STRING GROUP 4, string CS41, includes memory cells MC41 to MC4n, which are connected between the fourth drain select transistor DST4 and the fourth source select transistor SST4.

[0110] Memory block reference including two serial groups Figures 5 to 7 However, as Figure 8 and Figure 9 As shown, a memory block comprising four serial groups can also be configured.

[0111] In one embodiment of this disclosure, Figure 9 The source selection lines SSL1 to SSL4 shown can be grouped into two source selection line groups. For example, suppose the first string group STRING GROUP 1 is the programming target. In this case, the first string group STRING GROUP 1 becomes the selected string group, and the second string group STRING GROUP 2 to the fourth string group STRING GROUP 4 become the unselected string groups. String CS11 is included in the selected string group, and each string in CS21, CS31, and CS41 is included in the unselected string groups.

[0112] For example, among source select lines SSL1 to SSL4, the first source select line SSL1 and the second source select line SSL2 may belong to the first source select line group. The first source select line SSL1 is connected to the first string group STRING GROUP 1, which is the selected string group, and the second source select line SSL2 is connected to any unselected string group (e.g., the second string group STRING GROUP 2). Meanwhile, the third source select line SSL3 and the fourth source select line SSL4 may belong to the second source select line group. The third source select line SSL3 and the fourth source select line SSL4 are connected to the remaining unselected string groups, i.e., connected to the third string group STRING GROUP 3 and the fourth string group STRING GROUP 4, respectively. According to a semiconductor memory device and a method of operating the semiconductor memory device according to an embodiment of the present disclosure, during the verification phase of programming operation of the semiconductor memory device, the voltage of the first source select line group may be increased, and the voltage of the second source select line group may be maintained. Accordingly, source select transistors SST1 and SST2 connected to the first source select line group are turned on, and source select transistors SST3 and SST4 connected to the second source select line group are turned off. Thereafter, a verification voltage can be applied to the selected word line connected to the selected memory block, and a verification pass voltage can be applied to the unselected word line.

[0113] In one embodiment, source select lines belonging to the same source select line group can be connected to each other. For example, the first source select line SSL1 and the second source select line SSL2, belonging to the first source select line group, can be electrically connected to each other. Furthermore, the third source select line SSL3 and the fourth source select line SSL4, belonging to the second source select line group, can be electrically connected to each other.

[0114] At the same time, Figure 9 The present disclosure illustrates one embodiment in which a memory block comprises four string groups, but is not limited thereto. For example, a memory block included in a semiconductor memory device according to an embodiment of the present disclosure may include N string groups. Here, N may be a natural number greater than or equal to 4.

[0115] refer to Figures 11 to 16 This document describes a semiconductor memory device and a method of operating the semiconductor memory device according to an embodiment of the present disclosure.

[0116] Figure 10 This is a diagram illustrating the programming operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0117] refer to Figure 10Programming operations for semiconductor memory devices can include multiple cycles. Each cycle includes a precharge phase, a programming phase, and a verification phase.

[0118] During the precharge phase, the bit line voltage of the serial group in the memory block that is the programming target is set, and the serial precharge operation of the serial group in the memory block that is not the programming target is performed.

[0119] Setting the bit line voltage of a string group as the programming target involves setting the bit line voltage to a programming enable voltage or a programming disable voltage so that data is programmed into the page targeted for programming. Since a programming pulse is applied to the selected word line in a subsequent programming stage, the threshold voltage of the memory cell connected to the bit line set to the programming enable voltage can be moved. Conversely, in a subsequent programming stage, the threshold voltage of the memory cell connected to the bit line set to the programming disable voltage may not be moved.

[0120] In one embodiment, the programming allows the voltage to be ground voltage. In this case, as in... Figure 7 In the structure of the page buffer PB1 shown, the ground voltage can be transmitted to the bit line BL1 through the fifth NMOS transistor N5, the fourth NMOS transistor N4 and the first NMOS transistor N1.

[0121] In one embodiment, the programming disable voltage can be the power supply voltage VCORE. In this case, as in... Figure 7 In the structure of the page buffer PB1 shown, the power supply voltage VCORE can be transmitted to the bit line BL1 via the first PMOS transistor P1, the second NMOS transistor N2, and the first NMOS transistor N1. In another embodiment, the power supply voltage VCORE can be transmitted to the bit line BL1 via the first PMOS transistor P1, the second PMOS transistor P2, the third NMOS transistor N3, and the first NMOS transistor N1.

[0122] When the programming allows voltage to be transmitted to the bit line and when the programming disables voltage transmission to the bit line, the first NMOS transistor N1 can be turned on, and thus the corresponding voltage is transmitted to the bit line. That is, the bit line voltage setting operation is performed by increasing the page buffer sensing signal PB_SENSE applied to the page buffers PB1 to PBm from the off voltage to the on voltage.

[0123] During the programming phase, a programming pulse is applied to the selected word line, and a programming voltage is applied to the unselected word lines to selectively move the threshold voltage of the memory cells included in the selected page. At this time, the threshold voltage of the memory cells included in the selected page can be moved or maintained according to the corresponding bit line voltage set in the precharge phase. That is, in memory cells connected to bit lines set to apply a programming enable voltage during the precharge phase, the threshold voltage can be moved because a programming pulse is applied to the selected word line. Furthermore, in memory cells connected to bit lines set to apply a programming disable voltage during the precharge phase, the threshold voltage will not move even if a programming pulse is applied to the selected word line.

[0124] During the verification phase, a verification voltage is used to check whether the memory cells included in the selected page are programmed to the target programming state. The programming operation is complete when the threshold voltage of a predetermined ratio or greater of the memory cells included in the selected page reaches the target level. In this case, no subsequent loop is executed, and the programming operation ends. If the number of memory cells whose threshold voltage reaches the target level is less than the predetermined ratio of the memory cells included in the selected page, the programming operation does not end, and a subsequent loop is executed. As used herein with respect to parameters such as a predetermined ratio, the term "predetermined" means that the value of the parameter is determined before it is used in the processing or algorithm. In some embodiments, the value of the parameter is determined before the processing or algorithm begins. In other embodiments, the value of the parameter is determined during the processing or algorithm, but before the parameter is used in the processing or algorithm.

[0125] Figure 11 This is a flowchart illustrating one embodiment of an embodiment of the present disclosure, showing a verification phase during programming operations of a semiconductor memory device. (Reference) Figure 11 The verification phase includes: increasing the voltage of a first source select line group, which includes a first source select line connected to a selected string group among a plurality of string groups included in the selected memory block, and maintaining the voltage of a second source select line group including the remaining source select lines (S110); applying a verification voltage to a selected word line among the word lines connected to the selected memory block, and applying a verification pass voltage to an unselected word line (S130); and decreasing the voltage of the first source select line group to a second level, while maintaining the voltage of the second source select line group (S150). Hereinafter, as an example, the following description illustrates this process. Figure 8 The case where the first string in the string group is the selected string group.

[0126] In step S110, the voltage of the first source select line group is increased to a first level, while the voltage of the second source select line group is maintained. The first source select line group may include at least the source select lines connected to the selected string group. (Refer to...) Figure 8 and Figure 9 In the described example, since the first string group STRING GROUP 1 is the selected string group, the first source select line group includes the first source select line SSL1. Furthermore, at least one of the second to fourth source select lines SSL2 to SSL4, respectively connected to unselected string groups, can be included in the first source select line group. For example, the second source select line SSL2 can be included in the first source select line group.

[0127] When the first source select line SSL1 and the second source select line SSL2 are included in the first source select line group, the third source select line SSL3 and the fourth source select line SSL4, which are the remaining source select lines, are included in the second source select line group.

[0128] That is, the first source select line group includes source select lines connected to the selected string group and source select lines connected to an unselected string group. Meanwhile, the second source select line group includes source select lines respectively connected to the unselected string groups.

[0129] Meanwhile, in step S110, the voltage of the drain selection line connected to the selected string group can be increased to the first level, and the voltage of the drain selection line connected to the unselected string group can be maintained.

[0130] In step S130, a verification voltage is applied to the selected word line connected to the selected memory block, and a verification voltage is applied to the unselected word line. Accordingly, a threshold voltage verification operation is performed on the memory cells in the selected string group that are connected to the selected word line.

[0131] In step S150, the voltage of the first source select line group is reduced to a second level, while the voltage of the second source select line group is maintained. In one embodiment, the second level may be ground voltage. Accordingly, the voltage of the first source select line group, which was increased to a first level in step S110, can be reduced back to ground voltage. In step S150, the voltage of the second source select line group can be maintained at ground voltage.

[0132] With steps S110 to S150 executed, the verification phase, included in a programming loop during the programming operation, can be performed. (See reference) Figure 13 Describe steps S110 to S150.

[0133] Figure 12 This is a flowchart according to an embodiment of the present disclosure, illustrating an embodiment of the pre-charge phase during programming operations of a semiconductor memory device.

[0134] refer to Figure 12 The pre-charge phase includes: applying a pre-charge voltage to the common source line (S210); increasing the voltage of the first source select line group to a first level and maintaining the voltage of the second source select line group (S230); and decreasing the voltage of the first source select line group to a second level (S250).

[0135] In step S210, a pre-charge voltage is applied to the common source line. This pre-charge voltage is used to pre-charge the negative boost channel voltage of the cell strings included in the unselected string group, which is connected to the second source select line SSL2 in the first source select line group, i.e., the second string group STRING GROUP 2. Subsequently, in step S230, as the voltage of the first source select line group increases to a first level serving as the turn-on voltage, the second source select transistor SST2 included in the second string group STRING GROUP 2 is turned on. Accordingly, the negative boost channel voltage of the cell strings CS21 to CS2m included in the second string group STRING GROUP 2 is pre-charged.

[0136] Subsequently, in step S250, the voltage of the first source selection line group can be reduced to a second level, i.e., ground voltage. With steps S210 to S250 executed, a pre-charge phase included in a programming cycle during the programming operation can be performed. (See reference...) Figure 13 Describe steps S210 to S250.

[0137] Figure 13 The diagram is based on Figure 11 and Figure 12 Timing diagram of an embodiment. In Figure 13 The diagram illustrates the verification phase of the (N-1)th programming loop and the pre-charge phase of the Nth programming loop. (See reference...) Figure 13 This illustrates a scenario where the first of the first to fourth string groups included in a memory block is selected as the programming target. For example, in... Figure 13 The following scenario is illustrated, in which the memory cell connected to the i-th word line WLi among the memory cells included in the first string group is selected as the programming target memory cell.

[0138] exist Figure 13The diagram illustrates the voltage applied to the selected i-th word line WLi and the voltage applied to the unselected word lines. Furthermore, it shows the voltage applied to the first drain select line DSL1 connected to the selected first string group STRING GROUP 1, and the voltage applied to the second drain select lines DSL2 to the fourth drain select line DSL4 connected to the second string groups STRING GROUP 2 to STRING GROUP 4, respectively. Additionally, it shows the voltage applied to the first source select line group, which includes the first source select line SSL1 connected to the selected first string group STRING GROUP 1, and the voltage applied to the second source select line group, which includes the remaining unselected source select lines. For example, the first source select line group includes the first source select line SSL1 and the second source select line SSL2, and the second source select line group includes the third source select line SSL3 and the fourth source select line SSL4. Meanwhile, in... Figure 13 The voltage across the common source line CSL is shown in the diagram. Furthermore, Figure 13 The channel potentials of the unit strings included in the second string group STRING GROUP 2, which is not selected, are shown. The second string group STRING GROUP 2 is connected to the second source select line SSL2, which belongs to the first source select line group. The channel potentials of the unit strings included in the third string group STRING GROUP 3 and the fourth string group STRING GROUP 4 are also shown. The third string group STRING GROUP 3 and the fourth string group STRING GROUP 4 are connected to the third source select line SSL3 and the fourth source select line SSL4, which belong to the second source select line group.

[0139] At time t1 during the verification phase, the verification voltage V is... VRF It is applied to the selected word line WLi and verified by voltage V. VRPASS The voltage is applied to the unselected word line. Simultaneously, an on-state voltage V1 is applied to the first drain select line DSL1, and a ground voltage, serving as the off-state voltage, is applied to the second drain select lines DSL2 through DSL4. Furthermore, the on-state voltage V1 is applied to the first source select line SSL1 and the second source select line SSL2, which belong to the first source select line group, while the voltages of the third source select line SSL3 and the fourth source select line SSL4, which belong to the second source select line group, remain at ground. Simultaneously, the voltage of the common source line CSL also remains at ground.

[0140] At time t1, because a turn-on voltage is applied to the first source select line SSL1 and the second source select line SSL2, the channel potential of the cell strings included in the first string group 1 and the second string group 2 remains at 0V. This is because the first source select transistor SST1 and the second source select transistor SST2 are turned on, and thus the voltage of the common source line CSL is transferred to the channel. Simultaneously, at time t1, because a turn-off voltage is applied to the third source select line SSL3 and the fourth source select line SSL4, the channel potential of the cell strings included in the third string group 3 and the fourth string group 4 is boosted to voltage V2 according to the increase in word line voltage.

[0141] At time t1, the on-state voltage is applied to both the first source select line SSL1 and the second source select line SSL2, but the on-state voltage is applied only to the first drain select line DSL1, and the off-state voltage is applied only to the second drain select line DSL2. Therefore, verification operations can be performed only on the memory cells included in the first string group STRING GROUP 1.

[0142] Let's refer to each other. Figure 11 Step S110 can be executed at time t1. That is, due to the execution of step S110, the voltages of the first source select line SSL1 and the second source select line SSL2, which belong to the first source select line group, increase to voltage V1, where voltage V1 is the first level. At the same time, due to the execution of step S110, the voltages of the third source select line SSL3 and the fourth source select line SSL4, which belong to the second source select line group, remain at ground voltage.

[0143] Furthermore, step S130 can also be executed at time t1. That is, at... Figure 11 In this case, step S110 is executed after step S130, but this disclosure is not limited thereto. That is, steps S110 and S130 can be executed simultaneously, or step S110 can be executed after step S130.

[0144] Simultaneously, at time t2, the voltage of the word line can be reduced to the ground voltage. Furthermore, at time t2, the voltage of the first drain select line DSL1 can be reduced to the ground voltage. Also at time t2, the voltages of the first source select line SSL1 and the second source select line SSL2, belonging to the first source select line group, can be reduced to the ground voltage.

[0145] As the voltage of the second source select line SSL2 decreases to ground at time t2, the second source select transistor SST2 is turned off. Simultaneously, because the voltages of all word lines decrease together, the channel potential of the cell strings CS21 to CS2m of the second string group 2 connected to the second source select line SSL2 can be negatively boosted to voltage V3, which is a negative value.

[0146] Simultaneously, the channel potentials of cell strings CS31 to CS3m and CS41 to CS4m can also be negatively boosted to voltage V4. Cell strings CS31 to CS3m and CS41 to CS4m are included in the third string group STRING GROUP 3 and the fourth string group STRING GROUP 4, respectively connected to the third source select line SSL3 and the fourth source select line SSL4. However, since the channel potentials of cell strings CS31 to CS3m and CS41 to CS4m have already been boosted to voltage V2 at time t1, even if the channel voltage is negatively boosted at time t2, the final potential of voltage V4 can still have a positive value.

[0147] On the other hand, since the channel potentials of the cell strings CS21 to CS2m in the second string group STRING GROUP 2 are negatively boosted from the ground voltage, the final potential of voltage V3 can be negative. Therefore, the channel voltage that has been negatively boosted to a negative value needs to be increased during the pre-charge phase.

[0148] Let's refer to each other. Figure 11 Step S150 can be executed at time t2. That is, at time t2, the voltages of the first source select line SSL1 and the second source select line SSL2 belonging to the first source select line group can be reduced to the second level, i.e., the ground voltage, and the voltages of the third source select line SSL3 and the fourth source select line SSL4 belonging to the second source select line group can be maintained.

[0149] That is, in Figure 13 During the time period t1 to t2, the verification phase of the N-1 programming loop is executed.

[0150] Subsequently, at time t3, the pre-charge voltage V PRCH A common source line CSL is applied. In this state, at time t4, the voltages of the first source select line SSL1 and the second source select line SSL2, belonging to the first source select line group, increase to a first voltage level V1. Since the first source select transistor SST1 and the second source select transistor SST2 are turned on, the channel potentials of the cell strings CS21 to CS2m of the second string group STRING GROUP 2, which are negatively boosted to a negative voltage value V3, can increase to voltage V5. In one embodiment, the voltage value V5 can be related to the pre-charge voltage V. PRCHEssentially the same. Meanwhile, since the voltages of the third source select line SSL3 and the fourth source select line SSL4, belonging to the second source select line group, are maintained at 0V at time t4, the third source select transistor SST3 and the fourth source select transistor SST4 remain off. That is, the channel potentials of the cell strings CS31 to CS3m and CS41 to CS4m included in the third string group 3 and the fourth string group 4 can be maintained. Subsequently, at time t5, the voltages of the first source select line SSL1 and the second source select line SSL2, belonging to the first source select line group, can be reduced to ground voltage, which is the second level.

[0151] Let's refer to each other. Figure 12 Step S210 can be executed at time t3, and step S230 can be executed at time t4. That is, at... Figure 12 and Figure 13 In step S230, before increasing the voltage of the first source select line SSL1 and the second source select line SSL2 belonging to the first source select line group, the pre-charge voltage V is increased. PRCH Step S210 is applied to the common source line CSL. However, this is an example, and this disclosure is not limited thereto. Figure 12 and Figure 13 As shown, steps S210 and S230 can be executed simultaneously, or step S230 can be executed before step S210. Meanwhile, Figure 12 Step S250 can be executed at time t5.

[0152] That is, in Figure 13 During the time period t3 to t5, the precharge phase of the Nth programming loop is executed.

[0153] refer to Figure 13 The channel potential of the cell strings in the second string group STRING GROUP 2 (which is reduced to a negative voltage during the verification phase via negative boost) can be precharged during the precharge phase. Correspondingly, programming disturbances can be prevented because the channel potential of the cell strings included in the unselected string group is sufficiently increased during the programming phase.

[0154] Figure 14 This is a flowchart according to another embodiment of the present disclosure, illustrating one embodiment of the verification phase during programming operations of a semiconductor memory device.

[0155] refer to Figure 14The verification phase includes: increasing the voltage of a first source select line group to a first level, the first source select line group including a first source select line connected to a selected string group among a plurality of string groups included in the selected memory block, and maintaining the voltage of a second source select line group including the remaining source select lines (S111); and applying a verification voltage to the selected word line among the word lines connected to the selected memory block, and applying a verification pass voltage to the unselected word line (S131). Step S111 can be combined with... Figure 11 Step S110 is basically the same, and step S131 can be the same as... Figure 11 Step S130 is essentially the same. Therefore, repeated descriptions are omitted.

[0156] Let's refer to each other. Figure 11 and Figure 14 , Figure 11 The embodiment includes reducing the voltage of the first source select line group to a second level, and maintaining the voltage of the second source select line group (S150). On the other hand, Figure 14 The corresponding steps are not included. Accordingly, even if the word line voltage decreases, there will be no negative boost of the channel potential in the second string group. This reference... Figure 16 Describe it.

[0157] Figure 15 This is a flowchart according to another embodiment of the present disclosure, illustrating one embodiment of a pre-charge phase during programming operations of a semiconductor memory device.

[0158] refer to Figure 15 The pre-charge phase includes: applying a pre-charge voltage to the common source line while maintaining the voltages of the first source selection line group and the second source selection line group (S211); and reducing the voltage of the first source selection line group to a second level (S251).

[0159] Step S211 is similar to Figure 12 Step S210, and step S251 are similar to Figure 12 Step S250. Therefore, repeated descriptions are omitted.

[0160] Let's refer to each other. Figure 12 and 15 , Figure 12 The embodiment includes: increasing the voltage of the first source select line group to a first level, and maintaining the voltage of the second source select line group (S230). On the other hand, Figure 15 The corresponding steps are not included. This is a reference. Figure 16 Describe it.

[0161] Figure 16 The diagram is based on Figure 14 and Figure 15 Timing diagram of an embodiment.

[0162] exist Figure 16 The diagram illustrates the verification phase of the (N-1)th programming loop and the pre-charge phase of the Nth programming loop. (See reference...) Figure 13 Similar descriptions, see reference. Figure 16 This illustrates a scenario where the first of the first to fourth string groups included in a memory block is selected as the programming target. For example, Figure 16 The following scenario illustrates a situation where a memory cell connected to the i-th word line WLi, among the memory cells included in the first string group, is selected as the programming target memory cell. In the following text, [the term is used in conjunction with...] Figure 13 Repeated descriptions are omitted.

[0163] At time t6 during the verification phase, the verification voltage V is... VRF It is applied to the selected word line WLi and verified by voltage V. VRPASS The voltage is applied to the unselected word line. Simultaneously, an on-state voltage V1 is applied to the first drain select line DSL1, and a ground voltage, serving as the off-state voltage, is applied to the second drain select lines DSL2 through DSL4. Furthermore, the on-state voltage V1 is applied to the first source select line SSL1 and the second source select line SSL2, which belong to the first source select line group, while the voltages of the third source select line SSL3 and the fourth source select line SSL4, which belong to the second source select line group, remain at ground. Simultaneously, the voltage of the common source line CSL also remains at ground.

[0164] At time t6, because a turn-on voltage is applied to the first source select line SSL1 and the second source select line SSL2, the channel potential of the cell strings included in the first string group 1 and the second string group 2 remains at 0V. This is because the first source select transistor SST1 and the second source select transistor SST2 are turned on, and thus the voltage of the common source line CSL is transferred to the channel. Simultaneously, at time t6, because a turn-off voltage is applied to the third source select line SSL3 and the fourth source select line SSL4, the channel potential of the cell strings included in the third string group 3 and the fourth string group 4 is boosted to voltage V2 according to the increase in word line voltage.

[0165] Let's refer to each other. Figure 14Step S111 can be executed at time t6. That is, due to the execution of step S111, the voltages of the first source select line SSL1 and the second source select line SSL2, which belong to the first source select line group, increase to voltage V1, where voltage V1 is the first level. At the same time, due to the execution of step S111, the voltages of the third source select line SSL3 and the fourth source select line SSL4, which belong to the second source select line group, remain at ground voltage.

[0166] Furthermore, step S131 can also be executed at time t6. That is, at... Figure 14 In this case, step S131 is executed after step S111, but this disclosure is not limited thereto. That is, steps S111 and S131 can be executed simultaneously, or step S111 can be executed after step S131.

[0167] Simultaneously, at time t7, the voltage of the word line can be reduced to ground voltage. Furthermore, at time t7, the voltage of the first drain select line DSL1 can be reduced to ground voltage. Simultaneously, at time t7, the voltages of the first source select line SSL1 and the second source select line SSL2, belonging to the first source select line group, can be maintained. This is consistent with... Figure 13 The implementation methods differ. Figure 13 In one embodiment, at time t2, the voltage of the first source select line SSL1 and the second source select line SSL2 belonging to the first source select line group can be reduced to the ground voltage (S150). On the other hand, in Figure 16 In one embodiment, at time t7, the voltages of the first source select line SSL1 and the second source select line SSL2 are maintained.

[0168] Because the voltage of the second source select line SSL2 remains on at time t7, the second source select transistor SST2 remains on. Therefore, even if the voltages of all word lines decrease together, the channel potential of the cell strings CS21 to CS2m of the second string group STRING GROUP2 connected to the second source select line SSL2 can remain at 0V.

[0169] Simultaneously, at time t7, the channel potentials of cell strings CS31 to CS3m and CS41 to CS4m can be negatively boosted to voltage V4. Cell strings CS31 to CS3m and CS41 to CS4m are included in the third string group STRING GROUP 3 and the fourth string group STRING GROUP 4, respectively connected to the third source select line SSL3 and the fourth source select line SSL4. However, since the channel potentials of cell strings CS31 to CS3m and CS41 to CS4m have already been boosted to voltage V2 at time t6, even if the channel voltage is negatively boosted at time t7, the final potential of voltage V4 can still have a positive value.

[0170] On the other hand, since the channel potential of the cell strings CS21 to CS2m of the second string group STRING GROUP 2 remains at ground voltage, the channel voltage needs to be increased during the pre-charge phase.

[0171] Subsequently, at time t8, the pre-charge voltage V PRCH It is applied to the common source line CSL. Therefore, at time t8, the channel potential of the cell strings CS21 to CS2m of the second string group STRING GROUP 2 can increase from the ground voltage to voltage V5. In one embodiment, the voltage value of V5 can be related to the pre-charge voltage V. PRCH Essentially the same. Meanwhile, since the voltages of the third source select line SSL3 and the fourth source select line SSL4, belonging to the second source select line group, are maintained at 0V at time t8, the third source select transistor SST3 and the fourth source select transistor SST4 remain off. That is, the channel potentials of the cell strings CS31 to CS3m and CS41 to CS4m included in the third string group 3 and the fourth string group 4 can be maintained. Subsequently, at time t9, the voltages of the first source select line SSL1 and the second source select line SSL2, belonging to the first source select line group, can be reduced to ground voltage, which is the second level.

[0172] Let's refer to each other. Figure 15 Step S211 can be executed at time t8, and step S251 can be executed at time t9. That is, at... Figure 16 During the period from t8 to t9, the pre-charge phase of the Nth programming loop is executed.

[0173] refer to Figure 16 During the verification phase, the channel potential of the unit strings in the second string group STRING GROUP 2 remains at ground voltage. Therefore, during the pre-charge phase, the channel potential of the unit strings in the second string group STRING GROUP 2 can be pre-charged. Correspondingly, since the channel potential of the unit strings included in the unselected string group is sufficiently increased during the programming phase, programming disturbances can be prevented.

[0174] Figure 17 This is a block diagram illustrating one embodiment of a memory system, the memory system including... Figure 1 Semiconductor memory device 100.

[0175] refer to Figure 17 The memory system 1000 includes a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference... Figure 1The semiconductor memory device described.

[0176] Memory controller 1100 connects to a host computer and semiconductor memory device 100. Memory controller 1100 is configured to access semiconductor memory device 100 in response to requests from the host computer. For example, memory controller 1100 is configured to control read, write, erase, and background operations of semiconductor memory device 100. Memory controller 1100 is configured to provide an interface between semiconductor memory device 100 and the host computer. Memory controller 1100 is configured to drive firmware for controlling semiconductor memory device 100.

[0177] The memory controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: operating memory for the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the memory controller 1100. Furthermore, during write operations, the memory controller 1100 can temporarily store programming data provided from the host.

[0178] The host interface 1130 includes protocols for performing data exchange between the host and the memory controller 1100. As one embodiment, the memory controller 1100 is configured to communicate with the host via at least one of various interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0179] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface 1140 includes a NAND interface or a NOR interface.

[0180] Error correction block 1150 is configured to detect and correct errors in data received from semiconductor memory device 100 using error correction codes (ECC). Processing unit 1120 can control semiconductor memory device 100 to adjust read voltage and perform a reread based on the error detection results of error correction block 1150. As an embodiment, the error correction block can be provided as a component of memory controller 1100.

[0181] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As one embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), or universal flash storage (UFS).

[0182] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). A semiconductor drive (SSD) includes a storage device configured to store data in semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is significantly improved.

[0183] As another example, the memory system 1000 is provided as one of a variety of components of an electronic device, such as a computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, web tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, 3D TV, digital recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, and digital video player, device capable of transmitting and receiving information in a wireless environment, one of a variety of electronic devices for configuring a home network, one of a variety of electronic devices for configuring a computer network, one of a variety of electronic devices for configuring a telematics network, RFID device, or one of a variety of components for configuring a computing system.

[0184] As an example, the semiconductor memory device 100 or memory system can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in ways such as: package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processed stacked package (WSP).

[0185] Figure 18 It is a diagram. Figure 17 A block diagram of an application example of a memory system.

[0186] refer to Figure 18 The memory system 2000 includes a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0187] exist Figure 18 In this context, the multiple groups communicate with the memory controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip is connected to a reference... Figure 1 The semiconductor memory device 100 described is similarly configured and operated.

[0188] Each group is configured to communicate with the memory controller 2200 via a shared channel. The memory controller 2200 and the reference... Figure 17 The memory controller 1100 described is similarly configured and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0189] Figure 19 This is a block diagram illustrating a computing system, which includes a reference... Figure 18 The memory system described.

[0190] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0191] The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0192] exist Figure 19 In this configuration, semiconductor memory device 2100 is connected to system bus 3500 via memory controller 2200. However, semiconductor memory device 2100 can also be configured to be directly connected to system bus 3500. In this case, the functions of memory controller 2200 are performed by central processing unit 3100 and RAM 3200.

[0193] exist Figure 19 The middle provides a reference. Figure 18 The memory system 2000 is described. However, the memory system 2000 can be described using references. Figure 17 The memory system 1000 described is used instead. As an embodiment, the computing system 3000 may include reference... Figure 17 and Figure 18 The memory systems 1000 and 2000 are described.

[0194] The embodiments of this disclosure disclosed in this specification and accompanying drawings are provided using specific examples and are only for describing the technical content of this disclosure and helping to understand this disclosure, and are not intended to limit the scope of this disclosure.

Claims

1. A semiconductor memory device, comprising: The memory block includes multiple serial groups, each of which is connected to a corresponding source select line among multiple source select lines. Peripheral circuitry is configured to perform programming operations that store data within the memory block. as well as The control logic is configured to control the programming operations of the peripheral circuitry. The plurality of source selection lines are grouped into a plurality of source selection line groups, wherein the plurality of source selection line groups include at least a first source selection line group and a second source selection line group. The first source selection line group includes at least a first source selection line and a second source selection line, and The control logic controls the peripheral circuit to increase the voltage of the first source selection line group among the plurality of source selection line groups to a first level. The first source selection line group includes a first source selection line connected to the selected string group and a second source selection line connected to the unselected string group. A verification voltage is applied to a selected word line among the word lines connected to the memory block; And the verification will be performed by applying voltage to the unselected word line.

2. The semiconductor memory device of claim 1, wherein the control logic controls the peripheral circuitry to reduce the voltage of the first source select line group to a second level after applying the verification voltage to the selected word line among the word lines connected to the memory block and applying the verification pass voltage to the unselected word line.

3. The semiconductor memory device of claim 2, wherein the control logic controls the peripheral circuitry to: increase the voltage of the first source select line group to the first level, apply the verification voltage to the selected word line among the word lines connected to the memory block, apply the verification pass voltage to the unselected word line, and decrease the voltage of the first source select line group to the second level, while maintaining the voltage of the second source select line group, which is different from the first source select line group.

4. The semiconductor memory device of claim 3, wherein the voltage of the second source select line group is maintained at the second level.

5. The semiconductor memory device of claim 4, wherein the first level is a voltage for turning on a source selection transistor connected to the first source selection line group, and the second level is a ground voltage.

6. The semiconductor memory device of claim 2, wherein the control logic controls the peripheral circuitry to: apply a precharge voltage to a common source line connected to the memory block, and increase the voltage of the first source select line group to the first level.

7. The semiconductor memory device of claim 6, wherein the control logic controls the peripheral circuitry to: increase the voltage of the first source select line group to the first level, and then decrease the voltage of the first source select line group to the second level.

8. The semiconductor memory device of claim 7, wherein the control logic controls the peripheral circuitry to: apply the precharge voltage to the common source line connected to the memory block, increase the voltage of the first source select line group to the first level, and decrease the voltage of the first source select line group to the second level, while maintaining the voltage of the second source select line group, which is different from the first source select line group.

9. The semiconductor memory device of claim 8, wherein the memory block includes a first string group to a fourth string group, the selected string group corresponding to the first string group, the first source select line group includes a first source select line and a second source select line respectively connected to the first string group and the second string group, and the second source select line group includes a third source select line and a fourth source select line respectively connected to the third string group and the fourth string group.

10. The semiconductor memory device according to claim 9, The first string group includes a first plurality of unit strings that share a first drain selection line or a first source selection line. The second string group includes a second plurality of unit strings that share a second drain select line or a second source select line. The third string group includes a third plurality of unit strings sharing a third drain select line or a third source select line, and The fourth string group includes a fourth plurality of unit strings that share a fourth drain select line or a fourth source select line.

11. The semiconductor memory device of claim 1, wherein the control logic controls the peripheral circuitry to apply a precharge voltage to a common source line connected to the memory block after applying the verification voltage to a selected word line among the word lines connected to the memory block and applying the verification pass voltage to the unselected word line.

12. The semiconductor memory device of claim 11, wherein the control logic controls the peripheral circuitry to reduce the voltage of the first source select line group to a second level after applying the precharge voltage to the common source line.

13. The semiconductor memory device of claim 1, wherein the source select lines belonging to the first source select line group are electrically connected to each other.

14. The semiconductor memory device of claim 3, wherein the source select lines belonging to the second source select line group are electrically connected to each other.

15. A method of operating a semiconductor memory device, the method performing programming operations on a memory block comprising a first set of strings to an Nth set of strings, wherein N is a natural number greater than or equal to 3. The programming operation includes multiple programming loops, each of which includes a pre-charge phase, a programming phase, and a verification phase. The verification phase includes: The voltage of the first source select line and the second source select line is increased to a first level. The first source select line is connected to the first string group selected as the programming target from the first string group to the Nth string group, and the second source select line is connected to the second string group not selected as the programming target from the first string group to the Nth string group.

16. The method of claim 15, wherein the verification phase further comprises: A verification voltage is applied to the selected word line among the word lines connected to the memory block, and a verification pass voltage is applied to the unselected word line.

17. The method of claim 15, wherein the verification phase further comprises: The voltages of the first source select line and the second source select line are reduced to a second level.

18. The method of claim 17, wherein the first level is a voltage capable of turning on the source select transistors included in the first string group and the second string group, the second level is a ground voltage, and during the verification phase, the voltages of the third source select line and the fourth source select line are maintained at the second level, the third source select line being connected to the third string group among the first string group to the Nth string group, and the fourth source select line being connected to the fourth string group among the first string group to the Nth string group.

19. The method of claim 18, wherein the pre-charging phase comprises: Apply a pre-charge voltage to the common source line connected to the memory block; as well as The voltage of the first source select line and the second source select line is increased to the first level.

20. The method of claim 19, wherein during the pre-charge phase, the voltages of the third source selection line and the fourth source selection line are maintained at the second level.

21. The method of claim 15, wherein the pre-charging phase comprises: Apply a pre-charge voltage to the common source line connected to the memory block; as well as The voltages of the first source select line and the second source select line are reduced to a second level.

22. The method of claim 18, wherein the first source select line and the second source select line are electrically connected to each other, and the third source select line and the fourth source select line are electrically connected to each other.

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