Read cache for resetting read disturb mitigation

Abstract

The present disclosure relates to a read cache for resetting read disturb mitigation. Methods and systems include a memory device having a plurality of memory cells configured to store data. The memory device also includes a cache configured to store at least a portion of the data to provide access to the at least a portion of the data without accessing the plurality of memory cells. The memory device also includes a control circuit system configured to receive a read command having a target address. Based on the target address, the control circuit system is configured to determine that the at least a portion of the data is present in the cache. Using the cache, the control circuit system also outputs read data from the cache without accessing the plurality of memory cells.

Description

Technical Field

[0001] The present disclosure relates to a read cache for reset read disturb mitigation. Background Art

[0002] This section is intended to introduce the reader to various technical aspects that may be related to the various aspects of the present technology described and / or claimed below. It is believed that this discussion is helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Therefore, it should be understood that these statements should be read in this sense and not as an admission of prior art.

[0003] In general, a computing system includes a processing circuit system, such as one or more processors or other suitable components, and a memory device, such as a chip or integrated circuit. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuit system. For example, based on a user input to the computing system, the processing circuit system may request the memory module to retrieve data corresponding to the user input from its memory device. In some examples, the retrieved data may include firmware or instructions that can be executed by the processing circuit system to perform an operation, and / or may include data to be used as input for the operation. In addition, in some cases, data output from an operation may be stored in a memory, such as to enable subsequent retrieval of the data from the memory.

[0004] Some memory devices include memory cells that can be accessed by turning on a transistor that couples the memory cell (e.g., a capacitor) to a word line or a bit line. In contrast, a threshold type memory device includes a memory device that is accessed by providing a voltage across a memory cell, wherein a data value is stored based on a threshold voltage of the memory cell. For example, the data value may be based on whether a threshold voltage of the memory cell is exceeded, and in response to the voltage provided across the memory cell, the memory cell conducts current. The stored data value may be changed, such as by applying a voltage sufficient to change the threshold voltage of the memory cell. One example of a threshold type memory cell may be a cross point memory cell.

[0005] For threshold type memory, the threshold voltage (VTH) determines when a particular action is performed. However, this threshold may suffer from reliability issues regarding read disturb at reset (RDR), which destroys the polarization effect by soft programming the opposite polarity. Specifically, as the number of read disturbs increases, the reliability issues may lead to cumulative VTH degradation (e.g., VTH decreases) until the memory operation fails. These reliability issues may be greater or more problematic for certain aspects of the memory device (e.g., read disturb at reset (RDR)) than for other aspects (e.g., write operations). Summary of the invention

[0006] In one aspect, the present disclosure relates to a memory device comprising: a plurality of memory cells configured to store data; a cache configured to store at least a portion of the data to provide read access to the at least a portion of the data without accessing the plurality of memory cells; and a control circuit system configured to: receive a read command having a target address; determine that the at least a portion of the data stored in the cache corresponds to the target address; and output read data from the cache without accessing the plurality of memory cells.

[0007] On the other hand, the present disclosure relates to a method, comprising: receiving a first read command at a control circuit system of a memory device having a first target address indicating a first position within a plurality of memory cells to be read; determining whether an on-device cache of the memory device has a first entry corresponding to the first target address; and in response to the on-device cache having the first entry corresponding to the first target address, outputting data from the on-device cache without disturbing the first position of the plurality of memory cells.

[0008] On the other hand, the present disclosure relates to a memory device, comprising: a plurality of memory cells configured to store data; a cache configured to store a portion of the data to provide read access to the portion of the data without accessing the plurality of memory cells; and a control circuit system configured to: receive a read command having a target address; determine, based on the target address, whether the target address corresponds to the portion of the data using an entry in the cache; if the entry indicates that the portion of the data corresponds to the target address, read the portion of the data from the cache without accessing the plurality of memory cells; and if the entry indicates that the target address does not correspond to the portion of the data, read the target address from the plurality of memory cells using a length of an inter-pulse delay between pulses of the read operation, wherein the length of the inter-pulse delay is based at least in part on a read operation from the cache without interfering with the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the drawings, in which:

[0010] Figure 1 is a simplified block diagram illustrating certain features of a memory device including a cache and a memory array of memory cells according to an embodiment of the present disclosure;

[0011] Figure 2The present invention is described in accordance with an embodiment of the present disclosure. Figure 1 a side view of a portion of a memory array;

[0012] Figure 3 is a negative final readout according to an embodiment of the present disclosure Figure 1 A timing diagram of a read operation of a memory device;

[0013] Figure 4 is a positive final readout according to an embodiment of the present disclosure Figure 1 A timing diagram of a read operation of a memory device;

[0014] Figure 5 The use of the embodiments according to the present disclosure Figure 3 A graph of voltage and row error rate for different numbers of reads of a timing diagram;

[0015] Figure 6 is a graph of interference cycles and bit error rates for different inter-pulse delays for a read operation according to an embodiment of the present disclosure;

[0016] Figure 7 is a block diagram of a process for a read operation according to an embodiment of the present disclosure, the process including determining in response to a read command whether Figure 1 cache or memory array read; and

[0017] Figure 8 is a block diagram of a process for a write operation according to an embodiment of the present disclosure, the process including determining in response to a write command in addition to writing to Figure 1 Whether to write to the memory array in addition to Figure 1 cache. DETAILED DESCRIPTION

[0018] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation (as in any engineering or design project), many implementation-specific decisions must be made to achieve the developer's specific goals, such as meeting system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be understood that such a development effort may be complex and time-consuming, but will still be a routine design, fabrication, and manufacturing task for a person of ordinary skill in the art who benefits from this disclosure.

[0019] The memory typically includes an array of memory cells, wherein each memory cell is coupled between at least two access lines. For example, a memory cell may be coupled to an access line such as a bit line and a word line. Each access line may be coupled to a large number of memory cells. To select a memory cell, one or more drivers may provide a selection signal (e.g., a voltage and / or current) on the access line to access the storage capacity of the memory cell. By applying a voltage and / or current to the corresponding access line, the memory cell may be accessed, such as writing data to the memory cell and / or reading data from the memory cell.

[0020] In some memories, the memory cells of the array may be organized into layers of memory cells. A layer of memory cells may be a single plane of memory cells disposed between a layer of word lines and a layer of bit lines. The array may be a layer stack that includes any number of layers (e.g., 0 layers, 1 layer, 2 layers, 4 layers, any number of layers) of memory cells as different layers of the array.

[0021] Within a plane, a two-dimensional array of memory cells may be arranged at different intersections of word lines and bit lines in a plane. As previously described for threshold-type memories, the threshold voltage (VTH) may suffer from reliability issues regarding read disturbance at reset (RDR), which destroys the polarization effect by soft programming the opposite polarity. Specifically, as the number of read disturbances increases, reliability issues may result in cumulative VTH degradation (e.g., VTH reduction) until the memory operation fails repeatedly. As discussed below, this VTH degradation can be mitigated by extending the inter-pulse delay (IPD) between pulses of the read operation. However, if this extension is not modified, compliance of the output transmission of data of the memory device may be hampered. To address this issue, a cache may be used to replace the read operation of the memory array itself. This time of performing a read operation without accessing the memory array can be used to extend the IPD for the read performed on the memory array itself, thereby mitigating the VTH degradation without sacrificing compliance with the specifications of the memory device.

[0022] Remember the above introduction, Figure 11 is a block diagram of a portion of a memory device 100. The memory device 100 may be any suitable form of memory, such as non-volatile memory (e.g., cross-point memory) and / or volatile memory. The memory device 100 may include one or more memory cells 102, one or more bit lines 104 (e.g., 104-0, 104-1, 104-2, 104-3), one or more word lines 106 (e.g., 106-0, 106-1, 106-2, 106-3), one or more word line decoders 108 (e.g., word line decoding circuitry), and one or more bit line decoders 110 (e.g., bit line decoding circuitry). The memory cells 102, bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 may form a memory array 112.

[0023] Each of the memory cells 102 may include a selector and / or a storage element. When the voltage across the selector of the respective memory cell reaches a threshold, the storage element may be accessed to read a data value from the storage element and / or write a data value to the storage element. In some embodiments, each of the memory cells 102 may not include a separate selector and storage element, and have a configuration such that the memory cell still functions as having a selector and a storage element (e.g., may include using a material that behaves like both a selector material and a storage element material). For ease of discussion, Figure 1 Discussion may be made in terms of bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110, but these designations are non-limiting. The scope of the present disclosure should be understood to cover memory cells 102 coupled to multiple access lines and accessed through corresponding decoders, where the access lines can be used to store data into and read data from the memory cells 102. In addition, the memory device 100 may include other circuitry, such as biasing circuitry configured to bias the bit lines 104 or word lines 106 in corresponding directions. For example, the bit lines 104 may be biased with positive biasing circuitry, while the word lines 106 may be biased with negative biasing circuitry.

[0024] The bit line decoders 110 may be organized in multiple groups of decoders. For example, the memory device 100 may include a first group of bit line decoders 114 (e.g., multiple bit line decoders 110) and / or a second group of bit line decoders 116 (e.g., different groups of multiple bit line decoders 110). Similarly, the word line decoders 108 may also be arranged into groups of word line decoders 108, such as a first group of word line decoders 118 and / or a second group of word line decoders 120. When selecting a target memory cell 102A from the memory cells 102, the decoders may be used in combination with each other to drive the memory cells 102 (e.g., pairs and / or pairs of pairs on either side of the word line 106 and / or the bit line 104). For example, the bit line decoder 110-3 may operate in conjunction with the bit line decoder 110'-3 and / or the word line decoders 108-0, 108'-0 to select the memory cell 102A. As may be appreciated herein, the decoder circuitry on either end of the word line 106 and / or the bit line 104 may be different.

[0025] Each of the bit lines 104 and / or word lines 106 may be a metal trace disposed in the memory array 112 and formed of a metal such as copper, aluminum, silver, tungsten, or the like. Thus, the bit lines 104 and word lines 106 may have a uniform resistance per length and a uniform parasitic capacitance per length so that the resulting parasitic load may increase uniformly per length. Note that the depicted components of the memory device 100 may include additional circuitry not specifically depicted and / or may be disposed in any suitable arrangement. For example, a subset of the word line decoders 108 and / or bit line decoders 110 may be disposed on different sides of the memory array 112 and / or different physical sides of any plane including circuitry.

[0026] The memory device 100 may also include control circuitry 122. The control circuitry 122 may be communicatively coupled to the respective word line decoders 108 and / or bit line decoders 110 to perform memory operations, such as by causing the decoding circuitry (e.g., a subset of the word line decoders 108 and / or the bit line decoders 110) to generate a selection signal (e.g., a selection voltage and / or a selection current) for selecting a target of a memory cell. In some embodiments, a positive voltage and a negative voltage may be provided to the target of the memory cell 102 on one or more of the bit lines 104 and / or the word lines 106, respectively. In some embodiments, the decoder circuitry may provide a bias electrical pulse (e.g., a voltage and / or a current) to the access line to access the memory cell. The electrical pulse may be a square pulse, or in other embodiments, other shaped pulses may be used. In some embodiments, the voltage provided to the access line may be a constant voltage.

[0027] Activating the decoder circuit may enable an electrical pulse to be delivered to the target of the memory cell 102, so that the control circuit 122 can access the data storage device of the target memory cell, such as reading from the data storage device or writing to the data storage device. After accessing the target of the memory cell 102, the data stored in the storage medium of the target memory cell may be read or written. Writing to the target memory cell may include changing the data value stored by the target memory cell. As previously discussed, the data value stored by the memory cell may be based on the threshold voltage of the memory cell. In some embodiments, the memory cell may be "set" to have a first threshold voltage, or may be "reset" to have a second threshold voltage. The set memory cell may have a lower threshold voltage than the reset memory cell. By setting or resetting the memory cell, different data values ​​may be stored by the memory cell. Reading the target of the memory cell 102 may include determining whether the target memory cell is characterized by a first threshold voltage and / or a second threshold voltage. In this way, the threshold voltage window may be analyzed to determine the value stored by the target of the memory cell 102. The threshold voltage window may be created by applying programming pulses with opposite polarity biases to the memory cells 102 (e.g., specifically, writing to the selector device (SD) material of the memory cells) and reading the memory cells 102 (e.g., specifically, reading the voltage stored by the SD material of the memory cells 102) using signals with a given (e.g., known) fixed polarity. In some embodiments, a select input 126 may be received from a host device 124, such as a host processor reading / writing data from / to the memory device 100, to cause the control circuit 122 to access a particular memory cell 102 using corresponding select signals to the corresponding word line decoders 108 and bit line decoders 110. Additionally, the control circuit 122 may include a cache 128, which may be used to reduce threshold degradation according to embodiments described in more detail below.

[0028] Figure 2 1 is a diagram illustrating a portion of a memory array 130 according to an embodiment of the present disclosure. Within the memory array 130, memory cells are located at the intersections of orthogonal lines. The memory array 130 may be a cross-point array including word lines 106 (e.g., 106-0, 106-1, ..., 106-N) and bit lines 104 (e.g., 104-0, 104-1, ..., 104-M). A memory cell 102 may be located at each of the intersections of the word lines 106 and the bit lines 104. The memory cell 102 may function in a dual-terminal architecture (e.g., where a particular word line 106 and bit line 104 combination serves as an electrode for the memory cell 102).

[0029] Each of the memory cells 102 may be a resistance variable memory cell, such as a resistance random access memory (RRAM) cell, a conductive bridge random access memory (CBRAM) cell, a phase change memory (PCM) cell, and / or a spin transfer torque magnetic random access memory (STT-RAM) cell, among other types of memory cells. Each of the memory cells 102 may include a memory element (e.g., a memory material) and a selector element (e.g., a selector device (SD) material) and / or a material layer that functionally replaces a separate memory element layer and a selector element layer. The selector element (e.g., SD material) may be disposed between a word line contact (e.g., a layer interface between a corresponding one of the word lines 106 and the memory material) and a bit line contact (e.g., a layer interface between a corresponding one of the bit lines 104 and the selector element) associated with a word line or a bit line forming the memory. When a read or write operation is performed on the memory cell, an electrical signal may be transmitted between the word line contact and the bit line contact.

[0030] The selector element may be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, etc., or formed similarly to the underlying cell structure. In some examples, the selector element may include a selector material, a first electrode material, and a second electrode material. The memory element of the memory cell 102 may include a memory portion of the memory cell 102 (e.g., a portion that is programmable to different states). For example, in a resistance variable memory cell 102, the memory element may include a portion of the memory cell that has a resistance that is programmable to a specific level corresponding to a specific state in response to an applied programming voltage and / or current pulse. In some embodiments, the memory cell 102 may be characterized as a threshold type memory cell that is selected (e.g., activated) based on a voltage and / or current crossing a threshold associated with the selector element and / or the memory element. Embodiments are not limited to a specific resistance variable material or materials associated with the memory element of the memory cell 102. For example, the resistance variable material may be a chalcogenide formed of various doped or undoped chalcogenide-based materials. Other examples of resistance variable materials that can be used to form memory elements include binary metal oxide materials, giant magnetoresistive materials, and / or various polymer-based resistance variable materials, among others.

[0031] In operation, the memory cells 102 may be programmed by applying a voltage (e.g., a write voltage) across the memory cells 102 via selected word lines 106 and bit lines 104. A sensing (e.g., a read) operation may be performed to determine the state of one or more memory cells 102 by sensing current. For example, in response to a particular voltage applied to the selected bit lines 104 / word lines 106 forming the respective memory cells 102, current may be sensed on the one or more bit lines 104 / one or more word lines 106 corresponding to the respective memory cells 102.

[0032] As illustrated, the memory array 130 may be arranged in a cross-point memory array architecture (e.g., a three-dimensional (3D) cross-point memory array architecture) that extends in any direction (e.g., x-axis, y-axis, z-axis). The multi-level cross-point memory array 130 may include a number of consecutive memory cells (e.g., 102B, 102C, 102D) disposed between alternating (e.g., interleaved) levels of word lines 106 and bit lines 104. The number of levels may be expanded in number or reduced in number, and should not be limited to the amounts or arrangements depicted. Each of the memory cells 102 may be formed between a word line 106 and a bit line 104 (e.g., between two access lines) such that a respective one of the memory cells 102 may be directly electrically coupled (e.g., electrically coupled in series) with its respective pair of bit lines 104 and word lines 106, and / or formed from electrodes (e.g., contacts) made from respective portions of metal of a pair of respective bit lines 104 and word lines 106. For example, memory array 130 may include a three-dimensional matrix of individually addressable (e.g., randomly accessible) memory cells 102 that may be accessed at a granularity as small as a single storage element and / or multiple storage elements for data operations (e.g., sensing and writing). In some cases, memory array 130 may include more than Figure 2 1. More or fewer bit lines 104, word lines 106, and / or memory cells 102 are shown in the examples of FIG. Each level can include one or more memory cells 102 aligned in the same plane.

[0033] As previously described, read disturbance (RDR) during reset may degrade the corresponding threshold. Specifically, the second threshold voltage corresponding to the reset may be particularly susceptible to threshold voltage degradation due to RDR. As previously described, this degradation may be at least partially due to the destruction of the polarization effect by RDR. In addition, the amount of degradation may be proportional to the magnitude of the polarization effect destroyed. In addition, when read disturbance occurs on a group, the first threshold voltage corresponding to the group may be less susceptible or even unaffected by such degradation, but may benefit from the mitigation of threshold voltage degradation. In RDR, the memory device 100 may have a minimum read-to-read tolerance (e.g., 80ns or 150ns) for the memory array 130, which may limit the number of RDR counts (e.g., 130k or 1M) before the cell fails repeatedly. As discussed below, since the length of the IPD may be proportional to the magnitude of the polarization effect destroyed by the RDR, this threshold degradation may be strongly dependent on the read cycle inter-pulse delay (IPD).

[0034] Back to Figure 1And as discussed below, the cache 128 can be used to reduce threshold degradation by extending the minimum read-to-read delay (i.e., enabling a larger IPD) to mitigate threshold degradation without causing the memory device 100 to operate outside the specification timing of the memory device 100. The cache 128 can be implemented using any suitable storage device, such as a first-in-first-out memory (FIFO). In addition, the cache 128 (such as a FIFO) can be implemented using a content addressable media (CAM) or other suitable implementation. For example, a static random access media (SRAM) can be used to implement the CAM. The CAM can use the CAM address as a counter that is incremented when a read misses the cache 128 because no address in the cache 128 matches the incoming address for the read.

[0035] Figure 3 1 is a timing diagram 150 of an RDR with a negative polarity final readout. As illustrated, the timing diagram 150 shows that a preset pulse / value 152 corresponds to a certain value before a reset pulse 154 used to initiate a reset (e.g., power-on reset (POR)) read. After a pre-read delay 156, a reset read 158 begins and has two or more pulses 160. In the reset read 158, an IPD 162 occurs between each of the two or more pulses 160 of the read. After a post-read delay 164, a final readout 166 is transmitted. In the illustrated embodiment of the timing diagram 150, the RDR has a negative polarity. A positive polarity RDR can be constructed similarly. For example, Figure 4 A timing diagram 170 is shown for an RDR having positive polarity. In the timing diagram 170, the RDR is identical to the RDR in the timing diagram 150, except that Figure 4 The RDR has a final readout of 172 having a positive polarity, while Figure 3 The final readout 166 has a negative polarity.

[0036] Figure 5 1 is a graph 180 comparing possible nominal voltages 182 (including stress voltage levels 183) to row error rates 184 for different RDR counts, each corresponding to lines 186, 188, 190, 192, 196, and 198 for negative polarity RDR. For example, each line may correspond to a different number of reads in rapid succession. For example, line 186 may correspond to 130k reads, line 188 may correspond to 40k reads, line 190 may correspond to 10k reads, line 192 may correspond to 1k reads, line 194 may correspond to 100 reads, and line 196 may correspond to 2 reads. In general, for either positive or negative polarity RDR, an increase in RDR is associated with a higher error rate between the stress voltage level 183 and some nominal voltage level 198.

[0037] Figure 6 200 is a graph comparing the number of interference cycles 202 and the threshold voltage bit error rate 204, wherein line 206 corresponds to different IPD durations for negative polarity RDR. Line 206 corresponds to increasing IPD durations along line 208. As illustrated, for longer IPDs, the degradation at the RDR count is at least partially alleviated. For RDRs with positive polarity final readout, similar relief can be obtained using longer IPD durations. In addition, regardless of the length of the pre-read delay 156 and / or the post-read delay 164, similar relief can be achieved. In fact, some embodiments of the memory device 100 can utilize extended and / or shortened pre-read delay 156 and / or post-read delay 164 while mitigating threshold degradation due to RDR, while others do not extend or shorten the pre-read delay 156 and / or post-read delay 164. For example, in some embodiments, the memory device 100 may extend or shorten the pre-read delay 156 and / or the post-read delay 164 to align the reset read 158 and / or the final readout 166, 172 to the corresponding position in the RDR. Although the extended IPD duration can mitigate threshold voltage degradation, the timing specifications of the memory device 100 may not allow reading from the memory array 130 in at least some cases. In such cases, the memory device 100 may utilize the cache 128 to extend the duration of the IPD to a longer duration than would be possible without using the cache 128 or operating outside the specifications of the memory device 100. For example, some reads may be performed using the cache 128 without interfering with the active array (e.g., the memory array 130). This time freed up in the active array using the read operation from the cache 128 can be used to extend the IPD duration to mitigate threshold voltage degradation for at least some operations (e.g., RDR) that would not be possible within the memory device specifications without the cache 128.

[0038] Figure 71 is a flow chart of a process 300 for a control circuit 122 that utilizes a cache 128 to mitigate threshold voltage degradation due to RDR and / or other read operations on memory cells of a memory device 100. The control circuit 122 receives an incoming read command (block 302). The read command has a corresponding read target address. The read command may be received from a host device 124. The control circuit 122 checks whether the target address matches any entry in the cache 128 (block 304). As previously described, the cache 128 may be implemented using a FIFO. In some embodiments, a FIFO may be included for each memory partition. For each partition, each entry may have one or more validity bits indicating whether the entry is valid or invalid. Each entry may also include a number (e.g., 24) of bits corresponding to an address within the partition. The entry may also include a number (e.g., 128) of data bits stored at the corresponding address. If the cache 128 includes 32 entries, it allows 32 reads with an interval of 80ns for 4,896 cells. Using cache 128, the IPD can be relaxed to 80ns*32=2.56ns. In some embodiments, other intervals and / or numbers of entries per partition may be used. In addition, by having 2^n (e.g., 32) reads, the counter can be wrapped around to overflow beyond a maximum number (e.g., 31) back to zero to continue FIFO behavior. In addition, as previously discussed, the FIFO can be implemented as an SRAM-based CAM, with the CAM address acting as a counter that wraps around on overflow. Using the CAM address as a counter enables the control circuit 122 to quickly determine whether the target address is in the cache 128.

[0039] If a match for the target address is not found in cache 128, control circuit 122 reads the target data from the active array (block 306). On this read miss, control circuit 122 then writes the data and corresponding address to cache 128 for subsequent read commands (block 308). The counter is then incremented to the next entry. Data is output from cache 128 and / or the active array (block 310).

[0040] If the target address matches an entry in cache 128, control circuit 122 reads from cache 128 without interrupting the active array (block 312). In the case where cache 128 is used to perform at least some of the reads, the output of the data may be sufficient to meet timing specifications while relaxing the IPD of the RDR (or other read disturb events) on the active array to mitigate threshold voltage degradation resulting from the RDR (and / or other read disturb events).

[0041] Because data in the active array may change when a write occurs, control circuitry 122 may update cache 128 when a write operation is performed. Figure 8 3 is a flow chart of process 320. Process 320 includes control circuit 122 receiving a write command from host device 124 (block 322). The write command has a target address. Control circuit 122 causes the data of the write command to be written to the active array at the target address (block 324). Control circuit 122 also checks whether the target address matches one or more entries in cache 128 (block 326). If no entry matches the target address, control circuit 122 considers the write operation to be over (block 328). However, if one or more entries match the target address, control circuit 122 updates cache 128 (block 330). Updating the cache can be implemented in a variety of techniques. For example, control circuit 122 can invalidate the entry in cache 128 corresponding to the write command. Control circuit 122 can then wait for the next read command of the active array to the target address to re-enable the entry again. Additionally or alternatively, control circuit 122 can update the entry with information for the target address to be written into the active array. Additionally or alternatively, control circuitry 122 may invalidate the entire cache 128 and rebuild cache 128 using a subsequent read operation.

[0042] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0043] The techniques presented and claimed herein are cited and applied to material objects and specific examples of a practical nature that significantly improve the art and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing the function] ..." or "steps for [performing the function] ...", then these elements are intended to be interpreted under 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, such elements are not intended to be interpreted under 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: a plurality of memory cells configured to store data; a cache configured to store at least a portion of the data to provide read access to the at least a portion of the data without accessing the plurality of memory cells; and A control circuit system configured to: receiving a read command having a target address; determining that the at least a portion of the data stored in the cache corresponds to the target address; outputting read data from the cache without accessing the plurality of memory cells, wherein an entry in the cache corresponding to the target address comprises: one or more validity bits indicating whether the entry is valid; a plurality of data bits indicating data stored at the target address; and a plurality of address bits indicating the target address; and An inter-pulse delay for reading of the plurality of memory cells is extended beyond specifications for data output from the memory device.

2. The memory device of claim 1, wherein the control circuitry is configured to receive the read command from a host device coupled to the memory device and to output the read data to the host device.

3. The memory device of claim 1, wherein the cache comprises a first-in-first-out memory (FIFO).

4. The memory device of claim 1, wherein the cache comprises a content addressable memory (CAM).

5. The memory device of claim 4, wherein the control circuitry is configured to use a CAM address of the CAM as a counter that is incremented when a read miss occurs to the cache for a received read command.

6. The memory device of claim 1 , wherein the control circuitry is configured to: receiving another read command having another target address; determining that the another target address does not correspond to an entry in the cache; and In response to the determining that the another target address does not correspond to the entry, data is written to the cache for the another target address.

7. The memory device of claim 1 , wherein the control circuitry is configured to: receiving a write command having a write target address and write data; writing the write data to at least a portion of the plurality of memory cells; determining that an entry in the cache corresponds to the write target address; and The cache is updated based at least in part on the determination that the entry in the cache corresponds to the write target address.

8. The memory device of claim 7, wherein updating the cache comprises: invalidate said entry; and Wait for a subsequent read command to re-enable the entry.

9. The memory device of claim 7, wherein updating the cache comprises overwriting the entry with the write data.

10. The memory device of claim 7, wherein updating the cache comprises: Invalidate the entire cache; and Subsequent read commands are used to rebuild the cache.

11. A method of operating a memory device, comprising: receiving a first read command at control circuitry of the memory device having a first target address indicating a first location within a plurality of memory cells to be read; determining whether an on-device cache of the memory device has a first entry corresponding to the first target address; in response to the on-device cache having the first entry corresponding to the first target address, outputting data from the on-device cache without disturbing the first location of the plurality of memory cells; receiving, at the control circuitry, a second read command having a second target address indicating a second location within the plurality of memory cells to be read; determining that the on-device cache of the memory device does not have a valid entry corresponding to the second target address; outputting data from the second location of the plurality of memory cells in response to the on-device cache not having a valid entry corresponding to the second target address; and An extended inter-pulse delay between pulses for reading the plurality of memory cells using a residual time created using a read operation performed using a cache on the device.

12. The method of claim 11, wherein the first entry comprises: one or more validity bits indicating whether the first entry is valid; a plurality of data bits indicating data stored at the first target address; and A plurality of address bits indicating the first target address.

13. The method according to claim 11, comprising: receiving a write command having a write target address and write data; storing the write data in a third location of the plurality of memory cells corresponding to the write target address; determining that a second entry in a cache on the device corresponds to the write target address; and The on-device cache is updated based at least in part on the determination that the second entry in the on-device cache corresponds to the write target address.

14. The method of claim 13, wherein updating the on-device cache comprises overwriting the second entry with the write data.

15. The method of claim 13, wherein updating the on-device cache comprises: invalidating the second entry; and A subsequent read is awaited to re-enable the second entry.

16. A memory device comprising: a plurality of memory cells configured to store data; a cache configured to store a portion of the data to provide read access to the portion of the data without accessing the plurality of memory cells; and A control circuit system configured to: receiving a read command having a target address; determining, based on the target address, using an entry in the cache, whether the target address corresponds to the portion of the data; reading the portion of the data from the cache without accessing the plurality of memory cells if the entry indicates that the portion of the data corresponds to the target address; and If the entry indicates that the target address does not correspond to the portion of the data, then the target address is read from the multiple memory cells using a length of an inter-pulse delay between pulses of a read operation, wherein the length of the inter-pulse delay is based at least in part on a read operation from the cache without disturbing the multiple memory cells.

17. The memory device of claim 16, wherein the control circuitry comprises the cache.

18. The memory device of claim 17, wherein the cache comprises a content addressable memory (CAM).

19. The memory device of claim 16, wherein the cache comprises a first-in-first-out memory (FIFO).

20. The memory device of claim 16, wherein the control circuitry is configured to: receiving a write command having a write target address and write data; writing the write data into a location in the plurality of memory cells corresponding to the write target address; determining that a write entry in the cache corresponds to the write target address; and The cache is updated based at least in part on the determination that the write entry in the cache corresponds to the write target address.

21. The memory device of claim 20, wherein the write entry comprises the entry.

Images