Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a plurality of discrete side walls on the substrate, the side walls including mask side walls and dummy mask side walls; removing part of the dummy mask side walls in a region, so that uniformity of a distance between the mask side walls and the remaining dummy mask side walls satisfies a preset range; patterning the substrate with the mask side walls and the remaining dummy mask side walls as masks, to form fins corresponding to the mask side walls and dummy fins corresponding to the remaining dummy mask side walls; and removing the dummy fins. The method for forming a semiconductor structure can improve the key size of fins formed by the prior art, so as to meet process requirements.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Currently, in semiconductor manufacturing, as semiconductor processes continue to miniaturize, the distance between the drain and source of traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) is constantly decreasing. The contact area between the gate and the drain and source is getting smaller and smaller, which leads to a decrease in the gate structure's control over the channel. It is also becoming more difficult to pinch off the channel with the gate voltage, making the subthreshold leakage phenomenon, also known as the short-channel effect (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor manufacturing processes have gradually shifted from planar MOSFETs to more efficient three-dimensional transistors, such as FinFETs. Depending on process requirements, fins with different pitches and critical dimensions (CDs) are typically formed. A common approach is to use a fin-cutting process to create these fins. Fin-cutting processes generally include cut-first and cut-last processes.

[0004] As the critical dimensions of the fins and the spacing between them continue to shrink, the related manufacturing processes become more stringent. While pre-cutting the fins can expand the fin cutting window, it can result in fins having different critical dimensions when forming them using a patterned substrate, failing to meet process requirements. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the critical dimensions of fins with different sizes formed in the prior art, thereby enabling them to meet process requirements.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Provide a base;

[0008] Multiple discrete sidewalls are formed on the substrate, including mask sidewalls and dummy mask sidewalls;

[0009] Remove some of the pseudo-mask sidewalls so that the uniformity of the spacing between the mask sidewalls and the remaining pseudo-mask sidewalls meets a preset range;

[0010] Using the mask sidewalls and the remaining pseudo mask sidewalls as masks, the substrate is patterned to form fins corresponding to the mask sidewalls and pseudo fins corresponding to the remaining pseudo mask sidewalls;

[0011] Remove the pseudofin portion.

[0012] Optionally, the number of adjacent pseudo-mask sidewalls in the removed portion of the region is less than or equal to 2.

[0013] Optionally, the distance between the adjacent pseudo-mask sidewalls of the removed portion of the region and the active region is less than or equal to a preset threshold.

[0014] Optionally, the preset threshold is 15 to 45 nm.

[0015] Optionally, removing the pseudo-mask sidewalls in the aforementioned portion of the region includes:

[0016] A first mask layer is formed on the substrate, the first mask layer having a first opening that exposes the pseudo mask sidewall of the partial area;

[0017] Using the first mask layer as a mask, remove the pseudo mask sidewalls of the portion of the area exposed by the first opening;

[0018] Remove the first mask layer.

[0019] Optionally, the material of the first mask layer is SOC.

[0020] Optionally, removing the pseudo-fin includes:

[0021] A second mask layer is formed on the substrate, the second mask layer having a second opening that exposes the remaining portion of the pseudofin portion;

[0022] The false fin is removed by masking with the second mask layer;

[0023] Remove the second mask layer.

[0024] Optionally, the material of the second mask layer is SOC.

[0025] Optionally, before forming the sidewall, the forming method further includes:

[0026] A hard mask material layer is formed on the substrate;

[0027] The graphical representation of the substrate includes:

[0028] Using the mask sidewalls and the remaining pseudo-mask sidewalls as masks, the hard mask material layer is etched to form a hard mask layer;

[0029] The substrate is etched using the hard mask layer as a mask.

[0030] Optionally, an anisotropic etching process can be used to remove the pseudo-mask sidewalls in the aforementioned regions.

[0031] This invention, through the formation of multiple discrete sidewalls on the substrate, including mask sidewalls and pseudo-mask sidewalls, and the removal of a portion of the pseudo-mask sidewalls, ensures that the uniformity of the spacing between the mask sidewalls and the remaining pseudo-mask sidewalls meets a preset range. In other words, the spacing distribution between the remaining pseudo-mask sidewalls and the mask sidewalls is more uniform. Consequently, when the substrate is patterned using the mask sidewalls and the remaining pseudo-mask sidewalls as masks, the etching rate is more uniform, and the consistency of the critical dimensions of the formed fins and pseudo-fins is stronger, thus better meeting the process requirements.

[0032] Furthermore, since the number of adjacent pseudo-mask sidewalls in the removed portion of the region is less than or equal to 2, the remaining mask sidewalls and pseudo-mask sidewalls are more evenly distributed and have a higher spacing density. Therefore, when the substrate is patterned using the mask sidewalls and the remaining pseudo-mask sidewalls as masks, the etching rate is more uniform, resulting in stronger consistency in the critical dimensions of the formed fins and pseudo-fins, thus better meeting the process requirements.

[0033] Furthermore, since the distance between the dummy mask sidewall of the removed portion and the active region is less than or equal to a preset threshold, the position of the etched dummy fin is a certain distance away from the active region. Therefore, during the etching process, the fin can be avoided from being damaged or the dummy fin can be left behind, thereby improving the yield of the semiconductor structure. Attached Figure Description

[0034] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0035] Figures 6 to 19 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] Figure 20 This is a schematic diagram of the key dimensions of the fin in a specific application scenario of Embodiment 1 of the present invention. Detailed Implementation

[0037] The devices currently being formed still have performance issues. This paper analyzes the reasons for the poor performance of the devices by combining a semiconductor structure formation method.

[0038] Reference Figures 1 to 5 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0039] Reference Figure 1 A substrate 1 is provided, and a plurality of discrete sidewalls are formed on the substrate 1, the sidewalls including mask sidewalls 2 and pseudo-mask sidewalls 3.

[0040] Reference Figure 2 A mask layer 4 is formed on the substrate, the mask layer 4 having an opening 5 that exposes the top of the pseudo mask sidewall 3.

[0041] Combination Figure 2 , refer to Figure 3 Using the mask layer 4 as a mask, a first photolithography and a first etching are performed to remove part of the pseudo mask sidewalls 3; then a second photolithography and a second etching are performed to remove the remaining pseudo mask sidewalls. After the above two consecutive steps, all the pseudo mask sidewalls 3 can be removed.

[0042] Reference Figure 4 Remove the mask layer 4.

[0043] Reference Figure 5 After removing the mask layer 4, the substrate 1 is patterned using the mask sidewall 2 as a mask to form a fin 6 corresponding to the mask sidewall.

[0044] In the above method for forming the semiconductor structure, the dummy mask sidewalls 3 are first removed. After removing the dummy mask sidewalls 3, the mask sidewalls 2 have different spacings, resulting in non-uniform pattern density of the mask sidewalls 2. Figure 3 As shown. During the mask patterning process using the mask sidewall 2 as the mask substrate, uneven etching rates occur in areas with different pattern densities, resulting in fins with varying critical dimensions that fail to meet process requirements, such as... Figure 5 As shown.

[0045] To address the aforementioned issues, embodiments of the present invention form multiple discrete sidewalls on the substrate, wherein the sidewalls include mask sidewalls and pseudo-mask sidewalls, and remove a portion of the pseudo-mask sidewalls. This ensures that the spacing between the mask sidewalls and the remaining pseudo-mask sidewalls meets a preset range. In other words, the spacing distribution between the remaining pseudo-mask sidewalls and the mask sidewalls is more uniform. Consequently, when the substrate is patterned using the mask sidewalls and the remaining pseudo-mask sidewalls as masks, the etching rate is more uniform, and the consistency of the critical dimensions of the formed fins and pseudo-fins is stronger, thereby better meeting process requirements.

[0046] To enable those skilled in the art to better understand and implement the embodiments of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Reference Figures 6 to 19 The diagram shown is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0048] Reference Figure 6 Provides a base of 100.

[0049] The substrate 100 provides a processing platform for subsequent process steps, and can also be used for the etching material layer in patterning processes. In this embodiment of the invention, the substrate 100 is used to form a substrate and fins and pseudo-fins protruding from the substrate.

[0050] In some embodiments of the present invention, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. In specific implementations, the substrate 100 may include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer. The first semiconductor layer provides a process basis for subsequent substrate formation, and the second semiconductor layer provides a process basis for subsequent fin formation.

[0051] In specific implementations, as an optional process step, a hard mask material layer 130 can also be formed on the substrate 100, such as... Figure 6 As shown, a hard mask layer can be formed based on the hard mask material layer 130, and the hard mask layer can serve as a mask for subsequent etching of the substrate 100.

[0052] In some embodiments of the present invention, the hard mask material layer 130 is made of silicon oxide. In other embodiments, depending on the materials of the substrate 100 and subsequent sidewalls, the hard mask material layer 130 may also be made of other suitable materials such as silicon oxynitride, silicon carbonitride, or silicon.

[0053] It should be noted that before forming the hard mask material layer 130 on the substrate 100, a pad oxide layer 110 and a polishing stop layer 120 located on the pad oxide layer 110 may also be formed on the substrate 100.

[0054] The pad oxide layer 110 serves to provide a buffer during the formation of the polishing stop layer 120, preventing misalignment during its formation. In this embodiment, the polishing stop layer 120 is made of silicon oxide.

[0055] During the subsequent formation of the fins on the patterned substrate 100, the polishing stop layer 120 is used to define the stop position of the polishing process. In this embodiment of the invention, the polishing stop layer 120 is made of silicon nitride.

[0056] After forming multiple discrete sidewalls on the substrate 100, the process further includes a step of forming a hard mask layer using the mask sidewalls and the remaining pseudo-mask sidewalls as masks and patterning the hard mask material layer 130.

[0057] Reference Figures 7 to 10 Multiple discrete sidewalls are formed on the substrate 100, including mask sidewalls 140 (e.g., Figure 11 (as shown) and the dummy mask sidewall 150 (as shown) Figure 11 (As shown). The mask sidewall 140 and the remaining pseudo mask sidewall 150 serve as etching masks for subsequent patterning of the substrate 100. A portion of the pseudo mask sidewall 150 serves as a sidewall to be removed to prevent unwanted patterns from forming during subsequent patterning of the substrate 100.

[0058] In specific implementations, the sidewall material includes silicon oxide, silicon oxynitride, silicon, or titanium oxide, etc. In some embodiments of the present invention, the sidewall material can be silicon nitride.

[0059] In this embodiment of the invention, the step of forming the sidewall includes:

[0060] Reference Figure 7 A discrete core layer 105 is formed on the substrate 100, and the sidewalls 145 (such as...) Figure 10 (As shown) is formed on the sidewall of the core layer 105, which provides support for the formed sidewall 145.

[0061] Subsequent processes will remove the core layer 105; therefore, the core layer 105 is made of a material that is easily removed. In specific implementations, the material of the core layer 105 includes amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, etc.

[0062] In some embodiments of the present invention, the step of forming the core layer 105 includes: forming a core material layer (not shown) on the substrate 100; patterning the core material layer, and using the remaining core material layer as the core layer 105. Specifically, the core layer material can be etched using a dry etching process.

[0063] Reference Figure 8 A protective layer is formed covering the top and sidewalls of the core layer 105 and the sidewall material layer 135 of the substrate 100, which is used for subsequent etching processes to form sidewalls.

[0064] In practice, atomic layer deposition (ALD) can be used to form the sidewall material layer 135. Using ALD improves the uniformity and density of the sidewall material layer 135's thickness, allowing for precise control of its thickness.

[0065] Reference Figure 9 Remove the sidewall material layer 135 located on top of the core layer 105 and on the base 100, and retain the sidewall material layer 135 located on the sidewall of the core layer 105 as the sidewall 145.

[0066] In this embodiment of the invention, an anisotropic etching process can be used to etch the sidewall material layer 135. By employing anisotropic etching, the sidewall material layer 135 located on top of the core layer 105 and on the substrate 100 can be removed using a maskless etching method. Specifically, a maskless dry etching process is used to etch the sidewall material layer 135.

[0067] Reference Figure 10 In this embodiment of the invention, after forming the sidewalls, the forming method further includes: removing the core layer 105 to expose the substrate 100 and the sidewalls of the sidewalls, in preparation for the subsequent removal of the formed partial pseudo-mask sidewalls 150.

[0068] In this embodiment of the invention, the core layer 105 can be removed by wet etching.

[0069] After removing the core layer 105, it is also necessary to remove some of the pseudo mask sidewalls so that the uniformity of the spacing between the remaining pseudo mask sidewalls 150 and mask sidewalls 140 meets the preset range.

[0070] Reference Figure 11 and Figure 12 A first mask layer 160 is formed on the substrate 100, the first mask layer 160 having a first opening 170 (e.g., ...). Figure 12 As shown), the first opening 170 exposes a portion of the pseudo-mask sidewall 150.

[0071] The first mask layer 160 can serve as an etching mask for subsequent removal of the pseudo-mask sidewall 150 in a portion of the area.

[0072] Subsequent processing steps will remove the first mask layer 160. Therefore, the first mask layer 160 is made of an easily removable material, and the process of removing the first mask layer 160 causes minimal damage to the mask sidewalls 140, the remaining dummy mask sidewalls 150, and the substrate 100. In some embodiments of the present invention, the material of the first mask layer 160 is spin-on carbon (SOC).

[0073] In other embodiments, the material of the first mask layer 160 may also be a bottom anti-reflective coating (BARC), an organic dielectric layer (ODL), a deep UV light absorbing oxide layer (DUO), etc.

[0074] In this embodiment of the invention, the steps of forming the first mask layer 160 and the first opening 170 include:

[0075] like Figure 11 As shown, the first mask layer 160 is formed on the substrate 100 using a spin coating process.

[0076] Continue to refer to Figure 11 A first anti-reflective coating 161 is formed on top of the first mask layer 160, and a first photoresist coating 162 is formed on the first anti-reflective coating 161. The first photoresist coating 162 has a first patterned opening that exposes a portion of the first anti-reflective coating 161. Figure 11 (Not shown in the image). The first anti-reflective coating 161 can reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. The pattern opening can be formed by photolithography processes such as exposure and development on the first photoresist coating 162.

[0077] Reference Figure 12 Using the first photoresist coating 162 as a mask, the anti-reflective coating 161 and the first mask layer 160 are sequentially etched along the first pattern opening, forming a first opening 170 in the first mask layer 160.

[0078] In this embodiment of the invention, a dry etching process can be used to etch the first mask layer 160 and the first anti-reflection coating 161.

[0079] In this embodiment of the invention, during the etching process, the anti-reflective coating 161 and the photoresist coating 162 are consumed in sequence. Therefore, after the first opening 170 is formed, only a portion of the thickness of the first mask layer 160 is retained.

[0080] Reference Figure 13 Using the first mask layer 160 as a mask, the pseudo-mask sidewall 150 of the part exposed by the first opening 170 is removed.

[0081] In this embodiment of the invention, the pseudo-mask sidewall 150 exposed in the first opening 170 corresponds to the position of the fin cut. Therefore, removing the pseudo-mask sidewall 150 exposed in the first opening 170 is a fin-first cut process.

[0082] In this embodiment of the invention, an anisotropic etching process can be used to remove the dummy mask sidewall 150 exposed in the first opening 170. The anisotropic etching process has anisotropic etching characteristics, and during the etching process using the first mask layer 160 as a mask to remove the mask sidewall 150 and the dummy mask sidewall 140 exposed by the first photoresist coating 162, it is less likely to damage the sidewalls hidden by the first photoresist coating 162.

[0083] In a specific implementation, the number of adjacent pseudo-mask sidewalls 150 in the portion of the exposed area of ​​the first opening 170 is less than or equal to two. Because the number of adjacent pseudo-mask sidewalls in the removed portion is less than or equal to two, the remaining mask sidewalls and pseudo-mask sidewalls are more evenly distributed and have a higher spacing density. Therefore, when the substrate is patterned using the mask sidewalls and the remaining pseudo-mask sidewalls as masks, the etching rate is more uniform, resulting in stronger consistency in the critical dimensions of the formed fins and pseudo-fins, thus better meeting process requirements.

[0084] The following combination Figure 13 , refer to Figure 20 The present invention will provide a detailed description of the fact that the number of adjacent pseudo-mask sidewalls in the removed portion of the region in the embodiments of the present invention is less than or equal to 2.

[0085] Reference Figure 20 The graph shows the critical dimensions of the fins, expressed in nm, on the vertical axis and on the horizontal axis, representing the patterns after removing different pseudo-mask sidewalls. Specifically, the bar chart in region A represents the critical dimensions of the fins formed after removing 4 pseudo-mask sidewalls; the bar chart in region B represents the critical dimensions of the fins formed after removing 3 pseudo-mask sidewalls; and the bar chart in region C represents the critical dimensions of the fins formed after removing 2 pseudo-mask sidewalls. The horizontal axis in region A represents the patterns of the remaining 3 and 15 fins after removing 4 pseudo-mask sidewalls; region B represents the patterns of the remaining 13, 14, and 15 fins after removing 3 pseudo-mask sidewalls; and region C represents the patterns of the remaining 13 and 14 fins after removing 2 pseudo-mask sidewalls.

[0086] As can be seen from the figure, the fins formed by removing different numbers of pseudo-mask sidewalls have different critical dimensions. Specifically, the critical dimensions of the fins formed by removing 4 pseudo-mask sidewalls are 18.8–19.1 nm, the critical dimensions of the fins formed by removing 3 pseudo-mask sidewalls are 16.6–18.2 nm, and the critical dimensions of the fins formed by removing 2 pseudo-mask sidewalls are 16.2–17.9 nm.

[0087] In specific implementation, since the critical size of the fin required by the process is around 16.3nm, the embodiments of the present invention use less than or equal to 2 adjacent pseudo-mask sidewalls of the removed part of the region. Specifically, the fin that meets the process requirements can be obtained by removing 1 or 2 adjacent pseudo-mask sidewalls of the part of the region. Alternatively, the fin that meets the process requirements can be obtained by removing 1 or 2 adjacent pseudo-mask sidewalls of the part of the region.

[0088] In practice, the distance between the removed pseudo-mask sidewalls and the active region is less than or equal to a preset threshold. Specifically, the preset threshold is the distance between adjacent fins. Because the distance between the removed pseudo-mask sidewalls and the active region is less than or equal to the preset threshold, the location of the etched pseudo-fins is at a certain distance from the active region. Depending on the number of pseudo-mask sidewalls removed, this distance is generally 15 to 45 nm. Therefore, during the etching process, damage to the fins or the problem of pseudo-fin residue can be avoided, thereby improving the yield of the semiconductor structure.

[0089] Reference Figure 14 Remove the first mask layer 160.

[0090] In this embodiment of the invention, the material of the first mask coating 160 is SOC, so the first mask layer 160 can be removed by an asher process. The process of removing the first mask layer 160 is simple and causes little damage to the mask sidewall 140, the remaining pseudo mask sidewall 150, and the substrate 100.

[0091] Combination Figure 14 , refer to Figure 15 Using the mask sidewall 140 and the remaining pseudo mask sidewall 150 as masks, a patterned substrate 100 is formed to create a fin 200 corresponding to the mask sidewall 140 and a pseudo fin 300 corresponding to the remaining pseudo mask sidewall 150.

[0092] In other embodiments of the present invention, the mask sidewall 140 and the remaining pseudo-mask sidewall 150 can be used as masks to etch the hard mask material layer 130 to form a hard mask layer, and then the substrate 100 can be etched using the hard mask layer as a mask. The hard mask layer can serve as an etching stop layer to prevent over-etching during the removal of the pseudo-mask sidewalls in the aforementioned area.

[0093] In this embodiment of the invention, after the patterned substrate 100 is used as a substrate, the remaining substrate 100 is used as a base, and fins 200 and pseudo-fins 300 are formed on the base.

[0094] In this embodiment of the invention, the fin 200 and the pseudo-fin 300 are integrally formed with the corresponding substrate. In other embodiments, when the substrate 100 includes a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, in the step of etching the substrate, only the first semiconductor layer is etched. The first semiconductor layer serves as the substrate, and the remaining second semiconductor layer protruding from the first semiconductor layer serves as the fin 200 or the pseudo-fin 300.

[0095] It should be noted that, in this embodiment of the invention, the mask sidewall 140 and the remaining pseudo mask sidewall 150 are consumed during the pattern transfer process. Therefore, after the substrate 100 is patterned, the mask sidewall 140 and the remaining pseudo mask sidewall 150 are removed.

[0096] After the above process, fins with the same key dimensions and meeting the process requirements can be obtained. However, since the first opening only exposes a portion of the pseudo-mask sidewalls, the remaining pseudo-mask sidewalls form pseudo-fins corresponding to the remaining mask sidewalls in subsequent processes, especially during the patterning of the substrate. Therefore, it is necessary to remove the pseudo-fins corresponding to the remaining mask sidewalls through subsequent processes. The following is a detailed description of the removal of pseudo-fins corresponding to the remaining mask sidewalls according to an embodiment of the present invention, with reference to the accompanying drawings.

[0097] Reference Figure 16 and Figure 17 As shown, a second mask layer 180 is formed on the remaining substrate 100, the second mask layer 180 having a second opening 190 (as shown). Figure 18 As shown), the second opening 190 exposes the pseudofin portion 300 corresponding to the remaining mask sidewall.

[0098] The second mask layer 180 can serve as an etching mask for subsequent removal of the pseudo-fin portion 300 corresponding to the remaining mask sidewalls.

[0099] Subsequent processing steps will remove the second mask layer 180. Therefore, the second mask layer 180 is made of an easily removable material, and the process of removing the second mask layer 180 causes minimal damage to the fins 200 corresponding to the mask sidewalls 140 and the substrate 100. In this embodiment of the invention, the material of the second mask layer 180 is spin-on carbon (SOC) material.

[0100] In other embodiments, the material of the second mask layer 180 may also be a bottom anti-reflective coating (BARC), an organic dielectric layer (ODL), a deep UV light absorbing oxide layer (DUO), etc.

[0101] It should be noted that, in this embodiment of the invention, the first and second photolithography processes differ significantly, therefore, the masks used are different, but the materials of the first and second mask layers can be the same. In other embodiments, the materials of the first and second mask layers in the semiconductor structure formed according to this embodiment of the invention can also be different, and this embodiment of the invention does not limit this.

[0102] In this embodiment of the invention, the step of forming the second mask layer 180 and the second opening 190 includes:

[0103] like Figure 16 As shown, the second mask layer 180 is formed on the remaining substrate 100 using a spin coating process.

[0104] Continue to refer to Figure 16 A second anti-reflective coating 181 is formed on top of the second mask layer 180, and a second photoresist coating 182 is formed on the second anti-reflective coating 181. The second photoresist coating 182 has a second patterned opening that exposes a portion of the second anti-reflective coating 181. Figure 17 (Not shown in the image), wherein the second anti-reflective coating 181 can reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern, and the pattern opening is formed by photolithography processes such as exposure and development on the second photoresist coating 182.

[0105] Reference Figure 17 Using the second photoresist coating 182 as a mask, the second anti-reflective coating 181 and the second mask layer 180 are sequentially etched along the second pattern opening, forming a second opening 190 in the second mask layer 180.

[0106] In this embodiment of the invention, a dry etching process is used to etch the second mask layer 180 and the second anti-reflective coating 181.

[0107] In this embodiment of the invention, during the etching process, the second anti-reflective coating 181 and the second photoresist coating 182 are consumed in sequence. Therefore, after the second opening 190 is formed, only a portion of the thickness of the second mask layer 180 is retained.

[0108] Reference Figure 18Using the second mask layer 180 as a mask, the pseudo fin portion 300 corresponding to the remaining mask sidewall is removed.

[0109] In this embodiment of the invention, the pseudofin portion 300 exposed by the second opening 190 corresponds to the position of the fin cut. Therefore, removing the pseudofin portion 300 exposed by the second opening 190 is a fin cut-last process.

[0110] Combination Figure 18 , refer to Figure 19 Remove the second mask layer by 180°.

[0111] In this embodiment of the invention, the material of the second mask coating 180 is SOC, so the second mask layer 180 can be removed by an asher process. The process of removing the second mask layer 180 is simple and causes little damage to the fin 200 and the substrate 100.

[0112] In this embodiment of the invention, the above process can remove the pseudo-fins corresponding to the remaining pseudo-mask sidewalls, resulting in a target pattern consisting entirely of fins. Furthermore, because the number and location of the removed pseudo-mask sidewalls are limited during the first photolithography and first etching processes, the etching process window is expanded, allowing the etched pseudo-fins to be positioned at a certain distance from the active region. The distance value can vary depending on the number of pseudo-mask sidewalls removed. In some embodiments of the invention, the distance value can range from 15 to 45 nm. Therefore, during the etching process, damage to the fins or the problem of residual pseudo-fins can be avoided, thereby improving the yield of the semiconductor structure.

[0113] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Multiple discrete sidewalls are formed on the substrate, including mask sidewalls and dummy mask sidewalls; A portion of the pseudo-mask sidewalls is removed, such that the uniformity of the spacing between the original mask sidewalls and the remaining pseudo-mask sidewalls meets a preset range. The number of pseudo-mask sidewalls removed from the portion is determined based on the critical dimensions of the fins required by the process. The number of adjacent pseudo-mask sidewalls in the removed portion is less than or equal to two. The distance between the removed pseudo-mask sidewalls and the active region is less than or equal to a preset threshold, which is 15 to 45 nm. Furthermore, the distance between the pseudo-mask sidewalls and the active region in the removed portion is the distance between adjacent fins. Using the mask sidewalls and the remaining pseudo mask sidewalls as masks, the substrate is patterned to form fins corresponding to the mask sidewalls and pseudo fins corresponding to the remaining pseudo mask sidewalls; Remove the pseudofin portion.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The removal of the pseudo-mask sidewall in the aforementioned region includes: A first mask layer is formed on the substrate, the first mask layer having a first opening that exposes the pseudo mask sidewall of the partial area; Using the first mask layer as a mask, remove the pseudo mask sidewalls of the portion of the area exposed by the first opening; Remove the first mask layer.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The material of the first mask layer is SOC.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The removal of the pseudo-fin portion includes: A second mask layer is formed on the substrate, the second mask layer having a second opening that exposes the remaining portion of the pseudofin portion; The false fin is removed by masking with the second mask layer; Remove the second mask layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The material of the second mask layer is SOC.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming the sidewall, the forming method further includes: forming a hard mask material layer on the substrate; The graphical representation of the substrate includes: Using the mask sidewalls and the remaining pseudo-mask sidewalls as masks, the hard mask material layer is etched to form a hard mask layer; The substrate is etched using the hard mask layer as a mask.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, An anisotropic etching process was used to remove the pseudo-mask sidewalls in the aforementioned region.

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