Metal wiring of semiconductor devices

Abstract

The application discloses a metal wiring of a semiconductor device, comprising: a plurality of metal line patterns arranged side by side on a substrate, the plurality of metal line patterns comprising first metal lines for transmitting control signals and second metal lines for transmitting power signals; the space between the first metal lines and the space between the first metal lines and the second metal lines are provided with tooth-shaped dummy metal patterns; and the space between the second metal lines is provided with a strip-shaped dummy metal pattern. The application considers the signal type transmitted by the metal line pattern, and then diversifies the configuration of the shape of the dummy metal pattern around the metal line pattern. Since the tooth-shaped dummy metal pattern can reduce the adjacent surface between the first metal lines, the signal crosstalk between the metal lines and the dummy metal pattern can be reduced, and the power signal used around can be strengthened. The space between the metal lines for transmitting the power signal is still configured with a strip-shaped dummy metal pattern, which is simple in layout design and preparation process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a metal wiring method for a semiconductor device. Background Technology

[0002] When wiring semiconductor devices with metal, the shape of the metal wire pattern is strip-shaped. During the manufacturing process, the optical proximity effect (OPE) is easily generated, which means that the strip pattern is distorted.

[0003] In related technologies, to reduce distortion of the metal line pattern and improve the linewidth uniformity of the metal line, a strip-shaped dummy metal pattern with the same shape as the metal line pattern is usually arranged in the empty area around the metal line pattern. However, arranging the dummy metal pattern in a strip shape around the metal line pattern can cause line coupling between the metal line and the dummy metal pattern, resulting in signal crosstalk problems. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and a method for forming the same to prevent pattern distortion, addressing the shortcomings of the prior art. This purpose is achieved through the following technical solutions.

[0005] The first aspect of this application provides a metal wiring for a semiconductor device, comprising: a plurality of metal line patterns arranged side by side on a semiconductor substrate, wherein the plurality of metal line patterns include a first metal line for transmitting control signals and a second metal line for transmitting power signals.

[0006] The empty areas between the first metal lines and the empty areas between the first metal lines and the second metal lines are all provided with tooth-shaped virtual metal patterns.

[0007] A strip-shaped, dummy metal pattern is provided in the empty area between the two second metal lines.

[0008] A second aspect of this application provides a semiconductor device comprising metal wiring as described in the first aspect above.

[0009] The metal wiring of the semiconductor device based on the first and second aspects described above has the following advantages:

[0010] This invention considers the signal type transmitted by each metal line pattern and then diversifies the configuration of the shape of the dummy metal patterns around the metal line patterns. Specifically, for metal lines used to transmit control signals, which are more sensitive to signal crosstalk, toothed dummy metal patterns with a smaller relative area than the existing strip-shaped dummy metal patterns are configured in the empty areas between metal lines used to transmit control signals and in the empty areas between metal lines used to transmit control signals and metal lines used to transmit power signals. Since the toothed dummy metal patterns can reduce the adjacent surfaces with the metal lines used to transmit control signals, signal crosstalk between the metal lines and the dummy metal patterns can be reduced, while also strengthening the power signals used in the surrounding area. For metal lines used to transmit power signals, which are not sensitive to signal crosstalk, and since the layout design and fabrication process of strip patterns is simpler than that of toothed patterns, the empty areas between metal lines used to transmit power signals are still configured with strip-shaped dummy metal patterns, which have a simpler layout design and fabrication process. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0012] Figure 1 This is a schematic diagram of the metal wiring structure of a semiconductor device in the prior art;

[0013] Figure 2 This is a schematic diagram of a metal wiring structure of a semiconductor device according to an exemplary embodiment of this application;

[0014] Figure 3 For along Figure 2 A schematic diagram of the cross-sectional structure obtained by cutting off AA' in the diagram;

[0015] Figure 4 This is a flowchart illustrating an embodiment of a method for forming metal wiring in a semiconductor device according to an exemplary embodiment of this application. Detailed Implementation

[0016] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0017] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0018] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0019] In the prior art, a strip-shaped dummy metal pattern with the same shape as the metal line pattern is arranged in the empty area around the metal line pattern to reduce the distortion of the metal line pattern and improve the uniformity of the metal line width.

[0020] See Figure 1 As shown, metal line patterns (10, 11, 12) are arranged side by side on a semiconductor substrate. Strip-shaped dummy metal patterns are arranged in the empty areas 13 between the metal line patterns to reduce the distortion of the metal line patterns and improve the line width uniformity of the metal line patterns.

[0021] However, if strip-shaped dummy metal patterns are arranged around the metal line pattern, the adjacent surfaces between the dummy metal patterns and the metal line pattern are relatively large, which can easily cause line coupling, resulting in signal crosstalk problems and thus reducing the performance stability of semiconductor devices.

[0022] To address the aforementioned technical problems, this invention proposes an improved metal wiring method for semiconductor devices, see [link to relevant documentation]. Figure 2 As shown, multiple metal line patterns are arranged on the semiconductor substrate 1. These metal line patterns include a first metal line 110 for transmitting control signals and a second metal line 100 for transmitting power signals. There is at least one first metal line 110 and at least one second metal line 100.

[0023] The difference from existing technologies lies in that this invention considers the signal type transmitted by each metal line pattern, and therefore, the shape of the dummy metal pattern in the empty area around the metal line pattern is configured in a variety of ways according to technical requirements, as follows:

[0024] Regarding the first metal line 110, since it is used to transmit control signals and is sensitive to signal crosstalk, the empty areas between two first metal lines 110 and the empty areas between the first metal line 110 and the second metal line 100 are both provided with serrated dummy metal patterns 140. It should be noted that, compared with the prior art, in the same size empty area, the serrated dummy metal pattern 140 configured in this invention has a smaller relative area than the existing strip-shaped dummy metal pattern. Because the serrated dummy metal pattern 140 can reduce the adjacent surfaces with the first metal line 110, it can reduce signal crosstalk between the first metal line 110 and the dummy metal pattern, and at the same time, it can also strengthen the power signals used in the surrounding area.

[0025] Regarding the second metal line 100, since the second metal line 100 is not sensitive to signal crosstalk, and the layout design and fabrication process of the toothed pattern described above is more complex than that of the striped pattern, the empty area between the second metal lines 100 does not need to be provided with a toothed dummy metal pattern. Instead, a striped dummy metal pattern 150 with a relatively simple layout design and fabrication process can still be provided to reduce the requirements for layout design and fabrication process.

[0026] It should be noted that, for example, Figure 2 As shown, the coupling capacitor 180 is a capacitor that is coupled between the first metal line 110 and the adjacent dummy metal pattern during the transmission of control signals. The coupling capacitor 180 between the existing strip-shaped dummy metal pattern and the first metal line 110 is very large, which can easily cause signal crosstalk problems. The purpose of this invention is to minimize the coupling capacitor 180 by setting a tooth-shaped dummy metal pattern 140 with a relatively small area, thereby reducing the signal crosstalk between the first metal line 110 and the dummy metal pattern.

[0027] In some embodiments, such as Figure 2 As shown, in order to reduce the difficulty of the layout design and fabrication process of the toothed dummy metal pattern 140, the layout design and fabrication process of square is relatively simpler than that of other shapes. Therefore, the toothed dummy metal pattern 140 can be specifically a square toothed dummy metal pattern.

[0028] Furthermore, the dummy metal pattern with square teeth comprises square metal patterns and strip metal patterns, with adjacent square metal patterns connected by strip metal patterns. It is noteworthy that the square metal patterns and strip metal patterns included in the dummy metal pattern with square teeth can be fabricated using a single process with a separately designed photomask.

[0029] In some embodiments, in practical applications, the resistance value of the second metal line 100 used for transmitting power signals between the power supply terminal and the logic block of the semiconductor device should be as small as possible. In order to minimize the resistance value of the second metal line 100 for transmitting power signals, the line width of the second metal line 100 should be set to be larger. However, the resistance value of the first metal line 110 for transmitting control signals does not need to be considered, so the line width of the first metal line 110 can be set to be smaller.

[0030] Therefore, in this invention, the line width of the first metal line 110 is smaller than the line width of the second metal line 100.

[0031] In some embodiments, based on the circuit design requirements of semiconductor devices, metal wiring may include metal lines used for both transmitting control signals and power signals. For example... Figure 2 As shown, the metal line patterns arranged on the semiconductor substrate 1 may also include a third metal line 120 used for transmitting both control signals and power signals.

[0032] Regarding the third metal line 120, since it is not very sensitive to signal crosstalk, and the layout design and fabrication process of the aforementioned toothed metal pattern is more complex than that of the strip metal pattern, the empty areas between the third metal line 120 and the second metal line 100, and the empty areas between two third metal lines 120, do not need to be provided with toothed dummy metal patterns. Instead, strip dummy metal patterns 150, which have a simpler layout design and fabrication process and are more conducive to power mesh, can still be provided. The empty areas between the third metal line 120 and the first metal line 110 can be provided with toothed dummy metal patterns 140 to reduce signal crosstalk of the first metal line 110 (as described above). Figure 2 (The case where there is a gap between the third metal line and the first metal line is not shown).

[0033] Furthermore, considering the requirements for the integration density of integrated circuits and the resistance value requirements of the metal lines transmitting power signals, the line width of the third metal line 120 can also be set to be smaller. For example, the line width of the third metal line 120 can be the same as the line width of the first metal line 110.

[0034] Therefore, it can be seen that the line width of the third metal line 120 is also smaller than that of the second metal line 100.

[0035] In some embodiments, such as Figure 2As shown, in the circuit design of semiconductor devices, metal lines for transmitting control signals are usually electrically connected to components in multiple film layers. Therefore, by setting end nodes at both ends of the first metal line 110, components in other film layers can be electrically connected through metal vias.

[0036] Based on the same principle, end nodes can also be set at both ends of the third metal line 120 to electrically connect with other components in the film layer through metal vias.

[0037] In some embodiments, to maximize the use of dummy metal patterns, the dummy metal patterns can be electrically connected to the metal patterns of the upper or lower film layer to enhance the power mesh used in the circuitry of the semiconductor device.

[0038] Therefore, for example... Figure 2 As shown, the metal wiring consisting of multiple metal line patterns (100, 110, 120), toothed dummy metal pattern 140, and striped dummy metal pattern 150 is located in the same film layer. The toothed dummy metal pattern 140 and / or the striped dummy metal pattern 150 can also be electrically connected to metal patterns 170 in other film layers to enhance the power mesh used in the circuit of the semiconductor device.

[0039] Furthermore, the toothed dummy metal pattern 140 and / or the striped dummy metal pattern 150 can be electrically connected to the metal patterns 170 in other film layers through the metal vias 160.

[0040] See Figure 3 As shown, Figure 2 The cross-sectional structure of AA' is shown in the diagram. The metal wiring consisting of multiple metal line patterns (100, 110, 120), toothed dummy metal pattern 140 and strip dummy metal pattern 150 on the semiconductor substrate 1 is located in the film layer 2. The strip dummy metal pattern 150 is electrically connected to the metal pattern 170 located in the film layer 3 through the metal via 160.

[0041] It should be noted that the present invention does not limit the vertical positional relationship between film layer 2 and film layer 3. Figure 3 This is merely an illustrative example; of course, membrane layer 3 could also be located below membrane layer 2.

[0042] Corresponding to the aforementioned embodiments of metal wiring for semiconductor devices, this application also provides embodiments of methods for forming metal wiring for semiconductor devices.

[0043] Figure 4 This is a flowchart illustrating an embodiment of a method for forming metal wiring in a semiconductor device according to an exemplary embodiment of this application. Figures 2 to 3Based on the illustrated embodiment, the method for forming the metal wiring of this semiconductor device includes the following steps:

[0044] Step 401: Form multiple metal line patterns arranged side by side on a semiconductor substrate. The multiple metal line patterns include a first metal line for transmitting control signals, a second metal line for transmitting power signals, and a third metal line for transmitting both control signals and power signals.

[0045] Step 402: Fill the empty areas between the first metal wires, the empty areas between the first metal wires and the second metal wires, and the empty areas between the third metal wire and the first metal wire with serrated virtual metal patterns respectively.

[0046] Step 403: Fill the empty areas between the second metal lines, the empty areas between the third metal lines, and the empty areas between the third metal lines with strip-shaped virtual metal patterns.

[0047] It is worth noting that the materials used for the metal line pattern, the serrated virtual metal pattern, and the strip virtual metal pattern are all metal.

[0048] For the specific implementation of steps 401 to 403 above, please refer to the above. Figures 2 to 3 The relevant descriptions of the embodiments shown are not detailed here.

[0049] This completes the above. Figure 4 As shown in the formation process, this application considers the signal type transmitted by each metal line pattern and then diversifies the configuration of the shape of the dummy metal pattern around the metal line pattern. Specifically, for metal lines used to transmit control signals, which are more sensitive to signal crosstalk, toothed dummy metal patterns with a smaller relative area than the existing strip-shaped dummy metal patterns are configured in the empty areas between metal lines used to transmit control signals and in the empty areas between metal lines used to transmit control signals and metal lines used to transmit power signals. Since toothed dummy metal patterns can reduce the adjacent surfaces with metal lines used to transmit control signals, signal crosstalk between metal lines and dummy metal patterns can be reduced, while also strengthening the power signals used in the surrounding area. For metal lines used to transmit power signals, which are not sensitive to signal crosstalk, and on the one hand, the layout design and fabrication process of strip patterns is simpler than that of toothed patterns, and on the other hand, it is more conducive to power mesh, so strip-shaped dummy metal patterns with simple layout design and fabrication process are still configured in the empty areas between metal lines used to transmit power signals.

[0050] This application also proposes a semiconductor device comprising the metal wiring of the semiconductor device as described in the above embodiments.

[0051] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0052] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A metal wiring of a semiconductor device, characterized by, The application relates to a semiconductor substrate. The semiconductor substrate comprises: a plurality of metal line patterns arranged side by side on the semiconductor substrate, the plurality of metal line patterns comprising first metal lines for transmitting control signals and second metal lines for transmitting power signals; a free area between the first metal lines and a free area between the first metal line and the second metal line are provided with a tooth-shaped dummy metal pattern; a free area between the second metal lines is provided with a strip-shaped dummy metal pattern; 2. The metal wiring of a semiconductor device according to claim 1, wherein, the line width of the first metal lines is smaller than that of the second metal lines.

3. The metal wiring of a semiconductor device according to claim 2, wherein The tooth-shaped dummy metal pattern is a square tooth-shaped dummy metal pattern. The square tooth-shaped dummy metal pattern comprises square metal patterns and strip-shaped metal patterns; 4. The metal wiring of a semiconductor device according to claim 1, wherein wherein adjacent square metal patterns are connected by strip-shaped metal patterns. The plurality of metal line patterns, the tooth-shaped dummy metal pattern and the strip-shaped dummy metal pattern are located in the same film layer; 5. The metal wiring of a semiconductor device according to claim 4, wherein The tooth-shaped dummy metal pattern and / or the strip-shaped dummy metal pattern are also electrically connected with metal patterns in other film layers.

6. The metal wiring of a semiconductor device according to claim 1, wherein The tooth-shaped dummy metal pattern and / or the strip-shaped dummy metal pattern are also electrically connected with metal patterns in other film layers through metal vias. The plurality of metal line patterns further comprise third metal lines for transmitting both control signals and power signals; a free area between the third metal lines and a free area between the third metal line and the second metal line are provided with strip-shaped dummy metal patterns; 7. The metal wiring of a semiconductor device according to claim 6, wherein a free area between the third metal line and the first metal line is provided with a tooth-shaped dummy metal pattern.

8. The metal wiring of a semiconductor device according to claim 6, wherein The line width of the third metal lines is smaller than that of the second metal lines. Both ends of the first metal lines are provided with end nodes; and / or, 9. A semiconductor device, characterized by comprising: Both ends of the third metal lines are provided with end nodes. The application further relates to a semiconductor substrate comprising the metal wiring as claimed in any one of claims 1-8.

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