Method of forming a semiconductor structure

Abstract

A method of forming a semiconductor structure is provided, including forming first and second fin structures, wherein each of the first and second fin structures includes interleaved stacks of first and second semiconductor layers; and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and the first and second dielectric layers are of different materials. First source / drain structures are formed in the first fin structure; the first mask structure is removed; second source / drain structures are formed in the second fin structure; the first semiconductor layers of the first and second fin structures are removed to form first and second nanostructures; and a gate stack is formed around the first and second nanostructures.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor structure, and more particularly to forming source / drain structures separately in different device regions. Background Technology

[0002] The electronics industry continues to grow its demand for smaller, faster electronic devices that simultaneously support increasingly complex and numerous functions. In summary, the ongoing trend in the semiconductor industry is to manufacture low-cost, high-efficiency, and low-power integrated circuits. To date, the primary method for achieving these goals has been to shrink the size of semiconductor integrated circuits (such as the minimum structural size), thereby improving production capacity and reducing related costs. However, shrinking size increases the complexity of semiconductor manufacturing processes. For semiconductor integrated circuits and device units to continue to advance, semiconductor manufacturing processes and technologies must also advance in a similar manner.

[0003] Multi-gate devices have recently been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects. One type of multi-gate device is the fully wound gate transistor (WWT). The name "WWT" comes from the fact that the gate structure extends to cover the channel region, providing pathways to the channel via two or four sides. WWTs are compatible with existing complementary metal-oxide-semiconductor (CMOS) processes and structures, thus maintaining gate control and mitigating short-channel effects while significantly reducing size. In existing processes, WWTs can provide channels within silicon nanowires. However, the fabrication methods for integrating the WWT around the nanowire can present challenges. For example, while existing methods meet many requirements, continuous improvement is still needed. Summary of the Invention

[0004] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure on a substrate, each of the first fin structure and the second fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method also includes forming a first masking structure to cover the second fin structure. The first masking structure includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer and the second dielectric layer being made of different materials. The method also includes forming a first source / drain structure in the first fin structure; removing the first masking structure; and forming a second source / drain structure in the second fin structure. The method further includes removing the first semiconductor layer of each of the first fin structure and the second fin structure to form a plurality of first nanostructures from the second semiconductor layer of the first fin structure and a plurality of second nanostructures from the second semiconductor layer of the second fin structure; and forming a gate stack around the first nanostructures and the second nanostructures.

[0005] In some embodiments, a method for forming a semiconductor structure is provided. The method includes interleaving and stacking a first semiconductor layer and a second semiconductor layer on a substrate; and patterning the first semiconductor layer and the second semiconductor layer into a first fin structure in a first region of the substrate, and a second fin structure in a second region of the substrate. The method also includes etching the first fin structure to form a first recess, and etching the second fin structure to form a second recess; and forming a first mask structure to cover the second recess and expose the first recess. The first mask structure includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, and the dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer. The method also includes forming a first source / drain structure in the first recess; and removing the first mask structure. The method also includes forming a second mask structure to cover the first source / drain structure and expose the second recess; forming a second source / drain structure in the second recess; and removing the second mask structure.

[0006] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure on a substrate; and forming a first recess in a first source / drain region of the first fin structure, and forming a second recess in a second source / drain region of the second fin structure. The method also includes sequentially forming a first dielectric layer and a second dielectric layer in the first and second recesses, wherein the first dielectric layer is composed of a silicon-containing dielectric material, and the second dielectric layer is composed of an oxide of an amphoteric metal. The method further includes forming a dielectric mask on the second dielectric layer and covering the second recess; and removing a first portion of the first and second dielectric layers and the dielectric mask from the first recess. The method also includes growing a first source / drain structure on the first fin structure in the first recess. Attached Figure Description

[0007] Figure 1 This is a perspective view of a semiconductor structure in some embodiments of this disclosure.

[0008] Figure 2A-1 , Figure 2A-2 , Figure 2B-1 , Figure 2B-2 , Figure 2C-1 , Figure 2C-2 , Figure 2D-1 , Figure 2D-2 , Figure 2E-1 , Figure 2E-2 , Figure 2F-1 , Figure 2F-2 , Figure 2G-1 , Figure 2G-2 , Figure 2H-1 , Figure 2H-2 , Figure 2I-1 , Figure 2I-2 , Figure 2J-1 , Figure 2J-2 , Figure 2K-1 , Figure 2K-2 , Figure 2L-1 , Figure 2L-2 , Figure 2M-1 , Figure 2M-2 , Figure 2N-1 , Figure 2N-2 , Figure 2O-1 , Figure 2O-2 , Figure 2P-1 , Figure 2P-2 , Figure 2Q-1 , Figure 2Q-2 , Figure 2R-1 , Figure 2R-2 , Figure 2S-1 , Figure 2S-2 , Figure 2T-1 , Figure 2T-2 , Figure 2U-1 ,and Figure 2U-2 This is a cross-sectional view of various intermediate stages in forming a semiconductor structure in some embodiments of this disclosure.

[0009] Figures 3A to 3G These are cross-sectional views of various intermediate stages in forming a semiconductor structure in some embodiments.

[0010] Figure 4 These are cross-sectional views of the semiconductor structure in some embodiments.

[0011] Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 , Figure 5C-2 , Figure 5D-1 , Figure 5D-2 , Figure 5E-1 ,and Figure 5E-2 This is a cross-sectional view of various intermediate stages in forming a semiconductor structure in some embodiments of this disclosure.

[0012] The reference numerals in the attached figures are explained as follows: CH: Passage area SD: Source / Drain Region T1, T2, T3, T4, T5, T6: Thickness XX, YY: Cross-section 50A: First Device Area 50B: Second Device Area 100, 200, 400: Semiconductor Structure 102: Substrate 104, 104A, 104B, 404B: Fin-like structures 104L, 404L: Lower fin units 106: First semiconductor layer 108: Second semiconductor layer 110: Isolation Structure 112, 128: Dummy gate structure 114: Dummy gate dielectric layer 116: Dummy gate layer 120, 122: Gate spacer layer 120', 122': Fin spacer layer 128A, 128B: Source / Drain Recesses 130: Gap 132: Inner spacer, inner spacer layer 134: First dielectric shielding layer 134', 134”: Reserved portion 136: Second dielectric shielding layer 138, 152: Filler layer 140: Third dielectric shielding layer 142, 156: Bottom anti-reflective coating 144, 158: Top light-blocking mask 146A, 146B: Source / Drain Structure 147, 168: Final gate stack 148: Fourth dielectric shielding layer 150: Fifth dielectric shielding layer 154: Sixth dielectric shielding layer 160: Contact Etching Stop Layer 162: Interlayer dielectric layer 164: Gate Trench 166: Gap 170: Gate dielectric layer 172: Metal gate layer 202: Gap Detailed Implementation

[0013] The following detailed description is accompanied by illustrations to aid in understanding all aspects of this disclosure. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of the various structures may be increased or decreased arbitrarily for clarity of explanation.

[0014] The different embodiments or examples provided below can implement different structures of this disclosure. The specific components and arrangements described below are intended to simplify the content of this disclosure and not to limit it. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of this disclosure may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same correspondence.

[0015] Some variations of the embodiments are described herein. In various exemplary embodiments, similar reference numerals are used to identify similar units. It should be understood that additional steps may be provided before, during, and after the method, and other embodiments of the method may replace or omit some of the steps described herein.

[0016] Furthermore, when a numerical value or range is described using terms such as "about," "approximately," or similar expressions, it includes + / - 10% of the stated value unless otherwise specified. For example, the term "about 5 nm" includes a size range of 4.5 nm to 5.5 nm.

[0017] The following fully-wound gate transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, resulting in a pattern pitch that is smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer can be formed on a substrate and patterned using a photolithography process. Spacers can be formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer can then be removed, and the remaining spacers can then be used to pattern the fully-wound gate structure.

[0018] The embodiments provide a method for forming a semiconductor structure. This disclosure relates to separately forming source / drain structures in different device regions. The method may include forming a silicon-containing dielectric mask layer, forming a high-dielectric-constant dielectric mask layer on the silicon-containing dielectric mask layer, patterning the dielectric mask layer into a source / drain mask structure to cover one device region and expose another device region, and then growing a source / drain structure in the exposed device region. This disclosure uses a silicon-containing dielectric mask layer as the bottom layer of the source / drain mask structure, which provides a good balance between the loss of low-dielectric-constant spacers (such as gate spacer layers and / or inner spacers) and the residual amount of the source / drain mask structure. Therefore, the process tolerance of the patterned source / drain mask structure can be increased.

[0019] Figure 1 These are perspective views of the semiconductor structure in some embodiments. For example... Figure 1 Some embodiments shown may receive or provide a semiconductor structure 100. In some embodiments, the semiconductor structure 100 includes a substrate 102 and a fin structure 104 located on the substrate 102. Although Figure 1 A fin structure 104 is shown, but multiple fin structures 104 may be formed on a single device region and / or multiple device regions of the semiconductor structure 100.

[0020] To facilitate understanding of the semiconductor structure, the drawings of embodiments of this disclosure provide XYZ reference coordinates. The X-axis and Y-axis are generally along a transverse (horizontal) direction and parallel to the main surface of substrate 102. The Y-axis is transverse to (or substantially perpendicular to) the X-axis. The Z-axis is generally along a vertical direction perpendicular to the main surface (or XY plane) of substrate 102.

[0021] In some embodiments, the fin structure 104 includes a lower fin unit 104L formed from a portion of the substrate 102, and an upper fin unit formed from an epitaxial stack containing an interleaved first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the fin structure 104 may extend in the X direction. In some embodiments, the longitudinal axis of the fin structure 104 may be parallel to the X direction. The X direction may also be considered as the direction in which the channel extends. Current in the final semiconductor device (such as a fully wound gate field-effect transistor) may flow through the channel in the X direction.

[0022] In some embodiments, the fin structure 104 includes a channel region CH and a source / drain region SD, wherein the channel region CH is defined between the source / drain regions SD. In embodiments of this disclosure, source / drain refers to a source and / or a drain. It is worth noting that the source and drain in embodiments of this disclosure are interchangeable and their structures are substantially the same. Figure 1 A channel region CH and two source / drain regions SD are shown for illustrative purposes and not for limiting the embodiments disclosed herein. The number of channel regions CH and the number of source / drain regions SD depend on semiconductor device design requirements and / or performance considerations. The vertical axis of the gate structure (not shown) of the gate stack may be parallel to the Y direction and may extend across and / or around the channel region CH of the fin structure 104. The Y direction may also be considered as the direction of gate extension.

[0023] Figure 1 The following figures also show reference cross-sections used in some embodiments. In some embodiments, cross-section XX is a plane parallel to the longitudinal axis (e.g., the X direction) and passing through the fin structure 104. In some embodiments, cross-section YY is a plane parallel to the longitudinal axis (Y direction) and passing through the source / drain region SD of the fin structure 104.

[0024] Figures 2A-1 to 2U-2 These are cross-sectional views of various intermediate stages in forming a semiconductor structure in some embodiments, wherein the figures end with "-1" (e.g. Figure 2A-1 ) is the corresponding Figure 1 The sectional view shown is a section view of section XX, and those with "-2" at the end of the symbol (such as...) Figure 2A-2 ) is the corresponding Figure 1 The cross-sectional view shown is a section YY.

[0025] Figure 2A-1 and Figure 2A-2 This is a cross-sectional view of the semiconductor structure 100 after the formation of fin structures 104A and 104B and isolation structure 110 in some embodiments.

[0026] like Figure 2A-1 and Figure 2A-2 Some embodiments shown may provide or receive a semiconductor structure 100, which includes a substrate 102 and fin structures 104A and 104B. The substrate 102 may be part of a semiconductor wafer, a semiconductor chip (or die), or the like. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes semiconductor elements such as germanium; semiconductor compounds such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; semiconductor alloys such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Furthermore, the substrate 102 may, where appropriate, include an epitaxial layer, may have stress to improve performance, may include a silicon-on-insulator structure, and / or may have other suitable enhancing structures.

[0027] like Figure 2A-1 and Figure 2A-2 In some embodiments shown, substrate 102 includes a first device region 50A formed therein by a fin structure 104A, and a second device region 50B formed therein by a fin structure 104B. In some embodiments, the first device region 50A is a p-type device region and is used to form a p-type semiconductor device (e.g., a p-channel nanostructure transistor such as a p-channel fully wound gate transistor). In some embodiments, the second device region 50B is an n-type device region and is used to form an n-type semiconductor device (e.g., an n-channel nanostructure transistor such as an n-channel fully wound gate transistor). Although the first device region 50A and the second device region 50B are adjacent to each other in the figures, they may be physically separated. Any number of device structures (e.g., other active devices, doped regions, isolation structures, or the like) may be present between the first device region 50A and the second device region 50B.

[0028] In some embodiments, the method of forming fin structures 104A and 104B may employ an epitaxial growth process to form an epitaxial stack on substrate 102. In some embodiments, the epitaxial stack may include an interleaved first semiconductor layer 106 and a second semiconductor layer 108. The epitaxial growth process may be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, or another suitable technique.

[0029] In some embodiments, the first semiconductor layer 106 is composed of a first semiconductor material, and the second semiconductor layer 108 is composed of a second semiconductor material. In some embodiments, the first semiconductor material used in the first semiconductor layer 106 and the second semiconductor material used in the second semiconductor layer 108 have different lattice constants. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etching selectivity. In some embodiments, the first semiconductor layer 106 is composed of silicon-germanium, and the germanium content in the silicon-germanium is approximately 20 atomic% to approximately 50 atomic%. The second semiconductor layer 108 is composed of pure silicon or substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si. 1-x Ge x (where x is greater than approximately 0.3) or germanium (x = 1.0), while the second semiconductor layer 108 is silicon or Si. 1-y Ge y (where y is less than approximately 0.4 and x > y).

[0030] In some embodiments, the first semiconductor layer 106 is configured as a sacrificial layer and can be removed to form a gap to accommodate gate material. The second semiconductor layer 108 forms a nanostructure (such as a nanowire or nanosheet) extending laterally between the source / drain structures and can serve as a channel for use in a final semiconductor device (such as a nanostructured transistor). The term "nanostructure" as used herein refers to a semiconductor layer having a cylindrical, rod-like, and / or sheet-like shape. In some embodiments, a gate stack (not shown) may be formed to encapsulate the nanostructure.

[0031] In some embodiments, the thickness of each first semiconductor layer 106 may be from about 5 nm to about 20 nm. In some embodiments, the thickness of each second semiconductor layer 108 may be from about 5 nm to about 20 nm. The thickness of the second semiconductor layer 108 may be greater than, equal to, or less than the thickness of the first semiconductor layer 106, depending on the amount of gate material filled in the space left after removing the first semiconductor layer 106. Although Figure 2A-1 and Figure 2A-2 Three first semiconductor layers 106 and three second semiconductor layers 108 are shown, but the number of semiconductor layers is not limited to 3, but can be 1, 2, or more than 3 but less than 20. The drive current of the final fully wound gate field-effect transistor can be adjusted by adjusting the number of semiconductor layers.

[0032] In some embodiments, the epitaxial stack containing the first semiconductor layer 106 and the second semiconductor layer 108 is then patterned into fin structures 104A in the first device region 50A and fin structures 104B in the second device region 50B. In some embodiments, the patterning process includes forming a patterned hard mask layer (not shown) on the epitaxial stack. In some embodiments, an etching process is then performed to remove portions of the epitaxial stack not covered by the patterned hard mask layer and the underlying substrate 102, thereby forming trenches and fin structures 104A and 104B protruding from the trenches. The etching process may be an anisotropic etching process, such as dry plasma etching.

[0033] In some embodiments, a portion of the substrate 102 protruding from adjacent trenches may form lower fin units 104L of fin structures 104A and 104B. In some embodiments, the reserved portion of the epitaxial stack (including the first semiconductor layer 106 and the second semiconductor layer 108) forms upper fin units of fin structures 104A and 104B on the individual lower fin units 104L.

[0034] In some embodiments, fin structures 104A and 104B extend in the X direction. In some embodiments, the longitudinal axis of fin structures 104A and 104B is parallel to the X direction. Figure 2A-2 The first device region 50A and the second device region 50B each have a fin structure, which is shown for illustrative purposes only and is not intended to limit the embodiments disclosed herein. The number of fin structures 104A and 104B in the first device region 50A and the second device region 50B may depend on the semiconductor device design requirements and / or performance considerations.

[0035] like Figure 2A-2 In some embodiments shown, an isolation structure 110 is formed to surround the lower fin unit 104L of the fin structures 104A and 104B. In some embodiments, the isolation structure 110 is configured to isolate the active region (such as the fin structures 104A and 104B) of the electrically isolated semiconductor structure 100, and can also be considered as a shallow trench isolation structure.

[0036] In some embodiments, the method of forming the isolation structure 110 includes forming an insulating material to overfill the trench. In some embodiments, the insulating material comprises silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material, the multilayers described above, and / or combinations thereof. In some embodiments, the deposition method of the insulating material may employ chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio processes, or flowable chemical vapor deposition), atomic layer deposition, another suitable technique, and / or combinations thereof. In some embodiments, the insulating material may be a double layer, such as a liner layer and a substrate layer above the liner layer. The liner layer may repair damage caused during the etching process that forms the fin structure. The substrate layer may have good gap-filling capabilities to fill the trench without forming holes or gaps therein.

[0037] In some embodiments, a planarization process is performed on the insulating material to remove a portion of the insulating material above the patterned hard mask layer (not shown) until the patterned hard mask layer (not shown) is exposed. In some embodiments, the patterned hard mask layer is also removed during the planarization process, exposing the upper surfaces of the fin structures 104A and 104B. The planarization process may be chemical mechanical polishing, etch-back, or a combination thereof. In some embodiments, the insulating material is then recessed using an etching process (such as dry plasma etching and / or wet chemical etching) until the upper fin units of the fin structures 104A or 104B are exposed. The recessed insulating material forms the isolation structure 110.

[0038] Figure 2B-1 and Figure 2B-2 This is a cross-sectional view of the semiconductor structure 100 after the dummy gate structure 112 is formed in some embodiments.

[0039] like Figure 2B-1 In some embodiments shown, a dummy gate structure 112 is formed on the semiconductor structure 100. In some embodiments, the dummy gate structure 112 extends across and around the channel regions of the fin structures 104A and 104B to define the channel regions and the source / drain regions. In some embodiments, the dummy gate structure 112 is configured as a sacrificial structure that will later be replaced by the final gate stack. In some embodiments, the dummy gate structure 112 extends in the Y direction. In some embodiments, the longitudinal axis of the dummy gate structure 112 is parallel to the Y direction. Figure 2B-1 A dummy gate structure 112 is shown for illustrative purposes and not for limiting the embodiments disclosed herein. The number of dummy gate structures 112 depends on semiconductor device design requirements and / or performance considerations.

[0040] like Figure 2B-1In some embodiments shown, the dummy gate structure 112 includes a dummy gate dielectric layer 114 and a dummy gate layer 116 formed on the dummy gate dielectric layer 114. In some embodiments, the dummy gate dielectric layer 114 may be composed of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium zirconium oxide, hafnium silicon oxide, hafnium titanium oxide, hafnium aluminum oxide, and / or combinations thereof. In some embodiments, the dielectric material may be formed using atomic layer deposition, chemical vapor deposition, thermal oxidation, physical vapor deposition, another suitable technique, and / or combinations thereof. In some embodiments, the dummy gate layer 116 may be composed of a semiconductor material such as polycrystalline silicon or polycrystalline silicon germanium. In some embodiments, the dummy gate layer 116 may be composed of a conductive material such as a metal nitride, a metal silicide, a metal, and / or combinations thereof. In some embodiments, the material of the dummy gate layer 116 may be formed using chemical vapor deposition, another suitable technique, and / or combinations thereof.

[0041] In some embodiments, the method of forming the dummy gate structure 112 includes fully compliantly depositing the dielectric material used for the dummy gate dielectric layer 114 on the semiconductor structure 100, depositing the material used for the dummy gate layer 116 on the dielectric material, planarizing the material used for the dummy gate layer 116, and patterning the dielectric material and the material used for the dummy gate layer 116 to form the dummy gate structure 112. In some embodiments, the patterning process includes forming a patterned hard mask layer (not shown) on the material used for the dummy gate layer 116 to cover the channel regions of the fin structures 104A and 104B. In some embodiments, etching removes the dummy gate layer 116 and the material used for the dielectric material not covered by the patterned hard mask layer until the source / drain regions of the fin structures 104A and 104B are exposed.

[0042] Figure 2C-1 and Figure 2C-2 This is a cross-sectional view of the semiconductor structure 100 after the formation of gate spacer layers 120 and 122 in some embodiments.

[0043] like Figure 2C-1 and Figure 2C-2 In some embodiments shown, gate spacer layers 120 and 122 are sequentially formed on semiconductor structure 100. In some embodiments, gate spacer layers 120 and 122 cover and extend along the upper surface and sidewalls of dummy gate structure 112 (and patterned mask layer, if present), the upper surface and sidewalls of the upper fin units of fin structures 104A and 104B, and the upper surface of isolation structure 110.

[0044] In some embodiments, the gate spacer layers 120 and 122 are composed of a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, and / or oxygen-doped silicon carbonitride. In some embodiments, the gate spacer layers 120 and 122 can be deposited conformally to all conditions, and the deposition method can be atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), another suitable method, and / or a combination thereof.

[0045] In some embodiments, gate spacer layers 120 and 122 are composed of a low-dielectric-constant dielectric material. For example, the dielectric constant of gate spacer layers 120 and 122 may be lower than that of silicon oxide, such as lower than 4.2, or less than or equal to about 3.9 (e.g., about 3.5 to about 3.9). In some embodiments, gate spacer layer 120 and gate spacer layer 122 are composed of different materials and have different dielectric constants. For example, gate spacer layer 120 is a silicon carbonitride layer, while gate spacer layer 122 is an oxygen-doped silicon carbonitride layer. The oxygen concentration in the silicon carbonitride layer may be greater than the oxygen concentration in the oxygen-doped silicon carbonitride layer. In some embodiments, the thickness of gate spacer layer 120 is about 10 Å to about 60 Å. In some embodiments, the thickness of gate spacer layer 122 is about 15 Å to about 90 Å.

[0046] Figure 2D-1 and Figure 2D-2 This is a cross-sectional view of the semiconductor structure 100 after the source / drain recesses 128A and 128B are formed in some embodiments.

[0047] like Figure 2D-1 and Figure 2D-2 In some embodiments shown, one or more etching processes are performed to remove the horizontal portions of the gate spacer layers 120 and 122, followed by recessing the source / drain regions of the fin structures 104A and 104B to form source / drain recesses 128A in the first device region 50A and source / drain recesses 128B in the second device region 50B. The one or more etching processes may be anisotropic etching processes (such as dry plasma etching), isotropic etching processes (such as dry chemical etching, far-end plasma etching, or wet chemical etching), and / or combinations thereof.

[0048] For example, some embodiments perform a first etching process to remove horizontal portions of gate spacer layers 120 and 122 along lateral surfaces (e.g., the upper surface of the dummy gate structure 112, the upper surface of the upper fin units of fin structures 104A and 104B, and the upper surface of the isolation structure 110). In some embodiments, the source / drain regions of fin structures 104A and 104B may be exposed after the first etching process. In some embodiments, vertical portions of gate spacer layers 120 and 122 are retained on the sidewalls of the dummy gate structure 112 as gate spacers. In some embodiments, the gate spacers are used to deflect subsequently formed source / drain structures and separate the source / drain structures from the gate structure. Furthermore, as... Figure 2D-2 In some embodiments shown, the vertical portions of the gate spacer layers 120 and 122 are also retained on the sidewalls of the upper fin units of the fin structures 104A and 104B as fin spacer layers 120' and 122'.

[0049] In some embodiments, the gate spacer layers 120 and 122 and the dummy gate structure 112 can then be used as an etching mask for a second etching process, causing the source / drain regions of the fin structures 104A and 104B to be recessed, thus aligning the source / drain recesses 128A and 128B to both sides of the dummy gate structure 112. In some embodiments, no additional photolithography process is required during the first and second etching processes. In some embodiments, the source / drain recesses 128A and 128B extend through the upper fin unit of the fin structure 104. In some embodiments, the lower surfaces of the source / drain recesses 128A and 128B may extend to a position substantially below the upper surface of the isolation structure 110.

[0050] Figure 2E-1 and Figure 2E-2 This is a cross-sectional view of the semiconductor structure 100 after the notch 130 is formed in some embodiments.

[0051] In some embodiments, an etching process is performed on the semiconductor structure 100, and the first semiconductor layer 106 of the fin structures 104A and 104B is laterally recessed from the source / drain recesses 128A and 128B to form a notch 130, such as... Figure 2E-2As shown. In some embodiments, the etching rate (or etching amount) of the first semiconductor layer 106 in the etching process is greater than the etching rate (or etching amount) of the second semiconductor layer 108 to form a notch 130 between adjacent second semiconductor layers 108, and between the lowermost second semiconductor layer 108 and the lower fin unit 104L. In some embodiments, the etching process is isotropic etching such as dry etching, distal plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof. In some embodiments, the notch 130 extends from the source / drain region to the channel region and is located directly below the gate spacer layers 120 and 122. In some embodiments, the sidewalls of the notch 130 are arc-shaped (e.g., the surface of the first semiconductor layer is recessed towards the channel region). In some embodiments, the etching process causes the end portions of the second semiconductor layers 108 of the fin structures 104A and 104B to be recessed.

[0052] Figure 2F-1 and Figure 2F-2 This is a cross-sectional view of the semiconductor structure 100 after the inner spacer layer 132 is formed in some embodiments.

[0053] like Figure 2F-1 In some embodiments shown, an inner spacer layer 132 is formed in the notch 130 to abut the recessed side surface of the first semiconductor layer 106. In some embodiments, the inner spacer layer 132 is interposed between the subsequently formed source / drain structure and the gate stack to prevent the source / drain structure from directly contacting the gate stack and to reduce parasitic capacitances (such as the capacitance between the gate and the source, and the capacitance between the gate and the drain) between the metal gate stack and the source / drain structure.

[0054] In some embodiments, the inner spacer layer 132 is composed of a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, and / or oxygen-doped silicon carbonitride. In some embodiments, the inner spacer layer 132 is composed of a dielectric material with a low dielectric constant. For example, the dielectric constant of the inner spacer layer 132 may be lower than that of silicon oxide, such as lower than 4.2 or less than or equal to about 3.9 (e.g., about 3.5 to about 3.9).

[0055] In some embodiments, the dielectric material used for the inner spacer layer 132 is deposited comprehensively and compliantly on the semiconductor structure 100 to fill the gap 130, followed by etch-back of the dielectric material to remove the dielectric material outside the gap 130, thereby forming the inner spacer layer 132. In some embodiments, the dielectric material retained in the gap 130 may form the inner spacer layer 132. In some embodiments, the deposition process includes atomic layer deposition, chemical vapor deposition (such as plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, or high aspect ratio processes), another suitable technique, and / or a combination thereof. In some embodiments, the etch-back process includes anisotropic etching processes (such as dry plasma etching), isotropic etching processes (such as dry chemical etching, distal plasma etching, or wet chemical etching), and / or a combination thereof. In some embodiments, gaps (not shown) may be formed in the inner spacer layer 132 due to the compliant deposition process.

[0056] like Figures 2G-1 to 2L-2 As shown, the source / drain shielding structure used to form the second device region 50B. Figure 2G-1 and Figure 2G-2 This is a cross-sectional view of the semiconductor structure 100 after the formation of the first dielectric masking layer 134 and the second dielectric masking layer 136 in some embodiments.

[0057] like Figure 2G-1 and Figure 2G-2 In some embodiments shown, a first dielectric masking layer 134 is formed on the semiconductor structure 100. In some embodiments, the first dielectric masking layer 134 extends along and covers the lower surfaces and sidewalls of the source / drain recesses 128A and 128B, the sidewalls and upper surfaces of the gate spacer layers 122 and 120, and the upper surface of the dummy gate layer 116. The first dielectric masking layer 134 also extends along and covers the upper surfaces and sidewalls of the fin spacer layers 120' and 122' and the upper surface of the isolation structure 110.

[0058] In some embodiments, the first dielectric masking layer 134 is composed of a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, another suitable silicon-containing dielectric material, and / or a combination thereof. In some embodiments, the method for fully conformally depositing the first dielectric masking layer 134 may employ atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), another suitable method, and / or a combination thereof.

[0059] In some embodiments, the composition of the first dielectric masking layer 134 differs from the composition of the gate spacer layers 120 and 122 and the inner spacer 132. The etch selectivity of the first dielectric masking layer 134 differs from the etch selectivity of the gate spacer layers 120 and 122 and the inner spacer 132. In some embodiments, the first dielectric masking layer 134 is composed of a dielectric material with a low dielectric constant (e.g., less than about 7). In one embodiment, the first dielectric masking layer 134 is composed of silicon oxide. In some embodiments, the dielectric constant of the first dielectric masking layer 134 is greater than the dielectric constant of the gate spacer layers 120 and 122 and the inner spacer 132. In some embodiments, the thickness T1 of the first dielectric masking layer 134 is about 10 Å to about 50 Å.

[0060] like Figure 2G-1 and Figure 2G-2 In some embodiments shown, a second dielectric masking layer 136 may be formed on a first dielectric masking layer 134. In some embodiments, the first dielectric masking layer 134 and the second dielectric masking layer 136 may partially fill the source / drain recesses 128A and 128B.

[0061] In some embodiments, the second dielectric masking layer 136 is composed of a silicon-free dielectric material. In some embodiments, the second dielectric masking layer 136 is composed of an oxide of an amphoteric metal, such as zinc oxide, aluminum oxide, tin oxide, lead oxide, beryllium oxide, chromium oxide (e.g., chromium monoxide, chromium trioxide, or chromium tetroxide), and / or a combination thereof. In some embodiments, the method for fully conformally depositing the second dielectric masking layer 136 may employ atomic layer deposition, chemical vapor deposition (e.g., low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), physical vapor deposition, another suitable method, or a combination thereof. In some embodiments, the second dielectric masking layer 136 may also be formed on the back side and sidewalls (or bevels) of the wafer. After the deposition process, a cleaning process may be performed to remove the second dielectric masking layer 136 from the back side and sidewalls (or bevels) of the wafer. The second dielectric masking layer 136 on the front side of the wafer is not cleaned, so there is no material loss.

[0062] In some embodiments, the composition of the second dielectric masking layer 136 is different from that of the first dielectric masking layer 134. In some embodiments, the etch selectivity of the second dielectric masking layer 136 is different from that of the first dielectric masking layer 134. In some embodiments, the second dielectric masking layer 136 is composed of a dielectric material with a high dielectric constant (e.g., greater than about 7). In some embodiments, the second dielectric masking layer 136 is composed of aluminum oxide. In some embodiments, the dielectric constant of the second dielectric masking layer 136 is higher than that of the first dielectric masking layer 134, the gate spacer layers 120 and 122, and the inner spacer 132. In some embodiments, the thickness T2 of the second dielectric masking layer 136 is from about 10 Å to about 50 Å. In some embodiments, the thickness T2 of the second dielectric masking layer 136 may be greater than, substantially equal to, or less than the thickness T1 of the first dielectric masking layer 134.

[0063] Figure 2H-1 and Figure 2H-2 This is a cross-sectional view of the semiconductor structure 100 after the formation of a three-layer mask structure in some embodiments.

[0064] like Figure 2H-1 and Figure 2H-2 In some embodiments shown, a fill layer 138 is formed on the second dielectric masking layer 136 and overfills the remainder of the source / drain recesses 128A and 128B. In some embodiments, the fill layer 138 is formed on the upper surface of the dummy gate structure 112. The fill layer 138 may serve as a planarization layer to provide a substantially flat surface for subsequent photolithography processes.

[0065] In some embodiments, the filler layer 138 is a bottom antireflective coating such as an inorganic or organic material (e.g., a polymer, oligomer, or monomer). In some embodiments, the filler layer 138 is composed of a carbon- and oxygen-containing organic material, which is a cross-linked photosensitive material. In some embodiments, the filler layer 138 may be formed by a spin coating process, a chemical vapor deposition process (e.g., low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), another suitable method, or a combination thereof. In some embodiments, the etch selectivity of the filler layer 138 differs from that of the second dielectric mask layer 136. In some embodiments, the thickness T3 of the filler layer 138 is about 700 Å to about 1100 Å, which can be measured from the bottom of the source / drain recess 128A or 128B.

[0066] In some embodiments, a three-layer mask structure is formed on the filler layer 138. For example... Figure 2H-1 and 2H-2In some embodiments shown, the three-layer mask structure includes a third dielectric mask layer 140 as the bottom layer, a bottom anti-reflective coating 142 as the intermediate layer, and a top photoresist mask 144. In some embodiments, the third dielectric mask layer 140 is formed on the filler layer 138. In some embodiments, the third dielectric mask layer 140 is composed of a silicon-free dielectric material. In some embodiments, the third dielectric mask layer 140 is composed of an oxide of an amphoteric metal, such as zinc oxide, aluminum oxide, tin oxide, lead oxide, beryllium oxide, chromium oxide (e.g., chromium monoxide, chromium trioxide, or chromium tetroxide), and / or combinations thereof. In some embodiments, the method for fully conformally depositing the third dielectric mask layer 140 may employ atomic layer deposition, chemical vapor deposition (e.g., low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), physical vapor deposition, another suitable method, or a combination thereof.

[0067] In some embodiments, the third dielectric masking layer 140 is composed of a dielectric material with a high dielectric constant (e.g., greater than about 7). In some embodiments, the composition of the third dielectric masking layer 140 is the same as that of the second dielectric masking layer 136. In some embodiments, the third dielectric masking layer 140 is composed of aluminum oxide. In some embodiments, the etch selectivity of the third dielectric masking layer 140 differs from the etch selectivity of the underlying filler layer 138 and the upper bottom anti-reflective coating 142. In some embodiments, the thickness T4 of the third dielectric masking layer 140 is about 30 Å to about 70 Å. In some embodiments, the thickness T4 of the third dielectric masking layer 140 is greater than the thickness T1 of the first dielectric masking layer 134 and the thickness T2 of the second dielectric masking layer 136.

[0068] In some embodiments, a bottom antireflective coating 142 is formed on the filler layer 138. The bottom antireflective coating 142 may be similar to or the same as the bottom antireflective coating material described above. In some embodiments, the thickness T5 of the bottom antireflective coating 142 is about 150 Å to about 250 Å. In some embodiments, the thickness T5 of the bottom antireflective coating 142 is greater than the thickness T3 of the third dielectric shielding layer 140.

[0069] In some embodiments, a top photoresist mask 144 is formed on a bottom antireflective coating 142. In some embodiments, the top photoresist mask 144 covers the second device region 50B of the substrate 102 but does not cover the first device region 50A. In some embodiments, the thickness T6 of the top photoresist mask 144 is about 700 Å to about 900 Å. In some embodiments, the thickness T6 of the top photoresist mask 144 is greater than the thickness T5 of the bottom antireflective coating 142.

[0070] In some embodiments, the top photoresist mask 144 is formed by a photolithography process. The photolithography process may include forming a photoresist layer on a bottom antireflective coating 142 (e.g., spin coating), performing a pre-exposure baking process, performing an exposure process using a photomask, performing a post-exposure baking process, and performing a development process. During the exposure process, the photoresist layer may be exposed to X-ray energy (e.g., ultraviolet, deep ultraviolet, or extreme ultraviolet), wherein the photomask blocks, penetrates, and / or reflects X-rays to the photoresist layer, depending on the illumination pattern and / or the type of photomask, to project an image corresponding to the photomask pattern onto the photoresist layer. Because the photoresist layer is sensitive to X-ray energy, the exposed portion of the photoresist layer will undergo a chemical change, and the exposed portion (or unexposed portion) of the photoresist layer will dissolve during the development process, depending on the characteristics of the photoresist layer and the characteristics of the developing solution used in the development process. After development, the patterned photoresist layer forms the bottom photoresist mask 144, which includes a photoresist pattern corresponding to the photomask.

[0071] Figure 2I-1 and Figure 2I-2 This is a cross-sectional view of a semiconductor structure 100 after one or more etching processes in some embodiments.

[0072] like Figure 2I-1 and Figure 2I-2 In some embodiments shown, one or more etching processes are performed using a top photoresist mask 144 to remove portions of the bottom anti-reflective coating 142, the third dielectric mask layer 140, and the filler layer 138 in the first device region 50A of the substrate 102, exposing the second dielectric mask layer 136 in the first device region 50A. In some embodiments, after one or more etching processes, a portion of the third dielectric mask layer 140 in the second device region 50B is exposed.

[0073] For example, a first etching process may be performed to remove a portion of the bottom antireflective coating 142 in the first device region 50A until a third dielectric mask layer 140 is exposed (which may serve as an etch stop layer in the first etching process). In some embodiments, the first etching process may be an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching, far-end plasma etching, or wet chemical etching), an ashing process, and / or a combination thereof. After the first etching process, the top photoresist mask 144 in the second device region 50B may be completely consumed, or the top photoresist mask 144 in the second device region 50B may be removed by an additional ashing process to expose a portion of the bottom antireflective coating 142 in the second device region 50B, which may serve as an etch mask for subsequent etching processes.

[0074] A second etching process can then be performed to remove a portion of the third dielectric masking layer 140 in the first device region 50A until the filler layer 138 (which can serve as an etch stop layer in the second etching process) is exposed. In some embodiments, the second etching process is a wet etching process using an acidic solution with a pH of about 3 to about 6.8, or an alkaline solution with a pH of about 7.2 to about 11. In some embodiments, the second etching process uses a Caros solution containing sulfuric acid and hydrogen peroxide. After the second etching process, the undercoat antireflective coating 142 in the second device region 50B can be removed by an additional etching process or an ashing process to expose a portion of the third dielectric masking layer 140 in the second device region 50B. The third dielectric masking layer 140 can serve as an etch mask for subsequent etching processes.

[0075] A third etching process can then be performed to remove a portion of the filler layer 138 in the first device region 50A until the second dielectric mask layer 136 is exposed. The second dielectric mask layer 136 can serve as an etch stop layer in the third etching process. In some embodiments, the third etching process can be an anisotropic dry etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching, far-end plasma etching, or wet chemical etching), an ashing process, and / or a combination thereof. After the third etching process, a portion of the third dielectric mask layer 140 in the second device region 50B can remain substantially unetched and can serve as an etch mask in subsequent etching processes.

[0076] Figure 2J-1 and Figure 2J-2 This is a cross-sectional view of the semiconductor structure 100 after a portion of the second dielectric masking layer 136 in the first device region 50A has been removed in some embodiments.

[0077] like Figure 2J-1 and Figure 2J-2 In some embodiments shown, an etching process is performed to remove a portion of the second dielectric masking layer 136 in the first device region 50A to expose a portion of the first dielectric masking layer 134 in the first device region 50A. In some embodiments, the third dielectric masking layer 140 in the second device region 50B may also be removed during the etching process to expose the filler layer 138 in the second device region 50B. In some embodiments, the source / drain masking structure covers the second device region 50B and partially fills the source / drain recess 128B.

[0078] In some embodiments, the etching process employs a wet etching process, which may use an acidic solution with a pH of about 3 to about 6.8, such as a diluted hydrogen chloride solution, a diluted hydrofluoric acid solution, another suitable solution, and / or a combination thereof. In some embodiments, the hydrofluoric acid concentration of the dilute hydrofluoric acid solution is about 0.1 vol% to about 0.3 vol%. In some embodiments, the etching process employs an alkaline solution with a pH of about 7.2 to about 11, such as a dilute ammonium hydroxide solution.

[0079] Figure 2K-1 and Figure 2K-2 This is a cross-sectional view of the semiconductor structure 100 after a portion of the first dielectric masking layer 134 in the first device region 50A has been removed in some embodiments.

[0080] like Figure 2K-1 and Figure 2K-2 In some embodiments shown, an etching process is performed to remove a portion of the first dielectric masking layer 134 in the first device region 50A to expose the source / drain regions, inner spacers 132, gate spacer layers 122 and 120, and dummy gate layer 116 of the fin structure 104A. In some embodiments, the fin spacer layers 120' and 122' and the isolation structure 110 in the first device region 50A may also be exposed. In some embodiments, portions of the first dielectric masking layer 134 and the second dielectric masking layer 136 in the second device region 50B may together serve as a source / drain masking structure.

[0081] In some embodiments, the etching process employs a wet etching process using an acidic solution with a pH of about 3 to about 6.8, such as a diluted hydrogen chloride solution or a diluted hydrofluoric acid solution. In some embodiments, the hydrofluoric acid concentration of the diluted hydrofluoric acid solution is about 0.1 vol% to about 0.3 vol%. In some embodiments, the etching process employs a wet etching process using an alkaline solution with a pH of about 7.2 to about 11, such as a diluted ammonium hydroxide solution. In some embodiments, the etching process used to remove the second dielectric masking layer 136 and the etching process used to remove the first dielectric masking layer 134 are a single continuous etching process, thus allowing the second dielectric masking layer 136 and the first dielectric masking layer 134 to be removed simultaneously. In some embodiments, the etching process used to remove the second dielectric masking layer 136 and the etching process used to remove the first dielectric masking layer 134 are separate etching processes.

[0082] In some embodiments, the etching process used to remove the first dielectric mask layer 134 may include a main etching step that removes a major portion of the first dielectric mask layer 134 from the first device region 50A. The main etching step is completed once some layers (such as fin structure 104A, inner spacers 132, gate spacer layers 122 and 120, dummy gate layer 116, isolation structure 110, and / or fin spacer layer 120') begin to be exposed from the first dielectric mask layer 134. The duration of the main etching step depends on the etching time pattern or endpoint pattern.

[0083] In some embodiments, the etching process used to remove the first dielectric masking layer 134 also includes an over-etching step after the main etching step to partially or completely remove the remainder of the first dielectric masking layer 134 from the first device region 50A. The time of the over-etching step may be from 5% to about 30% of the time of the main etching step. To avoid additional loss of gate spacer layers 122 and 120 and / or inner spacer 132 during the etching process used to remove the first dielectric masking layer 134, the time of the over-etching step may depend on the difference in etch selectivity between the first dielectric masking layer 134 and the gate spacer layers 122 and 120 (or inner spacer 132). Loss of low dielectric constant material from the gate spacer layers 122 and 120 and / or inner spacer 132 may degrade the performance of the final semiconductor device, such as speed. In some embodiments, the etching process used to remove the first dielectric masking layer 134 does not include an over-etching step, and residues of the first dielectric masking layer 134 may remain on the aforementioned layers.

[0084] For example, when the difference in etch selectivity between the first dielectric masking layer 134 and the gate spacer layers 122 and 120 (or the inner spacer 132) is large, an over-etching step can be performed until the residual first dielectric masking layer 134 is completely removed. When the difference in etch selectivity between the first dielectric masking layer 134 and the gate spacer layers 122 and 120 (or the inner spacer 132) is small, a small amount of the first dielectric masking layer 134 may remain on the source / drain regions, the inner spacer 132, and / or the gate spacer layers 122 and 120 of the fin structure 104A after the over-etching step.

[0085] When a small amount of the first dielectric masking layer 134 remains on the source / drain region of the fin structure 104A, it will not negatively affect the subsequent epitaxial growth of the source / drain structure, because the first dielectric masking layer 134 is composed of a silicon-containing dielectric material such as silicon oxide. Furthermore, the first dielectric masking layer 134 remaining on the gate spacer layers 122 and 120 and / or the inner spacer 132 will not significantly increase the overall capacitance between the subsequently formed source / drain structure and the final gate stack, because the first dielectric masking layer 134 has a low dielectric constant.

[0086] In some cases where a first dielectric masking layer 134 is not formed, the presence of a second dielectric masking layer 136 (composed of an oxide of an amphoteric metal, such as aluminum oxide, and having a high dielectric constant) remaining on the source / drain region may negatively impact the epitaxial growth of the subsequently formed source / drain structure. Furthermore, even a small amount of the second dielectric masking layer 136 remaining on the gate spacer layers 122 and 120 and / or the inner spacer 132 may significantly increase the overall capacitance between the subsequently formed source / drain structure and the final gate stack, thereby degrading the performance, such as speed, of the final semiconductor device. However, performing an etching step to completely remove the remaining second dielectric masking layer 136 may result in the loss of excessive amounts of low-dielectric-constant material from the gate spacer layers 122 and 120 and / or the inner spacer 132, which also degrades the performance, such as speed, of the final semiconductor device.

[0087] This embodiment employs a low-dielectric-constant first dielectric masking layer 134 as the bottom layer of the source / drain masking structure, thus allowing for the substantial removal of the high-dielectric-constant second dielectric masking layer 136. Furthermore, the low-dielectric-constant first dielectric masking layer 134 provides a good balance between the loss of low-dielectric-constant spacers and the residual amount of the source / drain masking structure, thereby increasing the process tolerance of the patterned source / drain masking structure.

[0088] Figure 2L-1 and Figure 2L-2 This is a cross-sectional view of the semiconductor structure 100 after a portion of the fill layer 138 in the second device region 50B has been removed in some embodiments.

[0089] like Figure 2L-1 and Figure 2L-2 In some embodiments shown, the filler layer 138 is removed from the second device region 50B of the substrate 102 until the second dielectric mask layer 136 is exposed. In some embodiments, the removal process may be an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching, remote plasma etching, or wet chemical etching), an ashing process, and / or a combination thereof.

[0090] Figure 2M-1 and Figure 2M-2 This is a cross-sectional view of the semiconductor structure 100 after the source / drain structure 146A is formed in some embodiments.

[0091] like Figure 2M-1 and Figure 2M-2In some embodiments shown, a source / drain structure 146A is formed in a source / drain recess 128A of a first device region 50A of a semiconductor structure 100 using an epitaxial growth process. The epitaxial growth process can be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, another suitable technique, or a combination thereof. A pre-cleaning process can be performed prior to the epitaxial growth process. For example, a wet cleaning process using a diluted ammonium hydroxide solution and / or a silicon-cobalt-nickel cleaning process can be used. In some embodiments, the source / drain structure 146A is grown on the source / drain region of a fin structure 104A. In some embodiments, the source / drain structure 146A is adjacent to a second semiconductor layer 108 and an inner spacer layer 132 of the fin structure 104A.

[0092] In some embodiments, the fin structure 104A is used to form a p-type channel nanostructure transistor, while the source / drain structure 146A is composed of a semiconductor material such as silicon-germanium, silicon, gallium arsenide, another suitable semiconductor material, or a combination thereof. In some embodiments, the source / drain structure 146A is doped with a p-type dopant during the epitaxial growth process. For example, the p-type dopant may be boron or boron difluoride. For example, the source / drain structure 146A may be epitaxially grown silicon-germanium doped with boron to form a boron-doped silicon-germanium source / drain structure.

[0093] In some embodiments, the second dielectric masking layer 136 of the source / drain masking structure is sufficient to prevent epitaxial semiconductor material from growing on the dielectric surface of the second dielectric masking layer 136 during the epitaxial growth of the source / drain structure 146A. This allows the source / drain masking structure to be easily removed in subsequent processes.

[0094] In some embodiments, the growth of the source / drain structure 146A is initially confined by the fin spacer layers 120' and 122', thus the source / drain structure 146A has a narrow bottom. Once the source / drain structure 146A has grown to protrude from the fin spacer layers 120' and 122', the source / drain structure 146A can grow to have a crystal surface with a specific crystal orientation, giving the source / drain structure 146A a wider upper portion. Although the source / drain structure 146A in the figures has a crystal plane, the source / drain structure 146A in some other embodiments may have an arcuate surface.

[0095] Figure 2N-1 and Figure 2N-2 This is a cross-sectional view of the semiconductor structure 100 after removing portions of the second dielectric masking layer 136 and the first dielectric masking layer 134 in the second device region 50B, according to some embodiments.

[0096] like Figure 2N-1 and Figure 2N-2In some embodiments shown, the second dielectric masking layer 136 and the first dielectric masking layer 134 are removed from the second device region 50B of the substrate 102 to expose the source / drain regions, inner spacers 132, gate spacer layers 122 and 120, and dummy gate layer 116 of the fin structure 104B. In some embodiments, the isolation structure 110 and the fin spacer layers 120' and 122' in the second device region 50B are also exposed.

[0097] In some embodiments, the removal process of the second dielectric masking layer 136 and the first dielectric masking layer 134 may be an etching process using a Caros solution containing sulfuric acid and hydrogen peroxide. In some embodiments, the method for removing the second dielectric masking layer 136 may be an etching process, which may be combined with... Figure 2J-1 and Figure 2J-2 The aforementioned etching process is the same as or similar to the above-described etching process. In some embodiments, the removal process of the first dielectric mask layer 134 may be an etching process, which may be similar to... Figure 2K-1 and Figure 2K-2 The etching processes described above are similar or identical. During the etching process, due to the large difference between the etching selectivity of the first dielectric masking layer 134 and the second dielectric masking layer 136 and the etching selectivity of the source / drain structure 146A, the epitaxial semiconductor material loss of the source / drain structure 146A is small.

[0098] Similarly, when a small amount of the first dielectric masking layer 134 remains on the source / drain region of the fin structure 104B, it will not negatively affect the subsequent epitaxial growth of the source / drain structure. Furthermore, the first dielectric masking layer 134 remaining on the gate spacer layers 120 and 122 and / or the inner spacer 132 will not significantly increase the overall capacitance between the subsequently formed source / drain structure and the final gate stack.

[0099] like Figures 2O-1 to 2P-2 As shown, a source / drain masking structure is formed for the first device region 50A. The method for forming the source / drain masking structure used in the first device region 50A can be compared with... Figures 2G-1 to 2L-1 The source / drain shielding structure used in the second device region 50B shown is formed in a similar way. Figure 2O-1 and Figure 2O-2 This is a cross-sectional view of the semiconductor structure 100 after the formation of a three-layer mask structure in some embodiments.

[0100] like Figure 2O-1 and Figure 2O-2In some embodiments shown, a fourth dielectric masking layer 148, a fifth dielectric masking layer 150, a filler layer 152, and a three-layer masking structure are sequentially formed on the semiconductor structure 100. In some embodiments, the three-layer masking structure includes a sixth dielectric masking layer 154 as a bottom layer, a bottom anti-reflective coating 156 as an intermediate layer, and a top photoresist mask 158. In some embodiments, the top photoresist mask 158 covers the first device region 50A of the substrate 102 but does not cover the second device region 50B.

[0101] The materials and formation methods of the fourth dielectric masking layer 148 and the fifth dielectric masking layer 150 can be compared with those of the others. Figure 2G-1 and Figure 2G-2 The materials and formation methods of the first dielectric masking layer 134 and the second dielectric masking layer 136 shown above are similar or the same. The materials and formation methods of the filler layer 152, the sixth dielectric masking layer 154, the bottom anti-reflective coating 156, and the top photoresist mask 158 can be the same as those of the first dielectric masking layer 134 and the second dielectric masking layer 136 shown above. Figure 2H-1 and Figure 2H-2 The materials and formation methods of the above-mentioned filler layer 138, third dielectric mask layer 140, bottom anti-reflective coating 142 and top photoresist mask 144 are similar or the same.

[0102] Figure 2P-1 and Figure 2P-2 This is a cross-sectional view of the semiconductor structure 100 after the source / drain mask structure used to form the first device region 50A in some embodiments.

[0103] like Figure 2P-1 and Figure 2P-2 In some embodiments shown, multiple etching processes can be performed on the semiconductor structure 100 using the top photoresist mask 158 to remove the bottom anti-reflective coating 156, the sixth dielectric mask layer 154, the fill layer 152, the fifth dielectric mask layer 150, and the fourth dielectric mask layer 148 from the second device region 50B, exposing the source / drain regions, inner spacers 132, gate spacer layers 122 and 120, and the dummy gate layer 116 of the fin structure 104B. In some embodiments, the isolation structure 110 and the fin spacer layers 120' and 122' in the second device region 50B are also exposed.

[0104] The etching process used to remove the bottom anti-reflective coating 156, the sixth dielectric mask layer 154, and the filler layer 152 is compatible with... Figure 2I-1 and Figure 2I-2 The etching process shown above is similar to or the same as that described above. The etching process used to remove the fifth dielectric mask layer 150 can be compared with... Figure 2J-1 and Figure 2J-2 The etching process described above is similar to or the same as the etching process used to remove the fourth dielectric mask layer 148. Figure 2K-1 and Figure 2K-2The etching processes shown above are similar or identical.

[0105] In some embodiments, the filler layer 152 is then removed from the second device region 50B. The etching process used to remove the filler layer 152 can be compared with... Figure 2L-1 and Figure 2L-2 The etching processes shown above are similar or identical.

[0106] Similarly, after the etching process used to remove the fourth dielectric masking layer 148, if a small amount of the fourth dielectric masking layer 148 remains on the source / drain region of the fin structure 104B, it will not negatively affect the subsequent epitaxial growth of the source / drain structure, because the fourth dielectric masking layer 148 is composed of a silicon-containing dielectric material (such as silicon oxide). Furthermore, the presence of the fourth dielectric masking layer 148 on the gate spacer layers 122 and 120 and / or the inner spacer 132 will not significantly increase the overall capacitance between the subsequently formed source / drain structure and the final gate stack, because the fourth dielectric masking layer 148 has a low dielectric constant.

[0107] This embodiment employs a low-dielectric-constant fourth dielectric masking layer 148 as the bottom layer of the source / drain structure, thus allowing for the substantial removal of the high-dielectric-constant fifth dielectric masking layer 150. Furthermore, the low-dielectric-constant fourth dielectric masking layer 148 provides a good balance between the loss of low-dielectric-constant spacers and the residue of the source / drain masking structure, thereby increasing the process tolerance of the patterned source / drain masking structure.

[0108] Figure 2Q-1 and Figure 2Q-2 This is a cross-sectional view of the semiconductor structure 100 after the source / drain structure 146B is formed in some embodiments.

[0109] like Figure 2Q-1 and Figure 2Q-2 In some embodiments shown, a source / drain structure 146B is formed in the source / drain recess 128B of the second device region 50B of the semiconductor structure 100 using an epitaxial growth process. The epitaxial growth process can be molecular beam epitaxy, metal-organic chemical vapor deposition, vapor phase epitaxy, another suitable technique, or a combination thereof. A pre-cleaning process can be performed prior to the epitaxial growth process. For example, a wet cleaning process using a diluted ammonium hydroxide solution and / or a silicon-cobalt-nickel cleaning process can be used. In some embodiments, the source / drain structure 146B is grown on the source / drain region of the fin structure 104B. In some embodiments, the source / drain structure 146B is adjacent to the second semiconductor layer 108 and the inner spacer layer 132 of the fin structure 104B.

[0110] In some embodiments, the fin structure 104B is used to form an n-type channel nanostructure transistor, and the source / drain structure 146B is composed of a semiconductor material such as silicon phosphide, silicon arsenide, silicon carbide, silicon carbide, silicon, gallium arsenide, another suitable semiconductor material, or a combination thereof. In some embodiments, the source / drain structure 146B may be doped with an n-type dopant during the epitaxial growth process. For example, the n-type dopant may be phosphorus or arsenic. For example, the source / drain structure 146B may be epitaxially grown silicon and doped with phosphorus to form a phosphorus-doped silicon source / drain structure, and / or doped with arsenic to form an arsenic-doped silicon source / drain structure.

[0111] In some embodiments, the fifth dielectric masking layer 150 of the source / drain masking structure is sufficient to prevent the epitaxial semiconductor material from growing on the dielectric surface of the fifth dielectric masking layer 150 during the epitaxial growth process of the source / drain structure 146B. This allows the source / drain masking structure to be easily removed in subsequent processes. The narrow bottom of the source / drain structure 146B may be confined between the fin spacer layers 120' and 122', while the wider upper portion has a crystal surface. Although the source / drain structure 146B in the figures has a crystal surface, the source / drain structure 146B in some other embodiments may have an arcuate surface.

[0112] Figure 2R-1 and Figure 2R-2 This is a cross-sectional view of the semiconductor structure 100 after removing portions of the fifth dielectric masking layer 150 and the fourth dielectric masking layer 148 in the first device region 50A in some embodiments.

[0113] like Figure 2R-1 and Figure 2R-2 In some embodiments shown, the fifth dielectric masking layer 150 and the fourth dielectric masking layer 148 are removed from the first device region 50A of the substrate 102 to expose the source / drain structure 146A, gate spacer layers 122 and 120, and the dummy gate layer 116. In some embodiments, the isolation structure 110 and the fin spacer layers 120' and 122' in the first device region 50A are also exposed. The removal process can be compared with... Figure 2N-1 and Figure 2N-2 The removal process described above is similar or identical. Similarly, when a small amount of the fourth dielectric masking layer 148 remains on the gate spacer layers 122 and 120, the overall capacitance between the source / drain structure 146A and the subsequently formed final gate stack does not increase significantly.

[0114] Figure 2S-1 and Figure 2S-2 This is a cross-sectional view of the semiconductor structure 100 after the formation of the contact etch stop layer 160 and the interlayer dielectric layer 162 in some embodiments.

[0115] like Figure 2S-1 and Figure 2S-2 In some embodiments shown, a contact etch stop layer 160 is formed on the semiconductor structure 100. In some embodiments, the contact etch stop layer 160 covers and extends along the surfaces of the wider upper portions of the source / drain structures 146A and 146B, the sidewalls of the gate spacer layer 122, the sidewalls of the upper portion of the fin spacer layer 122', the upper portion of the fin spacer layer 120', and the upper surface of the isolation structure 110. Figure 2S-1 and Figure 2S-2 In some of the embodiments shown, an interlayer dielectric layer 162 is then formed on the contact etch stop layer 160.

[0116] In some embodiments, the contact etch stop layer 160 is composed of a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide, oxygen-doped silicon carbide, oxygen-doped silicon carbonitride, or a combination thereof. In some embodiments, the dielectric material used for the contact etch stop layer 160 can be deposited compliantly on the semiconductor structure 100, and the deposition method can be chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), atomic layer deposition, another suitable method, or a combination thereof.

[0117] In some embodiments, the interlayer dielectric layer 162 is composed of a dielectric material such as undoped silicate glass, doped silicon oxide (such as borosilicate glass, fluorosilicate glass, phosphosilicate glass, or borosilicate glass), and / or another suitable dielectric material. In some embodiments, the material of the interlayer dielectric layer 162 may be different from that of the contact etch stop layer 160. In some embodiments, the deposition method of the dielectric material used for the interlayer dielectric layer 162 may employ chemical vapor deposition (such as high-density plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), another suitable technique, and / or a combination thereof. Subsequently, the dielectric material of the contact etch stop layer 160 and the interlayer dielectric layer 162 above the upper surface of the dummy gate layer 116 is removed using methods such as chemical mechanical polishing until the upper surface of the dummy gate structure 112 is exposed. In some embodiments, the upper surface of the interlayer dielectric layer 162 is substantially coplanar with the upper surface of the dummy gate layer 116.

[0118] Figure 2T-1 and Figure 2T-2 This is a cross-sectional view of the semiconductor structure 100 after the gate trench 164 and gap 166 are formed in some embodiments.

[0119] like Figure 2T-1In some embodiments shown, an etching process is used to remove the dummy gate structure 112 to form a gate trench 164. In some embodiments, the gate trench 164 exposes the channel regions CH of the fin structures 104A and 104B. In some embodiments, the gate trench 164 also exposes the inner sidewalls of the gate spacer layer 120 facing the channel regions.

[0120] In some embodiments, the etching process includes one or more etching passes. For example, when the dummy gate layer 116 is composed of polysilicon, a wet etchant such as tetramethylammonium hydroxide can be used to selectively remove the dummy gate layer 116. For example, plasma dry etching, dry chemical etching, and / or wet etching can then be used to remove the dummy gate dielectric layer 114.

[0121] like Figure 2T-1 In some embodiments shown, an etching process is used to remove the first semiconductor layer 106 of fin structures 104A and 104B to form a gap 166. The inner spacer layer 132 can serve as an etch stop layer in the etching process, protecting the source / drain structures 146A and 146B from damage. In some embodiments, the gap 166 is formed between the adjacent second semiconductor layers 108 of fin structures 104A and 104B, and between the lowermost second semiconductor layer 108 and the lower fin unit 104L. In some embodiments, the gap 166 also exposes the inner sidewall of the inner spacer layer 132 facing the channel region.

[0122] In some embodiments, the four main surfaces of the second semiconductor layer 108 are exposed after the etching process. Figure 2T-1 (Only the upper and lower surfaces are shown). In some embodiments, the exposed second semiconductor layer 108 may form a nanostructure that serves as a channel region for a final semiconductor device, such as a nanostructure transistor.

[0123] In some embodiments, the etching process includes a selective wet etching process, such as an etching process using a mixture of ammonium hydroxide, hydrogen peroxide, and water. In some embodiments, the wet etching process uses etchants such as ammonium hydroxide, tetramethylammonium hydroxide, ethylenediamine catechol, and / or potassium hydroxide solution. In some embodiments, the inner spacer layer 132 serves as an etching stop layer in the etching process.

[0124] Figure 2U-1 and Figure 2U-2 This is a cross-sectional view of the semiconductor structure 100 after the final gate stack 168 is formed in some embodiments.

[0125] like Figure 2U-1In some embodiments shown, a gate dielectric layer 170 is formed on and covers the exposed surface of a nanostructure such as the second semiconductor layer 108. In some embodiments, the gate dielectric layer 170 also extends along and covers the inner sidewall of the gate spacer layer 120 facing the channel region. In some embodiments, the gate dielectric layer 170 also extends along and covers the inner sidewall of the inner spacer layer 132 facing the channel region.

[0126] The gate dielectric layer 170 may include an interface layer and a high-dielectric-constant dielectric layer formed on the interface layer. The interface layer may be composed of chemically formed silicon oxide, and its formation method may be one or more cleaning processes, such as a cleaning process containing a mixture of ozone, ammonium hydroxide, and hydrogen peroxide and water, and / or a mixture of hydrogen chloride and hydrogen peroxide and water. The interface layer may be formed by oxidizing the outer portion of a nanostructure, such as the second semiconductor layer 108, and may be formed on the exposed main surface of the nanostructure, such as the second semiconductor layer 108, rather than on the surface of the dielectric layer (such as the gate spacer and the inner spacer). In some embodiments, the high-dielectric-constant dielectric layer is composed of a dielectric material having a high dielectric constant (e.g., greater than 3.9). In some embodiments, the high-dielectric-constant dielectric layer comprises hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum trioxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum pentoxide, yttrium oxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, silicon nitride, silicon oxynitride, combinations thereof, or another suitable material. The deposition method for the high-dielectric-constant dielectric layer may employ atomic layer deposition, physical vapor deposition, chemical vapor deposition, and / or another suitable technique.

[0127] like Figure 2U-1 In some embodiments shown, a metal gate layer 172 is formed on the gate dielectric layer 170 and fills the remaining portion of the gate trench 164 and the gap. In some embodiments, the metal gate layer 172 covers a nanostructure such as the second semiconductor layer 108. In some embodiments, the metal gate layer 172 is composed of a variety of conductive materials such as metals, metal alloys, conductive metal oxides and / or nitrides, another suitable conductive material, and / or combinations thereof. For example, the metal gate layer 172 may be composed of titanium, silver, aluminum, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, silicon tantalum nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, copper, tungsten, rhenium, iridium, cobalt, nickel, another suitable conductive material, or a multilayer thereof.

[0128] The metal gate layer 172 can be a multilayer structure consisting of a diffusion barrier layer, a work function layer having a selected work function to improve the device performance (e.g., threshold voltage) of an n-channel or p-channel MOSFET, a capping layer to prevent oxidation of the work function layer, an adhesion layer to hold the work function layer to the next layer, a metal filler layer to reduce the overall stacking of gate layers, and / or another suitable layer. The metal gate layer 172 can be formed using atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or another suitable process. The metal gate layer 172 used for forming n-channel nanostructure transistors (such as the transistor in the second device region 50B) and p-type nanostructure transistors (such as the transistor in the first device region 50A) can be formed separately, allowing the use of different work function materials.

[0129] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed on the semiconductor structure 100 to remove material from the gate dielectric layer 170 and the metal gate layer 172 above the upper surface of the interlayer dielectric layer 162. In some embodiments, after the planarization process, the upper surface of the metal gate layer 172 and the upper surface of the interlayer dielectric layer 162 are substantially coplanar.

[0130] In some embodiments, the gate dielectric layer 170 and the metal gate layer 172 may be combined to form a final gate stack 168. In some embodiments, the final gate stack 168 extends in the Y direction. Therefore, in some embodiments, the longitudinal axis of the final gate stack 168 is parallel to the Y direction. In some embodiments, the final gate stack 168 covers each nanostructure such as the second semiconductor layer 108 and is interposed between the source / drain structures 146A and between the source / drain structures 146B.

[0131] In some embodiments, in the first device region 50A, the final gate stack 168 is combined with the source / drain structure 146A to form a nanostructure transistor such as a p-type channel nanostructure transistor. In some embodiments, in the second device region 50B, the final gate stack 168 is combined with the source / drain structure 146B to form a nanostructure transistor such as an n-type channel nanostructure transistor. The final gate stack 147 may join the channel region of a nanostructure such as the second semiconductor layer 108, allowing current to flow between the source / drain structures 146A and between the source / drain structures 146B during operation.

[0132] It should be understood that the semiconductor structure 100 can be subjected to subsequent complementary metal-oxide-semiconductor processes to form various structures (such as multilayer interconnect structures, such as contacts, vias, lines, intermetallic dielectric layers, passivation layers, or the like) on the semiconductor structure 100.

[0133] This disclosure employs a dual-layer source / drain mask structure, comprising a silicon-containing dielectric mask layer (such as a first dielectric mask layer 134 and a fourth dielectric mask layer 148) and a high-dielectric-constant dielectric mask layer (such as a second dielectric mask layer 136 and a fifth dielectric mask layer 150) located on the silicon-containing dielectric mask layer. This provides a good balance between low-dielectric-constant spacer loss and source / drain mask structure residuals, thereby increasing the process tolerance of the patterned source / drain mask structure. This improves the yield and performance of the final semiconductor device.

[0134] Figures 3A to 3G In some embodiments, semiconductor structures with various intermediate stages correspond to... Figure 1 The sectional view of section XX shown. Figures 3A to 3G Implementation examples and Figures 2A-1 to 2U-2 The embodiments shown are similar, except that the first dielectric shielding layer 134 is retained in the inner spacer 132.

[0135] Figure 3A In some embodiments, Figures 2A-1 to 2F-2 A cross-sectional view of the semiconductor structure 200 after the above steps.

[0136] In some embodiments, fin structures 104A and 104B are formed on substrate 102, and an isolation structure 110 is formed. Figure 2A-2 The fin units 104L surround the lower side of the fin structures 104A and 104B. In some embodiments, a dummy gate structure 112 is formed to surround the channel regions of the fin structures 104A and 104B, and gate spacer layers 120 and 122 are sequentially formed on the semiconductor structure 200. In some embodiments, one or more etching processes are performed to remove the horizontal portions of the gate spacer layers 120 and 122, and to recess the source / drain regions of the fin structures 104A and 104B to form source / drain recesses 128A in the first device region 50A and source / drain recesses 128B in the second device region 50B. In some embodiments, an etching process is performed on the semiconductor structure 200 to laterally recess the first semiconductor layer 106 of the fin structures 104A and 104B from the source / drain recesses 128A and 128B, thereby forming a notch 130 adjacent to the first semiconductor layer 106 of the fin structures 104A and 104B. For example... Figure 3A In some embodiments shown, gaps 202 are formed in the inner spacer layer 132 due to the compliant deposition of the inner spacer layer 132.

[0137] Figure 3B In some embodiments, Figures 2G-1 to 2H-2 A cross-sectional view of the semiconductor structure 200 after the above steps.

[0138] In some embodiments, a three-layer mask structure comprising a first dielectric mask layer 134, a second dielectric mask layer 136, a fill layer 138, and a third dielectric mask layer 140, a bottom anti-reflective coating 142, and a top photoresist mask 144 is formed on a semiconductor structure 200. In some embodiments, a three-layer mask structure comprising a first dielectric mask layer 134, a second dielectric mask layer 136, a fill layer 138, and a third dielectric mask layer 140, a bottom anti-reflective coating 142, and a top photoresist mask 144 is formed on a semiconductor structure 200. For example... Figure 3B In some embodiments shown, a first dielectric masking layer 134 is formed to fill the gap 202.

[0139] Figure 3C In some embodiments, Figures 2I-1 to 2L-2 The diagram shows a cross-sectional view of the semiconductor structure 200 after the steps described above.

[0140] In some embodiments, one or more etching processes are performed using a top photoresist mask 144 to remove portions of the bottom anti-reflective coating 142, the third dielectric mask layer 140, the fill layer 138, the second dielectric mask layer 136, and the first dielectric mask layer 134 in the first device region 50A of the substrate 102, thereby exposing the source / drain regions of the fin structure 104A. Some embodiments involve etching processes to remove the first dielectric mask layer 134 (…). Figure 2K-1 and Figure 2K-2 After that, a portion of the first dielectric masking layer 134 that fills the gap 202 remains in the inner spacer 132 and is marked as the retained portion 134'. The retained portion 134' of the first dielectric masking layer 134 can be part of the inner spacer.

[0141] Figure 3D In some embodiments, Figures 2M-1 to 2M-2 A cross-sectional view of the semiconductor structure 200 after the above steps.

[0142] In some embodiments, an epitaxial growth process is used to form a source / drain structure 146A in the source / drain recess 128A of the first device region 50A of the semiconductor structure 200.

[0143] Figure 3E In some embodiments, Figures 2N-1 to 2P-2 A cross-sectional view of the semiconductor structure 200 after the above steps.

[0144] In some embodiments, the masking structure used in the second device region 50B is removed. Some embodiments involve an etching process to remove the first dielectric masking layer 134. Figure 2N-1 and Figure 2N-2After that, a portion of the first dielectric masking layer 134 that fills the gap 202 remains in the inner spacer 132 and is marked as the retained portion 134'. The retained portion 134' of the first dielectric masking layer 134 can be part of the inner spacer.

[0145] In some embodiments, the fourth dielectric masking layer 148, the fifth dielectric masking layer 150, and the filling layer 152 ( Figure 2O-1 ), and a three-layer mask structure containing a sixth dielectric mask layer 154, a bottom anti-reflective coating 156, and a top photoresist mask 158. Figure 2O-1 The fin structure 104B is formed on the semiconductor structure 200. In some embodiments, one or more etching processes are performed using a top photoresist mask 158 to remove the bottom anti-reflective coating 156, the sixth dielectric mask layer 154, the fill layer 152, the fifth dielectric mask layer 150, and the fourth dielectric mask layer 148 in the second device region 50B of the substrate 102, thereby exposing the source / drain regions of the fin structure 104B.

[0146] Figure 3F In some embodiments, Figures 2Q-1 to 2R-2 A cross-sectional view of the semiconductor structure 200 after the above steps.

[0147] In some embodiments, a source / drain structure 146B is formed in the source / drain recess 128B of the second device region 50B of the semiconductor structure 200 using an epitaxial growth process. In some embodiments, the mask structure used in the first device region 50A is removed.

[0148] Figure 3G In some embodiments, Figures 2S-1 to 2U-2 A cross-sectional view of the semiconductor structure 200 after the above steps.

[0149] In some embodiments, a contact etch stop layer 160 and an interlayer dielectric layer 162 are sequentially formed on the semiconductor structure 200. In some embodiments, an etching process is used to remove the dummy gate structure 112 to form a gate trench 164. Figure 2T-1 In some embodiments, an etching process is used to remove the first semiconductor layer 106 of the fin structures 104A and 104B to form a gap 166. Figure 2T-1 In some embodiments, a final gate stack 168 is formed to encapsulate each nanostructure (such as the second semiconductor layer 108 of the fin structure 104A).

[0150] The reserved portion 134' of the first dielectric masking layer 134 remains within the inner spacer 132, thus not negatively impacting the epitaxial growth of the source / drain structure. Furthermore, it does not significantly increase the overall capacitance between the source / drain structure and the final gate stack. Additionally, because the reserved portion 134' of the first dielectric masking layer 134 fills the gap 202, the inner spacer layer 132 (along with the reserved portion 134') is more robust to resist the formation of the gap 166. Figure 2U-1 The etching process used can improve the yield and performance of the final semiconductor device.

[0151] Figure 4 This is a cross-sectional view of the semiconductor structure 400 in some embodiments. Figure 4 The semiconductor structure 400 shown is Figure 2U-1 The semiconductor structure 100 shown is similar, except that the first dielectric masking layer 134 is retained on the gate spacer layer 122.

[0152] Some embodiments involve an etching process that removes the first dielectric mask layer 134 from the first device region 50A. Figure 2K-1 and Figure 2K-2 Afterwards, a portion of the first dielectric masking layer 134 remains on the gate spacer layer 122 in the first device region 50A. Some embodiments involve an etching process that removes the first dielectric masking layer 134 from the second device region 50B. Figure 2N-1 and Figure 2N-2 Subsequently, a portion of the first dielectric masking layer 134 may be retained on the gate spacer layer 122 in the second device region 50B. This retained portion of the first dielectric masking layer 134 may serve as part of the gate spacer layer and may be designated as "retained portion 134". The retained portion 134 of the first dielectric masking layer 134 on the gate spacer layer 122 will not negatively impact the epitaxial growth of the source / drain structure. Furthermore, the overall capacitance between the source / drain structure and the final gate stack will not significantly increase.

[0153] Figure 5A-1 and Figure 5A-2 These are cross-sectional views of various intermediate stages in forming a semiconductor structure in some embodiments, wherein the figures end with "-1" (e.g. Figure 5A-1 ) is the corresponding Figure 1 The sectional view shown is a section view of section XX, and those with "-2" at the end of the symbol (such as...) Figure 5A-2 ) is the corresponding Figure 1 The cross-sectional view shown is a section YY. Figure 5A-1 and Figure 5A-2 Implementation examples and Figures 2A-1 to 2U-2 The embodiments shown are similar, except that the fully wound gate field-effect transistor is formed in the first device region 50A, while the fin field-effect transistor device is formed in the second device region 50B.

[0154] Figure 5A-1 and Figure 5A-2 This is a cross-sectional view of the semiconductor structure 400 after the formation of fin structure 104A, fin structure 404B, and isolation structure 110 in some embodiments.

[0155] like Figure 5A-1 and Figure 5A-2 In some embodiments shown, the substrate 102 includes a first device region 50A formed therein by a fin structure 104A and a second device region 50B formed therein by a fin structure 404B. In some embodiments, the first device region 50A is a p-type device region and can be used to form a p-type semiconductor device (such as a p-type channel nanostructure transistor). In some embodiments, the second device region 50B is an n-type device region and can be used to form an n-type semiconductor device (such as an n-type channel fin field-effect transistor).

[0156] In some embodiments, the method of forming fin structures 104A and 404B includes using an etching process to recess the upper portion of the substrate 102 of the first device region 50A to form a space in the first device region 50A. Then, an epitaxial growth process is used to form an epitaxial stack on the substrate 102. The etching process may be an anisotropic etching process such as bar plasma etching, an isotropic etching process such as dry chemical etching, distal plasma etching, or wet chemical etching, and / or a combination thereof. The materials, composition, and formation method of the epitaxial stack may be consistent with those of other epitaxial stacks. Figure 2A-1 and Figure 2A-2 The epitaxial stacks shown above are similar or identical. In some embodiments, planarization processes such as chemical mechanical polishing or etch-back processes may be performed to remove a portion of the epitaxial stack on substrate 102 until the upper surface of substrate 102 is exposed. In some embodiments, after the planarization process, the upper surface of the epitaxial stack and the upper surface of substrate 102 may be substantially coplanar. In some embodiments, the epitaxial stack in the first device region 50A and the upper portion of substrate 102 in the second device region 50B may then be patterned to form fin structure 104A in the first device region 50A and fin structure 404B in the second device region 50B. In this way, in some embodiments, the fin structure 404B and the upper portion of substrate 102 may be formed from a single continuous semiconductor material.

[0157] like Figure 5A-2 In some embodiments shown, an isolation structure 110 is formed to surround the lower fin unit 104L of the fin structure 104A and the lower fin unit 404L of the fin structure 404B. In some embodiments, the fin structure 404B includes an upper fin unit protruding from between the isolation structures 110. The material and formation method of the isolation structure 110 may be consistent with... Figure 2A-1 and Figure 2A-2 The isolation structure 110 shown above is similar to or the same as that described above.

[0158] Figure 5B-1 and 5B-2 In some embodiments, Figures 2B-1 to 2F-2 A cross-sectional view of the semiconductor structure 400 after the above steps.

[0159] In some embodiments, a dummy gate structure 112 is formed to surround the channel regions of the fin structure 104A and the channel regions of the fin structure 404B, and gate spacer layers 120 and 122 are sequentially formed on the semiconductor structure 400. In some embodiments, one or more etching processes are performed to remove the horizontal portions of the gate spacer layers 120 and 122, and to recess the source / drain regions of the fin structure 104A and the source / drain regions of the fin structure 404B to form source / drain recesses 128A in the first device region 50A and source / drain recesses 128B in the second device region 50B. Some embodiments perform etching processes on the semiconductor structure 400 to recess the first semiconductor layer 106 of the fin structure 104A from the source / drain recesses 128A to form a notch 130. Figure 2E-1 ), and form an inner spacer layer 132 in the notch 130 to adjacent the first semiconductor layer 106 of the fin structure 104.

[0160] Figure 5C-1 and Figure 5C-2 In some embodiments, Figures 2G-1 to 2M-2 A cross-sectional view of the semiconductor structure 400 after the above steps.

[0161] In some embodiments, a masking structure containing a first dielectric masking layer 134 and a second dielectric masking layer 136 covers the second device region 50B. In some embodiments, a source / drain structure 146A is formed in the source / drain recess 128A of the first device region 50A of the semiconductor structure 400 using an epitaxial growth process.

[0162] Figure 5D-1 and Figure 5D-2 In some embodiments, Figures 2N-1 to 2Q-2 A cross-sectional view of the semiconductor structure 400 after the above steps.

[0163] In some embodiments, the masking structure used in the second device region 50B is removed. In some embodiments, a masking structure containing a fourth dielectric masking layer 148 and a fifth dielectric masking layer 150 is formed to cover the first device region 50A. Some embodiments employ an epitaxial growth process to form a source / drain structure 146B in the source / drain recess 128B of the second device region 50B of the semiconductor structure 400.

[0164] Figure 5E-1 and Figure 5E-2 In some embodiments, Figures 2R-1 to 2U-2 The diagram shows a cross-sectional view of the semiconductor structure 400 after the steps described above.

[0165] In some embodiments, the mask structure used in the first device region 50A is removed. In some embodiments, a contact etch stop layer 160 and an interlayer dielectric layer 162 are sequentially formed on the semiconductor structure 400. In some embodiments, an etching process is used to remove the dummy gate structure 112 to form a gate trench 164. Figure 2T-1 In some embodiments, an etching process is used to remove the first semiconductor layer 106 of the fin structure 104A to form a gap 166. Figure 2T-1 In some embodiments, the final gate stack 168 covers each nanostructure (such as the second semiconductor layer 108 of fin structure 104A) and the channel region of fin structure 404B to form a p-type channel fully wound gate field-effect transistor in the first device region 50A and an n-type channel fin field-effect transistor in the second device region 50B.

[0166] The hybrid structure provided in this embodiment contains a fully wound gate field-effect transistor and a fin field-effect transistor formed on the same semiconductor substrate (or wafer). Integrated circuits containing the hybrid structure can have better electrical performance and greater design flexibility. Figures 5A-2 to 5E-2 Embodiments of p-channel fully wound gate field-effect transistors and n-channel fin field-effect transistors are shown, but are not limited thereto. Embodiments of this disclosure are used to form source / drain mask structures, which can also be implemented in embodiments of p-channel fin field-effect transistors and n-channel fully wound gate field-effect transistors, and / or p-channel fin field-effect transistors and n-channel fin field-effect transistors.

[0167] As described above, embodiments of this disclosure relate to the separate formation of source / drain structures in different device regions. The method of the embodiments includes forming a silicon-containing dielectric mask layer (such as a first dielectric mask layer 134 or a fourth dielectric mask layer 148) and a high-dielectric-constant dielectric mask layer (such as a second dielectric mask layer 136 or a fifth dielectric mask layer 150) on the silicon-containing dielectric mask layer, patterning the dielectric mask layer into a source / drain mask structure to cover one device region and expose another device region, and then growing a source / drain structure in the exposed device region. Therefore, embodiments of this disclosure use a silicon-containing dielectric mask layer as the bottom layer of the source / drain mask structure, which provides a good balance between the loss of low-dielectric-constant spacers (such as gate spacer layers 120 and 122 and / or inner spacer 132) and the residual amount of the source / drain mask structure. This increases the process tolerance of the patterned source / drain mask structure.

[0168] Embodiments provide a method for forming a semiconductor structure. The method may include forming a first fin structure and a second fin structure, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric mask layer and a second dielectric mask layer thereon, wherein the first and second dielectric mask layers are made of different materials. The method also includes forming a first source / drain structure in the first fin structure and removing the first mask structure to expose the second fin structure. This provides a good balance between low dielectric constant spacer loss and residual source / drain mask structure, thereby increasing the process tolerance of patterned source / drain mask structures.

[0169] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure on a substrate, each of the first fin structure and the second fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method also includes forming a first masking structure to cover the second fin structure. The first masking structure includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer and the second dielectric layer being made of different materials. The method also includes forming a first source / drain structure in the first fin structure; removing the first masking structure; and forming a second source / drain structure in the second fin structure. The method further includes removing the first semiconductor layer of each of the first fin structure and the second fin structure to form a plurality of first nanostructures from the second semiconductor layer of the first fin structure and a plurality of second nanostructures from the second semiconductor layer of the second fin structure; and forming a gate stack around the first nanostructures and the second nanostructures.

[0170] In some embodiments, the step of forming the first mask structure includes: sequentially forming a first dielectric layer and a second dielectric layer on the first fin structure and the second fin structure; and etching a first portion of the first dielectric layer and the second dielectric layer on the first fin structure to expose the first fin structure, and retaining a second portion of the first dielectric layer and the second dielectric layer on the second fin structure to form the first mask structure.

[0171] In some embodiments, the method further includes: etching the first fin structure and the second fin structure to form a first source / drain recess and a second source / drain recess, respectively, wherein the first dielectric layer and the second dielectric layer partially fill the first source / drain recess and the second source / drain recess.

[0172] In some embodiments, the method further includes: overfilling the first source / drain recess and the second source / drain recess with a fill layer; forming a dielectric mask on the fill layer and covering the second fin structure; using the dielectric mask and etching the fill layer until a first portion of the second dielectric layer on the first fin structure is exposed; and etching the dielectric mask while etching the first dielectric layer and the first portion of the second dielectric layer on the first fin structure.

[0173] In some embodiments, the first dielectric layer is composed of silicon oxide, and the second dielectric layer is composed of an oxide of an amphoteric metal.

[0174] In some embodiments, the first source / drain structure and the second source / drain structure have different conductivity types.

[0175] In some embodiments, the method further includes: forming a second masking structure to cover the first source / drain structure before forming the second source / drain structure in the second fin structure, wherein the second masking structure includes a third dielectric layer and a fourth dielectric layer located on the third dielectric layer, and the third dielectric layer and the fourth dielectric layer are composed of different materials; and removing the second masking structure to expose the first source / drain structure after forming the second source / drain structure in the second fin structure.

[0176] In some embodiments, a method for forming a semiconductor structure is provided. The method includes interleaving and stacking a first semiconductor layer and a second semiconductor layer on a substrate; and patterning the first semiconductor layer and the second semiconductor layer into a first fin structure in a first region of the substrate, and a second fin structure in a second region of the substrate. The method also includes etching the first fin structure to form a first recess, and etching the second fin structure to form a second recess; and forming a first mask structure to cover the second recess and expose the first recess. The first mask structure includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, and the dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer. The method also includes forming a first source / drain structure in the first recess; and removing the first mask structure. The method also includes forming a second mask structure to cover the first source / drain structure and expose the second recess; forming a second source / drain structure in the second recess; and removing the second mask structure.

[0177] In some embodiments, the method further includes: forming a first dielectric layer to cover a first region and a second region of a substrate; forming a second dielectric layer on the first dielectric layer; etching a portion of the second dielectric layer in the first region; and etching a portion of the first dielectric layer in the first region.

[0178] In some embodiments, the step of etching a portion of the second dielectric layer includes a wet etching process using an alkaline solution with a pH of about 7.2 to about 11.

[0179] In some embodiments, the step of etching a portion of the first dielectric layer includes a wet etching process using an acidic solution with a pH of about 3 to about 6.8.

[0180] In some embodiments, the method further includes: laterally recessing the first semiconductor layer of the second fin structure from the second recess to form a plurality of gaps; forming a plurality of inner spacers in the gaps, wherein the inner spacers are separated from the second dielectric layer by the first dielectric layer.

[0181] In some embodiments, the inner spacer has a sidewall facing the second recess, and a portion of the first dielectric layer after the removal of the first shielding structure remains on the sidewall of the inner spacer.

[0182] In some embodiments, the second masking structure includes a third dielectric layer and a fourth dielectric layer located on the third dielectric layer, and the dielectric constant of the third dielectric layer is less than the dielectric constant of the fourth dielectric layer.

[0183] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure on a substrate; and forming a first recess in a first source / drain region of the first fin structure, and forming a second recess in a second source / drain region of the second fin structure. The method also includes sequentially forming a first dielectric layer and a second dielectric layer in the first and second recesses, wherein the first dielectric layer is composed of a silicon-containing dielectric material, and the second dielectric layer is composed of an oxide of an amphoteric metal. The method further includes forming a dielectric mask on the second dielectric layer and covering the second recess; and removing a first portion of the first and second dielectric layers and the dielectric mask from the first recess. The method also includes growing a first source / drain structure on the first fin structure in the first recess.

[0184] In some embodiments, the first fin structure includes interleaved stacked first semiconductor layers and second semiconductor layers, and the second fin structure and the upper portion of the substrate are composed of a single continuous material.

[0185] In some embodiments, the method further includes, after growing the first source / drain structure, removing a second portion of the first dielectric layer and the second dielectric layer in the second recess; growing a second source / drain structure on the second fin structure in the second recess; and forming a gate stack to extend over the first fin structure and the second fin structure.

[0186] In some embodiments, the step of removing the first portion of the first dielectric layer and the second dielectric layer and the dielectric mask in the first recess includes a wet etching process using an acidic solution with a pH of about 3 to about 6.8.

[0187] In some embodiments, the method further includes: forming a dummy gate structure over the first fin structure and the second fin structure; forming a gate spacer layer along the sidewall of the dummy gate structure, wherein the first dielectric layer is located between the gate spacer layer and the second dielectric layer; and removing the dummy gate structure after growing the second source / drain structure.

[0188] In some embodiments, after a first portion of the first dielectric layer in the first recess is removed, the remaining portion of the first dielectric layer remains on the sidewall of the gate spacer layer.

[0189] The features of the above embodiments are beneficial for those skilled in the art to understand this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A first fin structure and a second fin structure are formed on a substrate, wherein each of the first fin structure and the second fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in an alternating manner. The first fin structure is etched to form a first source / drain recess, and the second fin structure is etched to form a second source / drain recess. A first masking structure is formed to cover the second fin-like structure, wherein the first masking structure includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, and the first dielectric layer and the second dielectric layer are made of different materials, wherein the step of forming the first masking structure includes: The first dielectric layer and the second dielectric layer are formed sequentially in the first source / drain recess and the second source / drain recess; Remove a first portion of the second dielectric layer in the first source / drain recess to expose a first portion of the first dielectric layer in the first source / drain recess; When removing the first portion of the second dielectric layer, a dielectric mask on the first mask structure is removed; After removing the dielectric shield, the first portion of the first dielectric layer is removed to expose the first fin structure; A first source / drain structure is formed in the first fin structure; Remove the first mask structure; A second source / drain structure is formed in the second fin structure; Remove the first semiconductor layer from each of the first fin structure and the second fin structure to form a plurality of first nanostructures from the second semiconductor layer of the first fin structure, and to form a plurality of second nanostructures from the second semiconductor layer of the second fin structure; and A gate is formed around the first nanostructure and the second nanostructure.

2. The method for forming a semiconductor structure as described in claim 1, further comprising: An overfill layer is applied to the first source / drain recess and the second source / drain recess; The dielectric shield is formed on the filler layer and covers the second fin structure; The dielectric mask is used and the fill layer is etched.

3. The method for forming a semiconductor structure as described in claim 1, wherein the first dielectric layer is composed of silicon oxide, and the second dielectric layer is composed of an oxide of an amphoteric metal.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein the first source / drain structure and the second source / drain structure have different conductivity types.

5. The method for forming a semiconductor structure as described in claim 1, further comprising: Before forming the second source / drain structure in the second fin structure, a second masking structure is formed to cover the first source / drain structure, wherein the second masking structure includes a third dielectric layer and a fourth dielectric layer located on the third dielectric layer, and the third dielectric layer and the fourth dielectric layer are composed of different materials. as well as After the second source / drain structure is formed in the second fin structure, the second masking structure is removed to expose the first source / drain structure.

6. A method for forming a semiconductor structure, comprising: Multiple first semiconductor layers and multiple second semiconductor layers are stacked alternately on a substrate; The first semiconductor layer and the second semiconductor layer are patterned into a first fin-like structure in a first region of the substrate, and a second fin-like structure is formed in a second region of the substrate; The first fin structure is etched to form a first recess, and the second fin structure is etched to form a second recess; A first masking structure is formed to cover the second recess and expose the first recess, wherein the first masking structure includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, and the dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer, wherein the step of forming the first masking structure includes: The first dielectric layer and the second dielectric layer are formed sequentially in the first recess and the second recess; Remove a first portion of the second dielectric layer in the first recess to expose a first portion of the first dielectric layer in the first recess; When removing the first portion of the second dielectric layer, a dielectric mask on the first mask structure is removed; After removing the dielectric shield, the first portion of the first dielectric layer is removed to expose the first fin structure; A first source / drain structure is formed in the first recess; Remove the first mask structure; A second shielding structure is formed to cover the first source / drain structure and expose the second recess; A second source / drain structure is formed in the second recess; and Remove the second mask structure.

7. The method for forming a semiconductor structure as claimed in claim 6, wherein the step of removing the first portion of the second dielectric layer includes a wet etching process using an alkaline solution with a pH of about 7.2 to about 11.

8. The method of forming a semiconductor structure as claimed in claim 6, wherein the step of removing the first portion of the first dielectric layer includes a wet etching process using an acidic solution with a pH of about 3 to about 6.

8.

9. The method for forming a semiconductor structure as described in claim 6, further comprising: The second recess causes the first semiconductor layer of the second fin structure to be laterally recessed to form multiple gaps; Multiple inner spacers are formed in the notch, wherein the inner spacers are separated from the second dielectric layer by the first dielectric layer.

10. The method of forming a semiconductor structure as claimed in claim 9, wherein the inner spacer has a plurality of sidewalls facing the second recess, and a retained portion of the first dielectric layer after the removal of the first masking structure remains on the sidewalls of the inner spacer.

11. The method for forming a semiconductor structure as claimed in claim 6, wherein the second masking structure includes a third dielectric layer and a fourth dielectric layer located on the third dielectric layer, and the dielectric constant of the third dielectric layer is less than the dielectric constant of the fourth dielectric layer.

12. A method for forming a semiconductor structure, comprising: A first fin-like structure and a second fin-like structure are formed on a substrate; A first recess is formed in a first source / drain region of the first fin structure, and a second recess is formed in a second source / drain region of the second fin structure; A first dielectric layer and a second dielectric layer are sequentially formed in the first recess and the second recess, wherein the first dielectric layer is composed of a silicon-containing dielectric material, and the second dielectric layer is composed of an oxide of an amphoteric metal. A dielectric shield is formed on the second dielectric layer and covers the second recess; Remove a first portion of the second dielectric layer in the first recess to expose a first portion of the first dielectric layer in the first recess; When removing the first portion of the second dielectric layer, the dielectric mask is removed; After removing the dielectric mask, the first portion of the first dielectric layer is removed to expose the first fin structure; and A first source / drain structure is grown on the first fin structure in the first recess.

13. The method of forming a semiconductor structure as claimed in claim 12, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in an alternating manner, and the second fin structure and an upper portion of the substrate are composed of a single continuous material.

14. The method for forming a semiconductor structure as described in claim 12, further comprising: After growing the first source / drain structure, the first dielectric layer and multiple second portions of the second dielectric layer in the second recess are removed; A second source / drain structure is grown on the second fin structure in the second recess; and A gate stack is formed to pass over the first fin structure and the second fin structure.

15. The method of forming a semiconductor structure as claimed in claim 12, wherein the step of removing the first portion of the first dielectric layer and the second dielectric layer and the dielectric mask from the first recess includes a wet etching process using an acidic solution with a pH of about 3 to about 6.

8.

16. The method for forming a semiconductor structure as described in claim 12, further comprising: A dummy gate structure is formed to pass over the first fin structure and the second fin structure; as well as A gate spacer layer is formed along the sidewall of the dummy gate structure, wherein the first dielectric layer is located between the gate spacer layer and the second dielectric layer; as well as The dummy gate structure is removed after the second source / drain structure is grown.

17. The method of forming a semiconductor structure as claimed in claim 16, wherein after removing the first portion of the first dielectric layer in the first recess, the remaining portion of the first dielectric layer remains on the sidewall of the gate spacer layer.

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