Package structure and method of forming the same

Abstract

The application provides a packaging structure and a forming method thereof. The packaging structure comprises a first substrate, a second substrate located above the first substrate, an optical integrated circuit located above the second substrate, and an electrical integrated circuit. The optical integrated circuit is electrically connected to the electrical integrated circuit through the first substrate and the second substrate. The above technical scheme of the application can improve the electrical connectivity of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a packaging structure and a method for forming the same. Background Technology

[0002] like Figure 1 As shown, the package structure includes a PIC (Optical Integrated Circuit) 12, such as a silicon photonics (Si-Ph) chip. In this package structure, a FAU (Fiber Array Unit) 14 needs to be attached to the active side of the PIC before the active side of the PIC is bonded to an EIC (Electrical Integrated Circuit) 16. Since the FAU 14 is relatively thick (the diameter of a single fiber is 125 μm + the shell thickness), a relatively high conductive post 15 is required for electrical connection between the PIC 12 and the EIC 16 (the height of the conductive post can be approximately 200 μm). However, due to the presence of the relatively high conductive post, during the bonding process between the PIC 12 and the EIC 16, some of the conductive posts 15 may be unable to withstand the bonding force and bend 19, resulting in poor electrical connection. Summary of the Invention

[0003] To address the aforementioned problems in related technologies, this invention proposes a packaging structure and its formation method, which can avoid the existing problems of poor electrical connection.

[0004] An embodiment of the present invention provides a packaging structure, including: a first substrate; a second substrate located above the first substrate; an optical integrated circuit located above the second substrate; and an electrical integrated circuit, wherein the optical integrated circuit is electrically connected to the electrical integrated circuit through the first substrate and the second substrate.

[0005] In some embodiments, the thickness of the first substrate is greater than the thickness of the second substrate.

[0006] In some embodiments, the second substrate includes redistribution lines (RDLs).

[0007] In some embodiments, the first substrate is bonded to the second substrate via an adhesive layer.

[0008] In some embodiments, the first substrate and the electrical integrated circuit are arranged side by side in the lateral direction, and the total thickness of the first substrate and the second substrate is greater than the thickness of the electrical integrated circuit.

[0009] In some embodiments, a first I / O connector is provided on the side of the first substrate away from the second substrate, and a second I / O connector is provided on the side of the second substrate away from the first substrate, wherein the pitch of the first I / O connector is different from the pitch of the second I / O connector. In some embodiments, the pitch of the first I / O connector is greater than the pitch of the second I / O connector.

[0010] In some embodiments, the packaging structure further includes a third substrate, on which the first substrate and the electrical integrated circuit are located, wherein the optical integrated circuit is also electrically connected to the optical integrated circuit through the third substrate.

[0011] In some embodiments, the third substrate includes redistribution lines (RDLs).

[0012] In some embodiments, the packaging structure further includes a first fiber optic array unit located above the electrical integrated circuit and below the optical integrated circuit. The first fiber optic array unit has a first sidewall extending from below the optical integrated circuit to above the electrical integrated circuit, at least a portion of which is inclined.

[0013] In some embodiments, the package structure further includes another integrated circuit located below the optical integrated circuit and on opposite sides of the first and second substrates, together with the electrical integrated circuit.

[0014] In some embodiments, the packaging structure further includes a second fiber array unit located above another integrated circuit and below the optical integrated circuit. The second fiber array unit has a second sidewall extending from below the optical integrated circuit to above the other integrated circuit, at least a portion of which is inclined.

[0015] In some embodiments, another integrated circuit is a power management integrated circuit.

[0016] In some embodiments, the packaging structure further includes: an underfill material that encapsulates the first substrate and the second substrate.

[0017] Embodiments of the present invention also provide a method for forming a package structure, comprising: placing a first substrate and a second substrate on the first substrate adjacent to an electrical integrated circuit; and stacking an optical integrated circuit on the second substrate such that the optical integrated circuit is electrically connected to the electrical integrated circuit through the first substrate and the second substrate.

[0018] In some embodiments, after placing the first substrate and the second substrate, the method further includes: placing an optical fiber array unit above the electrical integrated circuit, wherein the optical integrated circuit is located above the second substrate and the optical fiber array unit.

[0019] In some embodiments, prior to placing the first substrate and the second substrate, the method further includes placing an electrical integrated circuit and another integrated circuit on a third substrate.

[0020] In some embodiments, the method further includes: forming a molded article surrounding an electrical integrated circuit and another integrated circuit; forming an opening in the molded article between the electrical integrated circuit and the other integrated circuit, wherein a first substrate and a second substrate are placed in the opening.

[0021] In some embodiments, after stacking the optical integrated circuit, the method further includes: forming a bottom filler to encapsulate the first substrate and the second substrate.

[0022] In some embodiments, forming the bottom filler includes: forming a first portion of the bottom filler using a first bottom filler material; and forming a second portion of the bottom filler using a second bottom filler material different from the first bottom filler material. Attached Figure Description

[0023] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1 This is a cross-sectional schematic diagram of an existing packaging structure that includes optical integrated circuits.

[0025] Figure 2A This is a cross-sectional schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 2B and Figure 2C yes Figure 2A A partially enlarged cross-sectional schematic diagram.

[0026] Figures 3A to 3Q This is a schematic diagram of the various intermediate stages of forming the packaging structure according to the embodiments of this application.

[0027] Figure 4 This is a cross-sectional schematic diagram of the packaging structure according to other embodiments of the present invention.

[0028] Figure 5 This is a cross-sectional schematic diagram of the packaging structure according to other embodiments of the present invention.

[0029] Figure 6A and Figure 6B as well as Figure 6C and Figure 6D These are cross-sectional and top views of the packaging structure according to different embodiments of the present invention.

[0030] Figures 7 to 8 This is a cross-sectional schematic diagram of the packaging structure according to other embodiments of the present invention. Specific Implementation

[0031] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0032] Figure 2A This is a cross-sectional schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 2A As shown, the package structure includes a first substrate 210 and a second substrate 220 located above the first substrate 210. A PIC 212 is disposed above the second substrate 220. In one embodiment, the PIC 212 may be, for example, a silicon photonics (Si-Ph) chip. The PIC 212 is electrically connected to the EIC 216 via the first substrate 210 and the second substrate 220.

[0033] like Figure 1 As shown, since FAU 14 is needed to conduct light from PIC 12 and FAU 14 is located between PIC 12 and EIC 16, in the prior art, the thickness of FAU 14 results in a large distance between PIC 12 and EIC 16, necessitating the use of highly conductive pillars 15 for electrical connection. Furthermore, a bonding process is required to electrically connect PIC 12 and EIC 16, during which force is applied to the highly conductive pillars 15, causing them to bend 19. Instead, PIC 212 and EIC 216 are electrically connected via a first substrate 210 and a second substrate 220. Compared to the existing method of electrically connecting PIC 212 and EIC 216 via highly conductive pillars, this avoids the problem of poor electrical connection caused by bending of some highly conductive pillars during the PIC 212 and EIC 216 bonding process, thus improving the electrical connectivity of the package structure.

[0034] In some embodiments, such as Figure 2AAs shown, the second substrate 220 is electrically connected to the active surface of the PIC 212. The second substrate 220 may have a redistribution line (RDL). In such embodiments, the first substrate 210 and the second substrate 220 may also be referred to as fan-out substrates. The input / output (I / O) connectors 217 of the PIC 212 can be fanned out through the second substrate 220, and the EIC 216 is electrically connected to the PIC 212 through the RDL of the second substrate 220. In some embodiments, the second substrate 220 may include a single RDL layer. In other embodiments, the second substrate 220 may include multiple RDL layers.

[0035] Combination Figure 2A and Figure 2B As shown, the first substrate 210 has a first I / O connector 219 on the side away from the second substrate 220. In some embodiments, the first I / O connector 219 is a C4 bump. The first I / O connector 219 is used for electrical connection to the EIC 216. The second substrate 220 has a second I / O connector 222 on the side away from the first substrate 210. The second I / O connector 222 can be electrically connected to the active surface of the PIC 212. In some embodiments, the second I / O connector 222 is a microbump. In some embodiments, the diameter of the microbump can be in the range of 10 μm to 20 μm. The diameter of the C4 bump can be in the range of 30 μm to 100 μm. The pitch of the first I / O connector 219 is different from the pitch of the second I / O connector 222. In the illustrated embodiment, the pitch of the first I / O connector 219 is greater than the pitch of the second I / O connector 222. In some embodiments, the pitch of the second I / O connector 222 (e.g., microbump metal) can be in the range of 15 μm to 60 μm. The pitch of the first I / O connector 219 (e.g., C4 bump metal) can be in the range of 50 μm to 150 μm.

[0036] The first substrate 210 may include, for example, vias and lines located in the dielectric material 211 for electrical connection, and be electrically connected to the RDL of the second substrate 220 through the vias and lines. In some embodiments, the material of the dielectric material 211 may include PI (Polyimide), epoxy resin, ABF (Ajinomoto buildup film), PP (polypropylene), etc. In other embodiments, the material of the dielectric material 211 may include organic photosensitive liquid, organic non-photosensitive liquid, and / or dry film material. The thickness of the first substrate 210 may be greater than the thickness of the second substrate 220. An adhesive layer 230 may be provided between the first substrate 210 and the second substrate 220, and the first substrate 210 is bonded to the second substrate 220 through the adhesive layer 230. In some embodiments, the thickness of the adhesive layer 230 may be in the range of 20 μm to 80 μm. The thickness of the second substrate 220 may be in the range of 3 μm to 10 μm.

[0037] A first FAU 242 is disposed above EIC 216 and partially below PIC 212. The first FAU 242 has a sidewall 241 extending from below PIC 212 to above EIC 216, at least a portion of which is inclined. Another sidewall 243 of the first FAU 242 may extend laterally beyond the sidewall of EIC 216. A first substrate 210 is disposed laterally alongside EIC 216. By stacking a second substrate 220 on the first substrate 210, the total thickness of the first substrate 210 and the second substrate 220 is greater than the thickness of EIC 216. The second substrate 220 increases the spacing between PIC 212 and EIC 216 (to accommodate the space required for the first FAU 242). Subsequently, an underfill 250 can be provided to encapsulate the first substrate 210 and the second substrate 220, using the underfill 250 to fix and protect the PIC 212, FAU 242 and 244, the second substrate 220, and the first substrate 210. In some embodiments, the material of the underfill 250 may include PI (Polyimide), epoxy resin, ABF (Ajinomoto buildup film), PP (polypropylene), etc. In other embodiments, the material of the underfill 250 may include organic photosensitive liquid, organic non-photosensitive liquid, and / or dry film material.

[0038] Continue to refer to Figure 2AAs shown, both the first substrate 210 and the EIC 216 are located on the third substrate 260. The PIC 212 is also electrically connected to the PIC 212 via the third substrate 260. In some embodiments, the third substrate 260 may include a dielectric material 261 and redistribution lines (RDLs) 262 located in the dielectric material 261 to electrically connect the PIC 212 to the EIC 216. In some embodiments, the material of the dielectric material 261 may include PI, epoxy resin, ABF, PP, etc. In other embodiments, the material of the dielectric material 261 may include an organic photosensitive liquid, an organic non-photosensitive liquid, or / and a dry film material.

[0039] On the opposite side of EIC 216 located on the first substrate 210 and the second substrate 220, another integrated circuit 218 is also disposed, which is partially located below PIC 212. In some embodiments, the other integrated circuit 218 is a power management integrated circuit (PMIC). The thickness of the other integrated circuit 218 can be in the range of 20 μm to 100 μm. The thickness of EIC 216 can be in the range of 20 μm to 100 μm. The thickness of PIC 212 can be in the range of 20 μm to 100 μm. EIC 216 and the other integrated circuit 218 are surrounded by molding compound 270, which protects EIC 216 and the other integrated circuit 218. In some embodiments, the material of molding compound 270 may include PI, epoxy resin, ABF, PP, etc. In other embodiments, the material of molding compound 270 may include organic photosensitive liquid, organic non-photosensitive liquid, and / or dry film material. The second FAU 244 is disposed above another integrated circuit 218 and partially below PIC 212, wherein the second FAU 244 has a similar structure to the first FAU 242.

[0040] An adhesive layer 235 may be provided between EIC 216 and the first FAU, and between another integrated circuit and the second FAU 244, to secure the first FAU 242 and the second FAU 244. Figure 2A and Figure 2C As shown, a light guide layer 280 is disposed between the first FAU 242 and the second FAU 244 and the PIC 212. The light guide layer 280 is used for the propagation and reflection of light 285. In addition, the bottom filler 250, besides protecting the PIC 212, FAUs 242 and 244, the second substrate 220, and the first substrate 210, can also serve as a reflective material for the light 285. Figure 2A and Figure 2CAs shown, taking the first FAU 242 as an example, the inclined sidewall 241 of the first FAU 242 forms a reflection angle θ with the horizontal direction. In some embodiments, the reflection angle θ is in the range of 10° to 80°. An inclined interface is formed between the first FAU 242 and the bottom filler 250, which can be used to reflect light according to design requirements, while also increasing adhesion strength and supporting the PIC 212. In addition, due to the inclined sidewalls of the first FAU 242 and the second FAU 244, the FAU needs to be cut twice (first cut at the top, second cut at the bottom), which can avoid damaging the FAU during the cutting process. The structure of the first FAU 242 and the second FAU 244 can be configured in any suitable way, and is not limited to... Figure 2A The structure shown.

[0041] exist Figure 2A In the illustrated embodiment, the PIC 212 is provided with a heat sink 288 for heat dissipation. In other embodiments, the heat sink 288 may be omitted. The material of the heat sink 288 may be a metal, such as copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), or platinum alloy.

[0042] Figures 3A to 3Q A schematic diagram illustrating the various intermediate stages of forming a packaging structure according to embodiments of this application is shown. First, as Figure 3A As shown, for example, a first seed layer 304 is deposited over the support 302 via physical vapor deposition (PVD). Then, as... Figure 3B As shown, a first photomask 306 is formed on the first seed layer 304, and the first photomask 306 is patterned using a photolithography process to form a first opening 305 in the first photomask 306 that exposes a portion of the first seed layer 304, as shown. Figure 3C As shown. Furthermore, a first metal material 308 is plated in the first opening 305.

[0043] exist Figure 3D In the process, the first photomask 306 and the first seed layer 304 below the first photomask 306 are removed. A dielectric material 301 is then applied to the resulting first seed layer 304 and the first metal material 308, such as... Figure 3E The dielectric material 301 is patterned using photolithography. This patterning creates a second opening 311 in the dielectric material 301, exposing the first metal material 308, as shown below. Figure 3F As shown. A second seed layer 313 is deposited, for example, by PVD, on the patterned dielectric material 301 and within the second opening 311. A second photomask 315 is formed on the second seed layer 313, as shown. Figure 3GA second photomask 315 is patterned using photolithography to form a third opening 316 within the second photomask 315, the third opening 316 being located above the second opening 311. Subsequently, a second metal material 319 is deposited within the second opening 311 through the third opening 316, such as... Figure 3H Remove the second photomask 315 and the second seed layer 313 below the second photomask 315, as follows: Figure 3I Therefore, the RDL layer 360 is formed, the second seed layer 313 and the second metal material 319 can serve as through holes in the dielectric material 301, and the first metal material 308 can serve as lines in the dielectric material.

[0044] exist Figure 3J In this configuration, an EIC 316 and another integrated circuit 318 are bonded above the RDL layer 360. The other integrated circuit 318 can be, for example, a PMIC. The EIC 316 and the other integrated circuit 318 can be electrically connected to the RDL layer 360 via solder balls or conductive pillars. Figure 3K In the process, a molded object 370 encapsulating EIC 316 and another integrated circuit 318 is formed, and an adhesive layer 325 is applied to the molded object 370. Then, a portion of the molded object 370 and the adhesive layer 325 between EIC 316 and the other integrated circuit 318 is removed using a laser cutting process to form a fourth opening 329 between EIC 316 and the other integrated circuit 318, exposing the RDL layer 360. Figure 3L As shown. A first substrate 310 and a second substrate 320 are bonded together within a fourth opening 329 above the exposed RDL layer 360. The second substrate 320 is located above the first substrate 310, and its top surface has pads and solder balls (which may be referred to as I / O connectors) for subsequent electrical connections.

[0045] exist Figure 3M In this embodiment, a first FAU 342 and a second FAU 344 are formed above an adhesive layer 325 on another integrated circuit 318 and an EIC 316. The first FAU 342 and the second FAU 344 are located on opposite sides of the first substrate 310 and the second substrate 320. The sidewalls of the first FAU 342 and the second FAU 344 facing the first substrate 310 and the second substrate 320 are inclined.

[0046] like Figure 3N As shown, a PIC 312 is formed above the first FAU 342, the second FAU 344, and the second substrate 320, and the PIC 312 is electrically connected to the second substrate 320. Figure 3OIn the process, a bottom filler 350 is injected. The bottom filler 350 fills between the first FAU and the second FAU to encapsulate the first substrate 310 and the second substrate 320. The bottom filler 350 also encapsulates the bottom of the PIC 312. Furthermore, a heat sink 388 is provided on the top surface of the PIC 312. In some embodiments, the heat sink 388 may be omitted. It should also be noted that, although... Figure 3M and Figure 3N The illustration shows an embodiment where the FAU is placed first, followed by the PIC on top of the FAU 3. However, any other suitable method can be used to place the FAU. For example, sufficient space can be reserved for placing the FAU, and then the FAU can be placed into the reserved space, for example, by a pick and placing method.

[0047] exist Figure 3O In the process, the resulting structure is flipped, and the carrier 302 is removed to expose the first seed layer 304 in the RDL layer 360. The first seed layer 304 is then removed, exposing the first metallic material 308, such as... Figure 3P Furthermore, solder balls 365 are formed on the first metal material 308, such as... Figure 3Q Subsequently, a cutting process can be performed and the resulting structure can be flipped again to form the packaging structure of the present invention (e.g., Figure 2A ).

[0048] Figure 4 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2A Compared to the bottom filler 350 and the molded part 370 formed simultaneously, in Figure 4 In one embodiment, only the molded part 270 is formed, and the top surface of the molded part 270 is flush with the top surface of the heat sink 288 on the PIC 212 to enclose the bottom and sidewalls of the PIC 212. In this embodiment, the first FAU 242 and the second FAU 244 also extend upward to the top surface of the molded part.

[0049] Figure 5 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2A Compared to the bottom filler 250 formed in one step with the same material, in Figure 5In this embodiment, the underfill 250 of different materials can be formed multiple times (e.g., twice). A first portion 251 of the underfill 250 is formed using a first underfill material, and a second portion 252 of the underfill 250 is formed using a second underfill material different from the first underfill material, with the second portion 252 above the first portion 251. The first portion 251 can use an underfill material with good flowability, which better meets the filling requirements between I / O connectors. The second portion 252 can use a material with good adhesion (e.g., a dielectric material, such as PI (Polyimide)) to improve bonding between different interfaces.

[0050] Figure 6A and Figure 6B as well as Figure 6C and Figure 6D These are cross-sectional and top views of the packaging structure according to different embodiments of the present invention. Figure 6A and Figure 6B As shown, multiple FAU 240s can be formed, for example, four. The four FAU 240s are configured in pairs, opposite each other. (See diagram.) Figure 6C and Figure 6D As shown, a FAU 240 can be formed, and a FAU 240 can be located on either side of the package structure.

[0051] Figure 7 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2A Compared to the flip chip configuration, the EIC in China is set up in a different way. Figure 7 In this embodiment, the EIC 216 is electrically connected to the third substrate 360 ​​via bonding leads 292. The material of the bonding leads 292 may include Cu, Pt, Ag, Au, solder, Al, or Ni alloy.

[0052] Figure 8 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2A Compared to the first substrate 210 having its bottom surface covered by the third substrate 260, in Figure 8 In one embodiment, the bottom surface of the first substrate 210 may be exposed by the third substrate 260.

[0053] It should be understood that Figures 4 to 8 Other aspects of the embodiments shown are related to... Figures 2A to 2C The description is similar and therefore will not be repeated.

[0054] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A packaging structure, characterized in that, include: First substrate; The second substrate is located above the first substrate; A third substrate, wherein the first substrate is located above the third substrate; Optical integrated circuits; An electrical integrated circuit is provided, wherein the first substrate and the electrical integrated circuit are both located on the third substrate and are arranged side by side in the horizontal direction. The total thickness of the first substrate and the second substrate is greater than the thickness of the electrical integrated circuit. The optical integrated circuit is located above the second substrate and the electrical integrated circuit. The optical integrated circuit is electrically connected to the electrical integrated circuit through the first substrate, the second substrate and the third substrate. A first fiber array unit is located above the electrical integrated circuit and below the optical integrated circuit. The first fiber array unit has a first sidewall extending from below the optical integrated circuit to above the electrical integrated circuit, wherein at least a portion of the first sidewall is gradually inclined toward the electrical integrated circuit in a direction laterally away from the second substrate.

2. The packaging structure according to claim 1, characterized in that, The second substrate includes redistribution lines (RDLs).

3. The packaging structure according to claim 1, characterized in that, The first substrate is bonded to the second substrate through an adhesive layer.

4. The packaging structure according to claim 1, characterized in that, The first substrate has a first I / O connector on the side away from the second substrate, and the second substrate has a second I / O connector on the side away from the first substrate, wherein the pitch of the first I / O connector is different from the pitch of the second I / O connector.

5. The packaging structure according to claim 4, characterized in that, The pitch of the first I / O connector is greater than the pitch of the second I / O connector.

6. The packaging structure according to claim 1, characterized in that, Also includes: Another integrated circuit is located below the optical integrated circuit and is situated on opposite sides of the first substrate and the second substrate, respectively, along with the electrical integrated circuit.

7. The packaging structure according to claim 1, characterized in that, Also includes: A bottom filler that encapsulates the first substrate and the second substrate.

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